From: Luke Kenneth Casson Leighton Date: Sat, 22 May 2021 11:02:59 +0000 (+0000) Subject: update PLL to use submodule Instance X-Git-Tag: LS180_RC3~63 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=db874e1234c72432a822e6d69b54f73e6a911664;p=soclayout.git update PLL to use submodule Instance --- diff --git a/experiments9/non_generated/full_core_4_4ksram_libresoc.v b/experiments9/non_generated/full_core_4_4ksram_libresoc.v index 77cd9a9..a54a773 100644 --- a/experiments9/non_generated/full_core_4_4ksram_libresoc.v +++ b/experiments9/non_generated/full_core_4_4ksram_libresoc.v @@ -2,8 +2,15 @@ (* \nmigen.hierarchy = "test_issuer.ti.core.dec_ALU.dec.ALU_dec19" *) (* generator = "nMigen" *) -module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_sel, ALU_dec19_in2_sel, ALU_dec19_cr_in, ALU_dec19_cr_out, ALU_dec19_ldst_len, ALU_dec19_rc_sel, ALU_dec19_cry_in, ALU_dec19_inv_a, ALU_dec19_inv_out, ALU_dec19_cry_out, ALU_dec19_is_32b, ALU_dec19_sgn, opcode_in); +module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_SV_Ptype, ALU_dec19_in1_sel, ALU_dec19_in2_sel, ALU_dec19_cr_in, ALU_dec19_cr_out, ALU_dec19_ldst_len, ALU_dec19_rc_sel, ALU_dec19_cry_in, ALU_dec19_inv_a, ALU_dec19_inv_out, ALU_dec19_cry_out, ALU_dec19_is_32b, ALU_dec19_sgn, opcode_in); reg \initial = 0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] ALU_dec19_SV_Ptype; + reg [1:0] ALU_dec19_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -13,7 +20,7 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec19_cr_in; reg [2:0] ALU_dec19_cr_in; (* enum_base_type = "CROutSel" *) @@ -23,44 +30,47 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec19_cr_out; reg [2:0] ALU_dec19_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] ALU_dec19_cry_in; reg [1:0] ALU_dec19_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec19_cry_out; reg ALU_dec19_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] ALU_dec19_function_unit; - reg [13:0] ALU_dec19_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] ALU_dec19_function_unit; + reg [14:0] ALU_dec19_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec19_in1_sel; reg [2:0] ALU_dec19_in1_sel; (* enum_base_type = "In2Sel" *) @@ -78,7 +88,8 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] ALU_dec19_in2_sel; reg [3:0] ALU_dec19_in2_sel; (* enum_base_type = "MicrOp" *) @@ -156,16 +167,18 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] ALU_dec19_internal_op; reg [6:0] ALU_dec19_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec19_inv_a; reg ALU_dec19_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec19_inv_out; reg ALU_dec19_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec19_is_32b; reg ALU_dec19_is_32b; (* enum_base_type = "LdstLen" *) @@ -174,39 +187,49 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] ALU_dec19_ldst_len; reg [3:0] ALU_dec19_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] ALU_dec19_rc_sel; reg [1:0] ALU_dec19_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec19_sgn; reg ALU_dec19_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [9:0] opcode_switch; always @* begin if (\initial ) begin end - ALU_dec19_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + ALU_dec19_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: - ALU_dec19_function_unit = 14'h0002; + ALU_dec19_function_unit = 15'h0002; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec19_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 10'h096: + ALU_dec19_cry_in = 2'h0; endcase end always @* begin if (\initial ) begin end ALU_dec19_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: ALU_dec19_inv_a = 1'h0; endcase @@ -214,9 +237,9 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s always @* begin if (\initial ) begin end ALU_dec19_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: ALU_dec19_inv_out = 1'h0; endcase @@ -224,9 +247,9 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s always @* begin if (\initial ) begin end ALU_dec19_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: ALU_dec19_cry_out = 1'h0; endcase @@ -234,9 +257,9 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s always @* begin if (\initial ) begin end ALU_dec19_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: ALU_dec19_is_32b = 1'h0; endcase @@ -244,9 +267,9 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s always @* begin if (\initial ) begin end ALU_dec19_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: ALU_dec19_sgn = 1'h0; endcase @@ -254,19 +277,29 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s always @* begin if (\initial ) begin end ALU_dec19_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: ALU_dec19_internal_op = 7'h24; endcase end + always @* begin + if (\initial ) begin end + ALU_dec19_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 10'h096: + ALU_dec19_SV_Ptype = 2'h0; + endcase + end always @* begin if (\initial ) begin end ALU_dec19_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: ALU_dec19_in1_sel = 3'h0; endcase @@ -274,9 +307,9 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s always @* begin if (\initial ) begin end ALU_dec19_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: ALU_dec19_in2_sel = 4'h0; endcase @@ -284,9 +317,9 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s always @* begin if (\initial ) begin end ALU_dec19_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: ALU_dec19_cr_in = 3'h0; endcase @@ -294,9 +327,9 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s always @* begin if (\initial ) begin end ALU_dec19_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: ALU_dec19_cr_out = 3'h0; endcase @@ -304,9 +337,9 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s always @* begin if (\initial ) begin end ALU_dec19_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: ALU_dec19_ldst_len = 4'h0; endcase @@ -314,30 +347,27 @@ module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_s always @* begin if (\initial ) begin end ALU_dec19_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: ALU_dec19_rc_sel = 2'h0; endcase end - always @* begin - if (\initial ) begin end - ALU_dec19_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) - casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 10'h096: - ALU_dec19_cry_in = 2'h0; - endcase - end assign opcode_switch = opcode_in[10:1]; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_ALU.dec.ALU_dec31" *) (* generator = "nMigen" *) -module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_sel, ALU_dec31_in2_sel, ALU_dec31_cr_in, ALU_dec31_cr_out, ALU_dec31_ldst_len, ALU_dec31_rc_sel, ALU_dec31_cry_in, ALU_dec31_inv_a, ALU_dec31_inv_out, ALU_dec31_cry_out, ALU_dec31_is_32b, ALU_dec31_sgn, opcode_in); +module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_SV_Ptype, ALU_dec31_in1_sel, ALU_dec31_in2_sel, ALU_dec31_cr_in, ALU_dec31_cr_out, ALU_dec31_ldst_len, ALU_dec31_rc_sel, ALU_dec31_cry_in, ALU_dec31_inv_a, ALU_dec31_inv_out, ALU_dec31_cry_out, ALU_dec31_is_32b, ALU_dec31_sgn, opcode_in); reg \initial = 0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] ALU_dec31_SV_Ptype; + reg [1:0] ALU_dec31_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -347,7 +377,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_cr_in; reg [2:0] ALU_dec31_cr_in; (* enum_base_type = "CROutSel" *) @@ -357,19 +387,25 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_cr_out; reg [2:0] ALU_dec31_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] ALU_dec31_cry_in; reg [1:0] ALU_dec31_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_cry_out; reg ALU_dec31_cry_out; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -379,7 +415,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -388,40 +424,43 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -438,7 +477,8 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -515,13 +555,15 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -529,18 +571,24 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] ALU_dec31_dec_sub0_opcode_in; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -550,7 +598,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -559,40 +607,43 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -609,7 +660,8 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -686,13 +738,15 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -700,18 +754,24 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] ALU_dec31_dec_sub10_opcode_in; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -721,7 +781,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -730,40 +790,43 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -780,7 +843,8 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -857,13 +921,15 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -871,18 +937,24 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] ALU_dec31_dec_sub22_opcode_in; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -892,7 +964,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -901,40 +973,43 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -951,7 +1026,8 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -1028,13 +1104,15 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -1042,18 +1120,24 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] ALU_dec31_dec_sub26_opcode_in; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -1063,7 +1147,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -1072,40 +1156,43 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -1122,7 +1209,8 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -1199,13 +1287,15 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -1213,43 +1303,46 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] ALU_dec31_dec_sub8_opcode_in; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] ALU_dec31_function_unit; - reg [13:0] ALU_dec31_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] ALU_dec31_function_unit; + reg [14:0] ALU_dec31_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_in1_sel; reg [2:0] ALU_dec31_in1_sel; (* enum_base_type = "In2Sel" *) @@ -1267,7 +1360,8 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] ALU_dec31_in2_sel; reg [3:0] ALU_dec31_in2_sel; (* enum_base_type = "MicrOp" *) @@ -1345,16 +1439,18 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] ALU_dec31_internal_op; reg [6:0] ALU_dec31_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_inv_a; reg ALU_dec31_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_inv_out; reg ALU_dec31_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_is_32b; reg ALU_dec31_is_32b; (* enum_base_type = "LdstLen" *) @@ -1363,26 +1459,27 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] ALU_dec31_ldst_len; reg [3:0] ALU_dec31_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] ALU_dec31_rc_sel; reg [1:0] ALU_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_sgn; reg ALU_dec31_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:355" *) wire [4:0] opc_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [9:0] opcode_switch; ALU_dec31_dec_sub0 ALU_dec31_dec_sub0 ( + .ALU_dec31_dec_sub0_SV_Ptype(ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_SV_Ptype), .ALU_dec31_dec_sub0_cr_in(ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in), .ALU_dec31_dec_sub0_cr_out(ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out), .ALU_dec31_dec_sub0_cry_in(ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in), @@ -1400,6 +1497,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s .opcode_in(ALU_dec31_dec_sub0_opcode_in) ); ALU_dec31_dec_sub10 ALU_dec31_dec_sub10 ( + .ALU_dec31_dec_sub10_SV_Ptype(ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_SV_Ptype), .ALU_dec31_dec_sub10_cr_in(ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in), .ALU_dec31_dec_sub10_cr_out(ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out), .ALU_dec31_dec_sub10_cry_in(ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in), @@ -1417,6 +1515,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s .opcode_in(ALU_dec31_dec_sub10_opcode_in) ); ALU_dec31_dec_sub22 ALU_dec31_dec_sub22 ( + .ALU_dec31_dec_sub22_SV_Ptype(ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_SV_Ptype), .ALU_dec31_dec_sub22_cr_in(ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in), .ALU_dec31_dec_sub22_cr_out(ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out), .ALU_dec31_dec_sub22_cry_in(ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_in), @@ -1434,6 +1533,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s .opcode_in(ALU_dec31_dec_sub22_opcode_in) ); ALU_dec31_dec_sub26 ALU_dec31_dec_sub26 ( + .ALU_dec31_dec_sub26_SV_Ptype(ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_SV_Ptype), .ALU_dec31_dec_sub26_cr_in(ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in), .ALU_dec31_dec_sub26_cr_out(ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out), .ALU_dec31_dec_sub26_cry_in(ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_in), @@ -1451,6 +1551,7 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s .opcode_in(ALU_dec31_dec_sub26_opcode_in) ); ALU_dec31_dec_sub8 ALU_dec31_dec_sub8 ( + .ALU_dec31_dec_sub8_SV_Ptype(ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_SV_Ptype), .ALU_dec31_dec_sub8_cr_in(ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in), .ALU_dec31_dec_sub8_cr_out(ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out), .ALU_dec31_dec_sub8_cry_in(ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in), @@ -1467,24 +1568,46 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s .ALU_dec31_dec_sub8_sgn(ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn), .opcode_in(ALU_dec31_dec_sub8_opcode_in) ); + always @* begin + if (\initial ) begin end + ALU_dec31_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0a: + ALU_dec31_in1_sel = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h00: + ALU_dec31_in1_sel = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + ALU_dec31_in1_sel = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in1_sel; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + ALU_dec31_in1_sel = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in1_sel; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h08: + ALU_dec31_in1_sel = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel; + endcase + end always @* begin if (\initial ) begin end ALU_dec31_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: ALU_dec31_in2_sel = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_in2_sel = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: ALU_dec31_in2_sel = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_in2_sel = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_in2_sel = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel; endcase @@ -1492,21 +1615,21 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s always @* begin if (\initial ) begin end ALU_dec31_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: ALU_dec31_cr_in = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_cr_in = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: ALU_dec31_cr_in = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_cr_in = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_cr_in = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in; endcase @@ -1514,21 +1637,21 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s always @* begin if (\initial ) begin end ALU_dec31_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: ALU_dec31_cr_out = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_cr_out = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: ALU_dec31_cr_out = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_cr_out = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_cr_out = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out; endcase @@ -1536,21 +1659,21 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s always @* begin if (\initial ) begin end ALU_dec31_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: ALU_dec31_ldst_len = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_ldst_len = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: ALU_dec31_ldst_len = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_ldst_len = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_ldst_len = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len; endcase @@ -1558,21 +1681,21 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s always @* begin if (\initial ) begin end ALU_dec31_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: ALU_dec31_rc_sel = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_rc_sel = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: ALU_dec31_rc_sel = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_rc_sel = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_rc_sel = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel; endcase @@ -1580,21 +1703,21 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s always @* begin if (\initial ) begin end ALU_dec31_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: ALU_dec31_cry_in = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_cry_in = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: ALU_dec31_cry_in = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_cry_in = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_cry_in = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in; endcase @@ -1602,21 +1725,21 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s always @* begin if (\initial ) begin end ALU_dec31_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: ALU_dec31_inv_a = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_inv_a = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: ALU_dec31_inv_a = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_inv_a = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_inv_a = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a; endcase @@ -1624,21 +1747,21 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s always @* begin if (\initial ) begin end ALU_dec31_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: ALU_dec31_inv_out = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_inv_out = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: ALU_dec31_inv_out = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_inv_out = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_inv_out = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out; endcase @@ -1646,21 +1769,21 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s always @* begin if (\initial ) begin end ALU_dec31_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: ALU_dec31_cry_out = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_cry_out = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: ALU_dec31_cry_out = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_cry_out = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_cry_out = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out; endcase @@ -1668,21 +1791,21 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s always @* begin if (\initial ) begin end ALU_dec31_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: ALU_dec31_is_32b = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_is_32b = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: ALU_dec31_is_32b = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_is_32b = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_is_32b = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b; endcase @@ -1690,43 +1813,43 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s always @* begin if (\initial ) begin end ALU_dec31_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: ALU_dec31_sgn = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_sgn = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: ALU_dec31_sgn = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_sgn = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_sgn = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn; endcase end always @* begin if (\initial ) begin end - ALU_dec31_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + ALU_dec31_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: ALU_dec31_function_unit = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_function_unit = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: ALU_dec31_function_unit = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_function_unit = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_function_unit = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit; endcase @@ -1734,45 +1857,45 @@ module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_s always @* begin if (\initial ) begin end ALU_dec31_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: ALU_dec31_internal_op = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_internal_op = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: ALU_dec31_internal_op = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_internal_op = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_internal_op = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op; endcase end always @* begin if (\initial ) begin end - ALU_dec31_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + ALU_dec31_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: - ALU_dec31_in1_sel = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_SV_Ptype = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - ALU_dec31_in1_sel = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_SV_Ptype = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: - ALU_dec31_in1_sel = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_SV_Ptype = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: - ALU_dec31_in1_sel = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_SV_Ptype = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: - ALU_dec31_in1_sel = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel; + ALU_dec31_SV_Ptype = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_SV_Ptype; endcase end assign ALU_dec31_dec_sub8_opcode_in = opcode_in; @@ -1786,8 +1909,15 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub0" *) (* generator = "nMigen" *) -module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_internal_op, ALU_dec31_dec_sub0_in1_sel, ALU_dec31_dec_sub0_in2_sel, ALU_dec31_dec_sub0_cr_in, ALU_dec31_dec_sub0_cr_out, ALU_dec31_dec_sub0_ldst_len, ALU_dec31_dec_sub0_rc_sel, ALU_dec31_dec_sub0_cry_in, ALU_dec31_dec_sub0_inv_a, ALU_dec31_dec_sub0_inv_out, ALU_dec31_dec_sub0_cry_out, ALU_dec31_dec_sub0_is_32b, ALU_dec31_dec_sub0_sgn, opcode_in); +module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_internal_op, ALU_dec31_dec_sub0_SV_Ptype, ALU_dec31_dec_sub0_in1_sel, ALU_dec31_dec_sub0_in2_sel, ALU_dec31_dec_sub0_cr_in, ALU_dec31_dec_sub0_cr_out, ALU_dec31_dec_sub0_ldst_len, ALU_dec31_dec_sub0_rc_sel, ALU_dec31_dec_sub0_cry_in, ALU_dec31_dec_sub0_inv_a, ALU_dec31_dec_sub0_inv_out, ALU_dec31_dec_sub0_cry_out, ALU_dec31_dec_sub0_is_32b, ALU_dec31_dec_sub0_sgn, opcode_in); reg \initial = 0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] ALU_dec31_dec_sub0_SV_Ptype; + reg [1:0] ALU_dec31_dec_sub0_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -1797,7 +1927,7 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_dec_sub0_cr_in; reg [2:0] ALU_dec31_dec_sub0_cr_in; (* enum_base_type = "CROutSel" *) @@ -1807,44 +1937,47 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_dec_sub0_cr_out; reg [2:0] ALU_dec31_dec_sub0_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] ALU_dec31_dec_sub0_cry_in; reg [1:0] ALU_dec31_dec_sub0_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub0_cry_out; reg ALU_dec31_dec_sub0_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] ALU_dec31_dec_sub0_function_unit; - reg [13:0] ALU_dec31_dec_sub0_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] ALU_dec31_dec_sub0_function_unit; + reg [14:0] ALU_dec31_dec_sub0_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_dec_sub0_in1_sel; reg [2:0] ALU_dec31_dec_sub0_in1_sel; (* enum_base_type = "In2Sel" *) @@ -1862,7 +1995,8 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] ALU_dec31_dec_sub0_in2_sel; reg [3:0] ALU_dec31_dec_sub0_in2_sel; (* enum_base_type = "MicrOp" *) @@ -1940,16 +2074,18 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] ALU_dec31_dec_sub0_internal_op; reg [6:0] ALU_dec31_dec_sub0_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub0_inv_a; reg ALU_dec31_dec_sub0_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub0_inv_out; reg ALU_dec31_dec_sub0_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub0_is_32b; reg ALU_dec31_dec_sub0_is_32b; (* enum_base_type = "LdstLen" *) @@ -1958,51 +2094,67 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] ALU_dec31_dec_sub0_ldst_len; reg [3:0] ALU_dec31_dec_sub0_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] ALU_dec31_dec_sub0_rc_sel; reg [1:0] ALU_dec31_dec_sub0_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub0_sgn; reg ALU_dec31_dec_sub0_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - ALU_dec31_dec_sub0_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + ALU_dec31_dec_sub0_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - ALU_dec31_dec_sub0_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_dec_sub0_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - ALU_dec31_dec_sub0_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_dec_sub0_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: - ALU_dec31_dec_sub0_function_unit = 14'h0002; + ALU_dec31_dec_sub0_function_unit = 15'h0002; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub0_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h00: + ALU_dec31_dec_sub0_cry_in = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h07: + ALU_dec31_dec_sub0_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h01: + ALU_dec31_dec_sub0_cry_in = 2'h1; endcase end always @* begin if (\initial ) begin end ALU_dec31_dec_sub0_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub0_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub0_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub0_inv_a = 1'h1; endcase @@ -2010,15 +2162,15 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub0_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub0_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub0_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub0_inv_out = 1'h0; endcase @@ -2026,15 +2178,15 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub0_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub0_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub0_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub0_cry_out = 1'h0; endcase @@ -2042,15 +2194,15 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub0_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub0_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub0_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub0_is_32b = 1'h0; endcase @@ -2058,15 +2210,15 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub0_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub0_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub0_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub0_sgn = 1'h0; endcase @@ -2074,31 +2226,47 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub0_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub0_internal_op = 7'h0a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub0_internal_op = 7'h0c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub0_internal_op = 7'h0a; endcase end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub0_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h00: + ALU_dec31_dec_sub0_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h07: + ALU_dec31_dec_sub0_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h01: + ALU_dec31_dec_sub0_SV_Ptype = 2'h1; + endcase + end always @* begin if (\initial ) begin end ALU_dec31_dec_sub0_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub0_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub0_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub0_in1_sel = 3'h1; endcase @@ -2106,15 +2274,15 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub0_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub0_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub0_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub0_in2_sel = 4'h1; endcase @@ -2122,15 +2290,15 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub0_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub0_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub0_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub0_cr_in = 3'h0; endcase @@ -2138,15 +2306,15 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub0_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub0_cr_out = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub0_cr_out = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub0_cr_out = 3'h2; endcase @@ -2154,15 +2322,15 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub0_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub0_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub0_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub0_ldst_len = 4'h0; endcase @@ -2170,42 +2338,33 @@ module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub0_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub0_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub0_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub0_rc_sel = 2'h0; endcase end - always @* begin - if (\initial ) begin end - ALU_dec31_dec_sub0_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) - casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h00: - ALU_dec31_dec_sub0_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h07: - ALU_dec31_dec_sub0_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h01: - ALU_dec31_dec_sub0_cry_in = 2'h1; - endcase - end assign opcode_switch = opcode_in[10:6]; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub10" *) (* generator = "nMigen" *) -module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub10_internal_op, ALU_dec31_dec_sub10_in1_sel, ALU_dec31_dec_sub10_in2_sel, ALU_dec31_dec_sub10_cr_in, ALU_dec31_dec_sub10_cr_out, ALU_dec31_dec_sub10_ldst_len, ALU_dec31_dec_sub10_rc_sel, ALU_dec31_dec_sub10_cry_in, ALU_dec31_dec_sub10_inv_a, ALU_dec31_dec_sub10_inv_out, ALU_dec31_dec_sub10_cry_out, ALU_dec31_dec_sub10_is_32b, ALU_dec31_dec_sub10_sgn, opcode_in); +module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub10_internal_op, ALU_dec31_dec_sub10_SV_Ptype, ALU_dec31_dec_sub10_in1_sel, ALU_dec31_dec_sub10_in2_sel, ALU_dec31_dec_sub10_cr_in, ALU_dec31_dec_sub10_cr_out, ALU_dec31_dec_sub10_ldst_len, ALU_dec31_dec_sub10_rc_sel, ALU_dec31_dec_sub10_cry_in, ALU_dec31_dec_sub10_inv_a, ALU_dec31_dec_sub10_inv_out, ALU_dec31_dec_sub10_cry_out, ALU_dec31_dec_sub10_is_32b, ALU_dec31_dec_sub10_sgn, opcode_in); reg \initial = 0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] ALU_dec31_dec_sub10_SV_Ptype; + reg [1:0] ALU_dec31_dec_sub10_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -2215,7 +2374,7 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_dec_sub10_cr_in; reg [2:0] ALU_dec31_dec_sub10_cr_in; (* enum_base_type = "CROutSel" *) @@ -2225,44 +2384,47 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_dec_sub10_cr_out; reg [2:0] ALU_dec31_dec_sub10_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] ALU_dec31_dec_sub10_cry_in; reg [1:0] ALU_dec31_dec_sub10_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub10_cry_out; reg ALU_dec31_dec_sub10_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] ALU_dec31_dec_sub10_function_unit; - reg [13:0] ALU_dec31_dec_sub10_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] ALU_dec31_dec_sub10_function_unit; + reg [14:0] ALU_dec31_dec_sub10_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_dec_sub10_in1_sel; reg [2:0] ALU_dec31_dec_sub10_in1_sel; (* enum_base_type = "In2Sel" *) @@ -2280,7 +2442,8 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] ALU_dec31_dec_sub10_in2_sel; reg [3:0] ALU_dec31_dec_sub10_in2_sel; (* enum_base_type = "MicrOp" *) @@ -2358,16 +2521,18 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] ALU_dec31_dec_sub10_internal_op; reg [6:0] ALU_dec31_dec_sub10_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub10_inv_a; reg ALU_dec31_dec_sub10_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub10_inv_out; reg ALU_dec31_dec_sub10_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub10_is_32b; reg ALU_dec31_dec_sub10_is_32b; (* enum_base_type = "LdstLen" *) @@ -2376,93 +2541,130 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] ALU_dec31_dec_sub10_ldst_len; reg [3:0] ALU_dec31_dec_sub10_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] ALU_dec31_dec_sub10_rc_sel; reg [1:0] ALU_dec31_dec_sub10_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub10_sgn; reg ALU_dec31_dec_sub10_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - ALU_dec31_dec_sub10_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + ALU_dec31_dec_sub10_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: - ALU_dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_dec_sub10_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - ALU_dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_dec_sub10_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - ALU_dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_dec_sub10_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - ALU_dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_dec_sub10_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - ALU_dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_dec_sub10_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: - ALU_dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_dec_sub10_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - ALU_dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_dec_sub10_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: - ALU_dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_dec_sub10_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: - ALU_dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_dec_sub10_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: - ALU_dec31_dec_sub10_function_unit = 14'h0002; + ALU_dec31_dec_sub10_function_unit = 15'h0002; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub10_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h08: + ALU_dec31_dec_sub10_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h18: + ALU_dec31_dec_sub10_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h00: + ALU_dec31_dec_sub10_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + ALU_dec31_dec_sub10_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h04: + ALU_dec31_dec_sub10_cry_in = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + ALU_dec31_dec_sub10_cry_in = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h07: + ALU_dec31_dec_sub10_cry_in = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + ALU_dec31_dec_sub10_cry_in = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h06: + ALU_dec31_dec_sub10_cry_in = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + ALU_dec31_dec_sub10_cry_in = 2'h2; endcase end always @* begin if (\initial ) begin end ALU_dec31_dec_sub10_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: ALU_dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: ALU_dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: ALU_dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: ALU_dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: ALU_dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: ALU_dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_dec_sub10_inv_a = 1'h0; endcase @@ -2470,36 +2672,36 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 always @* begin if (\initial ) begin end ALU_dec31_dec_sub10_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: ALU_dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: ALU_dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: ALU_dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: ALU_dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: ALU_dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: ALU_dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_dec_sub10_inv_out = 1'h0; endcase @@ -2507,36 +2709,36 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 always @* begin if (\initial ) begin end ALU_dec31_dec_sub10_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_dec_sub10_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: ALU_dec31_dec_sub10_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub10_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: ALU_dec31_dec_sub10_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: ALU_dec31_dec_sub10_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: ALU_dec31_dec_sub10_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub10_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: ALU_dec31_dec_sub10_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: ALU_dec31_dec_sub10_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_dec_sub10_cry_out = 1'h1; endcase @@ -2544,36 +2746,36 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 always @* begin if (\initial ) begin end ALU_dec31_dec_sub10_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: ALU_dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: ALU_dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: ALU_dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: ALU_dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: ALU_dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: ALU_dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_dec_sub10_is_32b = 1'h0; endcase @@ -2581,36 +2783,36 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 always @* begin if (\initial ) begin end ALU_dec31_dec_sub10_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: ALU_dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: ALU_dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: ALU_dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: ALU_dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: ALU_dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: ALU_dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_dec_sub10_sgn = 1'h0; endcase @@ -2618,73 +2820,110 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 always @* begin if (\initial ) begin end ALU_dec31_dec_sub10_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: ALU_dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: ALU_dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: ALU_dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: ALU_dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: ALU_dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: ALU_dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_dec_sub10_internal_op = 7'h02; endcase end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub10_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h08: + ALU_dec31_dec_sub10_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h18: + ALU_dec31_dec_sub10_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h00: + ALU_dec31_dec_sub10_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + ALU_dec31_dec_sub10_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h04: + ALU_dec31_dec_sub10_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + ALU_dec31_dec_sub10_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h07: + ALU_dec31_dec_sub10_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + ALU_dec31_dec_sub10_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h06: + ALU_dec31_dec_sub10_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + ALU_dec31_dec_sub10_SV_Ptype = 2'h2; + endcase + end always @* begin if (\initial ) begin end ALU_dec31_dec_sub10_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: ALU_dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: ALU_dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: ALU_dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: ALU_dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: ALU_dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: ALU_dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_dec_sub10_in1_sel = 3'h1; endcase @@ -2692,36 +2931,36 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 always @* begin if (\initial ) begin end ALU_dec31_dec_sub10_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_dec_sub10_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: ALU_dec31_dec_sub10_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub10_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: ALU_dec31_dec_sub10_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: ALU_dec31_dec_sub10_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: ALU_dec31_dec_sub10_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub10_in2_sel = 4'h9; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: ALU_dec31_dec_sub10_in2_sel = 4'h9; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: ALU_dec31_dec_sub10_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_dec_sub10_in2_sel = 4'h0; endcase @@ -2729,36 +2968,36 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 always @* begin if (\initial ) begin end ALU_dec31_dec_sub10_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: ALU_dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: ALU_dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: ALU_dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: ALU_dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: ALU_dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: ALU_dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_dec_sub10_cr_in = 3'h0; endcase @@ -2766,36 +3005,36 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 always @* begin if (\initial ) begin end ALU_dec31_dec_sub10_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: ALU_dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: ALU_dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: ALU_dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: ALU_dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: ALU_dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: ALU_dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_dec_sub10_cr_out = 3'h1; endcase @@ -2803,36 +3042,36 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 always @* begin if (\initial ) begin end ALU_dec31_dec_sub10_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: ALU_dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: ALU_dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: ALU_dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: ALU_dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: ALU_dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: ALU_dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_dec_sub10_ldst_len = 4'h0; endcase @@ -2840,84 +3079,54 @@ module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub1 always @* begin if (\initial ) begin end ALU_dec31_dec_sub10_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: ALU_dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: ALU_dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: ALU_dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: ALU_dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: ALU_dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: ALU_dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_dec_sub10_rc_sel = 2'h2; endcase end - always @* begin - if (\initial ) begin end - ALU_dec31_dec_sub10_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) - casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h08: - ALU_dec31_dec_sub10_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h18: - ALU_dec31_dec_sub10_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h00: - ALU_dec31_dec_sub10_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h10: - ALU_dec31_dec_sub10_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h04: - ALU_dec31_dec_sub10_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h14: - ALU_dec31_dec_sub10_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h07: - ALU_dec31_dec_sub10_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h17: - ALU_dec31_dec_sub10_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h06: - ALU_dec31_dec_sub10_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h16: - ALU_dec31_dec_sub10_cry_in = 2'h2; - endcase - end assign opcode_switch = opcode_in[10:6]; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub22" *) (* generator = "nMigen" *) -module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub22_internal_op, ALU_dec31_dec_sub22_in1_sel, ALU_dec31_dec_sub22_in2_sel, ALU_dec31_dec_sub22_cr_in, ALU_dec31_dec_sub22_cr_out, ALU_dec31_dec_sub22_ldst_len, ALU_dec31_dec_sub22_rc_sel, ALU_dec31_dec_sub22_cry_in, ALU_dec31_dec_sub22_inv_a, ALU_dec31_dec_sub22_inv_out, ALU_dec31_dec_sub22_cry_out, ALU_dec31_dec_sub22_is_32b, ALU_dec31_dec_sub22_sgn, opcode_in); +module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub22_internal_op, ALU_dec31_dec_sub22_SV_Ptype, ALU_dec31_dec_sub22_in1_sel, ALU_dec31_dec_sub22_in2_sel, ALU_dec31_dec_sub22_cr_in, ALU_dec31_dec_sub22_cr_out, ALU_dec31_dec_sub22_ldst_len, ALU_dec31_dec_sub22_rc_sel, ALU_dec31_dec_sub22_cry_in, ALU_dec31_dec_sub22_inv_a, ALU_dec31_dec_sub22_inv_out, ALU_dec31_dec_sub22_cry_out, ALU_dec31_dec_sub22_is_32b, ALU_dec31_dec_sub22_sgn, opcode_in); reg \initial = 0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] ALU_dec31_dec_sub22_SV_Ptype; + reg [1:0] ALU_dec31_dec_sub22_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -2927,7 +3136,7 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_dec_sub22_cr_in; reg [2:0] ALU_dec31_dec_sub22_cr_in; (* enum_base_type = "CROutSel" *) @@ -2937,44 +3146,47 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_dec_sub22_cr_out; reg [2:0] ALU_dec31_dec_sub22_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] ALU_dec31_dec_sub22_cry_in; reg [1:0] ALU_dec31_dec_sub22_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub22_cry_out; reg ALU_dec31_dec_sub22_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] ALU_dec31_dec_sub22_function_unit; - reg [13:0] ALU_dec31_dec_sub22_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] ALU_dec31_dec_sub22_function_unit; + reg [14:0] ALU_dec31_dec_sub22_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_dec_sub22_in1_sel; reg [2:0] ALU_dec31_dec_sub22_in1_sel; (* enum_base_type = "In2Sel" *) @@ -2992,7 +3204,8 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] ALU_dec31_dec_sub22_in2_sel; reg [3:0] ALU_dec31_dec_sub22_in2_sel; (* enum_base_type = "MicrOp" *) @@ -3070,16 +3283,18 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] ALU_dec31_dec_sub22_internal_op; reg [6:0] ALU_dec31_dec_sub22_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub22_inv_a; reg ALU_dec31_dec_sub22_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub22_inv_out; reg ALU_dec31_dec_sub22_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub22_is_32b; reg ALU_dec31_dec_sub22_is_32b; (* enum_base_type = "LdstLen" *) @@ -3088,75 +3303,103 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] ALU_dec31_dec_sub22_ldst_len; reg [3:0] ALU_dec31_dec_sub22_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] ALU_dec31_dec_sub22_rc_sel; reg [1:0] ALU_dec31_dec_sub22_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub22_sgn; reg ALU_dec31_dec_sub22_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - ALU_dec31_dec_sub22_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + ALU_dec31_dec_sub22_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: - ALU_dec31_dec_sub22_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_dec_sub22_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: - ALU_dec31_dec_sub22_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_dec_sub22_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: - ALU_dec31_dec_sub22_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_dec_sub22_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - ALU_dec31_dec_sub22_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_dec_sub22_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: - ALU_dec31_dec_sub22_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_dec_sub22_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - ALU_dec31_dec_sub22_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_dec_sub22_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: - ALU_dec31_dec_sub22_function_unit = 14'h0002; + ALU_dec31_dec_sub22_function_unit = 15'h0002; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub22_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h02: + ALU_dec31_dec_sub22_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h01: + ALU_dec31_dec_sub22_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h08: + ALU_dec31_dec_sub22_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h07: + ALU_dec31_dec_sub22_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + ALU_dec31_dec_sub22_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h00: + ALU_dec31_dec_sub22_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + ALU_dec31_dec_sub22_cry_in = 2'h0; endcase end always @* begin if (\initial ) begin end ALU_dec31_dec_sub22_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: ALU_dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: ALU_dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: ALU_dec31_dec_sub22_inv_a = 1'h0; endcase @@ -3164,27 +3407,27 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub22_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: ALU_dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: ALU_dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: ALU_dec31_dec_sub22_inv_out = 1'h0; endcase @@ -3192,27 +3435,27 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub22_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: ALU_dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: ALU_dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: ALU_dec31_dec_sub22_cry_out = 1'h0; endcase @@ -3220,27 +3463,27 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub22_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: ALU_dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: ALU_dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: ALU_dec31_dec_sub22_is_32b = 1'h0; endcase @@ -3248,27 +3491,27 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub22_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: ALU_dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: ALU_dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: ALU_dec31_dec_sub22_sgn = 1'h0; endcase @@ -3276,55 +3519,83 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub22_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: ALU_dec31_dec_sub22_internal_op = 7'h01; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub22_internal_op = 7'h01; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_dec_sub22_internal_op = 7'h01; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub22_internal_op = 7'h01; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: ALU_dec31_dec_sub22_internal_op = 7'h21; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub22_internal_op = 7'h01; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: ALU_dec31_dec_sub22_internal_op = 7'h01; endcase end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub22_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h02: + ALU_dec31_dec_sub22_SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h01: + ALU_dec31_dec_sub22_SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h08: + ALU_dec31_dec_sub22_SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h07: + ALU_dec31_dec_sub22_SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + ALU_dec31_dec_sub22_SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h00: + ALU_dec31_dec_sub22_SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + ALU_dec31_dec_sub22_SV_Ptype = 2'h0; + endcase + end always @* begin if (\initial ) begin end ALU_dec31_dec_sub22_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: ALU_dec31_dec_sub22_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub22_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_dec_sub22_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub22_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: ALU_dec31_dec_sub22_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub22_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: ALU_dec31_dec_sub22_in1_sel = 3'h0; endcase @@ -3332,27 +3603,27 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub22_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: ALU_dec31_dec_sub22_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub22_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_dec_sub22_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub22_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: ALU_dec31_dec_sub22_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub22_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: ALU_dec31_dec_sub22_in2_sel = 4'h0; endcase @@ -3360,27 +3631,27 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub22_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: ALU_dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: ALU_dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: ALU_dec31_dec_sub22_cr_in = 3'h0; endcase @@ -3388,27 +3659,27 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub22_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: ALU_dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: ALU_dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: ALU_dec31_dec_sub22_cr_out = 3'h0; endcase @@ -3416,27 +3687,27 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub22_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: ALU_dec31_dec_sub22_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub22_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_dec_sub22_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub22_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: ALU_dec31_dec_sub22_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub22_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: ALU_dec31_dec_sub22_ldst_len = 4'h0; endcase @@ -3444,66 +3715,45 @@ module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub22_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: ALU_dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: ALU_dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: ALU_dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: ALU_dec31_dec_sub22_rc_sel = 2'h0; endcase end - always @* begin - if (\initial ) begin end - ALU_dec31_dec_sub22_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) - casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h02: - ALU_dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h01: - ALU_dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h08: - ALU_dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h07: - ALU_dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h1e: - ALU_dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h00: - ALU_dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h12: - ALU_dec31_dec_sub22_cry_in = 2'h0; - endcase - end assign opcode_switch = opcode_in[10:6]; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub26" *) (* generator = "nMigen" *) -module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub26_internal_op, ALU_dec31_dec_sub26_in1_sel, ALU_dec31_dec_sub26_in2_sel, ALU_dec31_dec_sub26_cr_in, ALU_dec31_dec_sub26_cr_out, ALU_dec31_dec_sub26_ldst_len, ALU_dec31_dec_sub26_rc_sel, ALU_dec31_dec_sub26_cry_in, ALU_dec31_dec_sub26_inv_a, ALU_dec31_dec_sub26_inv_out, ALU_dec31_dec_sub26_cry_out, ALU_dec31_dec_sub26_is_32b, ALU_dec31_dec_sub26_sgn, opcode_in); +module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub26_internal_op, ALU_dec31_dec_sub26_SV_Ptype, ALU_dec31_dec_sub26_in1_sel, ALU_dec31_dec_sub26_in2_sel, ALU_dec31_dec_sub26_cr_in, ALU_dec31_dec_sub26_cr_out, ALU_dec31_dec_sub26_ldst_len, ALU_dec31_dec_sub26_rc_sel, ALU_dec31_dec_sub26_cry_in, ALU_dec31_dec_sub26_inv_a, ALU_dec31_dec_sub26_inv_out, ALU_dec31_dec_sub26_cry_out, ALU_dec31_dec_sub26_is_32b, ALU_dec31_dec_sub26_sgn, opcode_in); reg \initial = 0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] ALU_dec31_dec_sub26_SV_Ptype; + reg [1:0] ALU_dec31_dec_sub26_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -3513,7 +3763,7 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_dec_sub26_cr_in; reg [2:0] ALU_dec31_dec_sub26_cr_in; (* enum_base_type = "CROutSel" *) @@ -3523,44 +3773,47 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_dec_sub26_cr_out; reg [2:0] ALU_dec31_dec_sub26_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] ALU_dec31_dec_sub26_cry_in; reg [1:0] ALU_dec31_dec_sub26_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub26_cry_out; reg ALU_dec31_dec_sub26_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] ALU_dec31_dec_sub26_function_unit; - reg [13:0] ALU_dec31_dec_sub26_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] ALU_dec31_dec_sub26_function_unit; + reg [14:0] ALU_dec31_dec_sub26_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_dec_sub26_in1_sel; reg [2:0] ALU_dec31_dec_sub26_in1_sel; (* enum_base_type = "In2Sel" *) @@ -3578,7 +3831,8 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] ALU_dec31_dec_sub26_in2_sel; reg [3:0] ALU_dec31_dec_sub26_in2_sel; (* enum_base_type = "MicrOp" *) @@ -3656,16 +3910,18 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] ALU_dec31_dec_sub26_internal_op; reg [6:0] ALU_dec31_dec_sub26_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub26_inv_a; reg ALU_dec31_dec_sub26_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub26_inv_out; reg ALU_dec31_dec_sub26_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub26_is_32b; reg ALU_dec31_dec_sub26_is_32b; (* enum_base_type = "LdstLen" *) @@ -3674,51 +3930,67 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] ALU_dec31_dec_sub26_ldst_len; reg [3:0] ALU_dec31_dec_sub26_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] ALU_dec31_dec_sub26_rc_sel; reg [1:0] ALU_dec31_dec_sub26_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub26_sgn; reg ALU_dec31_dec_sub26_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - ALU_dec31_dec_sub26_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + ALU_dec31_dec_sub26_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1d: + ALU_dec31_dec_sub26_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1c: + ALU_dec31_dec_sub26_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + ALU_dec31_dec_sub26_function_unit = 15'h0002; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub26_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: - ALU_dec31_dec_sub26_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: - ALU_dec31_dec_sub26_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: - ALU_dec31_dec_sub26_function_unit = 14'h0002; + ALU_dec31_dec_sub26_cry_in = 2'h0; endcase end always @* begin if (\initial ) begin end ALU_dec31_dec_sub26_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: ALU_dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: ALU_dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: ALU_dec31_dec_sub26_inv_a = 1'h0; endcase @@ -3726,15 +3998,15 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub26_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: ALU_dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: ALU_dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: ALU_dec31_dec_sub26_inv_out = 1'h0; endcase @@ -3742,15 +4014,15 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub26_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: ALU_dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: ALU_dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: ALU_dec31_dec_sub26_cry_out = 1'h0; endcase @@ -3758,15 +4030,15 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub26_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: ALU_dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: ALU_dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: ALU_dec31_dec_sub26_is_32b = 1'h0; endcase @@ -3774,15 +4046,15 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub26_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: ALU_dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: ALU_dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: ALU_dec31_dec_sub26_sgn = 1'h0; endcase @@ -3790,31 +4062,47 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub26_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: ALU_dec31_dec_sub26_internal_op = 7'h1f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: ALU_dec31_dec_sub26_internal_op = 7'h1f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: ALU_dec31_dec_sub26_internal_op = 7'h1f; endcase end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub26_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1d: + ALU_dec31_dec_sub26_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1c: + ALU_dec31_dec_sub26_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + ALU_dec31_dec_sub26_SV_Ptype = 2'h2; + endcase + end always @* begin if (\initial ) begin end ALU_dec31_dec_sub26_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: ALU_dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: ALU_dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: ALU_dec31_dec_sub26_in1_sel = 3'h4; endcase @@ -3822,15 +4110,15 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub26_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: ALU_dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: ALU_dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: ALU_dec31_dec_sub26_in2_sel = 4'h0; endcase @@ -3838,15 +4126,15 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub26_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: ALU_dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: ALU_dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: ALU_dec31_dec_sub26_cr_in = 3'h0; endcase @@ -3854,15 +4142,15 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub26_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: ALU_dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: ALU_dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: ALU_dec31_dec_sub26_cr_out = 3'h1; endcase @@ -3870,15 +4158,15 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub26_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: ALU_dec31_dec_sub26_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: ALU_dec31_dec_sub26_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: ALU_dec31_dec_sub26_ldst_len = 4'h4; endcase @@ -3886,42 +4174,33 @@ module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub2 always @* begin if (\initial ) begin end ALU_dec31_dec_sub26_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: ALU_dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: ALU_dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: ALU_dec31_dec_sub26_rc_sel = 2'h2; endcase end - always @* begin - if (\initial ) begin end - ALU_dec31_dec_sub26_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) - casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h1d: - ALU_dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h1c: - ALU_dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h1e: - ALU_dec31_dec_sub26_cry_in = 2'h0; - endcase - end assign opcode_switch = opcode_in[10:6]; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub8" *) (* generator = "nMigen" *) -module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_internal_op, ALU_dec31_dec_sub8_in1_sel, ALU_dec31_dec_sub8_in2_sel, ALU_dec31_dec_sub8_cr_in, ALU_dec31_dec_sub8_cr_out, ALU_dec31_dec_sub8_ldst_len, ALU_dec31_dec_sub8_rc_sel, ALU_dec31_dec_sub8_cry_in, ALU_dec31_dec_sub8_inv_a, ALU_dec31_dec_sub8_inv_out, ALU_dec31_dec_sub8_cry_out, ALU_dec31_dec_sub8_is_32b, ALU_dec31_dec_sub8_sgn, opcode_in); +module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_internal_op, ALU_dec31_dec_sub8_SV_Ptype, ALU_dec31_dec_sub8_in1_sel, ALU_dec31_dec_sub8_in2_sel, ALU_dec31_dec_sub8_cr_in, ALU_dec31_dec_sub8_cr_out, ALU_dec31_dec_sub8_ldst_len, ALU_dec31_dec_sub8_rc_sel, ALU_dec31_dec_sub8_cry_in, ALU_dec31_dec_sub8_inv_a, ALU_dec31_dec_sub8_inv_out, ALU_dec31_dec_sub8_cry_out, ALU_dec31_dec_sub8_is_32b, ALU_dec31_dec_sub8_sgn, opcode_in); reg \initial = 0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] ALU_dec31_dec_sub8_SV_Ptype; + reg [1:0] ALU_dec31_dec_sub8_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -3931,7 +4210,7 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_dec_sub8_cr_in; reg [2:0] ALU_dec31_dec_sub8_cr_in; (* enum_base_type = "CROutSel" *) @@ -3941,44 +4220,47 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_dec_sub8_cr_out; reg [2:0] ALU_dec31_dec_sub8_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] ALU_dec31_dec_sub8_cry_in; reg [1:0] ALU_dec31_dec_sub8_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub8_cry_out; reg ALU_dec31_dec_sub8_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] ALU_dec31_dec_sub8_function_unit; - reg [13:0] ALU_dec31_dec_sub8_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] ALU_dec31_dec_sub8_function_unit; + reg [14:0] ALU_dec31_dec_sub8_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_dec31_dec_sub8_in1_sel; reg [2:0] ALU_dec31_dec_sub8_in1_sel; (* enum_base_type = "In2Sel" *) @@ -3996,7 +4278,8 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] ALU_dec31_dec_sub8_in2_sel; reg [3:0] ALU_dec31_dec_sub8_in2_sel; (* enum_base_type = "MicrOp" *) @@ -4074,16 +4357,18 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] ALU_dec31_dec_sub8_internal_op; reg [6:0] ALU_dec31_dec_sub8_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub8_inv_a; reg ALU_dec31_dec_sub8_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub8_inv_out; reg ALU_dec31_dec_sub8_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub8_is_32b; reg ALU_dec31_dec_sub8_is_32b; (* enum_base_type = "LdstLen" *) @@ -4092,105 +4377,148 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] ALU_dec31_dec_sub8_ldst_len; reg [3:0] ALU_dec31_dec_sub8_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] ALU_dec31_dec_sub8_rc_sel; reg [1:0] ALU_dec31_dec_sub8_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_dec31_dec_sub8_sgn; reg ALU_dec31_dec_sub8_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - ALU_dec31_dec_sub8_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + ALU_dec31_dec_sub8_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: - ALU_dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_dec_sub8_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: - ALU_dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_dec_sub8_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: - ALU_dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_dec_sub8_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: - ALU_dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_dec_sub8_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - ALU_dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_dec_sub8_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - ALU_dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_dec_sub8_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - ALU_dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_dec_sub8_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: - ALU_dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_dec_sub8_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - ALU_dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_dec_sub8_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: - ALU_dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_dec_sub8_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: - ALU_dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_dec31_dec_sub8_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: - ALU_dec31_dec_sub8_function_unit = 14'h0002; + ALU_dec31_dec_sub8_function_unit = 15'h0002; + endcase + end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub8_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h03: + ALU_dec31_dec_sub8_cry_in = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + ALU_dec31_dec_sub8_cry_in = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h01: + ALU_dec31_dec_sub8_cry_in = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + ALU_dec31_dec_sub8_cry_in = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h00: + ALU_dec31_dec_sub8_cry_in = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + ALU_dec31_dec_sub8_cry_in = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h04: + ALU_dec31_dec_sub8_cry_in = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + ALU_dec31_dec_sub8_cry_in = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h07: + ALU_dec31_dec_sub8_cry_in = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + ALU_dec31_dec_sub8_cry_in = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h06: + ALU_dec31_dec_sub8_cry_in = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + ALU_dec31_dec_sub8_cry_in = 2'h2; endcase end always @* begin if (\initial ) begin end ALU_dec31_dec_sub8_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: ALU_dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: ALU_dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: ALU_dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: ALU_dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: ALU_dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: ALU_dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: ALU_dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: ALU_dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_dec_sub8_inv_a = 1'h1; endcase @@ -4198,42 +4526,42 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub8_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: ALU_dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: ALU_dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: ALU_dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: ALU_dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: ALU_dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: ALU_dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: ALU_dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: ALU_dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_dec_sub8_inv_out = 1'h0; endcase @@ -4241,42 +4569,42 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub8_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: ALU_dec31_dec_sub8_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: ALU_dec31_dec_sub8_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub8_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: ALU_dec31_dec_sub8_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub8_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: ALU_dec31_dec_sub8_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: ALU_dec31_dec_sub8_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: ALU_dec31_dec_sub8_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub8_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: ALU_dec31_dec_sub8_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: ALU_dec31_dec_sub8_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_dec_sub8_cry_out = 1'h1; endcase @@ -4284,42 +4612,42 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub8_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: ALU_dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: ALU_dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: ALU_dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: ALU_dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: ALU_dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: ALU_dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: ALU_dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: ALU_dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_dec_sub8_is_32b = 1'h0; endcase @@ -4327,42 +4655,42 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub8_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: ALU_dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: ALU_dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: ALU_dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: ALU_dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: ALU_dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: ALU_dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: ALU_dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: ALU_dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_dec_sub8_sgn = 1'h0; endcase @@ -4370,85 +4698,128 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub8_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: ALU_dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: ALU_dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: ALU_dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: ALU_dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: ALU_dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: ALU_dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: ALU_dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: ALU_dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_dec_sub8_internal_op = 7'h02; endcase end + always @* begin + if (\initial ) begin end + ALU_dec31_dec_sub8_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h03: + ALU_dec31_dec_sub8_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + ALU_dec31_dec_sub8_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h01: + ALU_dec31_dec_sub8_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + ALU_dec31_dec_sub8_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h00: + ALU_dec31_dec_sub8_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + ALU_dec31_dec_sub8_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h04: + ALU_dec31_dec_sub8_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + ALU_dec31_dec_sub8_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h07: + ALU_dec31_dec_sub8_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + ALU_dec31_dec_sub8_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h06: + ALU_dec31_dec_sub8_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + ALU_dec31_dec_sub8_SV_Ptype = 2'h2; + endcase + end always @* begin if (\initial ) begin end ALU_dec31_dec_sub8_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: ALU_dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: ALU_dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: ALU_dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: ALU_dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: ALU_dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: ALU_dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: ALU_dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: ALU_dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_dec_sub8_in1_sel = 3'h1; endcase @@ -4456,42 +4827,42 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub8_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: ALU_dec31_dec_sub8_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: ALU_dec31_dec_sub8_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub8_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: ALU_dec31_dec_sub8_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub8_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: ALU_dec31_dec_sub8_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: ALU_dec31_dec_sub8_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: ALU_dec31_dec_sub8_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub8_in2_sel = 4'h9; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: ALU_dec31_dec_sub8_in2_sel = 4'h9; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: ALU_dec31_dec_sub8_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_dec_sub8_in2_sel = 4'h0; endcase @@ -4499,42 +4870,42 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub8_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: ALU_dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: ALU_dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: ALU_dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: ALU_dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: ALU_dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: ALU_dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: ALU_dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: ALU_dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_dec_sub8_cr_in = 3'h0; endcase @@ -4542,42 +4913,42 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub8_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: ALU_dec31_dec_sub8_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: ALU_dec31_dec_sub8_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: ALU_dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: ALU_dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: ALU_dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: ALU_dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: ALU_dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: ALU_dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_dec_sub8_cr_out = 3'h1; endcase @@ -4585,42 +4956,42 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub8_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: ALU_dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: ALU_dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: ALU_dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: ALU_dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: ALU_dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: ALU_dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: ALU_dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: ALU_dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_dec_sub8_ldst_len = 4'h0; endcase @@ -4628,96 +4999,60 @@ module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_i always @* begin if (\initial ) begin end ALU_dec31_dec_sub8_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: ALU_dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: ALU_dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: ALU_dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: ALU_dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: ALU_dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: ALU_dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: ALU_dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: ALU_dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: ALU_dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: ALU_dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: ALU_dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: ALU_dec31_dec_sub8_rc_sel = 2'h2; endcase end - always @* begin - if (\initial ) begin end - ALU_dec31_dec_sub8_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) - casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h03: - ALU_dec31_dec_sub8_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h13: - ALU_dec31_dec_sub8_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h01: - ALU_dec31_dec_sub8_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h11: - ALU_dec31_dec_sub8_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h00: - ALU_dec31_dec_sub8_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h10: - ALU_dec31_dec_sub8_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h04: - ALU_dec31_dec_sub8_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h14: - ALU_dec31_dec_sub8_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h07: - ALU_dec31_dec_sub8_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h17: - ALU_dec31_dec_sub8_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h06: - ALU_dec31_dec_sub8_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h16: - ALU_dec31_dec_sub8_cry_in = 2'h2; - endcase - end assign opcode_switch = opcode_in[10:6]; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_BRANCH.dec.BRANCH_dec19" *) (* generator = "nMigen" *) -module BRANCH_dec19(BRANCH_dec19_function_unit, BRANCH_dec19_internal_op, BRANCH_dec19_in2_sel, BRANCH_dec19_cr_in, BRANCH_dec19_cr_out, BRANCH_dec19_rc_sel, BRANCH_dec19_is_32b, BRANCH_dec19_lk, opcode_in); +module BRANCH_dec19(BRANCH_dec19_function_unit, BRANCH_dec19_internal_op, BRANCH_dec19_SV_Ptype, BRANCH_dec19_in2_sel, BRANCH_dec19_cr_in, BRANCH_dec19_cr_out, BRANCH_dec19_rc_sel, BRANCH_dec19_is_32b, BRANCH_dec19_lk, opcode_in); reg \initial = 0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] BRANCH_dec19_SV_Ptype; + reg [1:0] BRANCH_dec19_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -4727,7 +5062,7 @@ module BRANCH_dec19(BRANCH_dec19_function_unit, BRANCH_dec19_internal_op, BRANCH (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] BRANCH_dec19_cr_in; reg [2:0] BRANCH_dec19_cr_in; (* enum_base_type = "CROutSel" *) @@ -4737,27 +5072,28 @@ module BRANCH_dec19(BRANCH_dec19_function_unit, BRANCH_dec19_internal_op, BRANCH (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] BRANCH_dec19_cr_out; reg [2:0] BRANCH_dec19_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] BRANCH_dec19_function_unit; - reg [13:0] BRANCH_dec19_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] BRANCH_dec19_function_unit; + reg [14:0] BRANCH_dec19_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -4773,7 +5109,8 @@ module BRANCH_dec19(BRANCH_dec19_function_unit, BRANCH_dec19_internal_op, BRANCH (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] BRANCH_dec19_in2_sel; reg [3:0] BRANCH_dec19_in2_sel; (* enum_base_type = "MicrOp" *) @@ -4851,70 +5188,88 @@ module BRANCH_dec19(BRANCH_dec19_function_unit, BRANCH_dec19_internal_op, BRANCH (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] BRANCH_dec19_internal_op; reg [6:0] BRANCH_dec19_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output BRANCH_dec19_is_32b; reg BRANCH_dec19_is_32b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output BRANCH_dec19_lk; reg BRANCH_dec19_lk; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] BRANCH_dec19_rc_sel; reg [1:0] BRANCH_dec19_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [9:0] opcode_switch; always @* begin if (\initial ) begin end - BRANCH_dec19_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + BRANCH_dec19_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: - BRANCH_dec19_function_unit = 14'h0020; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + BRANCH_dec19_function_unit = 15'h0020; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: - BRANCH_dec19_function_unit = 14'h0020; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + BRANCH_dec19_function_unit = 15'h0020; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: - BRANCH_dec19_function_unit = 14'h0020; + BRANCH_dec19_function_unit = 15'h0020; endcase end always @* begin if (\initial ) begin end BRANCH_dec19_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: BRANCH_dec19_internal_op = 7'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: BRANCH_dec19_internal_op = 7'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: BRANCH_dec19_internal_op = 7'h08; endcase end + always @* begin + if (\initial ) begin end + BRANCH_dec19_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 10'h210: + BRANCH_dec19_SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 10'h010: + BRANCH_dec19_SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 10'h230: + BRANCH_dec19_SV_Ptype = 2'h0; + endcase + end always @* begin if (\initial ) begin end BRANCH_dec19_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: BRANCH_dec19_in2_sel = 4'hc; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: BRANCH_dec19_in2_sel = 4'hc; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: BRANCH_dec19_in2_sel = 4'hc; endcase @@ -4922,15 +5277,15 @@ module BRANCH_dec19(BRANCH_dec19_function_unit, BRANCH_dec19_internal_op, BRANCH always @* begin if (\initial ) begin end BRANCH_dec19_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: BRANCH_dec19_cr_in = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: BRANCH_dec19_cr_in = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: BRANCH_dec19_cr_in = 3'h2; endcase @@ -4938,15 +5293,15 @@ module BRANCH_dec19(BRANCH_dec19_function_unit, BRANCH_dec19_internal_op, BRANCH always @* begin if (\initial ) begin end BRANCH_dec19_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: BRANCH_dec19_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: BRANCH_dec19_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: BRANCH_dec19_cr_out = 3'h0; endcase @@ -4954,15 +5309,15 @@ module BRANCH_dec19(BRANCH_dec19_function_unit, BRANCH_dec19_internal_op, BRANCH always @* begin if (\initial ) begin end BRANCH_dec19_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: BRANCH_dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: BRANCH_dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: BRANCH_dec19_rc_sel = 2'h0; endcase @@ -4970,15 +5325,15 @@ module BRANCH_dec19(BRANCH_dec19_function_unit, BRANCH_dec19_internal_op, BRANCH always @* begin if (\initial ) begin end BRANCH_dec19_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: BRANCH_dec19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: BRANCH_dec19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: BRANCH_dec19_is_32b = 1'h0; endcase @@ -4986,15 +5341,15 @@ module BRANCH_dec19(BRANCH_dec19_function_unit, BRANCH_dec19_internal_op, BRANCH always @* begin if (\initial ) begin end BRANCH_dec19_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: BRANCH_dec19_lk = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: BRANCH_dec19_lk = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: BRANCH_dec19_lk = 1'h1; endcase @@ -5004,8 +5359,15 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_CR.dec.CR_dec19" *) (* generator = "nMigen" *) -module CR_dec19(CR_dec19_function_unit, CR_dec19_internal_op, CR_dec19_cr_in, CR_dec19_cr_out, CR_dec19_rc_sel, opcode_in); +module CR_dec19(CR_dec19_function_unit, CR_dec19_internal_op, CR_dec19_SV_Ptype, CR_dec19_cr_in, CR_dec19_cr_out, CR_dec19_rc_sel, opcode_in); reg \initial = 0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] CR_dec19_SV_Ptype; + reg [1:0] CR_dec19_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -5015,7 +5377,7 @@ module CR_dec19(CR_dec19_function_unit, CR_dec19_internal_op, CR_dec19_cr_in, CR (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] CR_dec19_cr_in; reg [2:0] CR_dec19_cr_in; (* enum_base_type = "CROutSel" *) @@ -5025,27 +5387,28 @@ module CR_dec19(CR_dec19_function_unit, CR_dec19_internal_op, CR_dec19_cr_in, CR (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] CR_dec19_cr_out; reg [2:0] CR_dec19_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] CR_dec19_function_unit; - reg [13:0] CR_dec19_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] CR_dec19_function_unit; + reg [14:0] CR_dec19_function_unit; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -5121,118 +5484,154 @@ module CR_dec19(CR_dec19_function_unit, CR_dec19_internal_op, CR_dec19_cr_in, CR (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] CR_dec19_internal_op; reg [6:0] CR_dec19_internal_op; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] CR_dec19_rc_sel; reg [1:0] CR_dec19_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [9:0] opcode_switch; always @* begin if (\initial ) begin end - CR_dec19_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + CR_dec19_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: - CR_dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec19_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: - CR_dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec19_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: - CR_dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec19_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: - CR_dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec19_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: - CR_dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec19_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: - CR_dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec19_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: - CR_dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec19_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: - CR_dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec19_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: - CR_dec19_function_unit = 14'h0040; + CR_dec19_function_unit = 15'h0040; endcase end always @* begin if (\initial ) begin end CR_dec19_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: CR_dec19_internal_op = 7'h2a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: CR_dec19_internal_op = 7'h45; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: CR_dec19_internal_op = 7'h45; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: CR_dec19_internal_op = 7'h45; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: CR_dec19_internal_op = 7'h45; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: CR_dec19_internal_op = 7'h45; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: CR_dec19_internal_op = 7'h45; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: CR_dec19_internal_op = 7'h45; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: CR_dec19_internal_op = 7'h45; endcase end + always @* begin + if (\initial ) begin end + CR_dec19_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 10'h000: + CR_dec19_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 10'h101: + CR_dec19_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 10'h081: + CR_dec19_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 10'h121: + CR_dec19_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 10'h0e1: + CR_dec19_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 10'h021: + CR_dec19_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 10'h1c1: + CR_dec19_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 10'h1a1: + CR_dec19_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 10'h0c1: + CR_dec19_SV_Ptype = 2'h1; + endcase + end always @* begin if (\initial ) begin end CR_dec19_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: CR_dec19_cr_in = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: CR_dec19_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: CR_dec19_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: CR_dec19_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: CR_dec19_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: CR_dec19_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: CR_dec19_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: CR_dec19_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: CR_dec19_cr_in = 3'h4; endcase @@ -5240,33 +5639,33 @@ module CR_dec19(CR_dec19_function_unit, CR_dec19_internal_op, CR_dec19_cr_in, CR always @* begin if (\initial ) begin end CR_dec19_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: CR_dec19_cr_out = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: CR_dec19_cr_out = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: CR_dec19_cr_out = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: CR_dec19_cr_out = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: CR_dec19_cr_out = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: CR_dec19_cr_out = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: CR_dec19_cr_out = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: CR_dec19_cr_out = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: CR_dec19_cr_out = 3'h3; endcase @@ -5274,33 +5673,33 @@ module CR_dec19(CR_dec19_function_unit, CR_dec19_internal_op, CR_dec19_cr_in, CR always @* begin if (\initial ) begin end CR_dec19_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: CR_dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: CR_dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: CR_dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: CR_dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: CR_dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: CR_dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: CR_dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: CR_dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: CR_dec19_rc_sel = 2'h0; endcase @@ -5310,8 +5709,15 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_CR.dec.CR_dec31" *) (* generator = "nMigen" *) -module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR_dec31_cr_out, CR_dec31_rc_sel, opcode_in); +module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_SV_Ptype, CR_dec31_cr_in, CR_dec31_cr_out, CR_dec31_rc_sel, opcode_in); reg \initial = 0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] CR_dec31_SV_Ptype; + reg [1:0] CR_dec31_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -5321,7 +5727,7 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] CR_dec31_cr_in; reg [2:0] CR_dec31_cr_in; (* enum_base_type = "CROutSel" *) @@ -5331,9 +5737,15 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] CR_dec31_cr_out; reg [2:0] CR_dec31_cr_out; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] CR_dec31_dec_sub0_CR_dec31_dec_sub0_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -5343,7 +5755,7 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -5352,25 +5764,26 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -5446,16 +5859,24 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] CR_dec31_dec_sub0_opcode_in; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] CR_dec31_dec_sub15_CR_dec31_dec_sub15_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -5465,7 +5886,7 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -5474,25 +5895,26 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -5568,16 +5990,24 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] CR_dec31_dec_sub15_opcode_in; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] CR_dec31_dec_sub16_CR_dec31_dec_sub16_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -5587,7 +6017,7 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -5596,25 +6026,26 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -5690,16 +6121,24 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] CR_dec31_dec_sub16_opcode_in; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] CR_dec31_dec_sub19_CR_dec31_dec_sub19_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -5709,7 +6148,7 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -5718,25 +6157,26 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -5812,34 +6252,37 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] CR_dec31_dec_sub19_opcode_in; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] CR_dec31_function_unit; - reg [13:0] CR_dec31_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] CR_dec31_function_unit; + reg [14:0] CR_dec31_function_unit; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -5915,23 +6358,26 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] CR_dec31_internal_op; reg [6:0] CR_dec31_internal_op; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] CR_dec31_rc_sel; reg [1:0] CR_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:355" *) wire [4:0] opc_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [9:0] opcode_switch; CR_dec31_dec_sub0 CR_dec31_dec_sub0 ( + .CR_dec31_dec_sub0_SV_Ptype(CR_dec31_dec_sub0_CR_dec31_dec_sub0_SV_Ptype), .CR_dec31_dec_sub0_cr_in(CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in), .CR_dec31_dec_sub0_cr_out(CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out), .CR_dec31_dec_sub0_function_unit(CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit), @@ -5940,6 +6386,7 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR .opcode_in(CR_dec31_dec_sub0_opcode_in) ); CR_dec31_dec_sub15 CR_dec31_dec_sub15 ( + .CR_dec31_dec_sub15_SV_Ptype(CR_dec31_dec_sub15_CR_dec31_dec_sub15_SV_Ptype), .CR_dec31_dec_sub15_cr_in(CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in), .CR_dec31_dec_sub15_cr_out(CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out), .CR_dec31_dec_sub15_function_unit(CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit), @@ -5948,6 +6395,7 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR .opcode_in(CR_dec31_dec_sub15_opcode_in) ); CR_dec31_dec_sub16 CR_dec31_dec_sub16 ( + .CR_dec31_dec_sub16_SV_Ptype(CR_dec31_dec_sub16_CR_dec31_dec_sub16_SV_Ptype), .CR_dec31_dec_sub16_cr_in(CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in), .CR_dec31_dec_sub16_cr_out(CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out), .CR_dec31_dec_sub16_function_unit(CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit), @@ -5956,6 +6404,7 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR .opcode_in(CR_dec31_dec_sub16_opcode_in) ); CR_dec31_dec_sub19 CR_dec31_dec_sub19 ( + .CR_dec31_dec_sub19_SV_Ptype(CR_dec31_dec_sub19_CR_dec31_dec_sub19_SV_Ptype), .CR_dec31_dec_sub19_cr_in(CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in), .CR_dec31_dec_sub19_cr_out(CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out), .CR_dec31_dec_sub19_function_unit(CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit), @@ -5963,40 +6412,59 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR .CR_dec31_dec_sub19_rc_sel(CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel), .opcode_in(CR_dec31_dec_sub19_opcode_in) ); + always @* begin + if (\initial ) begin end + CR_dec31_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h00: + CR_dec31_cr_out = CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + CR_dec31_cr_out = CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0f: + CR_dec31_cr_out = CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + CR_dec31_cr_out = CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out; + endcase + end always @* begin if (\initial ) begin end CR_dec31_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: CR_dec31_rc_sel = CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: CR_dec31_rc_sel = CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: CR_dec31_rc_sel = CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: CR_dec31_rc_sel = CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel; endcase end always @* begin if (\initial ) begin end - CR_dec31_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + CR_dec31_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: CR_dec31_function_unit = CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: CR_dec31_function_unit = CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: CR_dec31_function_unit = CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: CR_dec31_function_unit = CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit; endcase @@ -6004,58 +6472,58 @@ module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR always @* begin if (\initial ) begin end CR_dec31_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: CR_dec31_internal_op = CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: CR_dec31_internal_op = CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: CR_dec31_internal_op = CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: CR_dec31_internal_op = CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op; endcase end always @* begin if (\initial ) begin end - CR_dec31_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + CR_dec31_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - CR_dec31_cr_in = CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_SV_Ptype = CR_dec31_dec_sub0_CR_dec31_dec_sub0_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: - CR_dec31_cr_in = CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_SV_Ptype = CR_dec31_dec_sub19_CR_dec31_dec_sub19_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: - CR_dec31_cr_in = CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_SV_Ptype = CR_dec31_dec_sub15_CR_dec31_dec_sub15_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - CR_dec31_cr_in = CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in; + CR_dec31_SV_Ptype = CR_dec31_dec_sub16_CR_dec31_dec_sub16_SV_Ptype; endcase end always @* begin if (\initial ) begin end - CR_dec31_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + CR_dec31_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - CR_dec31_cr_out = CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_cr_in = CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: - CR_dec31_cr_out = CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_cr_in = CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: - CR_dec31_cr_out = CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_cr_in = CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - CR_dec31_cr_out = CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out; + CR_dec31_cr_in = CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in; endcase end assign CR_dec31_dec_sub16_opcode_in = opcode_in; @@ -6068,8 +6536,15 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub0" *) (* generator = "nMigen" *) -module CR_dec31_dec_sub0(CR_dec31_dec_sub0_function_unit, CR_dec31_dec_sub0_internal_op, CR_dec31_dec_sub0_cr_in, CR_dec31_dec_sub0_cr_out, CR_dec31_dec_sub0_rc_sel, opcode_in); +module CR_dec31_dec_sub0(CR_dec31_dec_sub0_function_unit, CR_dec31_dec_sub0_internal_op, CR_dec31_dec_sub0_SV_Ptype, CR_dec31_dec_sub0_cr_in, CR_dec31_dec_sub0_cr_out, CR_dec31_dec_sub0_rc_sel, opcode_in); reg \initial = 0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] CR_dec31_dec_sub0_SV_Ptype; + reg [1:0] CR_dec31_dec_sub0_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -6079,7 +6554,7 @@ module CR_dec31_dec_sub0(CR_dec31_dec_sub0_function_unit, CR_dec31_dec_sub0_inte (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] CR_dec31_dec_sub0_cr_in; reg [2:0] CR_dec31_dec_sub0_cr_in; (* enum_base_type = "CROutSel" *) @@ -6089,27 +6564,28 @@ module CR_dec31_dec_sub0(CR_dec31_dec_sub0_function_unit, CR_dec31_dec_sub0_inte (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] CR_dec31_dec_sub0_cr_out; reg [2:0] CR_dec31_dec_sub0_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] CR_dec31_dec_sub0_function_unit; - reg [13:0] CR_dec31_dec_sub0_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] CR_dec31_dec_sub0_function_unit; + reg [14:0] CR_dec31_dec_sub0_function_unit; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -6185,46 +6661,58 @@ module CR_dec31_dec_sub0(CR_dec31_dec_sub0_function_unit, CR_dec31_dec_sub0_inte (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] CR_dec31_dec_sub0_internal_op; reg [6:0] CR_dec31_dec_sub0_internal_op; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] CR_dec31_dec_sub0_rc_sel; reg [1:0] CR_dec31_dec_sub0_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - CR_dec31_dec_sub0_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + CR_dec31_dec_sub0_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - CR_dec31_dec_sub0_function_unit = 14'h0040; + CR_dec31_dec_sub0_function_unit = 15'h0040; endcase end always @* begin if (\initial ) begin end CR_dec31_dec_sub0_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: CR_dec31_dec_sub0_internal_op = 7'h3b; endcase end + always @* begin + if (\initial ) begin end + CR_dec31_dec_sub0_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h04: + CR_dec31_dec_sub0_SV_Ptype = 2'h2; + endcase + end always @* begin if (\initial ) begin end CR_dec31_dec_sub0_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: CR_dec31_dec_sub0_cr_in = 3'h3; endcase @@ -6232,9 +6720,9 @@ module CR_dec31_dec_sub0(CR_dec31_dec_sub0_function_unit, CR_dec31_dec_sub0_inte always @* begin if (\initial ) begin end CR_dec31_dec_sub0_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: CR_dec31_dec_sub0_cr_out = 3'h0; endcase @@ -6242,9 +6730,9 @@ module CR_dec31_dec_sub0(CR_dec31_dec_sub0_function_unit, CR_dec31_dec_sub0_inte always @* begin if (\initial ) begin end CR_dec31_dec_sub0_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: CR_dec31_dec_sub0_rc_sel = 2'h0; endcase @@ -6254,8 +6742,15 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub15" *) (* generator = "nMigen" *) -module CR_dec31_dec_sub15(CR_dec31_dec_sub15_function_unit, CR_dec31_dec_sub15_internal_op, CR_dec31_dec_sub15_cr_in, CR_dec31_dec_sub15_cr_out, CR_dec31_dec_sub15_rc_sel, opcode_in); +module CR_dec31_dec_sub15(CR_dec31_dec_sub15_function_unit, CR_dec31_dec_sub15_internal_op, CR_dec31_dec_sub15_SV_Ptype, CR_dec31_dec_sub15_cr_in, CR_dec31_dec_sub15_cr_out, CR_dec31_dec_sub15_rc_sel, opcode_in); reg \initial = 0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] CR_dec31_dec_sub15_SV_Ptype; + reg [1:0] CR_dec31_dec_sub15_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -6265,7 +6760,7 @@ module CR_dec31_dec_sub15(CR_dec31_dec_sub15_function_unit, CR_dec31_dec_sub15_i (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] CR_dec31_dec_sub15_cr_in; reg [2:0] CR_dec31_dec_sub15_cr_in; (* enum_base_type = "CROutSel" *) @@ -6275,27 +6770,28 @@ module CR_dec31_dec_sub15(CR_dec31_dec_sub15_function_unit, CR_dec31_dec_sub15_i (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] CR_dec31_dec_sub15_cr_out; reg [2:0] CR_dec31_dec_sub15_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] CR_dec31_dec_sub15_function_unit; - reg [13:0] CR_dec31_dec_sub15_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] CR_dec31_dec_sub15_function_unit; + reg [14:0] CR_dec31_dec_sub15_function_unit; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -6371,222 +6867,224 @@ module CR_dec31_dec_sub15(CR_dec31_dec_sub15_function_unit, CR_dec31_dec_sub15_i (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] CR_dec31_dec_sub15_internal_op; reg [6:0] CR_dec31_dec_sub15_internal_op; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] CR_dec31_dec_sub15_rc_sel; reg [1:0] CR_dec31_dec_sub15_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: - CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: - CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: - CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: - CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: - CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: - CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: - CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: - CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: - CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: - CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: - CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: - CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: - CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: - CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: - CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: - CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: - CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: - CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: - CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: - CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: - CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: - CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: - CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: - CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: - CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: - CR_dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + CR_dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: - CR_dec31_dec_sub15_function_unit = 14'h0040; + CR_dec31_dec_sub15_function_unit = 15'h0040; endcase end always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: CR_dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: CR_dec31_dec_sub15_internal_op = 7'h23; endcase @@ -6594,102 +7092,205 @@ module CR_dec31_dec_sub15(CR_dec31_dec_sub15_function_unit, CR_dec31_dec_sub15_i always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h00: + CR_dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h01: + CR_dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h02: + CR_dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h03: + CR_dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h04: + CR_dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h05: + CR_dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h06: + CR_dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h07: + CR_dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h08: + CR_dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h09: + CR_dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0a: + CR_dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0b: + CR_dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0c: + CR_dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0d: + CR_dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0e: + CR_dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0f: + CR_dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + CR_dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + CR_dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + CR_dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + CR_dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + CR_dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + CR_dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + CR_dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + CR_dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h18: + CR_dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h19: + CR_dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + CR_dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + CR_dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1c: + CR_dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1d: + CR_dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + CR_dec31_dec_sub15_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1f: + CR_dec31_dec_sub15_SV_Ptype = 2'h1; + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: CR_dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: CR_dec31_dec_sub15_cr_in = 3'h5; endcase @@ -6697,102 +7298,102 @@ module CR_dec31_dec_sub15(CR_dec31_dec_sub15_function_unit, CR_dec31_dec_sub15_i always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: CR_dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: CR_dec31_dec_sub15_cr_out = 3'h0; endcase @@ -6800,102 +7401,102 @@ module CR_dec31_dec_sub15(CR_dec31_dec_sub15_function_unit, CR_dec31_dec_sub15_i always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: CR_dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: CR_dec31_dec_sub15_rc_sel = 2'h0; endcase @@ -6905,8 +7506,15 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub16" *) (* generator = "nMigen" *) -module CR_dec31_dec_sub16(CR_dec31_dec_sub16_function_unit, CR_dec31_dec_sub16_internal_op, CR_dec31_dec_sub16_cr_in, CR_dec31_dec_sub16_cr_out, CR_dec31_dec_sub16_rc_sel, opcode_in); +module CR_dec31_dec_sub16(CR_dec31_dec_sub16_function_unit, CR_dec31_dec_sub16_internal_op, CR_dec31_dec_sub16_SV_Ptype, CR_dec31_dec_sub16_cr_in, CR_dec31_dec_sub16_cr_out, CR_dec31_dec_sub16_rc_sel, opcode_in); reg \initial = 0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] CR_dec31_dec_sub16_SV_Ptype; + reg [1:0] CR_dec31_dec_sub16_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -6916,7 +7524,7 @@ module CR_dec31_dec_sub16(CR_dec31_dec_sub16_function_unit, CR_dec31_dec_sub16_i (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] CR_dec31_dec_sub16_cr_in; reg [2:0] CR_dec31_dec_sub16_cr_in; (* enum_base_type = "CROutSel" *) @@ -6926,27 +7534,28 @@ module CR_dec31_dec_sub16(CR_dec31_dec_sub16_function_unit, CR_dec31_dec_sub16_i (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] CR_dec31_dec_sub16_cr_out; reg [2:0] CR_dec31_dec_sub16_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] CR_dec31_dec_sub16_function_unit; - reg [13:0] CR_dec31_dec_sub16_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] CR_dec31_dec_sub16_function_unit; + reg [14:0] CR_dec31_dec_sub16_function_unit; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -7022,46 +7631,58 @@ module CR_dec31_dec_sub16(CR_dec31_dec_sub16_function_unit, CR_dec31_dec_sub16_i (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] CR_dec31_dec_sub16_internal_op; reg [6:0] CR_dec31_dec_sub16_internal_op; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] CR_dec31_dec_sub16_rc_sel; reg [1:0] CR_dec31_dec_sub16_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - CR_dec31_dec_sub16_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + CR_dec31_dec_sub16_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - CR_dec31_dec_sub16_function_unit = 14'h0040; + CR_dec31_dec_sub16_function_unit = 15'h0040; endcase end always @* begin if (\initial ) begin end CR_dec31_dec_sub16_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: CR_dec31_dec_sub16_internal_op = 7'h30; endcase end + always @* begin + if (\initial ) begin end + CR_dec31_dec_sub16_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h04: + CR_dec31_dec_sub16_SV_Ptype = 2'h2; + endcase + end always @* begin if (\initial ) begin end CR_dec31_dec_sub16_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: CR_dec31_dec_sub16_cr_in = 3'h6; endcase @@ -7069,9 +7690,9 @@ module CR_dec31_dec_sub16(CR_dec31_dec_sub16_function_unit, CR_dec31_dec_sub16_i always @* begin if (\initial ) begin end CR_dec31_dec_sub16_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: CR_dec31_dec_sub16_cr_out = 3'h4; endcase @@ -7079,9 +7700,9 @@ module CR_dec31_dec_sub16(CR_dec31_dec_sub16_function_unit, CR_dec31_dec_sub16_i always @* begin if (\initial ) begin end CR_dec31_dec_sub16_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: CR_dec31_dec_sub16_rc_sel = 2'h0; endcase @@ -7091,8 +7712,15 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub19" *) (* generator = "nMigen" *) -module CR_dec31_dec_sub19(CR_dec31_dec_sub19_function_unit, CR_dec31_dec_sub19_internal_op, CR_dec31_dec_sub19_cr_in, CR_dec31_dec_sub19_cr_out, CR_dec31_dec_sub19_rc_sel, opcode_in); +module CR_dec31_dec_sub19(CR_dec31_dec_sub19_function_unit, CR_dec31_dec_sub19_internal_op, CR_dec31_dec_sub19_SV_Ptype, CR_dec31_dec_sub19_cr_in, CR_dec31_dec_sub19_cr_out, CR_dec31_dec_sub19_rc_sel, opcode_in); reg \initial = 0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] CR_dec31_dec_sub19_SV_Ptype; + reg [1:0] CR_dec31_dec_sub19_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -7102,7 +7730,7 @@ module CR_dec31_dec_sub19(CR_dec31_dec_sub19_function_unit, CR_dec31_dec_sub19_i (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] CR_dec31_dec_sub19_cr_in; reg [2:0] CR_dec31_dec_sub19_cr_in; (* enum_base_type = "CROutSel" *) @@ -7112,27 +7740,28 @@ module CR_dec31_dec_sub19(CR_dec31_dec_sub19_function_unit, CR_dec31_dec_sub19_i (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] CR_dec31_dec_sub19_cr_out; reg [2:0] CR_dec31_dec_sub19_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] CR_dec31_dec_sub19_function_unit; - reg [13:0] CR_dec31_dec_sub19_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] CR_dec31_dec_sub19_function_unit; + reg [14:0] CR_dec31_dec_sub19_function_unit; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -7208,46 +7837,58 @@ module CR_dec31_dec_sub19(CR_dec31_dec_sub19_function_unit, CR_dec31_dec_sub19_i (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] CR_dec31_dec_sub19_internal_op; reg [6:0] CR_dec31_dec_sub19_internal_op; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] CR_dec31_dec_sub19_rc_sel; reg [1:0] CR_dec31_dec_sub19_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - CR_dec31_dec_sub19_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + CR_dec31_dec_sub19_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - CR_dec31_dec_sub19_function_unit = 14'h0040; + CR_dec31_dec_sub19_function_unit = 15'h0040; endcase end always @* begin if (\initial ) begin end CR_dec31_dec_sub19_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: CR_dec31_dec_sub19_internal_op = 7'h2d; endcase end + always @* begin + if (\initial ) begin end + CR_dec31_dec_sub19_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h00: + CR_dec31_dec_sub19_SV_Ptype = 2'h2; + endcase + end always @* begin if (\initial ) begin end CR_dec31_dec_sub19_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: CR_dec31_dec_sub19_cr_in = 3'h6; endcase @@ -7255,9 +7896,9 @@ module CR_dec31_dec_sub19(CR_dec31_dec_sub19_function_unit, CR_dec31_dec_sub19_i always @* begin if (\initial ) begin end CR_dec31_dec_sub19_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: CR_dec31_dec_sub19_cr_out = 3'h0; endcase @@ -7265,9 +7906,9 @@ module CR_dec31_dec_sub19(CR_dec31_dec_sub19_function_unit, CR_dec31_dec_sub19_i always @* begin if (\initial ) begin end CR_dec31_dec_sub19_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: CR_dec31_dec_sub19_rc_sel = 2'h0; endcase @@ -7277,8 +7918,15 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_DIV.dec.DIV_dec31" *) (* generator = "nMigen" *) -module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_sel, DIV_dec31_in2_sel, DIV_dec31_cr_in, DIV_dec31_cr_out, DIV_dec31_ldst_len, DIV_dec31_rc_sel, DIV_dec31_cry_in, DIV_dec31_inv_a, DIV_dec31_inv_out, DIV_dec31_cry_out, DIV_dec31_is_32b, DIV_dec31_sgn, opcode_in); +module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_SV_Ptype, DIV_dec31_in1_sel, DIV_dec31_in2_sel, DIV_dec31_cr_in, DIV_dec31_cr_out, DIV_dec31_ldst_len, DIV_dec31_rc_sel, DIV_dec31_cry_in, DIV_dec31_inv_a, DIV_dec31_inv_out, DIV_dec31_cry_out, DIV_dec31_is_32b, DIV_dec31_sgn, opcode_in); reg \initial = 0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] DIV_dec31_SV_Ptype; + reg [1:0] DIV_dec31_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -7288,7 +7936,7 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] DIV_dec31_cr_in; reg [2:0] DIV_dec31_cr_in; (* enum_base_type = "CROutSel" *) @@ -7298,19 +7946,25 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] DIV_dec31_cr_out; reg [2:0] DIV_dec31_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] DIV_dec31_cry_in; reg [1:0] DIV_dec31_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_dec31_cry_out; reg DIV_dec31_cry_out; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -7320,7 +7974,7 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -7329,40 +7983,43 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -7379,7 +8036,8 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -7456,13 +8114,15 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -7470,18 +8130,24 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] DIV_dec31_dec_sub11_opcode_in; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -7491,7 +8157,7 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -7500,40 +8166,43 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -7550,7 +8219,8 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -7627,13 +8297,15 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -7641,43 +8313,46 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] DIV_dec31_dec_sub9_opcode_in; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] DIV_dec31_function_unit; - reg [13:0] DIV_dec31_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] DIV_dec31_function_unit; + reg [14:0] DIV_dec31_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] DIV_dec31_in1_sel; reg [2:0] DIV_dec31_in1_sel; (* enum_base_type = "In2Sel" *) @@ -7695,7 +8370,8 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] DIV_dec31_in2_sel; reg [3:0] DIV_dec31_in2_sel; (* enum_base_type = "MicrOp" *) @@ -7773,16 +8449,18 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] DIV_dec31_internal_op; reg [6:0] DIV_dec31_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_dec31_inv_a; reg DIV_dec31_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_dec31_inv_out; reg DIV_dec31_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_dec31_is_32b; reg DIV_dec31_is_32b; (* enum_base_type = "LdstLen" *) @@ -7791,26 +8469,27 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] DIV_dec31_ldst_len; reg [3:0] DIV_dec31_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] DIV_dec31_rc_sel; reg [1:0] DIV_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_dec31_sgn; reg DIV_dec31_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:355" *) wire [4:0] opc_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [9:0] opcode_switch; DIV_dec31_dec_sub11 DIV_dec31_dec_sub11 ( + .DIV_dec31_dec_sub11_SV_Ptype(DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_SV_Ptype), .DIV_dec31_dec_sub11_cr_in(DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in), .DIV_dec31_dec_sub11_cr_out(DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out), .DIV_dec31_dec_sub11_cry_in(DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in), @@ -7828,6 +8507,7 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s .opcode_in(DIV_dec31_dec_sub11_opcode_in) ); DIV_dec31_dec_sub9 DIV_dec31_dec_sub9 ( + .DIV_dec31_dec_sub9_SV_Ptype(DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_SV_Ptype), .DIV_dec31_dec_sub9_cr_in(DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in), .DIV_dec31_dec_sub9_cr_out(DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out), .DIV_dec31_dec_sub9_cry_in(DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in), @@ -7844,15 +8524,28 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s .DIV_dec31_dec_sub9_sgn(DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn), .opcode_in(DIV_dec31_dec_sub9_opcode_in) ); + always @* begin + if (\initial ) begin end + DIV_dec31_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h09: + DIV_dec31_cr_out = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0b: + DIV_dec31_cr_out = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out; + endcase + end always @* begin if (\initial ) begin end DIV_dec31_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: DIV_dec31_ldst_len = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: DIV_dec31_ldst_len = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len; endcase @@ -7860,12 +8553,12 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s always @* begin if (\initial ) begin end DIV_dec31_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: DIV_dec31_rc_sel = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: DIV_dec31_rc_sel = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel; endcase @@ -7873,12 +8566,12 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s always @* begin if (\initial ) begin end DIV_dec31_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: DIV_dec31_cry_in = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: DIV_dec31_cry_in = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in; endcase @@ -7886,12 +8579,12 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s always @* begin if (\initial ) begin end DIV_dec31_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: DIV_dec31_inv_a = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: DIV_dec31_inv_a = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a; endcase @@ -7899,12 +8592,12 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s always @* begin if (\initial ) begin end DIV_dec31_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: DIV_dec31_inv_out = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: DIV_dec31_inv_out = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out; endcase @@ -7912,12 +8605,12 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s always @* begin if (\initial ) begin end DIV_dec31_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: DIV_dec31_cry_out = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: DIV_dec31_cry_out = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out; endcase @@ -7925,12 +8618,12 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s always @* begin if (\initial ) begin end DIV_dec31_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: DIV_dec31_is_32b = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: DIV_dec31_is_32b = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b; endcase @@ -7938,25 +8631,25 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s always @* begin if (\initial ) begin end DIV_dec31_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: DIV_dec31_sgn = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: DIV_dec31_sgn = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn; endcase end always @* begin if (\initial ) begin end - DIV_dec31_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + DIV_dec31_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: DIV_dec31_function_unit = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: DIV_dec31_function_unit = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit; endcase @@ -7964,25 +8657,38 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s always @* begin if (\initial ) begin end DIV_dec31_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: DIV_dec31_internal_op = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: DIV_dec31_internal_op = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op; endcase end + always @* begin + if (\initial ) begin end + DIV_dec31_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h09: + DIV_dec31_SV_Ptype = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0b: + DIV_dec31_SV_Ptype = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_SV_Ptype; + endcase + end always @* begin if (\initial ) begin end DIV_dec31_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: DIV_dec31_in1_sel = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: DIV_dec31_in1_sel = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel; endcase @@ -7990,12 +8696,12 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s always @* begin if (\initial ) begin end DIV_dec31_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: DIV_dec31_in2_sel = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: DIV_dec31_in2_sel = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel; endcase @@ -8003,29 +8709,16 @@ module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_s always @* begin if (\initial ) begin end DIV_dec31_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: DIV_dec31_cr_in = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: DIV_dec31_cr_in = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in; endcase end - always @* begin - if (\initial ) begin end - DIV_dec31_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) - casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h09: - DIV_dec31_cr_out = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h0b: - DIV_dec31_cr_out = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out; - endcase - end assign DIV_dec31_dec_sub11_opcode_in = opcode_in; assign DIV_dec31_dec_sub9_opcode_in = opcode_in; assign opc_in = opcode_switch[4:0]; @@ -8034,8 +8727,15 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_DIV.dec.DIV_dec31.DIV_dec31_dec_sub11" *) (* generator = "nMigen" *) -module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub11_internal_op, DIV_dec31_dec_sub11_in1_sel, DIV_dec31_dec_sub11_in2_sel, DIV_dec31_dec_sub11_cr_in, DIV_dec31_dec_sub11_cr_out, DIV_dec31_dec_sub11_ldst_len, DIV_dec31_dec_sub11_rc_sel, DIV_dec31_dec_sub11_cry_in, DIV_dec31_dec_sub11_inv_a, DIV_dec31_dec_sub11_inv_out, DIV_dec31_dec_sub11_cry_out, DIV_dec31_dec_sub11_is_32b, DIV_dec31_dec_sub11_sgn, opcode_in); +module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub11_internal_op, DIV_dec31_dec_sub11_SV_Ptype, DIV_dec31_dec_sub11_in1_sel, DIV_dec31_dec_sub11_in2_sel, DIV_dec31_dec_sub11_cr_in, DIV_dec31_dec_sub11_cr_out, DIV_dec31_dec_sub11_ldst_len, DIV_dec31_dec_sub11_rc_sel, DIV_dec31_dec_sub11_cry_in, DIV_dec31_dec_sub11_inv_a, DIV_dec31_dec_sub11_inv_out, DIV_dec31_dec_sub11_cry_out, DIV_dec31_dec_sub11_is_32b, DIV_dec31_dec_sub11_sgn, opcode_in); reg \initial = 0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] DIV_dec31_dec_sub11_SV_Ptype; + reg [1:0] DIV_dec31_dec_sub11_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -8045,7 +8745,7 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] DIV_dec31_dec_sub11_cr_in; reg [2:0] DIV_dec31_dec_sub11_cr_in; (* enum_base_type = "CROutSel" *) @@ -8055,44 +8755,47 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] DIV_dec31_dec_sub11_cr_out; reg [2:0] DIV_dec31_dec_sub11_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] DIV_dec31_dec_sub11_cry_in; reg [1:0] DIV_dec31_dec_sub11_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_dec31_dec_sub11_cry_out; reg DIV_dec31_dec_sub11_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] DIV_dec31_dec_sub11_function_unit; - reg [13:0] DIV_dec31_dec_sub11_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] DIV_dec31_dec_sub11_function_unit; + reg [14:0] DIV_dec31_dec_sub11_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] DIV_dec31_dec_sub11_in1_sel; reg [2:0] DIV_dec31_dec_sub11_in1_sel; (* enum_base_type = "In2Sel" *) @@ -8110,7 +8813,8 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] DIV_dec31_dec_sub11_in2_sel; reg [3:0] DIV_dec31_dec_sub11_in2_sel; (* enum_base_type = "MicrOp" *) @@ -8188,16 +8892,18 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] DIV_dec31_dec_sub11_internal_op; reg [6:0] DIV_dec31_dec_sub11_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_dec31_dec_sub11_inv_a; reg DIV_dec31_dec_sub11_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_dec31_dec_sub11_inv_out; reg DIV_dec31_dec_sub11_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_dec31_dec_sub11_is_32b; reg DIV_dec31_dec_sub11_is_32b; (* enum_base_type = "LdstLen" *) @@ -8206,93 +8912,130 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] DIV_dec31_dec_sub11_ldst_len; reg [3:0] DIV_dec31_dec_sub11_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] DIV_dec31_dec_sub11_rc_sel; reg [1:0] DIV_dec31_dec_sub11_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_dec31_dec_sub11_sgn; reg DIV_dec31_dec_sub11_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - DIV_dec31_dec_sub11_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + DIV_dec31_dec_sub11_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0c: + DIV_dec31_dec_sub11_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1c: + DIV_dec31_dec_sub11_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0d: + DIV_dec31_dec_sub11_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1d: + DIV_dec31_dec_sub11_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0e: + DIV_dec31_dec_sub11_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + DIV_dec31_dec_sub11_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0f: + DIV_dec31_dec_sub11_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1f: + DIV_dec31_dec_sub11_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h08: + DIV_dec31_dec_sub11_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h18: + DIV_dec31_dec_sub11_function_unit = 15'h0200; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_dec_sub11_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: - DIV_dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + DIV_dec31_dec_sub11_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: - DIV_dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + DIV_dec31_dec_sub11_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: - DIV_dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + DIV_dec31_dec_sub11_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: - DIV_dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + DIV_dec31_dec_sub11_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: - DIV_dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + DIV_dec31_dec_sub11_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: - DIV_dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + DIV_dec31_dec_sub11_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: - DIV_dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + DIV_dec31_dec_sub11_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: - DIV_dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + DIV_dec31_dec_sub11_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: - DIV_dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + DIV_dec31_dec_sub11_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - DIV_dec31_dec_sub11_function_unit = 14'h0200; + DIV_dec31_dec_sub11_cry_in = 2'h0; endcase end always @* begin if (\initial ) begin end DIV_dec31_dec_sub11_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: DIV_dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: DIV_dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: DIV_dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: DIV_dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: DIV_dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: DIV_dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: DIV_dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: DIV_dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: DIV_dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: DIV_dec31_dec_sub11_inv_a = 1'h0; endcase @@ -8300,36 +9043,36 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 always @* begin if (\initial ) begin end DIV_dec31_dec_sub11_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: DIV_dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: DIV_dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: DIV_dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: DIV_dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: DIV_dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: DIV_dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: DIV_dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: DIV_dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: DIV_dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: DIV_dec31_dec_sub11_inv_out = 1'h0; endcase @@ -8337,36 +9080,36 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 always @* begin if (\initial ) begin end DIV_dec31_dec_sub11_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: DIV_dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: DIV_dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: DIV_dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: DIV_dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: DIV_dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: DIV_dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: DIV_dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: DIV_dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: DIV_dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: DIV_dec31_dec_sub11_cry_out = 1'h0; endcase @@ -8374,36 +9117,36 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 always @* begin if (\initial ) begin end DIV_dec31_dec_sub11_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: DIV_dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: DIV_dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: DIV_dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: DIV_dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: DIV_dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: DIV_dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: DIV_dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: DIV_dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: DIV_dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: DIV_dec31_dec_sub11_is_32b = 1'h1; endcase @@ -8411,36 +9154,36 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 always @* begin if (\initial ) begin end DIV_dec31_dec_sub11_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: DIV_dec31_dec_sub11_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: DIV_dec31_dec_sub11_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: DIV_dec31_dec_sub11_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: DIV_dec31_dec_sub11_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: DIV_dec31_dec_sub11_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: DIV_dec31_dec_sub11_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: DIV_dec31_dec_sub11_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: DIV_dec31_dec_sub11_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: DIV_dec31_dec_sub11_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: DIV_dec31_dec_sub11_sgn = 1'h1; endcase @@ -8448,73 +9191,110 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 always @* begin if (\initial ) begin end DIV_dec31_dec_sub11_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: DIV_dec31_dec_sub11_internal_op = 7'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: DIV_dec31_dec_sub11_internal_op = 7'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: DIV_dec31_dec_sub11_internal_op = 7'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: DIV_dec31_dec_sub11_internal_op = 7'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: DIV_dec31_dec_sub11_internal_op = 7'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: DIV_dec31_dec_sub11_internal_op = 7'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: DIV_dec31_dec_sub11_internal_op = 7'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: DIV_dec31_dec_sub11_internal_op = 7'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: DIV_dec31_dec_sub11_internal_op = 7'h2f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: DIV_dec31_dec_sub11_internal_op = 7'h2f; endcase end + always @* begin + if (\initial ) begin end + DIV_dec31_dec_sub11_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0c: + DIV_dec31_dec_sub11_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1c: + DIV_dec31_dec_sub11_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0d: + DIV_dec31_dec_sub11_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1d: + DIV_dec31_dec_sub11_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0e: + DIV_dec31_dec_sub11_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + DIV_dec31_dec_sub11_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0f: + DIV_dec31_dec_sub11_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1f: + DIV_dec31_dec_sub11_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h08: + DIV_dec31_dec_sub11_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h18: + DIV_dec31_dec_sub11_SV_Ptype = 2'h1; + endcase + end always @* begin if (\initial ) begin end DIV_dec31_dec_sub11_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: DIV_dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: DIV_dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: DIV_dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: DIV_dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: DIV_dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: DIV_dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: DIV_dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: DIV_dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: DIV_dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: DIV_dec31_dec_sub11_in1_sel = 3'h1; endcase @@ -8522,36 +9302,36 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 always @* begin if (\initial ) begin end DIV_dec31_dec_sub11_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: DIV_dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: DIV_dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: DIV_dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: DIV_dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: DIV_dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: DIV_dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: DIV_dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: DIV_dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: DIV_dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: DIV_dec31_dec_sub11_in2_sel = 4'h1; endcase @@ -8559,36 +9339,36 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 always @* begin if (\initial ) begin end DIV_dec31_dec_sub11_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: DIV_dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: DIV_dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: DIV_dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: DIV_dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: DIV_dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: DIV_dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: DIV_dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: DIV_dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: DIV_dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: DIV_dec31_dec_sub11_cr_in = 3'h0; endcase @@ -8596,36 +9376,36 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 always @* begin if (\initial ) begin end DIV_dec31_dec_sub11_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: DIV_dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: DIV_dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: DIV_dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: DIV_dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: DIV_dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: DIV_dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: DIV_dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: DIV_dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: DIV_dec31_dec_sub11_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: DIV_dec31_dec_sub11_cr_out = 3'h0; endcase @@ -8633,36 +9413,36 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 always @* begin if (\initial ) begin end DIV_dec31_dec_sub11_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: DIV_dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: DIV_dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: DIV_dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: DIV_dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: DIV_dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: DIV_dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: DIV_dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: DIV_dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: DIV_dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: DIV_dec31_dec_sub11_ldst_len = 4'h0; endcase @@ -8670,84 +9450,54 @@ module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub1 always @* begin if (\initial ) begin end DIV_dec31_dec_sub11_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: DIV_dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: DIV_dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: DIV_dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: DIV_dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: DIV_dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: DIV_dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: DIV_dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: DIV_dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: DIV_dec31_dec_sub11_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: DIV_dec31_dec_sub11_rc_sel = 2'h0; endcase end - always @* begin - if (\initial ) begin end - DIV_dec31_dec_sub11_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) - casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h0c: - DIV_dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h1c: - DIV_dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h0d: - DIV_dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h1d: - DIV_dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h0e: - DIV_dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h1e: - DIV_dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h0f: - DIV_dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h1f: - DIV_dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h08: - DIV_dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h18: - DIV_dec31_dec_sub11_cry_in = 2'h0; - endcase - end assign opcode_switch = opcode_in[10:6]; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_DIV.dec.DIV_dec31.DIV_dec31_dec_sub9" *) (* generator = "nMigen" *) -module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_internal_op, DIV_dec31_dec_sub9_in1_sel, DIV_dec31_dec_sub9_in2_sel, DIV_dec31_dec_sub9_cr_in, DIV_dec31_dec_sub9_cr_out, DIV_dec31_dec_sub9_ldst_len, DIV_dec31_dec_sub9_rc_sel, DIV_dec31_dec_sub9_cry_in, DIV_dec31_dec_sub9_inv_a, DIV_dec31_dec_sub9_inv_out, DIV_dec31_dec_sub9_cry_out, DIV_dec31_dec_sub9_is_32b, DIV_dec31_dec_sub9_sgn, opcode_in); +module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_internal_op, DIV_dec31_dec_sub9_SV_Ptype, DIV_dec31_dec_sub9_in1_sel, DIV_dec31_dec_sub9_in2_sel, DIV_dec31_dec_sub9_cr_in, DIV_dec31_dec_sub9_cr_out, DIV_dec31_dec_sub9_ldst_len, DIV_dec31_dec_sub9_rc_sel, DIV_dec31_dec_sub9_cry_in, DIV_dec31_dec_sub9_inv_a, DIV_dec31_dec_sub9_inv_out, DIV_dec31_dec_sub9_cry_out, DIV_dec31_dec_sub9_is_32b, DIV_dec31_dec_sub9_sgn, opcode_in); reg \initial = 0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] DIV_dec31_dec_sub9_SV_Ptype; + reg [1:0] DIV_dec31_dec_sub9_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -8757,7 +9507,7 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] DIV_dec31_dec_sub9_cr_in; reg [2:0] DIV_dec31_dec_sub9_cr_in; (* enum_base_type = "CROutSel" *) @@ -8767,44 +9517,47 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] DIV_dec31_dec_sub9_cr_out; reg [2:0] DIV_dec31_dec_sub9_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] DIV_dec31_dec_sub9_cry_in; reg [1:0] DIV_dec31_dec_sub9_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_dec31_dec_sub9_cry_out; reg DIV_dec31_dec_sub9_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] DIV_dec31_dec_sub9_function_unit; - reg [13:0] DIV_dec31_dec_sub9_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] DIV_dec31_dec_sub9_function_unit; + reg [14:0] DIV_dec31_dec_sub9_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] DIV_dec31_dec_sub9_in1_sel; reg [2:0] DIV_dec31_dec_sub9_in1_sel; (* enum_base_type = "In2Sel" *) @@ -8822,7 +9575,8 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] DIV_dec31_dec_sub9_in2_sel; reg [3:0] DIV_dec31_dec_sub9_in2_sel; (* enum_base_type = "MicrOp" *) @@ -8900,16 +9654,18 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] DIV_dec31_dec_sub9_internal_op; reg [6:0] DIV_dec31_dec_sub9_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_dec31_dec_sub9_inv_a; reg DIV_dec31_dec_sub9_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_dec31_dec_sub9_inv_out; reg DIV_dec31_dec_sub9_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_dec31_dec_sub9_is_32b; reg DIV_dec31_dec_sub9_is_32b; (* enum_base_type = "LdstLen" *) @@ -8918,93 +9674,130 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] DIV_dec31_dec_sub9_ldst_len; reg [3:0] DIV_dec31_dec_sub9_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] DIV_dec31_dec_sub9_rc_sel; reg [1:0] DIV_dec31_dec_sub9_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_dec31_dec_sub9_sgn; reg DIV_dec31_dec_sub9_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - DIV_dec31_dec_sub9_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + DIV_dec31_dec_sub9_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0c: + DIV_dec31_dec_sub9_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1c: + DIV_dec31_dec_sub9_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0d: + DIV_dec31_dec_sub9_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1d: + DIV_dec31_dec_sub9_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0e: + DIV_dec31_dec_sub9_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + DIV_dec31_dec_sub9_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0f: + DIV_dec31_dec_sub9_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1f: + DIV_dec31_dec_sub9_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h08: + DIV_dec31_dec_sub9_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h18: + DIV_dec31_dec_sub9_function_unit = 15'h0200; + endcase + end + always @* begin + if (\initial ) begin end + DIV_dec31_dec_sub9_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: - DIV_dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + DIV_dec31_dec_sub9_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: - DIV_dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + DIV_dec31_dec_sub9_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: - DIV_dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + DIV_dec31_dec_sub9_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: - DIV_dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + DIV_dec31_dec_sub9_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: - DIV_dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + DIV_dec31_dec_sub9_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: - DIV_dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + DIV_dec31_dec_sub9_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: - DIV_dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + DIV_dec31_dec_sub9_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: - DIV_dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + DIV_dec31_dec_sub9_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: - DIV_dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + DIV_dec31_dec_sub9_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - DIV_dec31_dec_sub9_function_unit = 14'h0200; + DIV_dec31_dec_sub9_cry_in = 2'h0; endcase end always @* begin if (\initial ) begin end DIV_dec31_dec_sub9_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: DIV_dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: DIV_dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: DIV_dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: DIV_dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: DIV_dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: DIV_dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: DIV_dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: DIV_dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: DIV_dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: DIV_dec31_dec_sub9_inv_a = 1'h0; endcase @@ -9012,36 +9805,36 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i always @* begin if (\initial ) begin end DIV_dec31_dec_sub9_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: DIV_dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: DIV_dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: DIV_dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: DIV_dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: DIV_dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: DIV_dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: DIV_dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: DIV_dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: DIV_dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: DIV_dec31_dec_sub9_inv_out = 1'h0; endcase @@ -9049,36 +9842,36 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i always @* begin if (\initial ) begin end DIV_dec31_dec_sub9_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: DIV_dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: DIV_dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: DIV_dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: DIV_dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: DIV_dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: DIV_dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: DIV_dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: DIV_dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: DIV_dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: DIV_dec31_dec_sub9_cry_out = 1'h0; endcase @@ -9086,36 +9879,36 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i always @* begin if (\initial ) begin end DIV_dec31_dec_sub9_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: DIV_dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: DIV_dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: DIV_dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: DIV_dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: DIV_dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: DIV_dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: DIV_dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: DIV_dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: DIV_dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: DIV_dec31_dec_sub9_is_32b = 1'h0; endcase @@ -9123,36 +9916,36 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i always @* begin if (\initial ) begin end DIV_dec31_dec_sub9_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: DIV_dec31_dec_sub9_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: DIV_dec31_dec_sub9_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: DIV_dec31_dec_sub9_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: DIV_dec31_dec_sub9_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: DIV_dec31_dec_sub9_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: DIV_dec31_dec_sub9_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: DIV_dec31_dec_sub9_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: DIV_dec31_dec_sub9_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: DIV_dec31_dec_sub9_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: DIV_dec31_dec_sub9_sgn = 1'h1; endcase @@ -9160,73 +9953,110 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i always @* begin if (\initial ) begin end DIV_dec31_dec_sub9_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: DIV_dec31_dec_sub9_internal_op = 7'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: DIV_dec31_dec_sub9_internal_op = 7'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: DIV_dec31_dec_sub9_internal_op = 7'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: DIV_dec31_dec_sub9_internal_op = 7'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: DIV_dec31_dec_sub9_internal_op = 7'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: DIV_dec31_dec_sub9_internal_op = 7'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: DIV_dec31_dec_sub9_internal_op = 7'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: DIV_dec31_dec_sub9_internal_op = 7'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: DIV_dec31_dec_sub9_internal_op = 7'h2f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: DIV_dec31_dec_sub9_internal_op = 7'h2f; endcase end + always @* begin + if (\initial ) begin end + DIV_dec31_dec_sub9_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0c: + DIV_dec31_dec_sub9_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1c: + DIV_dec31_dec_sub9_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0d: + DIV_dec31_dec_sub9_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1d: + DIV_dec31_dec_sub9_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0e: + DIV_dec31_dec_sub9_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + DIV_dec31_dec_sub9_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0f: + DIV_dec31_dec_sub9_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1f: + DIV_dec31_dec_sub9_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h08: + DIV_dec31_dec_sub9_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h18: + DIV_dec31_dec_sub9_SV_Ptype = 2'h1; + endcase + end always @* begin if (\initial ) begin end DIV_dec31_dec_sub9_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: DIV_dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: DIV_dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: DIV_dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: DIV_dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: DIV_dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: DIV_dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: DIV_dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: DIV_dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: DIV_dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: DIV_dec31_dec_sub9_in1_sel = 3'h1; endcase @@ -9234,36 +10064,36 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i always @* begin if (\initial ) begin end DIV_dec31_dec_sub9_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: DIV_dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: DIV_dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: DIV_dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: DIV_dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: DIV_dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: DIV_dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: DIV_dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: DIV_dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: DIV_dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: DIV_dec31_dec_sub9_in2_sel = 4'h1; endcase @@ -9271,36 +10101,36 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i always @* begin if (\initial ) begin end DIV_dec31_dec_sub9_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: DIV_dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: DIV_dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: DIV_dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: DIV_dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: DIV_dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: DIV_dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: DIV_dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: DIV_dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: DIV_dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: DIV_dec31_dec_sub9_cr_in = 3'h0; endcase @@ -9308,36 +10138,36 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i always @* begin if (\initial ) begin end DIV_dec31_dec_sub9_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: DIV_dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: DIV_dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: DIV_dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: DIV_dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: DIV_dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: DIV_dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: DIV_dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: DIV_dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: DIV_dec31_dec_sub9_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: DIV_dec31_dec_sub9_cr_out = 3'h0; endcase @@ -9345,36 +10175,36 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i always @* begin if (\initial ) begin end DIV_dec31_dec_sub9_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: DIV_dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: DIV_dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: DIV_dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: DIV_dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: DIV_dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: DIV_dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: DIV_dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: DIV_dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: DIV_dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: DIV_dec31_dec_sub9_ldst_len = 4'h0; endcase @@ -9382,85 +10212,55 @@ module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_i always @* begin if (\initial ) begin end DIV_dec31_dec_sub9_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: DIV_dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: DIV_dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: DIV_dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: DIV_dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: DIV_dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: DIV_dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: DIV_dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: DIV_dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: DIV_dec31_dec_sub9_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: DIV_dec31_dec_sub9_rc_sel = 2'h0; endcase end - always @* begin - if (\initial ) begin end - DIV_dec31_dec_sub9_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) - casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h0c: - DIV_dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h1c: - DIV_dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h0d: - DIV_dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h1d: - DIV_dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h0e: - DIV_dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h1e: - DIV_dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h0f: - DIV_dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h1f: - DIV_dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h08: - DIV_dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h18: - DIV_dec31_dec_sub9_cry_in = 2'h0; - endcase - end assign opcode_switch = opcode_in[10:6]; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_LDST.dec.LDST_dec31" *) (* generator = "nMigen" *) -module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_in1_sel, LDST_dec31_in2_sel, LDST_dec31_cr_in, LDST_dec31_cr_out, LDST_dec31_ldst_len, LDST_dec31_upd, LDST_dec31_rc_sel, LDST_dec31_br, LDST_dec31_sgn_ext, LDST_dec31_is_32b, LDST_dec31_sgn, opcode_in); +module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_SV_Ptype, LDST_dec31_in1_sel, LDST_dec31_in2_sel, LDST_dec31_cr_in, LDST_dec31_cr_out, LDST_dec31_ldst_len, LDST_dec31_upd, LDST_dec31_rc_sel, LDST_dec31_br, LDST_dec31_sgn_ext, LDST_dec31_is_32b, LDST_dec31_sgn, opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] LDST_dec31_SV_Ptype; + reg [1:0] LDST_dec31_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_br; reg LDST_dec31_br; (* enum_base_type = "CRInSel" *) @@ -9472,7 +10272,7 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec31_cr_in; reg [2:0] LDST_dec31_cr_in; (* enum_base_type = "CROutSel" *) @@ -9482,10 +10282,16 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec31_cr_out; reg [2:0] LDST_dec31_cr_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -9496,7 +10302,7 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -9505,32 +10311,35 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -9547,7 +10356,8 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -9624,9 +10434,11 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -9634,28 +10446,34 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn_ext; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] LDST_dec31_dec_sub20_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -9666,7 +10484,7 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -9675,32 +10493,35 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -9717,7 +10538,8 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -9794,9 +10616,11 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -9804,28 +10628,34 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn_ext; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] LDST_dec31_dec_sub21_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -9836,7 +10666,7 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -9845,32 +10675,35 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -9887,7 +10720,8 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -9964,9 +10798,11 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -9974,28 +10810,34 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn_ext; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] LDST_dec31_dec_sub22_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -10006,7 +10848,7 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -10015,32 +10857,35 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -10057,7 +10902,8 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -10134,9 +10980,11 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -10144,52 +10992,55 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] LDST_dec31_dec_sub23_opcode_in; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] LDST_dec31_function_unit; - reg [13:0] LDST_dec31_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] LDST_dec31_function_unit; + reg [14:0] LDST_dec31_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec31_in1_sel; reg [2:0] LDST_dec31_in1_sel; (* enum_base_type = "In2Sel" *) @@ -10207,7 +11058,8 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LDST_dec31_in2_sel; reg [3:0] LDST_dec31_in2_sel; (* enum_base_type = "MicrOp" *) @@ -10285,10 +11137,12 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] LDST_dec31_internal_op; reg [6:0] LDST_dec31_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_is_32b; reg LDST_dec31_is_32b; (* enum_base_type = "LdstLen" *) @@ -10297,20 +11151,20 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LDST_dec31_ldst_len; reg [3:0] LDST_dec31_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LDST_dec31_rc_sel; reg [1:0] LDST_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_sgn; reg LDST_dec31_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_sgn_ext; reg LDST_dec31_sgn_ext; (* enum_base_type = "LDSTMode" *) @@ -10318,16 +11172,17 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LDST_dec31_upd; reg [1:0] LDST_dec31_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:355" *) wire [4:0] opc_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [9:0] opcode_switch; LDST_dec31_dec_sub20 LDST_dec31_dec_sub20 ( + .LDST_dec31_dec_sub20_SV_Ptype(LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_SV_Ptype), .LDST_dec31_dec_sub20_br(LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br), .LDST_dec31_dec_sub20_cr_in(LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in), .LDST_dec31_dec_sub20_cr_out(LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out), @@ -10344,6 +11199,7 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i .opcode_in(LDST_dec31_dec_sub20_opcode_in) ); LDST_dec31_dec_sub21 LDST_dec31_dec_sub21 ( + .LDST_dec31_dec_sub21_SV_Ptype(LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_SV_Ptype), .LDST_dec31_dec_sub21_br(LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br), .LDST_dec31_dec_sub21_cr_in(LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in), .LDST_dec31_dec_sub21_cr_out(LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_out), @@ -10360,6 +11216,7 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i .opcode_in(LDST_dec31_dec_sub21_opcode_in) ); LDST_dec31_dec_sub22 LDST_dec31_dec_sub22 ( + .LDST_dec31_dec_sub22_SV_Ptype(LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_SV_Ptype), .LDST_dec31_dec_sub22_br(LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br), .LDST_dec31_dec_sub22_cr_in(LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in), .LDST_dec31_dec_sub22_cr_out(LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out), @@ -10376,6 +11233,7 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i .opcode_in(LDST_dec31_dec_sub22_opcode_in) ); LDST_dec31_dec_sub23 LDST_dec31_dec_sub23 ( + .LDST_dec31_dec_sub23_SV_Ptype(LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_SV_Ptype), .LDST_dec31_dec_sub23_br(LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br), .LDST_dec31_dec_sub23_cr_in(LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in), .LDST_dec31_dec_sub23_cr_out(LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out), @@ -10391,21 +11249,40 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i .LDST_dec31_dec_sub23_upd(LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd), .opcode_in(LDST_dec31_dec_sub23_opcode_in) ); + always @* begin + if (\initial ) begin end + LDST_dec31_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + LDST_dec31_in2_sel = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in2_sel; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + LDST_dec31_in2_sel = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + LDST_dec31_in2_sel = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in2_sel; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + LDST_dec31_in2_sel = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in2_sel; + endcase + end always @* begin if (\initial ) begin end LDST_dec31_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: LDST_dec31_cr_in = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: LDST_dec31_cr_in = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: LDST_dec31_cr_in = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: LDST_dec31_cr_in = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in; endcase @@ -10413,18 +11290,18 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i always @* begin if (\initial ) begin end LDST_dec31_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: LDST_dec31_cr_out = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: LDST_dec31_cr_out = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: LDST_dec31_cr_out = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: LDST_dec31_cr_out = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out; endcase @@ -10432,18 +11309,18 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i always @* begin if (\initial ) begin end LDST_dec31_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: LDST_dec31_ldst_len = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: LDST_dec31_ldst_len = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: LDST_dec31_ldst_len = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: LDST_dec31_ldst_len = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len; endcase @@ -10451,18 +11328,18 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i always @* begin if (\initial ) begin end LDST_dec31_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: LDST_dec31_upd = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: LDST_dec31_upd = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: LDST_dec31_upd = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: LDST_dec31_upd = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd; endcase @@ -10470,18 +11347,18 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i always @* begin if (\initial ) begin end LDST_dec31_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: LDST_dec31_rc_sel = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: LDST_dec31_rc_sel = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: LDST_dec31_rc_sel = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: LDST_dec31_rc_sel = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel; endcase @@ -10489,18 +11366,18 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i always @* begin if (\initial ) begin end LDST_dec31_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: LDST_dec31_br = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: LDST_dec31_br = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: LDST_dec31_br = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: LDST_dec31_br = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br; endcase @@ -10508,18 +11385,18 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i always @* begin if (\initial ) begin end LDST_dec31_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: LDST_dec31_sgn_ext = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: LDST_dec31_sgn_ext = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: LDST_dec31_sgn_ext = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: LDST_dec31_sgn_ext = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext; endcase @@ -10527,18 +11404,18 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i always @* begin if (\initial ) begin end LDST_dec31_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: LDST_dec31_is_32b = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: LDST_dec31_is_32b = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: LDST_dec31_is_32b = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: LDST_dec31_is_32b = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b; endcase @@ -10546,37 +11423,37 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i always @* begin if (\initial ) begin end LDST_dec31_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: LDST_dec31_sgn = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: LDST_dec31_sgn = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: LDST_dec31_sgn = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: LDST_dec31_sgn = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn; endcase end always @* begin if (\initial ) begin end - LDST_dec31_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + LDST_dec31_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: LDST_dec31_function_unit = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: LDST_dec31_function_unit = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: LDST_dec31_function_unit = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: LDST_dec31_function_unit = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit; endcase @@ -10584,58 +11461,58 @@ module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_i always @* begin if (\initial ) begin end LDST_dec31_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: LDST_dec31_internal_op = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: LDST_dec31_internal_op = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: LDST_dec31_internal_op = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: LDST_dec31_internal_op = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op; endcase end always @* begin if (\initial ) begin end - LDST_dec31_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + LDST_dec31_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: - LDST_dec31_in1_sel = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_SV_Ptype = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: - LDST_dec31_in1_sel = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_SV_Ptype = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: - LDST_dec31_in1_sel = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_SV_Ptype = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: - LDST_dec31_in1_sel = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in1_sel; + LDST_dec31_SV_Ptype = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_SV_Ptype; endcase end always @* begin if (\initial ) begin end - LDST_dec31_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + LDST_dec31_in1_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: - LDST_dec31_in2_sel = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_in1_sel = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in1_sel; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: - LDST_dec31_in2_sel = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_in1_sel = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: - LDST_dec31_in2_sel = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_in1_sel = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in1_sel; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: - LDST_dec31_in2_sel = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in2_sel; + LDST_dec31_in1_sel = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in1_sel; endcase end assign LDST_dec31_dec_sub23_opcode_in = opcode_in; @@ -10648,9 +11525,16 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub20" *) (* generator = "nMigen" *) -module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_sub20_internal_op, LDST_dec31_dec_sub20_in1_sel, LDST_dec31_dec_sub20_in2_sel, LDST_dec31_dec_sub20_cr_in, LDST_dec31_dec_sub20_cr_out, LDST_dec31_dec_sub20_ldst_len, LDST_dec31_dec_sub20_upd, LDST_dec31_dec_sub20_rc_sel, LDST_dec31_dec_sub20_br, LDST_dec31_dec_sub20_sgn_ext, LDST_dec31_dec_sub20_is_32b, LDST_dec31_dec_sub20_sgn, opcode_in); +module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_sub20_internal_op, LDST_dec31_dec_sub20_SV_Ptype, LDST_dec31_dec_sub20_in1_sel, LDST_dec31_dec_sub20_in2_sel, LDST_dec31_dec_sub20_cr_in, LDST_dec31_dec_sub20_cr_out, LDST_dec31_dec_sub20_ldst_len, LDST_dec31_dec_sub20_upd, LDST_dec31_dec_sub20_rc_sel, LDST_dec31_dec_sub20_br, LDST_dec31_dec_sub20_sgn_ext, LDST_dec31_dec_sub20_is_32b, LDST_dec31_dec_sub20_sgn, opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] LDST_dec31_dec_sub20_SV_Ptype; + reg [1:0] LDST_dec31_dec_sub20_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_dec_sub20_br; reg LDST_dec31_dec_sub20_br; (* enum_base_type = "CRInSel" *) @@ -10662,7 +11546,7 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec31_dec_sub20_cr_in; reg [2:0] LDST_dec31_dec_sub20_cr_in; (* enum_base_type = "CROutSel" *) @@ -10672,34 +11556,37 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec31_dec_sub20_cr_out; reg [2:0] LDST_dec31_dec_sub20_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] LDST_dec31_dec_sub20_function_unit; - reg [13:0] LDST_dec31_dec_sub20_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] LDST_dec31_dec_sub20_function_unit; + reg [14:0] LDST_dec31_dec_sub20_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec31_dec_sub20_in1_sel; reg [2:0] LDST_dec31_dec_sub20_in1_sel; (* enum_base_type = "In2Sel" *) @@ -10717,7 +11604,8 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LDST_dec31_dec_sub20_in2_sel; reg [3:0] LDST_dec31_dec_sub20_in2_sel; (* enum_base_type = "MicrOp" *) @@ -10795,10 +11683,12 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] LDST_dec31_dec_sub20_internal_op; reg [6:0] LDST_dec31_dec_sub20_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_dec_sub20_is_32b; reg LDST_dec31_dec_sub20_is_32b; (* enum_base_type = "LdstLen" *) @@ -10807,20 +11697,20 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LDST_dec31_dec_sub20_ldst_len; reg [3:0] LDST_dec31_dec_sub20_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LDST_dec31_dec_sub20_rc_sel; reg [1:0] LDST_dec31_dec_sub20_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_dec_sub20_sgn; reg LDST_dec31_dec_sub20_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_dec_sub20_sgn_ext; reg LDST_dec31_dec_sub20_sgn_ext; (* enum_base_type = "LDSTMode" *) @@ -10828,59 +11718,84 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LDST_dec31_dec_sub20_upd; reg [1:0] LDST_dec31_dec_sub20_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - LDST_dec31_dec_sub20_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + LDST_dec31_dec_sub20_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: - LDST_dec31_dec_sub20_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub20_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: - LDST_dec31_dec_sub20_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub20_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - LDST_dec31_dec_sub20_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub20_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: - LDST_dec31_dec_sub20_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub20_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - LDST_dec31_dec_sub20_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub20_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: - LDST_dec31_dec_sub20_function_unit = 14'h0004; + LDST_dec31_dec_sub20_function_unit = 15'h0004; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub20_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h01: + LDST_dec31_dec_sub20_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h02: + LDST_dec31_dec_sub20_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + LDST_dec31_dec_sub20_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h03: + LDST_dec31_dec_sub20_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h00: + LDST_dec31_dec_sub20_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + LDST_dec31_dec_sub20_rc_sel = 2'h0; endcase end always @* begin if (\initial ) begin end LDST_dec31_dec_sub20_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LDST_dec31_dec_sub20_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: LDST_dec31_dec_sub20_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LDST_dec31_dec_sub20_br = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LDST_dec31_dec_sub20_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LDST_dec31_dec_sub20_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: LDST_dec31_dec_sub20_br = 1'h1; endcase @@ -10888,24 +11803,24 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub20_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LDST_dec31_dec_sub20_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: LDST_dec31_dec_sub20_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LDST_dec31_dec_sub20_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LDST_dec31_dec_sub20_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LDST_dec31_dec_sub20_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: LDST_dec31_dec_sub20_sgn_ext = 1'h0; endcase @@ -10913,24 +11828,24 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub20_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LDST_dec31_dec_sub20_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: LDST_dec31_dec_sub20_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LDST_dec31_dec_sub20_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LDST_dec31_dec_sub20_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LDST_dec31_dec_sub20_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: LDST_dec31_dec_sub20_is_32b = 1'h0; endcase @@ -10938,24 +11853,24 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub20_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LDST_dec31_dec_sub20_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: LDST_dec31_dec_sub20_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LDST_dec31_dec_sub20_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LDST_dec31_dec_sub20_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LDST_dec31_dec_sub20_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: LDST_dec31_dec_sub20_sgn = 1'h0; endcase @@ -10963,49 +11878,74 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub20_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LDST_dec31_dec_sub20_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: LDST_dec31_dec_sub20_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LDST_dec31_dec_sub20_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LDST_dec31_dec_sub20_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LDST_dec31_dec_sub20_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: LDST_dec31_dec_sub20_internal_op = 7'h26; endcase end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub20_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h01: + LDST_dec31_dec_sub20_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h02: + LDST_dec31_dec_sub20_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + LDST_dec31_dec_sub20_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h03: + LDST_dec31_dec_sub20_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h00: + LDST_dec31_dec_sub20_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + LDST_dec31_dec_sub20_SV_Ptype = 2'h2; + endcase + end always @* begin if (\initial ) begin end LDST_dec31_dec_sub20_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LDST_dec31_dec_sub20_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: LDST_dec31_dec_sub20_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LDST_dec31_dec_sub20_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LDST_dec31_dec_sub20_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LDST_dec31_dec_sub20_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: LDST_dec31_dec_sub20_in1_sel = 3'h2; endcase @@ -11013,24 +11953,24 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub20_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LDST_dec31_dec_sub20_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: LDST_dec31_dec_sub20_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LDST_dec31_dec_sub20_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LDST_dec31_dec_sub20_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LDST_dec31_dec_sub20_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: LDST_dec31_dec_sub20_in2_sel = 4'h1; endcase @@ -11038,24 +11978,24 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub20_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LDST_dec31_dec_sub20_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: LDST_dec31_dec_sub20_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LDST_dec31_dec_sub20_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LDST_dec31_dec_sub20_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LDST_dec31_dec_sub20_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: LDST_dec31_dec_sub20_cr_in = 3'h0; endcase @@ -11063,24 +12003,24 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub20_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LDST_dec31_dec_sub20_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: LDST_dec31_dec_sub20_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LDST_dec31_dec_sub20_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LDST_dec31_dec_sub20_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LDST_dec31_dec_sub20_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: LDST_dec31_dec_sub20_cr_out = 3'h0; endcase @@ -11088,24 +12028,24 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub20_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LDST_dec31_dec_sub20_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: LDST_dec31_dec_sub20_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LDST_dec31_dec_sub20_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LDST_dec31_dec_sub20_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LDST_dec31_dec_sub20_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: LDST_dec31_dec_sub20_ldst_len = 4'h8; endcase @@ -11113,61 +12053,43 @@ module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub20_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LDST_dec31_dec_sub20_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: LDST_dec31_dec_sub20_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LDST_dec31_dec_sub20_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LDST_dec31_dec_sub20_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LDST_dec31_dec_sub20_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: LDST_dec31_dec_sub20_upd = 2'h0; endcase end - always @* begin - if (\initial ) begin end - LDST_dec31_dec_sub20_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) - casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h01: - LDST_dec31_dec_sub20_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h02: - LDST_dec31_dec_sub20_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h10: - LDST_dec31_dec_sub20_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h03: - LDST_dec31_dec_sub20_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h00: - LDST_dec31_dec_sub20_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h14: - LDST_dec31_dec_sub20_rc_sel = 2'h0; - endcase - end assign opcode_switch = opcode_in[10:6]; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub21" *) (* generator = "nMigen" *) -module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_sub21_internal_op, LDST_dec31_dec_sub21_in1_sel, LDST_dec31_dec_sub21_in2_sel, LDST_dec31_dec_sub21_cr_in, LDST_dec31_dec_sub21_cr_out, LDST_dec31_dec_sub21_ldst_len, LDST_dec31_dec_sub21_upd, LDST_dec31_dec_sub21_rc_sel, LDST_dec31_dec_sub21_br, LDST_dec31_dec_sub21_sgn_ext, LDST_dec31_dec_sub21_is_32b, LDST_dec31_dec_sub21_sgn, opcode_in); +module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_sub21_internal_op, LDST_dec31_dec_sub21_SV_Ptype, LDST_dec31_dec_sub21_in1_sel, LDST_dec31_dec_sub21_in2_sel, LDST_dec31_dec_sub21_cr_in, LDST_dec31_dec_sub21_cr_out, LDST_dec31_dec_sub21_ldst_len, LDST_dec31_dec_sub21_upd, LDST_dec31_dec_sub21_rc_sel, LDST_dec31_dec_sub21_br, LDST_dec31_dec_sub21_sgn_ext, LDST_dec31_dec_sub21_is_32b, LDST_dec31_dec_sub21_sgn, opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] LDST_dec31_dec_sub21_SV_Ptype; + reg [1:0] LDST_dec31_dec_sub21_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_dec_sub21_br; reg LDST_dec31_dec_sub21_br; (* enum_base_type = "CRInSel" *) @@ -11179,7 +12101,7 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec31_dec_sub21_cr_in; reg [2:0] LDST_dec31_dec_sub21_cr_in; (* enum_base_type = "CROutSel" *) @@ -11189,34 +12111,37 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec31_dec_sub21_cr_out; reg [2:0] LDST_dec31_dec_sub21_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] LDST_dec31_dec_sub21_function_unit; - reg [13:0] LDST_dec31_dec_sub21_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] LDST_dec31_dec_sub21_function_unit; + reg [14:0] LDST_dec31_dec_sub21_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec31_dec_sub21_in1_sel; reg [2:0] LDST_dec31_dec_sub21_in1_sel; (* enum_base_type = "In2Sel" *) @@ -11234,7 +12159,8 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LDST_dec31_dec_sub21_in2_sel; reg [3:0] LDST_dec31_dec_sub21_in2_sel; (* enum_base_type = "MicrOp" *) @@ -11312,10 +12238,12 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] LDST_dec31_dec_sub21_internal_op; reg [6:0] LDST_dec31_dec_sub21_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_dec_sub21_is_32b; reg LDST_dec31_dec_sub21_is_32b; (* enum_base_type = "LdstLen" *) @@ -11324,20 +12252,20 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LDST_dec31_dec_sub21_ldst_len; reg [3:0] LDST_dec31_dec_sub21_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LDST_dec31_dec_sub21_rc_sel; reg [1:0] LDST_dec31_dec_sub21_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_dec_sub21_sgn; reg LDST_dec31_dec_sub21_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_dec_sub21_sgn_ext; reg LDST_dec31_dec_sub21_sgn_ext; (* enum_base_type = "LDSTMode" *) @@ -11345,107 +12273,156 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LDST_dec31_dec_sub21_upd; reg [1:0] LDST_dec31_dec_sub21_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - LDST_dec31_dec_sub21_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + LDST_dec31_dec_sub21_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: - LDST_dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub21_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: - LDST_dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub21_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: - LDST_dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub21_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - LDST_dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub21_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: - LDST_dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub21_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: - LDST_dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub21_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: - LDST_dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub21_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - LDST_dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub21_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: - LDST_dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub21_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: - LDST_dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub21_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: - LDST_dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub21_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - LDST_dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub21_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: - LDST_dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub21_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: - LDST_dec31_dec_sub21_function_unit = 14'h0004; + LDST_dec31_dec_sub21_function_unit = 15'h0004; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub21_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + LDST_dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + LDST_dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h01: + LDST_dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h00: + LDST_dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h19: + LDST_dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0b: + LDST_dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0a: + LDST_dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h18: + LDST_dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + LDST_dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1f: + LDST_dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h05: + LDST_dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h04: + LDST_dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1d: + LDST_dec31_dec_sub21_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1c: + LDST_dec31_dec_sub21_rc_sel = 2'h0; endcase end always @* begin if (\initial ) begin end LDST_dec31_dec_sub21_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: LDST_dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: LDST_dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LDST_dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LDST_dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: LDST_dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LDST_dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: LDST_dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: LDST_dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: LDST_dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: LDST_dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LDST_dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LDST_dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: LDST_dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LDST_dec31_dec_sub21_br = 1'h0; endcase @@ -11453,48 +12430,48 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub21_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: LDST_dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: LDST_dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LDST_dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LDST_dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: LDST_dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LDST_dec31_dec_sub21_sgn_ext = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: LDST_dec31_dec_sub21_sgn_ext = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: LDST_dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: LDST_dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: LDST_dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LDST_dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LDST_dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: LDST_dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LDST_dec31_dec_sub21_sgn_ext = 1'h0; endcase @@ -11502,48 +12479,48 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub21_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: LDST_dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: LDST_dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LDST_dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LDST_dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: LDST_dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LDST_dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: LDST_dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: LDST_dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: LDST_dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: LDST_dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LDST_dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LDST_dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: LDST_dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LDST_dec31_dec_sub21_is_32b = 1'h0; endcase @@ -11551,48 +12528,48 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub21_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: LDST_dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: LDST_dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LDST_dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LDST_dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: LDST_dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LDST_dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: LDST_dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: LDST_dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: LDST_dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: LDST_dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LDST_dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LDST_dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: LDST_dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LDST_dec31_dec_sub21_sgn = 1'h0; endcase @@ -11600,97 +12577,146 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub21_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: LDST_dec31_dec_sub21_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: LDST_dec31_dec_sub21_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LDST_dec31_dec_sub21_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LDST_dec31_dec_sub21_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: LDST_dec31_dec_sub21_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LDST_dec31_dec_sub21_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: LDST_dec31_dec_sub21_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: LDST_dec31_dec_sub21_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: LDST_dec31_dec_sub21_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: LDST_dec31_dec_sub21_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LDST_dec31_dec_sub21_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LDST_dec31_dec_sub21_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: LDST_dec31_dec_sub21_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LDST_dec31_dec_sub21_internal_op = 7'h26; endcase end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub21_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + LDST_dec31_dec_sub21_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + LDST_dec31_dec_sub21_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h01: + LDST_dec31_dec_sub21_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h00: + LDST_dec31_dec_sub21_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h19: + LDST_dec31_dec_sub21_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0b: + LDST_dec31_dec_sub21_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0a: + LDST_dec31_dec_sub21_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h18: + LDST_dec31_dec_sub21_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + LDST_dec31_dec_sub21_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1f: + LDST_dec31_dec_sub21_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h05: + LDST_dec31_dec_sub21_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h04: + LDST_dec31_dec_sub21_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1d: + LDST_dec31_dec_sub21_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1c: + LDST_dec31_dec_sub21_SV_Ptype = 2'h2; + endcase + end always @* begin if (\initial ) begin end LDST_dec31_dec_sub21_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: LDST_dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: LDST_dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LDST_dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LDST_dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: LDST_dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LDST_dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: LDST_dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: LDST_dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: LDST_dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: LDST_dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LDST_dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LDST_dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: LDST_dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LDST_dec31_dec_sub21_in1_sel = 3'h2; endcase @@ -11698,48 +12724,48 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub21_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: LDST_dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: LDST_dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LDST_dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LDST_dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: LDST_dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LDST_dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: LDST_dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: LDST_dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: LDST_dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: LDST_dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LDST_dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LDST_dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: LDST_dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LDST_dec31_dec_sub21_in2_sel = 4'h1; endcase @@ -11747,48 +12773,48 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub21_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: LDST_dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: LDST_dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LDST_dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LDST_dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: LDST_dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LDST_dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: LDST_dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: LDST_dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: LDST_dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: LDST_dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LDST_dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LDST_dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: LDST_dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LDST_dec31_dec_sub21_cr_in = 3'h0; endcase @@ -11796,48 +12822,48 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub21_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: LDST_dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: LDST_dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LDST_dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LDST_dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: LDST_dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LDST_dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: LDST_dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: LDST_dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: LDST_dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: LDST_dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LDST_dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LDST_dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: LDST_dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LDST_dec31_dec_sub21_cr_out = 3'h0; endcase @@ -11845,48 +12871,48 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub21_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: LDST_dec31_dec_sub21_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: LDST_dec31_dec_sub21_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LDST_dec31_dec_sub21_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LDST_dec31_dec_sub21_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: LDST_dec31_dec_sub21_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LDST_dec31_dec_sub21_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: LDST_dec31_dec_sub21_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: LDST_dec31_dec_sub21_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: LDST_dec31_dec_sub21_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: LDST_dec31_dec_sub21_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LDST_dec31_dec_sub21_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LDST_dec31_dec_sub21_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: LDST_dec31_dec_sub21_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LDST_dec31_dec_sub21_ldst_len = 4'h4; endcase @@ -11894,109 +12920,67 @@ module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub21_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: LDST_dec31_dec_sub21_upd = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: LDST_dec31_dec_sub21_upd = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LDST_dec31_dec_sub21_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LDST_dec31_dec_sub21_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: LDST_dec31_dec_sub21_upd = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LDST_dec31_dec_sub21_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: LDST_dec31_dec_sub21_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: LDST_dec31_dec_sub21_upd = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: LDST_dec31_dec_sub21_upd = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: LDST_dec31_dec_sub21_upd = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LDST_dec31_dec_sub21_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LDST_dec31_dec_sub21_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: LDST_dec31_dec_sub21_upd = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LDST_dec31_dec_sub21_upd = 2'h2; endcase end - always @* begin - if (\initial ) begin end - LDST_dec31_dec_sub21_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) - casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h1a: - LDST_dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h1b: - LDST_dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h01: - LDST_dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h00: - LDST_dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h19: - LDST_dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h0b: - LDST_dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h0a: - LDST_dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h18: - LDST_dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h1e: - LDST_dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h1f: - LDST_dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h05: - LDST_dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h04: - LDST_dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h1d: - LDST_dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h1c: - LDST_dec31_dec_sub21_rc_sel = 2'h0; - endcase - end assign opcode_switch = opcode_in[10:6]; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub22" *) (* generator = "nMigen" *) -module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_sub22_internal_op, LDST_dec31_dec_sub22_in1_sel, LDST_dec31_dec_sub22_in2_sel, LDST_dec31_dec_sub22_cr_in, LDST_dec31_dec_sub22_cr_out, LDST_dec31_dec_sub22_ldst_len, LDST_dec31_dec_sub22_upd, LDST_dec31_dec_sub22_rc_sel, LDST_dec31_dec_sub22_br, LDST_dec31_dec_sub22_sgn_ext, LDST_dec31_dec_sub22_is_32b, LDST_dec31_dec_sub22_sgn, opcode_in); +module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_sub22_internal_op, LDST_dec31_dec_sub22_SV_Ptype, LDST_dec31_dec_sub22_in1_sel, LDST_dec31_dec_sub22_in2_sel, LDST_dec31_dec_sub22_cr_in, LDST_dec31_dec_sub22_cr_out, LDST_dec31_dec_sub22_ldst_len, LDST_dec31_dec_sub22_upd, LDST_dec31_dec_sub22_rc_sel, LDST_dec31_dec_sub22_br, LDST_dec31_dec_sub22_sgn_ext, LDST_dec31_dec_sub22_is_32b, LDST_dec31_dec_sub22_sgn, opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] LDST_dec31_dec_sub22_SV_Ptype; + reg [1:0] LDST_dec31_dec_sub22_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_dec_sub22_br; reg LDST_dec31_dec_sub22_br; (* enum_base_type = "CRInSel" *) @@ -12008,7 +12992,7 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec31_dec_sub22_cr_in; reg [2:0] LDST_dec31_dec_sub22_cr_in; (* enum_base_type = "CROutSel" *) @@ -12018,34 +13002,37 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec31_dec_sub22_cr_out; reg [2:0] LDST_dec31_dec_sub22_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] LDST_dec31_dec_sub22_function_unit; - reg [13:0] LDST_dec31_dec_sub22_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] LDST_dec31_dec_sub22_function_unit; + reg [14:0] LDST_dec31_dec_sub22_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec31_dec_sub22_in1_sel; reg [2:0] LDST_dec31_dec_sub22_in1_sel; (* enum_base_type = "In2Sel" *) @@ -12063,7 +13050,8 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LDST_dec31_dec_sub22_in2_sel; reg [3:0] LDST_dec31_dec_sub22_in2_sel; (* enum_base_type = "MicrOp" *) @@ -12141,10 +13129,12 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] LDST_dec31_dec_sub22_internal_op; reg [6:0] LDST_dec31_dec_sub22_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_dec_sub22_is_32b; reg LDST_dec31_dec_sub22_is_32b; (* enum_base_type = "LdstLen" *) @@ -12153,20 +13143,20 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LDST_dec31_dec_sub22_ldst_len; reg [3:0] LDST_dec31_dec_sub22_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LDST_dec31_dec_sub22_rc_sel; reg [1:0] LDST_dec31_dec_sub22_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_dec_sub22_sgn; reg LDST_dec31_dec_sub22_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_dec_sub22_sgn_ext; reg LDST_dec31_dec_sub22_sgn_ext; (* enum_base_type = "LDSTMode" *) @@ -12174,71 +13164,102 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LDST_dec31_dec_sub22_upd; reg [1:0] LDST_dec31_dec_sub22_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - LDST_dec31_dec_sub22_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + LDST_dec31_dec_sub22_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h18: + LDST_dec31_dec_sub22_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + LDST_dec31_dec_sub22_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + LDST_dec31_dec_sub22_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h06: + LDST_dec31_dec_sub22_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1c: + LDST_dec31_dec_sub22_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + LDST_dec31_dec_sub22_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + LDST_dec31_dec_sub22_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h04: + LDST_dec31_dec_sub22_function_unit = 15'h0004; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub22_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - LDST_dec31_dec_sub22_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub22_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - LDST_dec31_dec_sub22_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub22_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: - LDST_dec31_dec_sub22_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub22_rc_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: - LDST_dec31_dec_sub22_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub22_rc_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: - LDST_dec31_dec_sub22_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub22_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: - LDST_dec31_dec_sub22_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub22_rc_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: - LDST_dec31_dec_sub22_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub22_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - LDST_dec31_dec_sub22_function_unit = 14'h0004; + LDST_dec31_dec_sub22_rc_sel = 2'h1; endcase end always @* begin if (\initial ) begin end LDST_dec31_dec_sub22_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: LDST_dec31_dec_sub22_br = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LDST_dec31_dec_sub22_br = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: LDST_dec31_dec_sub22_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: LDST_dec31_dec_sub22_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LDST_dec31_dec_sub22_br = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: LDST_dec31_dec_sub22_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: LDST_dec31_dec_sub22_br = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LDST_dec31_dec_sub22_br = 1'h0; endcase @@ -12246,30 +13267,30 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub22_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: LDST_dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LDST_dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: LDST_dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: LDST_dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LDST_dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: LDST_dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: LDST_dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LDST_dec31_dec_sub22_sgn_ext = 1'h0; endcase @@ -12277,30 +13298,30 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub22_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: LDST_dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LDST_dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: LDST_dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: LDST_dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LDST_dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: LDST_dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: LDST_dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LDST_dec31_dec_sub22_is_32b = 1'h0; endcase @@ -12308,30 +13329,30 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub22_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: LDST_dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LDST_dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: LDST_dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: LDST_dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LDST_dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: LDST_dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: LDST_dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LDST_dec31_dec_sub22_sgn = 1'h0; endcase @@ -12339,61 +13360,92 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub22_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: LDST_dec31_dec_sub22_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LDST_dec31_dec_sub22_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: LDST_dec31_dec_sub22_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: LDST_dec31_dec_sub22_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LDST_dec31_dec_sub22_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: LDST_dec31_dec_sub22_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: LDST_dec31_dec_sub22_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LDST_dec31_dec_sub22_internal_op = 7'h26; endcase end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub22_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h18: + LDST_dec31_dec_sub22_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + LDST_dec31_dec_sub22_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + LDST_dec31_dec_sub22_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h06: + LDST_dec31_dec_sub22_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1c: + LDST_dec31_dec_sub22_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + LDST_dec31_dec_sub22_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + LDST_dec31_dec_sub22_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h04: + LDST_dec31_dec_sub22_SV_Ptype = 2'h2; + endcase + end always @* begin if (\initial ) begin end LDST_dec31_dec_sub22_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: LDST_dec31_dec_sub22_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LDST_dec31_dec_sub22_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: LDST_dec31_dec_sub22_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: LDST_dec31_dec_sub22_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LDST_dec31_dec_sub22_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: LDST_dec31_dec_sub22_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: LDST_dec31_dec_sub22_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LDST_dec31_dec_sub22_in1_sel = 3'h2; endcase @@ -12401,30 +13453,30 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub22_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: LDST_dec31_dec_sub22_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LDST_dec31_dec_sub22_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: LDST_dec31_dec_sub22_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: LDST_dec31_dec_sub22_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LDST_dec31_dec_sub22_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: LDST_dec31_dec_sub22_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: LDST_dec31_dec_sub22_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LDST_dec31_dec_sub22_in2_sel = 4'h1; endcase @@ -12432,30 +13484,30 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub22_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: LDST_dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LDST_dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: LDST_dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: LDST_dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LDST_dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: LDST_dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: LDST_dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LDST_dec31_dec_sub22_cr_in = 3'h0; endcase @@ -12463,30 +13515,30 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub22_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: LDST_dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LDST_dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: LDST_dec31_dec_sub22_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: LDST_dec31_dec_sub22_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LDST_dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: LDST_dec31_dec_sub22_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: LDST_dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LDST_dec31_dec_sub22_cr_out = 3'h1; endcase @@ -12494,30 +13546,30 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub22_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: LDST_dec31_dec_sub22_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LDST_dec31_dec_sub22_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: LDST_dec31_dec_sub22_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: LDST_dec31_dec_sub22_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LDST_dec31_dec_sub22_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: LDST_dec31_dec_sub22_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: LDST_dec31_dec_sub22_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LDST_dec31_dec_sub22_ldst_len = 4'h4; endcase @@ -12525,73 +13577,49 @@ module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub22_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: LDST_dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LDST_dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: LDST_dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: LDST_dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LDST_dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: LDST_dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: LDST_dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LDST_dec31_dec_sub22_upd = 2'h0; endcase end - always @* begin - if (\initial ) begin end - LDST_dec31_dec_sub22_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) - casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h18: - LDST_dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h10: - LDST_dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h15: - LDST_dec31_dec_sub22_rc_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h06: - LDST_dec31_dec_sub22_rc_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h1c: - LDST_dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h16: - LDST_dec31_dec_sub22_rc_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h14: - LDST_dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h04: - LDST_dec31_dec_sub22_rc_sel = 2'h1; - endcase - end assign opcode_switch = opcode_in[10:6]; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub23" *) (* generator = "nMigen" *) -module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_sub23_internal_op, LDST_dec31_dec_sub23_in1_sel, LDST_dec31_dec_sub23_in2_sel, LDST_dec31_dec_sub23_cr_in, LDST_dec31_dec_sub23_cr_out, LDST_dec31_dec_sub23_ldst_len, LDST_dec31_dec_sub23_upd, LDST_dec31_dec_sub23_rc_sel, LDST_dec31_dec_sub23_br, LDST_dec31_dec_sub23_sgn_ext, LDST_dec31_dec_sub23_is_32b, LDST_dec31_dec_sub23_sgn, opcode_in); +module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_sub23_internal_op, LDST_dec31_dec_sub23_SV_Ptype, LDST_dec31_dec_sub23_in1_sel, LDST_dec31_dec_sub23_in2_sel, LDST_dec31_dec_sub23_cr_in, LDST_dec31_dec_sub23_cr_out, LDST_dec31_dec_sub23_ldst_len, LDST_dec31_dec_sub23_upd, LDST_dec31_dec_sub23_rc_sel, LDST_dec31_dec_sub23_br, LDST_dec31_dec_sub23_sgn_ext, LDST_dec31_dec_sub23_is_32b, LDST_dec31_dec_sub23_sgn, opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] LDST_dec31_dec_sub23_SV_Ptype; + reg [1:0] LDST_dec31_dec_sub23_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_dec_sub23_br; reg LDST_dec31_dec_sub23_br; (* enum_base_type = "CRInSel" *) @@ -12603,7 +13631,7 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec31_dec_sub23_cr_in; reg [2:0] LDST_dec31_dec_sub23_cr_in; (* enum_base_type = "CROutSel" *) @@ -12613,34 +13641,37 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec31_dec_sub23_cr_out; reg [2:0] LDST_dec31_dec_sub23_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] LDST_dec31_dec_sub23_function_unit; - reg [13:0] LDST_dec31_dec_sub23_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] LDST_dec31_dec_sub23_function_unit; + reg [14:0] LDST_dec31_dec_sub23_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec31_dec_sub23_in1_sel; reg [2:0] LDST_dec31_dec_sub23_in1_sel; (* enum_base_type = "In2Sel" *) @@ -12658,7 +13689,8 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LDST_dec31_dec_sub23_in2_sel; reg [3:0] LDST_dec31_dec_sub23_in2_sel; (* enum_base_type = "MicrOp" *) @@ -12736,10 +13768,12 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] LDST_dec31_dec_sub23_internal_op; reg [6:0] LDST_dec31_dec_sub23_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_dec_sub23_is_32b; reg LDST_dec31_dec_sub23_is_32b; (* enum_base_type = "LdstLen" *) @@ -12748,20 +13782,20 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LDST_dec31_dec_sub23_ldst_len; reg [3:0] LDST_dec31_dec_sub23_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LDST_dec31_dec_sub23_rc_sel; reg [1:0] LDST_dec31_dec_sub23_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_dec_sub23_sgn; reg LDST_dec31_dec_sub23_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec31_dec_sub23_sgn_ext; reg LDST_dec31_dec_sub23_sgn_ext; (* enum_base_type = "LDSTMode" *) @@ -12769,107 +13803,255 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LDST_dec31_dec_sub23_upd; reg [1:0] LDST_dec31_dec_sub23_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - LDST_dec31_dec_sub23_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + LDST_dec31_dec_sub23_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: - LDST_dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: - LDST_dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + LDST_dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + LDST_dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + LDST_dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + LDST_dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + LDST_dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + LDST_dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: - LDST_dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: - LDST_dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: - LDST_dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: - LDST_dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: - LDST_dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - LDST_dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - LDST_dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: - LDST_dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + LDST_dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + LDST_dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + LDST_dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + LDST_dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + LDST_dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: - LDST_dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: - LDST_dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: - LDST_dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - LDST_dec31_dec_sub23_function_unit = 14'h0004; + LDST_dec31_dec_sub23_function_unit = 15'h0004; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub23_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h03: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h02: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0b: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0a: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h09: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h08: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h01: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h00: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h07: + LDST_dec31_dec_sub23_rc_sel = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h06: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0d: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0c: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h05: + LDST_dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h04: + LDST_dec31_dec_sub23_rc_sel = 2'h0; endcase end always @* begin if (\initial ) begin end LDST_dec31_dec_sub23_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LDST_dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: LDST_dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + LDST_dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + LDST_dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + LDST_dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + LDST_dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + LDST_dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + LDST_dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LDST_dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: LDST_dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: LDST_dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: LDST_dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LDST_dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LDST_dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: LDST_dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: LDST_dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + LDST_dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + LDST_dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + LDST_dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + LDST_dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + LDST_dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: LDST_dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: LDST_dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LDST_dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LDST_dec31_dec_sub23_br = 1'h0; endcase @@ -12877,48 +14059,81 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub23_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LDST_dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: LDST_dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + LDST_dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + LDST_dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + LDST_dec31_dec_sub23_sgn_ext = 1'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + LDST_dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + LDST_dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + LDST_dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LDST_dec31_dec_sub23_sgn_ext = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: LDST_dec31_dec_sub23_sgn_ext = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: LDST_dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: LDST_dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LDST_dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LDST_dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: LDST_dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: LDST_dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + LDST_dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + LDST_dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + LDST_dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + LDST_dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + LDST_dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: LDST_dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: LDST_dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LDST_dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LDST_dec31_dec_sub23_sgn_ext = 1'h0; endcase @@ -12926,48 +14141,81 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub23_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LDST_dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: LDST_dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + LDST_dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + LDST_dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + LDST_dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + LDST_dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + LDST_dec31_dec_sub23_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + LDST_dec31_dec_sub23_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LDST_dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: LDST_dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: LDST_dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: LDST_dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LDST_dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LDST_dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: LDST_dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: LDST_dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + LDST_dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + LDST_dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + LDST_dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + LDST_dec31_dec_sub23_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + LDST_dec31_dec_sub23_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: LDST_dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: LDST_dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LDST_dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LDST_dec31_dec_sub23_is_32b = 1'h0; endcase @@ -12975,48 +14223,81 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub23_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LDST_dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: LDST_dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + LDST_dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + LDST_dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + LDST_dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + LDST_dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + LDST_dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + LDST_dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LDST_dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: LDST_dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: LDST_dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: LDST_dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LDST_dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LDST_dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: LDST_dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: LDST_dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + LDST_dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + LDST_dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + LDST_dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + LDST_dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + LDST_dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: LDST_dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: LDST_dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LDST_dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LDST_dec31_dec_sub23_sgn = 1'h0; endcase @@ -13024,97 +14305,245 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub23_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LDST_dec31_dec_sub23_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: LDST_dec31_dec_sub23_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + LDST_dec31_dec_sub23_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + LDST_dec31_dec_sub23_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + LDST_dec31_dec_sub23_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + LDST_dec31_dec_sub23_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + LDST_dec31_dec_sub23_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + LDST_dec31_dec_sub23_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LDST_dec31_dec_sub23_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: LDST_dec31_dec_sub23_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: LDST_dec31_dec_sub23_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: LDST_dec31_dec_sub23_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LDST_dec31_dec_sub23_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LDST_dec31_dec_sub23_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: LDST_dec31_dec_sub23_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: LDST_dec31_dec_sub23_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + LDST_dec31_dec_sub23_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + LDST_dec31_dec_sub23_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + LDST_dec31_dec_sub23_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + LDST_dec31_dec_sub23_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + LDST_dec31_dec_sub23_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: LDST_dec31_dec_sub23_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: LDST_dec31_dec_sub23_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LDST_dec31_dec_sub23_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LDST_dec31_dec_sub23_internal_op = 7'h26; endcase end + always @* begin + if (\initial ) begin end + LDST_dec31_dec_sub23_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h03: + LDST_dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h02: + LDST_dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + LDST_dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + LDST_dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + LDST_dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + LDST_dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + LDST_dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + LDST_dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0b: + LDST_dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0a: + LDST_dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h09: + LDST_dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h08: + LDST_dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h01: + LDST_dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h00: + LDST_dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h07: + LDST_dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h06: + LDST_dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + LDST_dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + LDST_dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + LDST_dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + LDST_dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + LDST_dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0d: + LDST_dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0c: + LDST_dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h05: + LDST_dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h04: + LDST_dec31_dec_sub23_SV_Ptype = 2'h2; + endcase + end always @* begin if (\initial ) begin end LDST_dec31_dec_sub23_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LDST_dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: LDST_dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + LDST_dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + LDST_dec31_dec_sub23_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + LDST_dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + LDST_dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + LDST_dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + LDST_dec31_dec_sub23_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LDST_dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: LDST_dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: LDST_dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: LDST_dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LDST_dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LDST_dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: LDST_dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: LDST_dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + LDST_dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + LDST_dec31_dec_sub23_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + LDST_dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + LDST_dec31_dec_sub23_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + LDST_dec31_dec_sub23_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: LDST_dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: LDST_dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LDST_dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LDST_dec31_dec_sub23_in1_sel = 3'h2; endcase @@ -13122,48 +14551,81 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub23_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LDST_dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: LDST_dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + LDST_dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + LDST_dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + LDST_dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + LDST_dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + LDST_dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + LDST_dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LDST_dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: LDST_dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: LDST_dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: LDST_dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LDST_dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LDST_dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: LDST_dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: LDST_dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + LDST_dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + LDST_dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + LDST_dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + LDST_dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + LDST_dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: LDST_dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: LDST_dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LDST_dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LDST_dec31_dec_sub23_in2_sel = 4'h1; endcase @@ -13171,48 +14633,81 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub23_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LDST_dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: LDST_dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + LDST_dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + LDST_dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + LDST_dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + LDST_dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + LDST_dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + LDST_dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LDST_dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: LDST_dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: LDST_dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: LDST_dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LDST_dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LDST_dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: LDST_dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: LDST_dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + LDST_dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + LDST_dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + LDST_dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + LDST_dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + LDST_dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: LDST_dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: LDST_dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LDST_dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LDST_dec31_dec_sub23_cr_in = 3'h0; endcase @@ -13220,48 +14715,81 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub23_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LDST_dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: LDST_dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + LDST_dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + LDST_dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + LDST_dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + LDST_dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + LDST_dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + LDST_dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LDST_dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: LDST_dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: LDST_dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: LDST_dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LDST_dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LDST_dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: LDST_dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: LDST_dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + LDST_dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + LDST_dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + LDST_dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + LDST_dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + LDST_dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: LDST_dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: LDST_dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LDST_dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LDST_dec31_dec_sub23_cr_out = 3'h0; endcase @@ -13269,48 +14797,81 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub23_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LDST_dec31_dec_sub23_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: LDST_dec31_dec_sub23_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + LDST_dec31_dec_sub23_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + LDST_dec31_dec_sub23_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + LDST_dec31_dec_sub23_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + LDST_dec31_dec_sub23_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + LDST_dec31_dec_sub23_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + LDST_dec31_dec_sub23_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LDST_dec31_dec_sub23_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: LDST_dec31_dec_sub23_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: LDST_dec31_dec_sub23_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: LDST_dec31_dec_sub23_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LDST_dec31_dec_sub23_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LDST_dec31_dec_sub23_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: LDST_dec31_dec_sub23_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: LDST_dec31_dec_sub23_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + LDST_dec31_dec_sub23_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + LDST_dec31_dec_sub23_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + LDST_dec31_dec_sub23_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + LDST_dec31_dec_sub23_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + LDST_dec31_dec_sub23_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: LDST_dec31_dec_sub23_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: LDST_dec31_dec_sub23_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LDST_dec31_dec_sub23_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LDST_dec31_dec_sub23_ldst_len = 4'h4; endcase @@ -13318,109 +14879,100 @@ module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_s always @* begin if (\initial ) begin end LDST_dec31_dec_sub23_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LDST_dec31_dec_sub23_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: LDST_dec31_dec_sub23_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + LDST_dec31_dec_sub23_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + LDST_dec31_dec_sub23_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + LDST_dec31_dec_sub23_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + LDST_dec31_dec_sub23_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + LDST_dec31_dec_sub23_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + LDST_dec31_dec_sub23_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LDST_dec31_dec_sub23_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: LDST_dec31_dec_sub23_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: LDST_dec31_dec_sub23_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: LDST_dec31_dec_sub23_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LDST_dec31_dec_sub23_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LDST_dec31_dec_sub23_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: LDST_dec31_dec_sub23_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: LDST_dec31_dec_sub23_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + LDST_dec31_dec_sub23_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + LDST_dec31_dec_sub23_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + LDST_dec31_dec_sub23_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + LDST_dec31_dec_sub23_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + LDST_dec31_dec_sub23_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: LDST_dec31_dec_sub23_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: LDST_dec31_dec_sub23_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LDST_dec31_dec_sub23_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LDST_dec31_dec_sub23_upd = 2'h0; endcase end - always @* begin - if (\initial ) begin end - LDST_dec31_dec_sub23_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) - casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h03: - LDST_dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h02: - LDST_dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h0b: - LDST_dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h0a: - LDST_dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h09: - LDST_dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h08: - LDST_dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h01: - LDST_dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h00: - LDST_dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h07: - LDST_dec31_dec_sub23_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h06: - LDST_dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h0d: - LDST_dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h0c: - LDST_dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h05: - LDST_dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h04: - LDST_dec31_dec_sub23_rc_sel = 2'h0; - endcase - end assign opcode_switch = opcode_in[10:6]; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_LDST.dec.LDST_dec58" *) (* generator = "nMigen" *) -module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_in1_sel, LDST_dec58_in2_sel, LDST_dec58_cr_in, LDST_dec58_cr_out, LDST_dec58_ldst_len, LDST_dec58_upd, LDST_dec58_rc_sel, LDST_dec58_br, LDST_dec58_sgn_ext, LDST_dec58_is_32b, LDST_dec58_sgn, opcode_in); +module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_SV_Ptype, LDST_dec58_in1_sel, LDST_dec58_in2_sel, LDST_dec58_cr_in, LDST_dec58_cr_out, LDST_dec58_ldst_len, LDST_dec58_upd, LDST_dec58_rc_sel, LDST_dec58_br, LDST_dec58_sgn_ext, LDST_dec58_is_32b, LDST_dec58_sgn, opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] LDST_dec58_SV_Ptype; + reg [1:0] LDST_dec58_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec58_br; reg LDST_dec58_br; (* enum_base_type = "CRInSel" *) @@ -13432,7 +14984,7 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec58_cr_in; reg [2:0] LDST_dec58_cr_in; (* enum_base_type = "CROutSel" *) @@ -13442,34 +14994,37 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec58_cr_out; reg [2:0] LDST_dec58_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] LDST_dec58_function_unit; - reg [13:0] LDST_dec58_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] LDST_dec58_function_unit; + reg [14:0] LDST_dec58_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec58_in1_sel; reg [2:0] LDST_dec58_in1_sel; (* enum_base_type = "In2Sel" *) @@ -13487,7 +15042,8 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LDST_dec58_in2_sel; reg [3:0] LDST_dec58_in2_sel; (* enum_base_type = "MicrOp" *) @@ -13565,10 +15121,12 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] LDST_dec58_internal_op; reg [6:0] LDST_dec58_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec58_is_32b; reg LDST_dec58_is_32b; (* enum_base_type = "LdstLen" *) @@ -13577,20 +15135,20 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LDST_dec58_ldst_len; reg [3:0] LDST_dec58_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LDST_dec58_rc_sel; reg [1:0] LDST_dec58_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec58_sgn; reg LDST_dec58_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec58_sgn_ext; reg LDST_dec58_sgn_ext; (* enum_base_type = "LDSTMode" *) @@ -13598,41 +15156,57 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LDST_dec58_upd; reg [1:0] LDST_dec58_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [1:0] opcode_switch; always @* begin if (\initial ) begin end - LDST_dec58_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + LDST_dec58_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: - LDST_dec58_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec58_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: - LDST_dec58_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec58_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: - LDST_dec58_function_unit = 14'h0004; + LDST_dec58_function_unit = 15'h0004; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec58_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 2'h0: + LDST_dec58_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 2'h1: + LDST_dec58_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 2'h2: + LDST_dec58_rc_sel = 2'h0; endcase end always @* begin if (\initial ) begin end LDST_dec58_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: LDST_dec58_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: LDST_dec58_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: LDST_dec58_br = 1'h0; endcase @@ -13640,15 +15214,15 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i always @* begin if (\initial ) begin end LDST_dec58_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: LDST_dec58_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: LDST_dec58_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: LDST_dec58_sgn_ext = 1'h1; endcase @@ -13656,15 +15230,15 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i always @* begin if (\initial ) begin end LDST_dec58_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: LDST_dec58_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: LDST_dec58_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: LDST_dec58_is_32b = 1'h0; endcase @@ -13672,15 +15246,15 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i always @* begin if (\initial ) begin end LDST_dec58_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: LDST_dec58_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: LDST_dec58_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: LDST_dec58_sgn = 1'h0; endcase @@ -13688,31 +15262,47 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i always @* begin if (\initial ) begin end LDST_dec58_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: LDST_dec58_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: LDST_dec58_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: LDST_dec58_internal_op = 7'h25; endcase end + always @* begin + if (\initial ) begin end + LDST_dec58_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 2'h0: + LDST_dec58_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 2'h1: + LDST_dec58_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 2'h2: + LDST_dec58_SV_Ptype = 2'h2; + endcase + end always @* begin if (\initial ) begin end LDST_dec58_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: LDST_dec58_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: LDST_dec58_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: LDST_dec58_in1_sel = 3'h2; endcase @@ -13720,15 +15310,15 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i always @* begin if (\initial ) begin end LDST_dec58_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: LDST_dec58_in2_sel = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: LDST_dec58_in2_sel = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: LDST_dec58_in2_sel = 4'h8; endcase @@ -13736,15 +15326,15 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i always @* begin if (\initial ) begin end LDST_dec58_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: LDST_dec58_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: LDST_dec58_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: LDST_dec58_cr_in = 3'h0; endcase @@ -13752,15 +15342,15 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i always @* begin if (\initial ) begin end LDST_dec58_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: LDST_dec58_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: LDST_dec58_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: LDST_dec58_cr_out = 3'h0; endcase @@ -13768,15 +15358,15 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i always @* begin if (\initial ) begin end LDST_dec58_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: LDST_dec58_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: LDST_dec58_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: LDST_dec58_ldst_len = 4'h4; endcase @@ -13784,43 +15374,34 @@ module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_i always @* begin if (\initial ) begin end LDST_dec58_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: LDST_dec58_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: LDST_dec58_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: LDST_dec58_upd = 2'h0; endcase end - always @* begin - if (\initial ) begin end - LDST_dec58_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) - casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 2'h0: - LDST_dec58_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 2'h1: - LDST_dec58_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 2'h2: - LDST_dec58_rc_sel = 2'h0; - endcase - end assign opcode_switch = opcode_in[1:0]; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_LDST.dec.LDST_dec62" *) (* generator = "nMigen" *) -module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_in1_sel, LDST_dec62_in2_sel, LDST_dec62_cr_in, LDST_dec62_cr_out, LDST_dec62_ldst_len, LDST_dec62_upd, LDST_dec62_rc_sel, LDST_dec62_br, LDST_dec62_sgn_ext, LDST_dec62_is_32b, LDST_dec62_sgn, opcode_in); +module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_SV_Ptype, LDST_dec62_in1_sel, LDST_dec62_in2_sel, LDST_dec62_cr_in, LDST_dec62_cr_out, LDST_dec62_ldst_len, LDST_dec62_upd, LDST_dec62_rc_sel, LDST_dec62_br, LDST_dec62_sgn_ext, LDST_dec62_is_32b, LDST_dec62_sgn, opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] LDST_dec62_SV_Ptype; + reg [1:0] LDST_dec62_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec62_br; reg LDST_dec62_br; (* enum_base_type = "CRInSel" *) @@ -13832,7 +15413,7 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec62_cr_in; reg [2:0] LDST_dec62_cr_in; (* enum_base_type = "CROutSel" *) @@ -13842,34 +15423,37 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec62_cr_out; reg [2:0] LDST_dec62_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] LDST_dec62_function_unit; - reg [13:0] LDST_dec62_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] LDST_dec62_function_unit; + reg [14:0] LDST_dec62_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_dec62_in1_sel; reg [2:0] LDST_dec62_in1_sel; (* enum_base_type = "In2Sel" *) @@ -13887,7 +15471,8 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LDST_dec62_in2_sel; reg [3:0] LDST_dec62_in2_sel; (* enum_base_type = "MicrOp" *) @@ -13965,10 +15550,12 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] LDST_dec62_internal_op; reg [6:0] LDST_dec62_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec62_is_32b; reg LDST_dec62_is_32b; (* enum_base_type = "LdstLen" *) @@ -13977,20 +15564,20 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LDST_dec62_ldst_len; reg [3:0] LDST_dec62_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LDST_dec62_rc_sel; reg [1:0] LDST_dec62_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec62_sgn; reg LDST_dec62_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_dec62_sgn_ext; reg LDST_dec62_sgn_ext; (* enum_base_type = "LDSTMode" *) @@ -13998,35 +15585,48 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LDST_dec62_upd; reg [1:0] LDST_dec62_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [1:0] opcode_switch; always @* begin if (\initial ) begin end - LDST_dec62_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + LDST_dec62_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: - LDST_dec62_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_dec62_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: - LDST_dec62_function_unit = 14'h0004; + LDST_dec62_function_unit = 15'h0004; + endcase + end + always @* begin + if (\initial ) begin end + LDST_dec62_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 2'h0: + LDST_dec62_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 2'h1: + LDST_dec62_rc_sel = 2'h0; endcase end always @* begin if (\initial ) begin end LDST_dec62_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: LDST_dec62_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: LDST_dec62_br = 1'h0; endcase @@ -14034,12 +15634,12 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i always @* begin if (\initial ) begin end LDST_dec62_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: LDST_dec62_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: LDST_dec62_sgn_ext = 1'h0; endcase @@ -14047,12 +15647,12 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i always @* begin if (\initial ) begin end LDST_dec62_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: LDST_dec62_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: LDST_dec62_is_32b = 1'h0; endcase @@ -14060,12 +15660,12 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i always @* begin if (\initial ) begin end LDST_dec62_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: LDST_dec62_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: LDST_dec62_sgn = 1'h0; endcase @@ -14073,25 +15673,38 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i always @* begin if (\initial ) begin end LDST_dec62_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: LDST_dec62_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: LDST_dec62_internal_op = 7'h26; endcase end + always @* begin + if (\initial ) begin end + LDST_dec62_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 2'h0: + LDST_dec62_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 2'h1: + LDST_dec62_SV_Ptype = 2'h2; + endcase + end always @* begin if (\initial ) begin end LDST_dec62_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: LDST_dec62_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: LDST_dec62_in1_sel = 3'h2; endcase @@ -14099,12 +15712,12 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i always @* begin if (\initial ) begin end LDST_dec62_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: LDST_dec62_in2_sel = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: LDST_dec62_in2_sel = 4'h8; endcase @@ -14112,12 +15725,12 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i always @* begin if (\initial ) begin end LDST_dec62_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: LDST_dec62_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: LDST_dec62_cr_in = 3'h0; endcase @@ -14125,12 +15738,12 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i always @* begin if (\initial ) begin end LDST_dec62_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: LDST_dec62_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: LDST_dec62_cr_out = 3'h0; endcase @@ -14138,12 +15751,12 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i always @* begin if (\initial ) begin end LDST_dec62_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: LDST_dec62_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: LDST_dec62_ldst_len = 4'h8; endcase @@ -14151,36 +15764,30 @@ module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_i always @* begin if (\initial ) begin end LDST_dec62_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: LDST_dec62_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: LDST_dec62_upd = 2'h1; endcase end - always @* begin - if (\initial ) begin end - LDST_dec62_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) - casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 2'h0: - LDST_dec62_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 2'h1: - LDST_dec62_rc_sel = 2'h0; - endcase - end assign opcode_switch = opcode_in[1:0]; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_LOGICAL.dec.LOGICAL_dec31" *) (* generator = "nMigen" *) -module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOGICAL_dec31_in1_sel, LOGICAL_dec31_in2_sel, LOGICAL_dec31_cr_in, LOGICAL_dec31_cr_out, LOGICAL_dec31_ldst_len, LOGICAL_dec31_rc_sel, LOGICAL_dec31_cry_in, LOGICAL_dec31_inv_a, LOGICAL_dec31_inv_out, LOGICAL_dec31_cry_out, LOGICAL_dec31_is_32b, LOGICAL_dec31_sgn, opcode_in); +module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOGICAL_dec31_SV_Ptype, LOGICAL_dec31_in1_sel, LOGICAL_dec31_in2_sel, LOGICAL_dec31_cr_in, LOGICAL_dec31_cr_out, LOGICAL_dec31_ldst_len, LOGICAL_dec31_rc_sel, LOGICAL_dec31_cry_in, LOGICAL_dec31_inv_a, LOGICAL_dec31_inv_out, LOGICAL_dec31_cry_out, LOGICAL_dec31_is_32b, LOGICAL_dec31_sgn, opcode_in); reg \initial = 0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] LOGICAL_dec31_SV_Ptype; + reg [1:0] LOGICAL_dec31_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -14190,7 +15797,7 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LOGICAL_dec31_cr_in; reg [2:0] LOGICAL_dec31_cr_in; (* enum_base_type = "CROutSel" *) @@ -14200,19 +15807,25 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LOGICAL_dec31_cr_out; reg [2:0] LOGICAL_dec31_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LOGICAL_dec31_cry_in; reg [1:0] LOGICAL_dec31_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_dec31_cry_out; reg LOGICAL_dec31_cry_out; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -14222,7 +15835,7 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -14231,40 +15844,43 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -14281,7 +15897,8 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -14358,13 +15975,15 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -14372,18 +15991,24 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] LOGICAL_dec31_dec_sub26_opcode_in; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -14393,7 +16018,7 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -14402,40 +16027,43 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -14452,7 +16080,8 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -14529,13 +16158,15 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -14543,43 +16174,46 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] LOGICAL_dec31_dec_sub28_opcode_in; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] LOGICAL_dec31_function_unit; - reg [13:0] LOGICAL_dec31_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] LOGICAL_dec31_function_unit; + reg [14:0] LOGICAL_dec31_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LOGICAL_dec31_in1_sel; reg [2:0] LOGICAL_dec31_in1_sel; (* enum_base_type = "In2Sel" *) @@ -14597,7 +16231,8 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LOGICAL_dec31_in2_sel; reg [3:0] LOGICAL_dec31_in2_sel; (* enum_base_type = "MicrOp" *) @@ -14675,16 +16310,18 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] LOGICAL_dec31_internal_op; reg [6:0] LOGICAL_dec31_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_dec31_inv_a; reg LOGICAL_dec31_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_dec31_inv_out; reg LOGICAL_dec31_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_dec31_is_32b; reg LOGICAL_dec31_is_32b; (* enum_base_type = "LdstLen" *) @@ -14693,26 +16330,27 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LOGICAL_dec31_ldst_len; reg [3:0] LOGICAL_dec31_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LOGICAL_dec31_rc_sel; reg [1:0] LOGICAL_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_dec31_sgn; reg LOGICAL_dec31_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:355" *) wire [4:0] opc_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [9:0] opcode_switch; LOGICAL_dec31_dec_sub26 LOGICAL_dec31_dec_sub26 ( + .LOGICAL_dec31_dec_sub26_SV_Ptype(LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_SV_Ptype), .LOGICAL_dec31_dec_sub26_cr_in(LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in), .LOGICAL_dec31_dec_sub26_cr_out(LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out), .LOGICAL_dec31_dec_sub26_cry_in(LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in), @@ -14730,6 +16368,7 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG .opcode_in(LOGICAL_dec31_dec_sub26_opcode_in) ); LOGICAL_dec31_dec_sub28 LOGICAL_dec31_dec_sub28 ( + .LOGICAL_dec31_dec_sub28_SV_Ptype(LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_SV_Ptype), .LOGICAL_dec31_dec_sub28_cr_in(LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in), .LOGICAL_dec31_dec_sub28_cr_out(LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out), .LOGICAL_dec31_dec_sub28_cry_in(LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in), @@ -14746,15 +16385,28 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG .LOGICAL_dec31_dec_sub28_sgn(LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn), .opcode_in(LOGICAL_dec31_dec_sub28_opcode_in) ); + always @* begin + if (\initial ) begin end + LOGICAL_dec31_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1c: + LOGICAL_dec31_cr_out = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + LOGICAL_dec31_cr_out = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out; + endcase + end always @* begin if (\initial ) begin end LOGICAL_dec31_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LOGICAL_dec31_ldst_len = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: LOGICAL_dec31_ldst_len = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len; endcase @@ -14762,12 +16414,12 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG always @* begin if (\initial ) begin end LOGICAL_dec31_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LOGICAL_dec31_rc_sel = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: LOGICAL_dec31_rc_sel = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel; endcase @@ -14775,12 +16427,12 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG always @* begin if (\initial ) begin end LOGICAL_dec31_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LOGICAL_dec31_cry_in = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: LOGICAL_dec31_cry_in = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in; endcase @@ -14788,12 +16440,12 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG always @* begin if (\initial ) begin end LOGICAL_dec31_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LOGICAL_dec31_inv_a = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: LOGICAL_dec31_inv_a = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a; endcase @@ -14801,12 +16453,12 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG always @* begin if (\initial ) begin end LOGICAL_dec31_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LOGICAL_dec31_inv_out = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: LOGICAL_dec31_inv_out = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out; endcase @@ -14814,12 +16466,12 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG always @* begin if (\initial ) begin end LOGICAL_dec31_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LOGICAL_dec31_cry_out = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: LOGICAL_dec31_cry_out = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out; endcase @@ -14827,12 +16479,12 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG always @* begin if (\initial ) begin end LOGICAL_dec31_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LOGICAL_dec31_is_32b = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: LOGICAL_dec31_is_32b = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b; endcase @@ -14840,25 +16492,25 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG always @* begin if (\initial ) begin end LOGICAL_dec31_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LOGICAL_dec31_sgn = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: LOGICAL_dec31_sgn = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn; endcase end always @* begin if (\initial ) begin end - LOGICAL_dec31_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + LOGICAL_dec31_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LOGICAL_dec31_function_unit = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: LOGICAL_dec31_function_unit = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit; endcase @@ -14866,25 +16518,38 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG always @* begin if (\initial ) begin end LOGICAL_dec31_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LOGICAL_dec31_internal_op = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: LOGICAL_dec31_internal_op = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op; endcase end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1c: + LOGICAL_dec31_SV_Ptype = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + LOGICAL_dec31_SV_Ptype = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_SV_Ptype; + endcase + end always @* begin if (\initial ) begin end LOGICAL_dec31_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LOGICAL_dec31_in1_sel = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: LOGICAL_dec31_in1_sel = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel; endcase @@ -14892,12 +16557,12 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG always @* begin if (\initial ) begin end LOGICAL_dec31_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LOGICAL_dec31_in2_sel = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: LOGICAL_dec31_in2_sel = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel; endcase @@ -14905,29 +16570,16 @@ module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOG always @* begin if (\initial ) begin end LOGICAL_dec31_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: LOGICAL_dec31_cr_in = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: LOGICAL_dec31_cr_in = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in; endcase end - always @* begin - if (\initial ) begin end - LOGICAL_dec31_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) - casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h1c: - LOGICAL_dec31_cr_out = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h1a: - LOGICAL_dec31_cr_out = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out; - endcase - end assign LOGICAL_dec31_dec_sub26_opcode_in = opcode_in; assign LOGICAL_dec31_dec_sub28_opcode_in = opcode_in; assign opc_in = opcode_switch[4:0]; @@ -14936,8 +16588,15 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec31_dec_sub26" *) (* generator = "nMigen" *) -module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_dec31_dec_sub26_internal_op, LOGICAL_dec31_dec_sub26_in1_sel, LOGICAL_dec31_dec_sub26_in2_sel, LOGICAL_dec31_dec_sub26_cr_in, LOGICAL_dec31_dec_sub26_cr_out, LOGICAL_dec31_dec_sub26_ldst_len, LOGICAL_dec31_dec_sub26_rc_sel, LOGICAL_dec31_dec_sub26_cry_in, LOGICAL_dec31_dec_sub26_inv_a, LOGICAL_dec31_dec_sub26_inv_out, LOGICAL_dec31_dec_sub26_cry_out, LOGICAL_dec31_dec_sub26_is_32b, LOGICAL_dec31_dec_sub26_sgn, opcode_in); +module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_dec31_dec_sub26_internal_op, LOGICAL_dec31_dec_sub26_SV_Ptype, LOGICAL_dec31_dec_sub26_in1_sel, LOGICAL_dec31_dec_sub26_in2_sel, LOGICAL_dec31_dec_sub26_cr_in, LOGICAL_dec31_dec_sub26_cr_out, LOGICAL_dec31_dec_sub26_ldst_len, LOGICAL_dec31_dec_sub26_rc_sel, LOGICAL_dec31_dec_sub26_cry_in, LOGICAL_dec31_dec_sub26_inv_a, LOGICAL_dec31_dec_sub26_inv_out, LOGICAL_dec31_dec_sub26_cry_out, LOGICAL_dec31_dec_sub26_is_32b, LOGICAL_dec31_dec_sub26_sgn, opcode_in); reg \initial = 0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] LOGICAL_dec31_dec_sub26_SV_Ptype; + reg [1:0] LOGICAL_dec31_dec_sub26_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -14947,7 +16606,7 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LOGICAL_dec31_dec_sub26_cr_in; reg [2:0] LOGICAL_dec31_dec_sub26_cr_in; (* enum_base_type = "CROutSel" *) @@ -14957,44 +16616,47 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LOGICAL_dec31_dec_sub26_cr_out; reg [2:0] LOGICAL_dec31_dec_sub26_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LOGICAL_dec31_dec_sub26_cry_in; reg [1:0] LOGICAL_dec31_dec_sub26_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_dec31_dec_sub26_cry_out; reg LOGICAL_dec31_dec_sub26_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] LOGICAL_dec31_dec_sub26_function_unit; - reg [13:0] LOGICAL_dec31_dec_sub26_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] LOGICAL_dec31_dec_sub26_function_unit; + reg [14:0] LOGICAL_dec31_dec_sub26_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LOGICAL_dec31_dec_sub26_in1_sel; reg [2:0] LOGICAL_dec31_dec_sub26_in1_sel; (* enum_base_type = "In2Sel" *) @@ -15012,7 +16674,8 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LOGICAL_dec31_dec_sub26_in2_sel; reg [3:0] LOGICAL_dec31_dec_sub26_in2_sel; (* enum_base_type = "MicrOp" *) @@ -15090,16 +16753,18 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] LOGICAL_dec31_dec_sub26_internal_op; reg [6:0] LOGICAL_dec31_dec_sub26_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_dec31_dec_sub26_inv_a; reg LOGICAL_dec31_dec_sub26_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_dec31_dec_sub26_inv_out; reg LOGICAL_dec31_dec_sub26_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_dec31_dec_sub26_is_32b; reg LOGICAL_dec31_dec_sub26_is_32b; (* enum_base_type = "LdstLen" *) @@ -15108,87 +16773,121 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LOGICAL_dec31_dec_sub26_ldst_len; reg [3:0] LOGICAL_dec31_dec_sub26_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LOGICAL_dec31_dec_sub26_rc_sel; reg [1:0] LOGICAL_dec31_dec_sub26_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_dec31_dec_sub26_sgn; reg LOGICAL_dec31_dec_sub26_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - LOGICAL_dec31_dec_sub26_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + LOGICAL_dec31_dec_sub26_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h01: + LOGICAL_dec31_dec_sub26_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h00: + LOGICAL_dec31_dec_sub26_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + LOGICAL_dec31_dec_sub26_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + LOGICAL_dec31_dec_sub26_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h03: + LOGICAL_dec31_dec_sub26_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0f: + LOGICAL_dec31_dec_sub26_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0b: + LOGICAL_dec31_dec_sub26_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h05: + LOGICAL_dec31_dec_sub26_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h04: + LOGICAL_dec31_dec_sub26_function_unit = 15'h0010; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_dec_sub26_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: - LOGICAL_dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LOGICAL_dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - LOGICAL_dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LOGICAL_dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: - LOGICAL_dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LOGICAL_dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - LOGICAL_dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LOGICAL_dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: - LOGICAL_dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LOGICAL_dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: - LOGICAL_dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LOGICAL_dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: - LOGICAL_dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LOGICAL_dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: - LOGICAL_dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LOGICAL_dec31_dec_sub26_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - LOGICAL_dec31_dec_sub26_function_unit = 14'h0010; + LOGICAL_dec31_dec_sub26_cry_in = 2'h0; endcase end always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub26_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LOGICAL_dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LOGICAL_dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: LOGICAL_dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LOGICAL_dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LOGICAL_dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: LOGICAL_dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LOGICAL_dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LOGICAL_dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LOGICAL_dec31_dec_sub26_inv_a = 1'h0; endcase @@ -15196,33 +16895,33 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub26_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LOGICAL_dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LOGICAL_dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: LOGICAL_dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LOGICAL_dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LOGICAL_dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: LOGICAL_dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LOGICAL_dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LOGICAL_dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LOGICAL_dec31_dec_sub26_inv_out = 1'h0; endcase @@ -15230,33 +16929,33 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub26_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LOGICAL_dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LOGICAL_dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: LOGICAL_dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LOGICAL_dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LOGICAL_dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: LOGICAL_dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LOGICAL_dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LOGICAL_dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LOGICAL_dec31_dec_sub26_cry_out = 1'h0; endcase @@ -15264,33 +16963,33 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub26_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LOGICAL_dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LOGICAL_dec31_dec_sub26_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: LOGICAL_dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LOGICAL_dec31_dec_sub26_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LOGICAL_dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: LOGICAL_dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LOGICAL_dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LOGICAL_dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LOGICAL_dec31_dec_sub26_is_32b = 1'h0; endcase @@ -15298,33 +16997,33 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub26_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LOGICAL_dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LOGICAL_dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: LOGICAL_dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LOGICAL_dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LOGICAL_dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: LOGICAL_dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LOGICAL_dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LOGICAL_dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LOGICAL_dec31_dec_sub26_sgn = 1'h0; endcase @@ -15332,67 +17031,101 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub26_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LOGICAL_dec31_dec_sub26_internal_op = 7'h0e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LOGICAL_dec31_dec_sub26_internal_op = 7'h0e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: LOGICAL_dec31_dec_sub26_internal_op = 7'h0e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LOGICAL_dec31_dec_sub26_internal_op = 7'h0e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LOGICAL_dec31_dec_sub26_internal_op = 7'h36; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: LOGICAL_dec31_dec_sub26_internal_op = 7'h36; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LOGICAL_dec31_dec_sub26_internal_op = 7'h36; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LOGICAL_dec31_dec_sub26_internal_op = 7'h37; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LOGICAL_dec31_dec_sub26_internal_op = 7'h37; endcase end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_dec_sub26_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h01: + LOGICAL_dec31_dec_sub26_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h00: + LOGICAL_dec31_dec_sub26_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + LOGICAL_dec31_dec_sub26_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + LOGICAL_dec31_dec_sub26_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h03: + LOGICAL_dec31_dec_sub26_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0f: + LOGICAL_dec31_dec_sub26_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0b: + LOGICAL_dec31_dec_sub26_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h05: + LOGICAL_dec31_dec_sub26_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h04: + LOGICAL_dec31_dec_sub26_SV_Ptype = 2'h2; + endcase + end always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub26_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LOGICAL_dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LOGICAL_dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: LOGICAL_dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LOGICAL_dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LOGICAL_dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: LOGICAL_dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LOGICAL_dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LOGICAL_dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LOGICAL_dec31_dec_sub26_in1_sel = 3'h4; endcase @@ -15400,33 +17133,33 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub26_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LOGICAL_dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LOGICAL_dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: LOGICAL_dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LOGICAL_dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LOGICAL_dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: LOGICAL_dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LOGICAL_dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LOGICAL_dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LOGICAL_dec31_dec_sub26_in2_sel = 4'h0; endcase @@ -15434,33 +17167,33 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub26_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LOGICAL_dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LOGICAL_dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: LOGICAL_dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LOGICAL_dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LOGICAL_dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: LOGICAL_dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LOGICAL_dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LOGICAL_dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LOGICAL_dec31_dec_sub26_cr_in = 3'h0; endcase @@ -15468,33 +17201,33 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub26_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LOGICAL_dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LOGICAL_dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: LOGICAL_dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LOGICAL_dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LOGICAL_dec31_dec_sub26_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: LOGICAL_dec31_dec_sub26_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LOGICAL_dec31_dec_sub26_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LOGICAL_dec31_dec_sub26_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LOGICAL_dec31_dec_sub26_cr_out = 3'h0; endcase @@ -15502,33 +17235,33 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub26_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LOGICAL_dec31_dec_sub26_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LOGICAL_dec31_dec_sub26_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: LOGICAL_dec31_dec_sub26_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LOGICAL_dec31_dec_sub26_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LOGICAL_dec31_dec_sub26_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: LOGICAL_dec31_dec_sub26_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LOGICAL_dec31_dec_sub26_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LOGICAL_dec31_dec_sub26_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LOGICAL_dec31_dec_sub26_ldst_len = 4'h4; endcase @@ -15536,78 +17269,51 @@ module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub26_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LOGICAL_dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LOGICAL_dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: LOGICAL_dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: LOGICAL_dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LOGICAL_dec31_dec_sub26_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: LOGICAL_dec31_dec_sub26_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: LOGICAL_dec31_dec_sub26_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: LOGICAL_dec31_dec_sub26_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: LOGICAL_dec31_dec_sub26_rc_sel = 2'h0; endcase end - always @* begin - if (\initial ) begin end - LOGICAL_dec31_dec_sub26_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) - casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h01: - LOGICAL_dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h00: - LOGICAL_dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h11: - LOGICAL_dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h10: - LOGICAL_dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h03: - LOGICAL_dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h0f: - LOGICAL_dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h0b: - LOGICAL_dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h05: - LOGICAL_dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h04: - LOGICAL_dec31_dec_sub26_cry_in = 2'h0; - endcase - end assign opcode_switch = opcode_in[10:6]; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec31_dec_sub28" *) (* generator = "nMigen" *) -module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_dec31_dec_sub28_internal_op, LOGICAL_dec31_dec_sub28_in1_sel, LOGICAL_dec31_dec_sub28_in2_sel, LOGICAL_dec31_dec_sub28_cr_in, LOGICAL_dec31_dec_sub28_cr_out, LOGICAL_dec31_dec_sub28_ldst_len, LOGICAL_dec31_dec_sub28_rc_sel, LOGICAL_dec31_dec_sub28_cry_in, LOGICAL_dec31_dec_sub28_inv_a, LOGICAL_dec31_dec_sub28_inv_out, LOGICAL_dec31_dec_sub28_cry_out, LOGICAL_dec31_dec_sub28_is_32b, LOGICAL_dec31_dec_sub28_sgn, opcode_in); +module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_dec31_dec_sub28_internal_op, LOGICAL_dec31_dec_sub28_SV_Ptype, LOGICAL_dec31_dec_sub28_in1_sel, LOGICAL_dec31_dec_sub28_in2_sel, LOGICAL_dec31_dec_sub28_cr_in, LOGICAL_dec31_dec_sub28_cr_out, LOGICAL_dec31_dec_sub28_ldst_len, LOGICAL_dec31_dec_sub28_rc_sel, LOGICAL_dec31_dec_sub28_cry_in, LOGICAL_dec31_dec_sub28_inv_a, LOGICAL_dec31_dec_sub28_inv_out, LOGICAL_dec31_dec_sub28_cry_out, LOGICAL_dec31_dec_sub28_is_32b, LOGICAL_dec31_dec_sub28_sgn, opcode_in); reg \initial = 0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] LOGICAL_dec31_dec_sub28_SV_Ptype; + reg [1:0] LOGICAL_dec31_dec_sub28_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -15617,7 +17323,7 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LOGICAL_dec31_dec_sub28_cr_in; reg [2:0] LOGICAL_dec31_dec_sub28_cr_in; (* enum_base_type = "CROutSel" *) @@ -15627,44 +17333,47 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LOGICAL_dec31_dec_sub28_cr_out; reg [2:0] LOGICAL_dec31_dec_sub28_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LOGICAL_dec31_dec_sub28_cry_in; reg [1:0] LOGICAL_dec31_dec_sub28_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_dec31_dec_sub28_cry_out; reg LOGICAL_dec31_dec_sub28_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] LOGICAL_dec31_dec_sub28_function_unit; - reg [13:0] LOGICAL_dec31_dec_sub28_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] LOGICAL_dec31_dec_sub28_function_unit; + reg [14:0] LOGICAL_dec31_dec_sub28_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LOGICAL_dec31_dec_sub28_in1_sel; reg [2:0] LOGICAL_dec31_dec_sub28_in1_sel; (* enum_base_type = "In2Sel" *) @@ -15682,7 +17391,8 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LOGICAL_dec31_dec_sub28_in2_sel; reg [3:0] LOGICAL_dec31_dec_sub28_in2_sel; (* enum_base_type = "MicrOp" *) @@ -15760,16 +17470,18 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] LOGICAL_dec31_dec_sub28_internal_op; reg [6:0] LOGICAL_dec31_dec_sub28_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_dec31_dec_sub28_inv_a; reg LOGICAL_dec31_dec_sub28_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_dec31_dec_sub28_inv_out; reg LOGICAL_dec31_dec_sub28_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_dec31_dec_sub28_is_32b; reg LOGICAL_dec31_dec_sub28_is_32b; (* enum_base_type = "LdstLen" *) @@ -15778,93 +17490,130 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LOGICAL_dec31_dec_sub28_ldst_len; reg [3:0] LOGICAL_dec31_dec_sub28_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LOGICAL_dec31_dec_sub28_rc_sel; reg [1:0] LOGICAL_dec31_dec_sub28_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_dec31_dec_sub28_sgn; reg LOGICAL_dec31_dec_sub28_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - LOGICAL_dec31_dec_sub28_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + LOGICAL_dec31_dec_sub28_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h00: + LOGICAL_dec31_dec_sub28_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h01: + LOGICAL_dec31_dec_sub28_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h07: + LOGICAL_dec31_dec_sub28_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0f: + LOGICAL_dec31_dec_sub28_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h08: + LOGICAL_dec31_dec_sub28_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0e: + LOGICAL_dec31_dec_sub28_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h03: + LOGICAL_dec31_dec_sub28_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0d: + LOGICAL_dec31_dec_sub28_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0c: + LOGICAL_dec31_dec_sub28_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h09: + LOGICAL_dec31_dec_sub28_function_unit = 15'h0010; + endcase + end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_dec_sub28_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - LOGICAL_dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LOGICAL_dec31_dec_sub28_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: - LOGICAL_dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LOGICAL_dec31_dec_sub28_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - LOGICAL_dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LOGICAL_dec31_dec_sub28_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: - LOGICAL_dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LOGICAL_dec31_dec_sub28_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: - LOGICAL_dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LOGICAL_dec31_dec_sub28_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: - LOGICAL_dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LOGICAL_dec31_dec_sub28_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: - LOGICAL_dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LOGICAL_dec31_dec_sub28_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: - LOGICAL_dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LOGICAL_dec31_dec_sub28_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: - LOGICAL_dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LOGICAL_dec31_dec_sub28_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: - LOGICAL_dec31_dec_sub28_function_unit = 14'h0010; + LOGICAL_dec31_dec_sub28_cry_in = 2'h0; endcase end always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub28_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LOGICAL_dec31_dec_sub28_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LOGICAL_dec31_dec_sub28_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: LOGICAL_dec31_dec_sub28_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: LOGICAL_dec31_dec_sub28_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: LOGICAL_dec31_dec_sub28_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: LOGICAL_dec31_dec_sub28_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LOGICAL_dec31_dec_sub28_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: LOGICAL_dec31_dec_sub28_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: LOGICAL_dec31_dec_sub28_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: LOGICAL_dec31_dec_sub28_inv_a = 1'h0; endcase @@ -15872,36 +17621,36 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub28_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LOGICAL_dec31_dec_sub28_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LOGICAL_dec31_dec_sub28_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: LOGICAL_dec31_dec_sub28_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: LOGICAL_dec31_dec_sub28_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: LOGICAL_dec31_dec_sub28_inv_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: LOGICAL_dec31_dec_sub28_inv_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LOGICAL_dec31_dec_sub28_inv_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: LOGICAL_dec31_dec_sub28_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: LOGICAL_dec31_dec_sub28_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: LOGICAL_dec31_dec_sub28_inv_out = 1'h0; endcase @@ -15909,36 +17658,36 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub28_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LOGICAL_dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LOGICAL_dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: LOGICAL_dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: LOGICAL_dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: LOGICAL_dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: LOGICAL_dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LOGICAL_dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: LOGICAL_dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: LOGICAL_dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: LOGICAL_dec31_dec_sub28_cry_out = 1'h0; endcase @@ -15946,36 +17695,36 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub28_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LOGICAL_dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LOGICAL_dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: LOGICAL_dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: LOGICAL_dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: LOGICAL_dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: LOGICAL_dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LOGICAL_dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: LOGICAL_dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: LOGICAL_dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: LOGICAL_dec31_dec_sub28_is_32b = 1'h0; endcase @@ -15983,36 +17732,36 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub28_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LOGICAL_dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LOGICAL_dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: LOGICAL_dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: LOGICAL_dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: LOGICAL_dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: LOGICAL_dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LOGICAL_dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: LOGICAL_dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: LOGICAL_dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: LOGICAL_dec31_dec_sub28_sgn = 1'h0; endcase @@ -16020,73 +17769,110 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub28_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LOGICAL_dec31_dec_sub28_internal_op = 7'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LOGICAL_dec31_dec_sub28_internal_op = 7'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: LOGICAL_dec31_dec_sub28_internal_op = 7'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: LOGICAL_dec31_dec_sub28_internal_op = 7'h0b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: LOGICAL_dec31_dec_sub28_internal_op = 7'h43; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: LOGICAL_dec31_dec_sub28_internal_op = 7'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LOGICAL_dec31_dec_sub28_internal_op = 7'h35; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: LOGICAL_dec31_dec_sub28_internal_op = 7'h35; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: LOGICAL_dec31_dec_sub28_internal_op = 7'h35; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: LOGICAL_dec31_dec_sub28_internal_op = 7'h43; endcase end + always @* begin + if (\initial ) begin end + LOGICAL_dec31_dec_sub28_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h00: + LOGICAL_dec31_dec_sub28_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h01: + LOGICAL_dec31_dec_sub28_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h07: + LOGICAL_dec31_dec_sub28_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0f: + LOGICAL_dec31_dec_sub28_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h08: + LOGICAL_dec31_dec_sub28_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0e: + LOGICAL_dec31_dec_sub28_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h03: + LOGICAL_dec31_dec_sub28_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0d: + LOGICAL_dec31_dec_sub28_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0c: + LOGICAL_dec31_dec_sub28_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h09: + LOGICAL_dec31_dec_sub28_SV_Ptype = 2'h1; + endcase + end always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub28_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LOGICAL_dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LOGICAL_dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: LOGICAL_dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: LOGICAL_dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: LOGICAL_dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: LOGICAL_dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LOGICAL_dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: LOGICAL_dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: LOGICAL_dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: LOGICAL_dec31_dec_sub28_in1_sel = 3'h4; endcase @@ -16094,36 +17880,36 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub28_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LOGICAL_dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LOGICAL_dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: LOGICAL_dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: LOGICAL_dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: LOGICAL_dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: LOGICAL_dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LOGICAL_dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: LOGICAL_dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: LOGICAL_dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: LOGICAL_dec31_dec_sub28_in2_sel = 4'h1; endcase @@ -16131,36 +17917,36 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub28_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LOGICAL_dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LOGICAL_dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: LOGICAL_dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: LOGICAL_dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: LOGICAL_dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: LOGICAL_dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LOGICAL_dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: LOGICAL_dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: LOGICAL_dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: LOGICAL_dec31_dec_sub28_cr_in = 3'h0; endcase @@ -16168,36 +17954,36 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub28_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LOGICAL_dec31_dec_sub28_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LOGICAL_dec31_dec_sub28_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: LOGICAL_dec31_dec_sub28_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: LOGICAL_dec31_dec_sub28_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: LOGICAL_dec31_dec_sub28_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: LOGICAL_dec31_dec_sub28_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LOGICAL_dec31_dec_sub28_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: LOGICAL_dec31_dec_sub28_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: LOGICAL_dec31_dec_sub28_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: LOGICAL_dec31_dec_sub28_cr_out = 3'h1; endcase @@ -16205,36 +17991,36 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub28_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LOGICAL_dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LOGICAL_dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: LOGICAL_dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: LOGICAL_dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: LOGICAL_dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: LOGICAL_dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LOGICAL_dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: LOGICAL_dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: LOGICAL_dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: LOGICAL_dec31_dec_sub28_ldst_len = 4'h0; endcase @@ -16242,84 +18028,54 @@ module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_de always @* begin if (\initial ) begin end LOGICAL_dec31_dec_sub28_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: LOGICAL_dec31_dec_sub28_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: LOGICAL_dec31_dec_sub28_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: LOGICAL_dec31_dec_sub28_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: LOGICAL_dec31_dec_sub28_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: LOGICAL_dec31_dec_sub28_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: LOGICAL_dec31_dec_sub28_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: LOGICAL_dec31_dec_sub28_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: LOGICAL_dec31_dec_sub28_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: LOGICAL_dec31_dec_sub28_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: LOGICAL_dec31_dec_sub28_rc_sel = 2'h2; endcase end - always @* begin - if (\initial ) begin end - LOGICAL_dec31_dec_sub28_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) - casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h00: - LOGICAL_dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h01: - LOGICAL_dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h07: - LOGICAL_dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h0f: - LOGICAL_dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h08: - LOGICAL_dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h0e: - LOGICAL_dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h03: - LOGICAL_dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h0d: - LOGICAL_dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h0c: - LOGICAL_dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h09: - LOGICAL_dec31_dec_sub28_cry_in = 2'h0; - endcase - end assign opcode_switch = opcode_in[10:6]; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_MUL.dec.MUL_dec31" *) (* generator = "nMigen" *) -module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_sel, MUL_dec31_cr_in, MUL_dec31_cr_out, MUL_dec31_rc_sel, MUL_dec31_is_32b, MUL_dec31_sgn, opcode_in); +module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_SV_Ptype, MUL_dec31_in2_sel, MUL_dec31_cr_in, MUL_dec31_cr_out, MUL_dec31_rc_sel, MUL_dec31_is_32b, MUL_dec31_sgn, opcode_in); reg \initial = 0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] MUL_dec31_SV_Ptype; + reg [1:0] MUL_dec31_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -16329,7 +18085,7 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] MUL_dec31_cr_in; reg [2:0] MUL_dec31_cr_in; (* enum_base_type = "CROutSel" *) @@ -16339,9 +18095,15 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] MUL_dec31_cr_out; reg [2:0] MUL_dec31_cr_out; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -16351,7 +18113,7 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -16360,25 +18122,26 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -16394,7 +18157,8 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -16471,20 +18235,28 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] MUL_dec31_dec_sub11_opcode_in; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -16494,7 +18266,7 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -16503,25 +18275,26 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -16537,7 +18310,8 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -16614,38 +18388,41 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] MUL_dec31_dec_sub9_opcode_in; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] MUL_dec31_function_unit; - reg [13:0] MUL_dec31_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] MUL_dec31_function_unit; + reg [14:0] MUL_dec31_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -16661,7 +18438,8 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] MUL_dec31_in2_sel; reg [3:0] MUL_dec31_in2_sel; (* enum_base_type = "MicrOp" *) @@ -16739,29 +18517,32 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] MUL_dec31_internal_op; reg [6:0] MUL_dec31_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output MUL_dec31_is_32b; reg MUL_dec31_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] MUL_dec31_rc_sel; reg [1:0] MUL_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output MUL_dec31_sgn; reg MUL_dec31_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:355" *) wire [4:0] opc_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [9:0] opcode_switch; MUL_dec31_dec_sub11 MUL_dec31_dec_sub11 ( + .MUL_dec31_dec_sub11_SV_Ptype(MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_SV_Ptype), .MUL_dec31_dec_sub11_cr_in(MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in), .MUL_dec31_dec_sub11_cr_out(MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out), .MUL_dec31_dec_sub11_function_unit(MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit), @@ -16773,6 +18554,7 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s .opcode_in(MUL_dec31_dec_sub11_opcode_in) ); MUL_dec31_dec_sub9 MUL_dec31_dec_sub9 ( + .MUL_dec31_dec_sub9_SV_Ptype(MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_SV_Ptype), .MUL_dec31_dec_sub9_cr_in(MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in), .MUL_dec31_dec_sub9_cr_out(MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out), .MUL_dec31_dec_sub9_function_unit(MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit), @@ -16783,15 +18565,28 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s .MUL_dec31_dec_sub9_sgn(MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn), .opcode_in(MUL_dec31_dec_sub9_opcode_in) ); + always @* begin + if (\initial ) begin end + MUL_dec31_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h09: + MUL_dec31_rc_sel = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0b: + MUL_dec31_rc_sel = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel; + endcase + end always @* begin if (\initial ) begin end MUL_dec31_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: MUL_dec31_is_32b = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: MUL_dec31_is_32b = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b; endcase @@ -16799,25 +18594,25 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s always @* begin if (\initial ) begin end MUL_dec31_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: MUL_dec31_sgn = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: MUL_dec31_sgn = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn; endcase end always @* begin if (\initial ) begin end - MUL_dec31_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + MUL_dec31_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: MUL_dec31_function_unit = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: MUL_dec31_function_unit = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit; endcase @@ -16825,25 +18620,38 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s always @* begin if (\initial ) begin end MUL_dec31_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: MUL_dec31_internal_op = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: MUL_dec31_internal_op = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op; endcase end + always @* begin + if (\initial ) begin end + MUL_dec31_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h09: + MUL_dec31_SV_Ptype = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0b: + MUL_dec31_SV_Ptype = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_SV_Ptype; + endcase + end always @* begin if (\initial ) begin end MUL_dec31_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: MUL_dec31_in2_sel = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: MUL_dec31_in2_sel = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel; endcase @@ -16851,12 +18659,12 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s always @* begin if (\initial ) begin end MUL_dec31_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: MUL_dec31_cr_in = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: MUL_dec31_cr_in = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in; endcase @@ -16864,29 +18672,16 @@ module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_s always @* begin if (\initial ) begin end MUL_dec31_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: MUL_dec31_cr_out = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: MUL_dec31_cr_out = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out; endcase end - always @* begin - if (\initial ) begin end - MUL_dec31_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) - casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h09: - MUL_dec31_rc_sel = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h0b: - MUL_dec31_rc_sel = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel; - endcase - end assign MUL_dec31_dec_sub11_opcode_in = opcode_in; assign MUL_dec31_dec_sub9_opcode_in = opcode_in; assign opc_in = opcode_switch[4:0]; @@ -16895,8 +18690,15 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_MUL.dec.MUL_dec31.MUL_dec31_dec_sub11" *) (* generator = "nMigen" *) -module MUL_dec31_dec_sub11(MUL_dec31_dec_sub11_function_unit, MUL_dec31_dec_sub11_internal_op, MUL_dec31_dec_sub11_in2_sel, MUL_dec31_dec_sub11_cr_in, MUL_dec31_dec_sub11_cr_out, MUL_dec31_dec_sub11_rc_sel, MUL_dec31_dec_sub11_is_32b, MUL_dec31_dec_sub11_sgn, opcode_in); +module MUL_dec31_dec_sub11(MUL_dec31_dec_sub11_function_unit, MUL_dec31_dec_sub11_internal_op, MUL_dec31_dec_sub11_SV_Ptype, MUL_dec31_dec_sub11_in2_sel, MUL_dec31_dec_sub11_cr_in, MUL_dec31_dec_sub11_cr_out, MUL_dec31_dec_sub11_rc_sel, MUL_dec31_dec_sub11_is_32b, MUL_dec31_dec_sub11_sgn, opcode_in); reg \initial = 0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] MUL_dec31_dec_sub11_SV_Ptype; + reg [1:0] MUL_dec31_dec_sub11_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -16906,7 +18708,7 @@ module MUL_dec31_dec_sub11(MUL_dec31_dec_sub11_function_unit, MUL_dec31_dec_sub1 (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] MUL_dec31_dec_sub11_cr_in; reg [2:0] MUL_dec31_dec_sub11_cr_in; (* enum_base_type = "CROutSel" *) @@ -16916,27 +18718,28 @@ module MUL_dec31_dec_sub11(MUL_dec31_dec_sub11_function_unit, MUL_dec31_dec_sub1 (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] MUL_dec31_dec_sub11_cr_out; reg [2:0] MUL_dec31_dec_sub11_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] MUL_dec31_dec_sub11_function_unit; - reg [13:0] MUL_dec31_dec_sub11_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] MUL_dec31_dec_sub11_function_unit; + reg [14:0] MUL_dec31_dec_sub11_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -16952,7 +18755,8 @@ module MUL_dec31_dec_sub11(MUL_dec31_dec_sub11_function_unit, MUL_dec31_dec_sub1 (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] MUL_dec31_dec_sub11_in2_sel; reg [3:0] MUL_dec31_dec_sub11_in2_sel; (* enum_base_type = "MicrOp" *) @@ -17030,97 +18834,124 @@ module MUL_dec31_dec_sub11(MUL_dec31_dec_sub11_function_unit, MUL_dec31_dec_sub1 (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] MUL_dec31_dec_sub11_internal_op; reg [6:0] MUL_dec31_dec_sub11_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output MUL_dec31_dec_sub11_is_32b; reg MUL_dec31_dec_sub11_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] MUL_dec31_dec_sub11_rc_sel; reg [1:0] MUL_dec31_dec_sub11_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output MUL_dec31_dec_sub11_sgn; reg MUL_dec31_dec_sub11_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - MUL_dec31_dec_sub11_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + MUL_dec31_dec_sub11_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: - MUL_dec31_dec_sub11_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + MUL_dec31_dec_sub11_function_unit = 15'h0100; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - MUL_dec31_dec_sub11_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + MUL_dec31_dec_sub11_function_unit = 15'h0100; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: - MUL_dec31_dec_sub11_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + MUL_dec31_dec_sub11_function_unit = 15'h0100; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - MUL_dec31_dec_sub11_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + MUL_dec31_dec_sub11_function_unit = 15'h0100; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - MUL_dec31_dec_sub11_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + MUL_dec31_dec_sub11_function_unit = 15'h0100; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: - MUL_dec31_dec_sub11_function_unit = 14'h0100; + MUL_dec31_dec_sub11_function_unit = 15'h0100; endcase end always @* begin if (\initial ) begin end MUL_dec31_dec_sub11_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: MUL_dec31_dec_sub11_internal_op = 7'h34; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: MUL_dec31_dec_sub11_internal_op = 7'h34; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: MUL_dec31_dec_sub11_internal_op = 7'h34; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: MUL_dec31_dec_sub11_internal_op = 7'h34; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: MUL_dec31_dec_sub11_internal_op = 7'h32; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: MUL_dec31_dec_sub11_internal_op = 7'h32; endcase end + always @* begin + if (\initial ) begin end + MUL_dec31_dec_sub11_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h02: + MUL_dec31_dec_sub11_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h00: + MUL_dec31_dec_sub11_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + MUL_dec31_dec_sub11_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + MUL_dec31_dec_sub11_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h07: + MUL_dec31_dec_sub11_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + MUL_dec31_dec_sub11_SV_Ptype = 2'h1; + endcase + end always @* begin if (\initial ) begin end MUL_dec31_dec_sub11_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: MUL_dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: MUL_dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: MUL_dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: MUL_dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: MUL_dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: MUL_dec31_dec_sub11_in2_sel = 4'h1; endcase @@ -17128,24 +18959,24 @@ module MUL_dec31_dec_sub11(MUL_dec31_dec_sub11_function_unit, MUL_dec31_dec_sub1 always @* begin if (\initial ) begin end MUL_dec31_dec_sub11_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: MUL_dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: MUL_dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: MUL_dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: MUL_dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: MUL_dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: MUL_dec31_dec_sub11_cr_in = 3'h0; endcase @@ -17153,24 +18984,24 @@ module MUL_dec31_dec_sub11(MUL_dec31_dec_sub11_function_unit, MUL_dec31_dec_sub1 always @* begin if (\initial ) begin end MUL_dec31_dec_sub11_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: MUL_dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: MUL_dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: MUL_dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: MUL_dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: MUL_dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: MUL_dec31_dec_sub11_cr_out = 3'h1; endcase @@ -17178,24 +19009,24 @@ module MUL_dec31_dec_sub11(MUL_dec31_dec_sub11_function_unit, MUL_dec31_dec_sub1 always @* begin if (\initial ) begin end MUL_dec31_dec_sub11_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: MUL_dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: MUL_dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: MUL_dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: MUL_dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: MUL_dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: MUL_dec31_dec_sub11_rc_sel = 2'h2; endcase @@ -17203,24 +19034,24 @@ module MUL_dec31_dec_sub11(MUL_dec31_dec_sub11_function_unit, MUL_dec31_dec_sub1 always @* begin if (\initial ) begin end MUL_dec31_dec_sub11_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: MUL_dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: MUL_dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: MUL_dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: MUL_dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: MUL_dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: MUL_dec31_dec_sub11_is_32b = 1'h1; endcase @@ -17228,24 +19059,24 @@ module MUL_dec31_dec_sub11(MUL_dec31_dec_sub11_function_unit, MUL_dec31_dec_sub1 always @* begin if (\initial ) begin end MUL_dec31_dec_sub11_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: MUL_dec31_dec_sub11_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: MUL_dec31_dec_sub11_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: MUL_dec31_dec_sub11_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: MUL_dec31_dec_sub11_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: MUL_dec31_dec_sub11_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: MUL_dec31_dec_sub11_sgn = 1'h1; endcase @@ -17255,8 +19086,15 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_MUL.dec.MUL_dec31.MUL_dec31_dec_sub9" *) (* generator = "nMigen" *) -module MUL_dec31_dec_sub9(MUL_dec31_dec_sub9_function_unit, MUL_dec31_dec_sub9_internal_op, MUL_dec31_dec_sub9_in2_sel, MUL_dec31_dec_sub9_cr_in, MUL_dec31_dec_sub9_cr_out, MUL_dec31_dec_sub9_rc_sel, MUL_dec31_dec_sub9_is_32b, MUL_dec31_dec_sub9_sgn, opcode_in); +module MUL_dec31_dec_sub9(MUL_dec31_dec_sub9_function_unit, MUL_dec31_dec_sub9_internal_op, MUL_dec31_dec_sub9_SV_Ptype, MUL_dec31_dec_sub9_in2_sel, MUL_dec31_dec_sub9_cr_in, MUL_dec31_dec_sub9_cr_out, MUL_dec31_dec_sub9_rc_sel, MUL_dec31_dec_sub9_is_32b, MUL_dec31_dec_sub9_sgn, opcode_in); reg \initial = 0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] MUL_dec31_dec_sub9_SV_Ptype; + reg [1:0] MUL_dec31_dec_sub9_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -17266,7 +19104,7 @@ module MUL_dec31_dec_sub9(MUL_dec31_dec_sub9_function_unit, MUL_dec31_dec_sub9_i (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] MUL_dec31_dec_sub9_cr_in; reg [2:0] MUL_dec31_dec_sub9_cr_in; (* enum_base_type = "CROutSel" *) @@ -17276,27 +19114,28 @@ module MUL_dec31_dec_sub9(MUL_dec31_dec_sub9_function_unit, MUL_dec31_dec_sub9_i (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] MUL_dec31_dec_sub9_cr_out; reg [2:0] MUL_dec31_dec_sub9_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] MUL_dec31_dec_sub9_function_unit; - reg [13:0] MUL_dec31_dec_sub9_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] MUL_dec31_dec_sub9_function_unit; + reg [14:0] MUL_dec31_dec_sub9_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -17312,7 +19151,8 @@ module MUL_dec31_dec_sub9(MUL_dec31_dec_sub9_function_unit, MUL_dec31_dec_sub9_i (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] MUL_dec31_dec_sub9_in2_sel; reg [3:0] MUL_dec31_dec_sub9_in2_sel; (* enum_base_type = "MicrOp" *) @@ -17390,97 +19230,124 @@ module MUL_dec31_dec_sub9(MUL_dec31_dec_sub9_function_unit, MUL_dec31_dec_sub9_i (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] MUL_dec31_dec_sub9_internal_op; reg [6:0] MUL_dec31_dec_sub9_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output MUL_dec31_dec_sub9_is_32b; reg MUL_dec31_dec_sub9_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] MUL_dec31_dec_sub9_rc_sel; reg [1:0] MUL_dec31_dec_sub9_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output MUL_dec31_dec_sub9_sgn; reg MUL_dec31_dec_sub9_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - MUL_dec31_dec_sub9_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + MUL_dec31_dec_sub9_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: - MUL_dec31_dec_sub9_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + MUL_dec31_dec_sub9_function_unit = 15'h0100; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - MUL_dec31_dec_sub9_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + MUL_dec31_dec_sub9_function_unit = 15'h0100; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: - MUL_dec31_dec_sub9_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + MUL_dec31_dec_sub9_function_unit = 15'h0100; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - MUL_dec31_dec_sub9_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + MUL_dec31_dec_sub9_function_unit = 15'h0100; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - MUL_dec31_dec_sub9_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + MUL_dec31_dec_sub9_function_unit = 15'h0100; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: - MUL_dec31_dec_sub9_function_unit = 14'h0100; + MUL_dec31_dec_sub9_function_unit = 15'h0100; endcase end always @* begin if (\initial ) begin end MUL_dec31_dec_sub9_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: MUL_dec31_dec_sub9_internal_op = 7'h33; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: MUL_dec31_dec_sub9_internal_op = 7'h33; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: MUL_dec31_dec_sub9_internal_op = 7'h33; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: MUL_dec31_dec_sub9_internal_op = 7'h33; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: MUL_dec31_dec_sub9_internal_op = 7'h32; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: MUL_dec31_dec_sub9_internal_op = 7'h32; endcase end + always @* begin + if (\initial ) begin end + MUL_dec31_dec_sub9_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h02: + MUL_dec31_dec_sub9_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h00: + MUL_dec31_dec_sub9_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + MUL_dec31_dec_sub9_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + MUL_dec31_dec_sub9_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h07: + MUL_dec31_dec_sub9_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + MUL_dec31_dec_sub9_SV_Ptype = 2'h1; + endcase + end always @* begin if (\initial ) begin end MUL_dec31_dec_sub9_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: MUL_dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: MUL_dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: MUL_dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: MUL_dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: MUL_dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: MUL_dec31_dec_sub9_in2_sel = 4'h1; endcase @@ -17488,24 +19355,24 @@ module MUL_dec31_dec_sub9(MUL_dec31_dec_sub9_function_unit, MUL_dec31_dec_sub9_i always @* begin if (\initial ) begin end MUL_dec31_dec_sub9_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: MUL_dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: MUL_dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: MUL_dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: MUL_dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: MUL_dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: MUL_dec31_dec_sub9_cr_in = 3'h0; endcase @@ -17513,24 +19380,24 @@ module MUL_dec31_dec_sub9(MUL_dec31_dec_sub9_function_unit, MUL_dec31_dec_sub9_i always @* begin if (\initial ) begin end MUL_dec31_dec_sub9_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: MUL_dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: MUL_dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: MUL_dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: MUL_dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: MUL_dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: MUL_dec31_dec_sub9_cr_out = 3'h1; endcase @@ -17538,24 +19405,24 @@ module MUL_dec31_dec_sub9(MUL_dec31_dec_sub9_function_unit, MUL_dec31_dec_sub9_i always @* begin if (\initial ) begin end MUL_dec31_dec_sub9_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: MUL_dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: MUL_dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: MUL_dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: MUL_dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: MUL_dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: MUL_dec31_dec_sub9_rc_sel = 2'h2; endcase @@ -17563,24 +19430,24 @@ module MUL_dec31_dec_sub9(MUL_dec31_dec_sub9_function_unit, MUL_dec31_dec_sub9_i always @* begin if (\initial ) begin end MUL_dec31_dec_sub9_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: MUL_dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: MUL_dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: MUL_dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: MUL_dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: MUL_dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: MUL_dec31_dec_sub9_is_32b = 1'h0; endcase @@ -17588,24 +19455,24 @@ module MUL_dec31_dec_sub9(MUL_dec31_dec_sub9_function_unit, MUL_dec31_dec_sub9_i always @* begin if (\initial ) begin end MUL_dec31_dec_sub9_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: MUL_dec31_dec_sub9_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: MUL_dec31_dec_sub9_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: MUL_dec31_dec_sub9_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: MUL_dec31_dec_sub9_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: MUL_dec31_dec_sub9_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: MUL_dec31_dec_sub9_sgn = 1'h1; endcase @@ -17615,8 +19482,15 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec30" *) (* generator = "nMigen" *) -module SHIFT_ROT_dec30(SHIFT_ROT_dec30_function_unit, SHIFT_ROT_dec30_internal_op, SHIFT_ROT_dec30_in2_sel, SHIFT_ROT_dec30_cr_in, SHIFT_ROT_dec30_cr_out, SHIFT_ROT_dec30_rc_sel, SHIFT_ROT_dec30_cry_in, SHIFT_ROT_dec30_inv_a, SHIFT_ROT_dec30_cry_out, SHIFT_ROT_dec30_is_32b, SHIFT_ROT_dec30_sgn, opcode_in); +module SHIFT_ROT_dec30(SHIFT_ROT_dec30_function_unit, SHIFT_ROT_dec30_internal_op, SHIFT_ROT_dec30_SV_Ptype, SHIFT_ROT_dec30_in2_sel, SHIFT_ROT_dec30_cr_in, SHIFT_ROT_dec30_cr_out, SHIFT_ROT_dec30_rc_sel, SHIFT_ROT_dec30_cry_in, SHIFT_ROT_dec30_inv_a, SHIFT_ROT_dec30_cry_out, SHIFT_ROT_dec30_is_32b, SHIFT_ROT_dec30_sgn, opcode_in); reg \initial = 0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] SHIFT_ROT_dec30_SV_Ptype; + reg [1:0] SHIFT_ROT_dec30_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -17626,7 +19500,7 @@ module SHIFT_ROT_dec30(SHIFT_ROT_dec30_function_unit, SHIFT_ROT_dec30_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SHIFT_ROT_dec30_cr_in; reg [2:0] SHIFT_ROT_dec30_cr_in; (* enum_base_type = "CROutSel" *) @@ -17636,37 +19510,38 @@ module SHIFT_ROT_dec30(SHIFT_ROT_dec30_function_unit, SHIFT_ROT_dec30_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SHIFT_ROT_dec30_cr_out; reg [2:0] SHIFT_ROT_dec30_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] SHIFT_ROT_dec30_cry_in; reg [1:0] SHIFT_ROT_dec30_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec30_cry_out; reg SHIFT_ROT_dec30_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] SHIFT_ROT_dec30_function_unit; - reg [13:0] SHIFT_ROT_dec30_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] SHIFT_ROT_dec30_function_unit; + reg [14:0] SHIFT_ROT_dec30_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -17682,7 +19557,8 @@ module SHIFT_ROT_dec30(SHIFT_ROT_dec30_function_unit, SHIFT_ROT_dec30_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] SHIFT_ROT_dec30_in2_sel; reg [3:0] SHIFT_ROT_dec30_in2_sel; (* enum_base_type = "MicrOp" *) @@ -17760,99 +19636,138 @@ module SHIFT_ROT_dec30(SHIFT_ROT_dec30_function_unit, SHIFT_ROT_dec30_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] SHIFT_ROT_dec30_internal_op; reg [6:0] SHIFT_ROT_dec30_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec30_inv_a; reg SHIFT_ROT_dec30_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec30_is_32b; reg SHIFT_ROT_dec30_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] SHIFT_ROT_dec30_rc_sel; reg [1:0] SHIFT_ROT_dec30_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec30_sgn; reg SHIFT_ROT_dec30_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [3:0] opcode_switch; always @* begin if (\initial ) begin end - SHIFT_ROT_dec30_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + SHIFT_ROT_dec30_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: - SHIFT_ROT_dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + SHIFT_ROT_dec30_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: - SHIFT_ROT_dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + SHIFT_ROT_dec30_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: - SHIFT_ROT_dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + SHIFT_ROT_dec30_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: - SHIFT_ROT_dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + SHIFT_ROT_dec30_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: - SHIFT_ROT_dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + SHIFT_ROT_dec30_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: - SHIFT_ROT_dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + SHIFT_ROT_dec30_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: - SHIFT_ROT_dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + SHIFT_ROT_dec30_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: - SHIFT_ROT_dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + SHIFT_ROT_dec30_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: - SHIFT_ROT_dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + SHIFT_ROT_dec30_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: - SHIFT_ROT_dec30_function_unit = 14'h0008; + SHIFT_ROT_dec30_function_unit = 15'h0008; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec30_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 4'h4: + SHIFT_ROT_dec30_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 4'h5: + SHIFT_ROT_dec30_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 4'h0: + SHIFT_ROT_dec30_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 4'h1: + SHIFT_ROT_dec30_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 4'h2: + SHIFT_ROT_dec30_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 4'h3: + SHIFT_ROT_dec30_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 4'h6: + SHIFT_ROT_dec30_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 4'h7: + SHIFT_ROT_dec30_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 4'h8: + SHIFT_ROT_dec30_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 4'h9: + SHIFT_ROT_dec30_cry_out = 1'h0; endcase end always @* begin if (\initial ) begin end SHIFT_ROT_dec30_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: SHIFT_ROT_dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: SHIFT_ROT_dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: SHIFT_ROT_dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: SHIFT_ROT_dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: SHIFT_ROT_dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: SHIFT_ROT_dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: SHIFT_ROT_dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: SHIFT_ROT_dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: SHIFT_ROT_dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: SHIFT_ROT_dec30_is_32b = 1'h0; endcase @@ -17860,36 +19775,36 @@ module SHIFT_ROT_dec30(SHIFT_ROT_dec30_function_unit, SHIFT_ROT_dec30_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec30_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: SHIFT_ROT_dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: SHIFT_ROT_dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: SHIFT_ROT_dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: SHIFT_ROT_dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: SHIFT_ROT_dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: SHIFT_ROT_dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: SHIFT_ROT_dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: SHIFT_ROT_dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: SHIFT_ROT_dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: SHIFT_ROT_dec30_sgn = 1'h0; endcase @@ -17897,73 +19812,110 @@ module SHIFT_ROT_dec30(SHIFT_ROT_dec30_function_unit, SHIFT_ROT_dec30_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec30_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: SHIFT_ROT_dec30_internal_op = 7'h38; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: SHIFT_ROT_dec30_internal_op = 7'h38; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: SHIFT_ROT_dec30_internal_op = 7'h39; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: SHIFT_ROT_dec30_internal_op = 7'h39; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: SHIFT_ROT_dec30_internal_op = 7'h3a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: SHIFT_ROT_dec30_internal_op = 7'h3a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: SHIFT_ROT_dec30_internal_op = 7'h38; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: SHIFT_ROT_dec30_internal_op = 7'h38; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: SHIFT_ROT_dec30_internal_op = 7'h39; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: SHIFT_ROT_dec30_internal_op = 7'h3a; endcase end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec30_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 4'h4: + SHIFT_ROT_dec30_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 4'h5: + SHIFT_ROT_dec30_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 4'h0: + SHIFT_ROT_dec30_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 4'h1: + SHIFT_ROT_dec30_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 4'h2: + SHIFT_ROT_dec30_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 4'h3: + SHIFT_ROT_dec30_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 4'h6: + SHIFT_ROT_dec30_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 4'h7: + SHIFT_ROT_dec30_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 4'h8: + SHIFT_ROT_dec30_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 4'h9: + SHIFT_ROT_dec30_SV_Ptype = 2'h1; + endcase + end always @* begin if (\initial ) begin end SHIFT_ROT_dec30_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: SHIFT_ROT_dec30_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: SHIFT_ROT_dec30_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: SHIFT_ROT_dec30_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: SHIFT_ROT_dec30_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: SHIFT_ROT_dec30_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: SHIFT_ROT_dec30_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: SHIFT_ROT_dec30_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: SHIFT_ROT_dec30_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: SHIFT_ROT_dec30_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: SHIFT_ROT_dec30_in2_sel = 4'h1; endcase @@ -17971,36 +19923,36 @@ module SHIFT_ROT_dec30(SHIFT_ROT_dec30_function_unit, SHIFT_ROT_dec30_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec30_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: SHIFT_ROT_dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: SHIFT_ROT_dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: SHIFT_ROT_dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: SHIFT_ROT_dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: SHIFT_ROT_dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: SHIFT_ROT_dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: SHIFT_ROT_dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: SHIFT_ROT_dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: SHIFT_ROT_dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: SHIFT_ROT_dec30_cr_in = 3'h0; endcase @@ -18008,36 +19960,36 @@ module SHIFT_ROT_dec30(SHIFT_ROT_dec30_function_unit, SHIFT_ROT_dec30_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec30_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: SHIFT_ROT_dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: SHIFT_ROT_dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: SHIFT_ROT_dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: SHIFT_ROT_dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: SHIFT_ROT_dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: SHIFT_ROT_dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: SHIFT_ROT_dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: SHIFT_ROT_dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: SHIFT_ROT_dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: SHIFT_ROT_dec30_cr_out = 3'h1; endcase @@ -18045,36 +19997,36 @@ module SHIFT_ROT_dec30(SHIFT_ROT_dec30_function_unit, SHIFT_ROT_dec30_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec30_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: SHIFT_ROT_dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: SHIFT_ROT_dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: SHIFT_ROT_dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: SHIFT_ROT_dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: SHIFT_ROT_dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: SHIFT_ROT_dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: SHIFT_ROT_dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: SHIFT_ROT_dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: SHIFT_ROT_dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: SHIFT_ROT_dec30_rc_sel = 2'h2; endcase @@ -18082,36 +20034,36 @@ module SHIFT_ROT_dec30(SHIFT_ROT_dec30_function_unit, SHIFT_ROT_dec30_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec30_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: SHIFT_ROT_dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: SHIFT_ROT_dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: SHIFT_ROT_dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: SHIFT_ROT_dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: SHIFT_ROT_dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: SHIFT_ROT_dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: SHIFT_ROT_dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: SHIFT_ROT_dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: SHIFT_ROT_dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: SHIFT_ROT_dec30_cry_in = 2'h0; endcase @@ -18119,84 +20071,54 @@ module SHIFT_ROT_dec30(SHIFT_ROT_dec30_function_unit, SHIFT_ROT_dec30_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec30_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: SHIFT_ROT_dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: SHIFT_ROT_dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: SHIFT_ROT_dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: SHIFT_ROT_dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: SHIFT_ROT_dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: SHIFT_ROT_dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: SHIFT_ROT_dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: SHIFT_ROT_dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: SHIFT_ROT_dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: SHIFT_ROT_dec30_inv_a = 1'h0; endcase end - always @* begin - if (\initial ) begin end - SHIFT_ROT_dec30_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) - casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 4'h4: - SHIFT_ROT_dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 4'h5: - SHIFT_ROT_dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 4'h0: - SHIFT_ROT_dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 4'h1: - SHIFT_ROT_dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 4'h2: - SHIFT_ROT_dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 4'h3: - SHIFT_ROT_dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 4'h6: - SHIFT_ROT_dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 4'h7: - SHIFT_ROT_dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 4'h8: - SHIFT_ROT_dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 4'h9: - SHIFT_ROT_dec30_cry_out = 1'h0; - endcase - end assign opcode_switch = opcode_in[4:1]; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31" *) (* generator = "nMigen" *) -module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_op, SHIFT_ROT_dec31_in2_sel, SHIFT_ROT_dec31_cr_in, SHIFT_ROT_dec31_cr_out, SHIFT_ROT_dec31_rc_sel, SHIFT_ROT_dec31_cry_in, SHIFT_ROT_dec31_inv_a, SHIFT_ROT_dec31_cry_out, SHIFT_ROT_dec31_is_32b, SHIFT_ROT_dec31_sgn, opcode_in); +module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_op, SHIFT_ROT_dec31_SV_Ptype, SHIFT_ROT_dec31_in2_sel, SHIFT_ROT_dec31_cr_in, SHIFT_ROT_dec31_cr_out, SHIFT_ROT_dec31_rc_sel, SHIFT_ROT_dec31_cry_in, SHIFT_ROT_dec31_inv_a, SHIFT_ROT_dec31_cry_out, SHIFT_ROT_dec31_is_32b, SHIFT_ROT_dec31_sgn, opcode_in); reg \initial = 0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] SHIFT_ROT_dec31_SV_Ptype; + reg [1:0] SHIFT_ROT_dec31_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -18206,7 +20128,7 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SHIFT_ROT_dec31_cr_in; reg [2:0] SHIFT_ROT_dec31_cr_in; (* enum_base_type = "CROutSel" *) @@ -18216,19 +20138,25 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SHIFT_ROT_dec31_cr_out; reg [2:0] SHIFT_ROT_dec31_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] SHIFT_ROT_dec31_cry_in; reg [1:0] SHIFT_ROT_dec31_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec31_cry_out; reg SHIFT_ROT_dec31_cry_out; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -18238,7 +20166,7 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -18247,33 +20175,34 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -18289,7 +20218,8 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -18366,22 +20296,30 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] SHIFT_ROT_dec31_dec_sub24_opcode_in; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -18391,7 +20329,7 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -18400,33 +20338,34 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -18442,7 +20381,8 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -18519,22 +20459,30 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] SHIFT_ROT_dec31_dec_sub26_opcode_in; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -18544,7 +20492,7 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -18553,33 +20501,34 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -18595,7 +20544,8 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -18672,40 +20622,43 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] SHIFT_ROT_dec31_dec_sub27_opcode_in; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] SHIFT_ROT_dec31_function_unit; - reg [13:0] SHIFT_ROT_dec31_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] SHIFT_ROT_dec31_function_unit; + reg [14:0] SHIFT_ROT_dec31_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -18721,7 +20674,8 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] SHIFT_ROT_dec31_in2_sel; reg [3:0] SHIFT_ROT_dec31_in2_sel; (* enum_base_type = "MicrOp" *) @@ -18799,32 +20753,35 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] SHIFT_ROT_dec31_internal_op; reg [6:0] SHIFT_ROT_dec31_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec31_inv_a; reg SHIFT_ROT_dec31_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec31_is_32b; reg SHIFT_ROT_dec31_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] SHIFT_ROT_dec31_rc_sel; reg [1:0] SHIFT_ROT_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec31_sgn; reg SHIFT_ROT_dec31_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:355" *) wire [4:0] opc_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [9:0] opcode_switch; SHIFT_ROT_dec31_dec_sub24 SHIFT_ROT_dec31_dec_sub24 ( + .SHIFT_ROT_dec31_dec_sub24_SV_Ptype(SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_SV_Ptype), .SHIFT_ROT_dec31_dec_sub24_cr_in(SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in), .SHIFT_ROT_dec31_dec_sub24_cr_out(SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out), .SHIFT_ROT_dec31_dec_sub24_cry_in(SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in), @@ -18839,6 +20796,7 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o .opcode_in(SHIFT_ROT_dec31_dec_sub24_opcode_in) ); SHIFT_ROT_dec31_dec_sub26 SHIFT_ROT_dec31_dec_sub26 ( + .SHIFT_ROT_dec31_dec_sub26_SV_Ptype(SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_SV_Ptype), .SHIFT_ROT_dec31_dec_sub26_cr_in(SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in), .SHIFT_ROT_dec31_dec_sub26_cr_out(SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out), .SHIFT_ROT_dec31_dec_sub26_cry_in(SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in), @@ -18853,6 +20811,7 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o .opcode_in(SHIFT_ROT_dec31_dec_sub26_opcode_in) ); SHIFT_ROT_dec31_dec_sub27 SHIFT_ROT_dec31_dec_sub27 ( + .SHIFT_ROT_dec31_dec_sub27_SV_Ptype(SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_SV_Ptype), .SHIFT_ROT_dec31_dec_sub27_cr_in(SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in), .SHIFT_ROT_dec31_dec_sub27_cr_out(SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out), .SHIFT_ROT_dec31_dec_sub27_cry_in(SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in), @@ -18866,18 +20825,34 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o .SHIFT_ROT_dec31_dec_sub27_sgn(SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn), .opcode_in(SHIFT_ROT_dec31_dec_sub27_opcode_in) ); + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + SHIFT_ROT_dec31_cr_out = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + SHIFT_ROT_dec31_cr_out = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h18: + SHIFT_ROT_dec31_cr_out = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out; + endcase + end always @* begin if (\initial ) begin end SHIFT_ROT_dec31_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: SHIFT_ROT_dec31_rc_sel = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: SHIFT_ROT_dec31_rc_sel = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: SHIFT_ROT_dec31_rc_sel = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel; endcase @@ -18885,15 +20860,15 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec31_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: SHIFT_ROT_dec31_cry_in = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: SHIFT_ROT_dec31_cry_in = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: SHIFT_ROT_dec31_cry_in = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in; endcase @@ -18901,15 +20876,15 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec31_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: SHIFT_ROT_dec31_inv_a = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: SHIFT_ROT_dec31_inv_a = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: SHIFT_ROT_dec31_inv_a = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_inv_a; endcase @@ -18917,15 +20892,15 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec31_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: SHIFT_ROT_dec31_cry_out = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: SHIFT_ROT_dec31_cry_out = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: SHIFT_ROT_dec31_cry_out = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out; endcase @@ -18933,15 +20908,15 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec31_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: SHIFT_ROT_dec31_is_32b = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: SHIFT_ROT_dec31_is_32b = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: SHIFT_ROT_dec31_is_32b = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b; endcase @@ -18949,31 +20924,31 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec31_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: SHIFT_ROT_dec31_sgn = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: SHIFT_ROT_dec31_sgn = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: SHIFT_ROT_dec31_sgn = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn; endcase end always @* begin if (\initial ) begin end - SHIFT_ROT_dec31_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + SHIFT_ROT_dec31_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: SHIFT_ROT_dec31_function_unit = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: SHIFT_ROT_dec31_function_unit = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: SHIFT_ROT_dec31_function_unit = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit; endcase @@ -18981,65 +20956,65 @@ module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_o always @* begin if (\initial ) begin end SHIFT_ROT_dec31_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: SHIFT_ROT_dec31_internal_op = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: SHIFT_ROT_dec31_internal_op = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: SHIFT_ROT_dec31_internal_op = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op; endcase end always @* begin if (\initial ) begin end - SHIFT_ROT_dec31_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + SHIFT_ROT_dec31_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: - SHIFT_ROT_dec31_in2_sel = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + SHIFT_ROT_dec31_SV_Ptype = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: - SHIFT_ROT_dec31_in2_sel = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + SHIFT_ROT_dec31_SV_Ptype = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - SHIFT_ROT_dec31_in2_sel = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel; + SHIFT_ROT_dec31_SV_Ptype = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_SV_Ptype; endcase end always @* begin if (\initial ) begin end - SHIFT_ROT_dec31_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + SHIFT_ROT_dec31_in2_sel = 4'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: - SHIFT_ROT_dec31_cr_in = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + SHIFT_ROT_dec31_in2_sel = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: - SHIFT_ROT_dec31_cr_in = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + SHIFT_ROT_dec31_in2_sel = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - SHIFT_ROT_dec31_cr_in = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in; + SHIFT_ROT_dec31_in2_sel = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel; endcase end always @* begin if (\initial ) begin end - SHIFT_ROT_dec31_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + SHIFT_ROT_dec31_cr_in = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: - SHIFT_ROT_dec31_cr_out = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + SHIFT_ROT_dec31_cr_in = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: - SHIFT_ROT_dec31_cr_out = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + SHIFT_ROT_dec31_cr_in = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - SHIFT_ROT_dec31_cr_out = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out; + SHIFT_ROT_dec31_cr_in = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in; endcase end assign SHIFT_ROT_dec31_dec_sub24_opcode_in = opcode_in; @@ -19051,8 +21026,15 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub24" *) (* generator = "nMigen" *) -module SHIFT_ROT_dec31_dec_sub24(SHIFT_ROT_dec31_dec_sub24_function_unit, SHIFT_ROT_dec31_dec_sub24_internal_op, SHIFT_ROT_dec31_dec_sub24_in2_sel, SHIFT_ROT_dec31_dec_sub24_cr_in, SHIFT_ROT_dec31_dec_sub24_cr_out, SHIFT_ROT_dec31_dec_sub24_rc_sel, SHIFT_ROT_dec31_dec_sub24_cry_in, SHIFT_ROT_dec31_dec_sub24_inv_a, SHIFT_ROT_dec31_dec_sub24_cry_out, SHIFT_ROT_dec31_dec_sub24_is_32b, SHIFT_ROT_dec31_dec_sub24_sgn, opcode_in); +module SHIFT_ROT_dec31_dec_sub24(SHIFT_ROT_dec31_dec_sub24_function_unit, SHIFT_ROT_dec31_dec_sub24_internal_op, SHIFT_ROT_dec31_dec_sub24_SV_Ptype, SHIFT_ROT_dec31_dec_sub24_in2_sel, SHIFT_ROT_dec31_dec_sub24_cr_in, SHIFT_ROT_dec31_dec_sub24_cr_out, SHIFT_ROT_dec31_dec_sub24_rc_sel, SHIFT_ROT_dec31_dec_sub24_cry_in, SHIFT_ROT_dec31_dec_sub24_inv_a, SHIFT_ROT_dec31_dec_sub24_cry_out, SHIFT_ROT_dec31_dec_sub24_is_32b, SHIFT_ROT_dec31_dec_sub24_sgn, opcode_in); reg \initial = 0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] SHIFT_ROT_dec31_dec_sub24_SV_Ptype; + reg [1:0] SHIFT_ROT_dec31_dec_sub24_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -19062,7 +21044,7 @@ module SHIFT_ROT_dec31_dec_sub24(SHIFT_ROT_dec31_dec_sub24_function_unit, SHIFT_ (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SHIFT_ROT_dec31_dec_sub24_cr_in; reg [2:0] SHIFT_ROT_dec31_dec_sub24_cr_in; (* enum_base_type = "CROutSel" *) @@ -19072,37 +21054,38 @@ module SHIFT_ROT_dec31_dec_sub24(SHIFT_ROT_dec31_dec_sub24_function_unit, SHIFT_ (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SHIFT_ROT_dec31_dec_sub24_cr_out; reg [2:0] SHIFT_ROT_dec31_dec_sub24_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] SHIFT_ROT_dec31_dec_sub24_cry_in; reg [1:0] SHIFT_ROT_dec31_dec_sub24_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec31_dec_sub24_cry_out; reg SHIFT_ROT_dec31_dec_sub24_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] SHIFT_ROT_dec31_dec_sub24_function_unit; - reg [13:0] SHIFT_ROT_dec31_dec_sub24_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] SHIFT_ROT_dec31_dec_sub24_function_unit; + reg [14:0] SHIFT_ROT_dec31_dec_sub24_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -19118,7 +21101,8 @@ module SHIFT_ROT_dec31_dec_sub24(SHIFT_ROT_dec31_dec_sub24_function_unit, SHIFT_ (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] SHIFT_ROT_dec31_dec_sub24_in2_sel; reg [3:0] SHIFT_ROT_dec31_dec_sub24_in2_sel; (* enum_base_type = "MicrOp" *) @@ -19196,63 +21180,84 @@ module SHIFT_ROT_dec31_dec_sub24(SHIFT_ROT_dec31_dec_sub24_function_unit, SHIFT_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] SHIFT_ROT_dec31_dec_sub24_internal_op; reg [6:0] SHIFT_ROT_dec31_dec_sub24_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec31_dec_sub24_inv_a; reg SHIFT_ROT_dec31_dec_sub24_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec31_dec_sub24_is_32b; reg SHIFT_ROT_dec31_dec_sub24_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] SHIFT_ROT_dec31_dec_sub24_rc_sel; reg [1:0] SHIFT_ROT_dec31_dec_sub24_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec31_dec_sub24_sgn; reg SHIFT_ROT_dec31_dec_sub24_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - SHIFT_ROT_dec31_dec_sub24_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + SHIFT_ROT_dec31_dec_sub24_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h00: + SHIFT_ROT_dec31_dec_sub24_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h18: + SHIFT_ROT_dec31_dec_sub24_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub24_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + SHIFT_ROT_dec31_dec_sub24_function_unit = 15'h0008; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub24_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - SHIFT_ROT_dec31_dec_sub24_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + SHIFT_ROT_dec31_dec_sub24_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - SHIFT_ROT_dec31_dec_sub24_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + SHIFT_ROT_dec31_dec_sub24_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: - SHIFT_ROT_dec31_dec_sub24_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + SHIFT_ROT_dec31_dec_sub24_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - SHIFT_ROT_dec31_dec_sub24_function_unit = 14'h0008; + SHIFT_ROT_dec31_dec_sub24_cry_out = 1'h0; endcase end always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub24_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: SHIFT_ROT_dec31_dec_sub24_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: SHIFT_ROT_dec31_dec_sub24_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: SHIFT_ROT_dec31_dec_sub24_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: SHIFT_ROT_dec31_dec_sub24_is_32b = 1'h1; endcase @@ -19260,18 +21265,18 @@ module SHIFT_ROT_dec31_dec_sub24(SHIFT_ROT_dec31_dec_sub24_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub24_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: SHIFT_ROT_dec31_dec_sub24_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: SHIFT_ROT_dec31_dec_sub24_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: SHIFT_ROT_dec31_dec_sub24_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: SHIFT_ROT_dec31_dec_sub24_sgn = 1'h0; endcase @@ -19279,37 +21284,56 @@ module SHIFT_ROT_dec31_dec_sub24(SHIFT_ROT_dec31_dec_sub24_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub24_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: SHIFT_ROT_dec31_dec_sub24_internal_op = 7'h3c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: SHIFT_ROT_dec31_dec_sub24_internal_op = 7'h3d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: SHIFT_ROT_dec31_dec_sub24_internal_op = 7'h3d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: SHIFT_ROT_dec31_dec_sub24_internal_op = 7'h3d; endcase end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub24_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h00: + SHIFT_ROT_dec31_dec_sub24_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h18: + SHIFT_ROT_dec31_dec_sub24_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub24_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + SHIFT_ROT_dec31_dec_sub24_SV_Ptype = 2'h1; + endcase + end always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub24_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: SHIFT_ROT_dec31_dec_sub24_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: SHIFT_ROT_dec31_dec_sub24_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: SHIFT_ROT_dec31_dec_sub24_in2_sel = 4'hb; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: SHIFT_ROT_dec31_dec_sub24_in2_sel = 4'h1; endcase @@ -19317,18 +21341,18 @@ module SHIFT_ROT_dec31_dec_sub24(SHIFT_ROT_dec31_dec_sub24_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub24_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: SHIFT_ROT_dec31_dec_sub24_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: SHIFT_ROT_dec31_dec_sub24_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: SHIFT_ROT_dec31_dec_sub24_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: SHIFT_ROT_dec31_dec_sub24_cr_in = 3'h0; endcase @@ -19336,18 +21360,18 @@ module SHIFT_ROT_dec31_dec_sub24(SHIFT_ROT_dec31_dec_sub24_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub24_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: SHIFT_ROT_dec31_dec_sub24_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: SHIFT_ROT_dec31_dec_sub24_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: SHIFT_ROT_dec31_dec_sub24_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: SHIFT_ROT_dec31_dec_sub24_cr_out = 3'h1; endcase @@ -19355,18 +21379,18 @@ module SHIFT_ROT_dec31_dec_sub24(SHIFT_ROT_dec31_dec_sub24_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub24_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: SHIFT_ROT_dec31_dec_sub24_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: SHIFT_ROT_dec31_dec_sub24_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: SHIFT_ROT_dec31_dec_sub24_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: SHIFT_ROT_dec31_dec_sub24_rc_sel = 2'h2; endcase @@ -19374,18 +21398,18 @@ module SHIFT_ROT_dec31_dec_sub24(SHIFT_ROT_dec31_dec_sub24_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub24_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: SHIFT_ROT_dec31_dec_sub24_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: SHIFT_ROT_dec31_dec_sub24_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: SHIFT_ROT_dec31_dec_sub24_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: SHIFT_ROT_dec31_dec_sub24_cry_in = 2'h0; endcase @@ -19393,48 +21417,36 @@ module SHIFT_ROT_dec31_dec_sub24(SHIFT_ROT_dec31_dec_sub24_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub24_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: SHIFT_ROT_dec31_dec_sub24_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: SHIFT_ROT_dec31_dec_sub24_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: SHIFT_ROT_dec31_dec_sub24_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: SHIFT_ROT_dec31_dec_sub24_inv_a = 1'h0; endcase end - always @* begin - if (\initial ) begin end - SHIFT_ROT_dec31_dec_sub24_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) - casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h00: - SHIFT_ROT_dec31_dec_sub24_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h18: - SHIFT_ROT_dec31_dec_sub24_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h19: - SHIFT_ROT_dec31_dec_sub24_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h10: - SHIFT_ROT_dec31_dec_sub24_cry_out = 1'h0; - endcase - end assign opcode_switch = opcode_in[10:6]; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub26" *) (* generator = "nMigen" *) -module SHIFT_ROT_dec31_dec_sub26(SHIFT_ROT_dec31_dec_sub26_function_unit, SHIFT_ROT_dec31_dec_sub26_internal_op, SHIFT_ROT_dec31_dec_sub26_in2_sel, SHIFT_ROT_dec31_dec_sub26_cr_in, SHIFT_ROT_dec31_dec_sub26_cr_out, SHIFT_ROT_dec31_dec_sub26_rc_sel, SHIFT_ROT_dec31_dec_sub26_cry_in, SHIFT_ROT_dec31_dec_sub26_inv_a, SHIFT_ROT_dec31_dec_sub26_cry_out, SHIFT_ROT_dec31_dec_sub26_is_32b, SHIFT_ROT_dec31_dec_sub26_sgn, opcode_in); +module SHIFT_ROT_dec31_dec_sub26(SHIFT_ROT_dec31_dec_sub26_function_unit, SHIFT_ROT_dec31_dec_sub26_internal_op, SHIFT_ROT_dec31_dec_sub26_SV_Ptype, SHIFT_ROT_dec31_dec_sub26_in2_sel, SHIFT_ROT_dec31_dec_sub26_cr_in, SHIFT_ROT_dec31_dec_sub26_cr_out, SHIFT_ROT_dec31_dec_sub26_rc_sel, SHIFT_ROT_dec31_dec_sub26_cry_in, SHIFT_ROT_dec31_dec_sub26_inv_a, SHIFT_ROT_dec31_dec_sub26_cry_out, SHIFT_ROT_dec31_dec_sub26_is_32b, SHIFT_ROT_dec31_dec_sub26_sgn, opcode_in); reg \initial = 0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] SHIFT_ROT_dec31_dec_sub26_SV_Ptype; + reg [1:0] SHIFT_ROT_dec31_dec_sub26_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -19444,7 +21456,7 @@ module SHIFT_ROT_dec31_dec_sub26(SHIFT_ROT_dec31_dec_sub26_function_unit, SHIFT_ (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SHIFT_ROT_dec31_dec_sub26_cr_in; reg [2:0] SHIFT_ROT_dec31_dec_sub26_cr_in; (* enum_base_type = "CROutSel" *) @@ -19454,37 +21466,38 @@ module SHIFT_ROT_dec31_dec_sub26(SHIFT_ROT_dec31_dec_sub26_function_unit, SHIFT_ (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SHIFT_ROT_dec31_dec_sub26_cr_out; reg [2:0] SHIFT_ROT_dec31_dec_sub26_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] SHIFT_ROT_dec31_dec_sub26_cry_in; reg [1:0] SHIFT_ROT_dec31_dec_sub26_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec31_dec_sub26_cry_out; reg SHIFT_ROT_dec31_dec_sub26_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] SHIFT_ROT_dec31_dec_sub26_function_unit; - reg [13:0] SHIFT_ROT_dec31_dec_sub26_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] SHIFT_ROT_dec31_dec_sub26_function_unit; + reg [14:0] SHIFT_ROT_dec31_dec_sub26_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -19500,7 +21513,8 @@ module SHIFT_ROT_dec31_dec_sub26(SHIFT_ROT_dec31_dec_sub26_function_unit, SHIFT_ (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] SHIFT_ROT_dec31_dec_sub26_in2_sel; reg [3:0] SHIFT_ROT_dec31_dec_sub26_in2_sel; (* enum_base_type = "MicrOp" *) @@ -19578,57 +21592,75 @@ module SHIFT_ROT_dec31_dec_sub26(SHIFT_ROT_dec31_dec_sub26_function_unit, SHIFT_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] SHIFT_ROT_dec31_dec_sub26_internal_op; reg [6:0] SHIFT_ROT_dec31_dec_sub26_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec31_dec_sub26_inv_a; reg SHIFT_ROT_dec31_dec_sub26_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec31_dec_sub26_is_32b; reg SHIFT_ROT_dec31_dec_sub26_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] SHIFT_ROT_dec31_dec_sub26_rc_sel; reg [1:0] SHIFT_ROT_dec31_dec_sub26_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec31_dec_sub26_sgn; reg SHIFT_ROT_dec31_dec_sub26_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - SHIFT_ROT_dec31_dec_sub26_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + SHIFT_ROT_dec31_dec_sub26_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: - SHIFT_ROT_dec31_dec_sub26_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + SHIFT_ROT_dec31_dec_sub26_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - SHIFT_ROT_dec31_dec_sub26_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + SHIFT_ROT_dec31_dec_sub26_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: - SHIFT_ROT_dec31_dec_sub26_function_unit = 14'h0008; + SHIFT_ROT_dec31_dec_sub26_function_unit = 15'h0008; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub26_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + SHIFT_ROT_dec31_dec_sub26_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h18: + SHIFT_ROT_dec31_dec_sub26_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub26_cry_out = 1'h1; endcase end always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub26_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: SHIFT_ROT_dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: SHIFT_ROT_dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: SHIFT_ROT_dec31_dec_sub26_is_32b = 1'h0; endcase @@ -19636,15 +21668,15 @@ module SHIFT_ROT_dec31_dec_sub26(SHIFT_ROT_dec31_dec_sub26_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub26_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: SHIFT_ROT_dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: SHIFT_ROT_dec31_dec_sub26_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: SHIFT_ROT_dec31_dec_sub26_sgn = 1'h1; endcase @@ -19652,31 +21684,47 @@ module SHIFT_ROT_dec31_dec_sub26(SHIFT_ROT_dec31_dec_sub26_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub26_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: SHIFT_ROT_dec31_dec_sub26_internal_op = 7'h20; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: SHIFT_ROT_dec31_dec_sub26_internal_op = 7'h3d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: SHIFT_ROT_dec31_dec_sub26_internal_op = 7'h3d; endcase end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub26_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + SHIFT_ROT_dec31_dec_sub26_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h18: + SHIFT_ROT_dec31_dec_sub26_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub26_SV_Ptype = 2'h2; + endcase + end always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub26_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: SHIFT_ROT_dec31_dec_sub26_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: SHIFT_ROT_dec31_dec_sub26_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: SHIFT_ROT_dec31_dec_sub26_in2_sel = 4'ha; endcase @@ -19684,15 +21732,15 @@ module SHIFT_ROT_dec31_dec_sub26(SHIFT_ROT_dec31_dec_sub26_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub26_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: SHIFT_ROT_dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: SHIFT_ROT_dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: SHIFT_ROT_dec31_dec_sub26_cr_in = 3'h0; endcase @@ -19700,15 +21748,15 @@ module SHIFT_ROT_dec31_dec_sub26(SHIFT_ROT_dec31_dec_sub26_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub26_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: SHIFT_ROT_dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: SHIFT_ROT_dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: SHIFT_ROT_dec31_dec_sub26_cr_out = 3'h1; endcase @@ -19716,15 +21764,15 @@ module SHIFT_ROT_dec31_dec_sub26(SHIFT_ROT_dec31_dec_sub26_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub26_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: SHIFT_ROT_dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: SHIFT_ROT_dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: SHIFT_ROT_dec31_dec_sub26_rc_sel = 2'h2; endcase @@ -19732,15 +21780,15 @@ module SHIFT_ROT_dec31_dec_sub26(SHIFT_ROT_dec31_dec_sub26_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub26_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: SHIFT_ROT_dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: SHIFT_ROT_dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: SHIFT_ROT_dec31_dec_sub26_cry_in = 2'h0; endcase @@ -19748,42 +21796,33 @@ module SHIFT_ROT_dec31_dec_sub26(SHIFT_ROT_dec31_dec_sub26_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub26_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: SHIFT_ROT_dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: SHIFT_ROT_dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: SHIFT_ROT_dec31_dec_sub26_inv_a = 1'h0; endcase end - always @* begin - if (\initial ) begin end - SHIFT_ROT_dec31_dec_sub26_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) - casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h1b: - SHIFT_ROT_dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h18: - SHIFT_ROT_dec31_dec_sub26_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h19: - SHIFT_ROT_dec31_dec_sub26_cry_out = 1'h1; - endcase - end assign opcode_switch = opcode_in[10:6]; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub27" *) (* generator = "nMigen" *) -module SHIFT_ROT_dec31_dec_sub27(SHIFT_ROT_dec31_dec_sub27_function_unit, SHIFT_ROT_dec31_dec_sub27_internal_op, SHIFT_ROT_dec31_dec_sub27_in2_sel, SHIFT_ROT_dec31_dec_sub27_cr_in, SHIFT_ROT_dec31_dec_sub27_cr_out, SHIFT_ROT_dec31_dec_sub27_rc_sel, SHIFT_ROT_dec31_dec_sub27_cry_in, SHIFT_ROT_dec31_dec_sub27_inv_a, SHIFT_ROT_dec31_dec_sub27_cry_out, SHIFT_ROT_dec31_dec_sub27_is_32b, SHIFT_ROT_dec31_dec_sub27_sgn, opcode_in); +module SHIFT_ROT_dec31_dec_sub27(SHIFT_ROT_dec31_dec_sub27_function_unit, SHIFT_ROT_dec31_dec_sub27_internal_op, SHIFT_ROT_dec31_dec_sub27_SV_Ptype, SHIFT_ROT_dec31_dec_sub27_in2_sel, SHIFT_ROT_dec31_dec_sub27_cr_in, SHIFT_ROT_dec31_dec_sub27_cr_out, SHIFT_ROT_dec31_dec_sub27_rc_sel, SHIFT_ROT_dec31_dec_sub27_cry_in, SHIFT_ROT_dec31_dec_sub27_inv_a, SHIFT_ROT_dec31_dec_sub27_cry_out, SHIFT_ROT_dec31_dec_sub27_is_32b, SHIFT_ROT_dec31_dec_sub27_sgn, opcode_in); reg \initial = 0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] SHIFT_ROT_dec31_dec_sub27_SV_Ptype; + reg [1:0] SHIFT_ROT_dec31_dec_sub27_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -19793,7 +21832,7 @@ module SHIFT_ROT_dec31_dec_sub27(SHIFT_ROT_dec31_dec_sub27_function_unit, SHIFT_ (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SHIFT_ROT_dec31_dec_sub27_cr_in; reg [2:0] SHIFT_ROT_dec31_dec_sub27_cr_in; (* enum_base_type = "CROutSel" *) @@ -19803,37 +21842,38 @@ module SHIFT_ROT_dec31_dec_sub27(SHIFT_ROT_dec31_dec_sub27_function_unit, SHIFT_ (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SHIFT_ROT_dec31_dec_sub27_cr_out; reg [2:0] SHIFT_ROT_dec31_dec_sub27_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] SHIFT_ROT_dec31_dec_sub27_cry_in; reg [1:0] SHIFT_ROT_dec31_dec_sub27_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec31_dec_sub27_cry_out; reg SHIFT_ROT_dec31_dec_sub27_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] SHIFT_ROT_dec31_dec_sub27_function_unit; - reg [13:0] SHIFT_ROT_dec31_dec_sub27_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] SHIFT_ROT_dec31_dec_sub27_function_unit; + reg [14:0] SHIFT_ROT_dec31_dec_sub27_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -19849,7 +21889,8 @@ module SHIFT_ROT_dec31_dec_sub27(SHIFT_ROT_dec31_dec_sub27_function_unit, SHIFT_ (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] SHIFT_ROT_dec31_dec_sub27_in2_sel; reg [3:0] SHIFT_ROT_dec31_dec_sub27_in2_sel; (* enum_base_type = "MicrOp" *) @@ -19927,63 +21968,84 @@ module SHIFT_ROT_dec31_dec_sub27(SHIFT_ROT_dec31_dec_sub27_function_unit, SHIFT_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] SHIFT_ROT_dec31_dec_sub27_internal_op; reg [6:0] SHIFT_ROT_dec31_dec_sub27_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec31_dec_sub27_inv_a; reg SHIFT_ROT_dec31_dec_sub27_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec31_dec_sub27_is_32b; reg SHIFT_ROT_dec31_dec_sub27_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] SHIFT_ROT_dec31_dec_sub27_rc_sel; reg [1:0] SHIFT_ROT_dec31_dec_sub27_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_dec31_dec_sub27_sgn; reg SHIFT_ROT_dec31_dec_sub27_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - SHIFT_ROT_dec31_dec_sub27_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + SHIFT_ROT_dec31_dec_sub27_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + SHIFT_ROT_dec31_dec_sub27_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h00: + SHIFT_ROT_dec31_dec_sub27_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub27_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + SHIFT_ROT_dec31_dec_sub27_function_unit = 15'h0008; + endcase + end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub27_cry_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: - SHIFT_ROT_dec31_dec_sub27_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + SHIFT_ROT_dec31_dec_sub27_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - SHIFT_ROT_dec31_dec_sub27_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + SHIFT_ROT_dec31_dec_sub27_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: - SHIFT_ROT_dec31_dec_sub27_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + SHIFT_ROT_dec31_dec_sub27_cry_out = 1'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - SHIFT_ROT_dec31_dec_sub27_function_unit = 14'h0008; + SHIFT_ROT_dec31_dec_sub27_cry_out = 1'h0; endcase end always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub27_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: SHIFT_ROT_dec31_dec_sub27_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: SHIFT_ROT_dec31_dec_sub27_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: SHIFT_ROT_dec31_dec_sub27_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: SHIFT_ROT_dec31_dec_sub27_is_32b = 1'h0; endcase @@ -19991,18 +22053,18 @@ module SHIFT_ROT_dec31_dec_sub27(SHIFT_ROT_dec31_dec_sub27_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub27_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: SHIFT_ROT_dec31_dec_sub27_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: SHIFT_ROT_dec31_dec_sub27_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: SHIFT_ROT_dec31_dec_sub27_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: SHIFT_ROT_dec31_dec_sub27_sgn = 1'h0; endcase @@ -20010,37 +22072,56 @@ module SHIFT_ROT_dec31_dec_sub27(SHIFT_ROT_dec31_dec_sub27_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub27_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: SHIFT_ROT_dec31_dec_sub27_internal_op = 7'h20; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: SHIFT_ROT_dec31_dec_sub27_internal_op = 7'h3c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: SHIFT_ROT_dec31_dec_sub27_internal_op = 7'h3d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: SHIFT_ROT_dec31_dec_sub27_internal_op = 7'h3d; endcase end + always @* begin + if (\initial ) begin end + SHIFT_ROT_dec31_dec_sub27_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + SHIFT_ROT_dec31_dec_sub27_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h00: + SHIFT_ROT_dec31_dec_sub27_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h19: + SHIFT_ROT_dec31_dec_sub27_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + SHIFT_ROT_dec31_dec_sub27_SV_Ptype = 2'h1; + endcase + end always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub27_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: SHIFT_ROT_dec31_dec_sub27_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: SHIFT_ROT_dec31_dec_sub27_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: SHIFT_ROT_dec31_dec_sub27_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: SHIFT_ROT_dec31_dec_sub27_in2_sel = 4'h1; endcase @@ -20048,18 +22129,18 @@ module SHIFT_ROT_dec31_dec_sub27(SHIFT_ROT_dec31_dec_sub27_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub27_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: SHIFT_ROT_dec31_dec_sub27_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: SHIFT_ROT_dec31_dec_sub27_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: SHIFT_ROT_dec31_dec_sub27_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: SHIFT_ROT_dec31_dec_sub27_cr_in = 3'h0; endcase @@ -20067,18 +22148,18 @@ module SHIFT_ROT_dec31_dec_sub27(SHIFT_ROT_dec31_dec_sub27_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub27_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: SHIFT_ROT_dec31_dec_sub27_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: SHIFT_ROT_dec31_dec_sub27_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: SHIFT_ROT_dec31_dec_sub27_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: SHIFT_ROT_dec31_dec_sub27_cr_out = 3'h1; endcase @@ -20086,18 +22167,18 @@ module SHIFT_ROT_dec31_dec_sub27(SHIFT_ROT_dec31_dec_sub27_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub27_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: SHIFT_ROT_dec31_dec_sub27_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: SHIFT_ROT_dec31_dec_sub27_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: SHIFT_ROT_dec31_dec_sub27_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: SHIFT_ROT_dec31_dec_sub27_rc_sel = 2'h2; endcase @@ -20105,18 +22186,18 @@ module SHIFT_ROT_dec31_dec_sub27(SHIFT_ROT_dec31_dec_sub27_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub27_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: SHIFT_ROT_dec31_dec_sub27_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: SHIFT_ROT_dec31_dec_sub27_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: SHIFT_ROT_dec31_dec_sub27_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: SHIFT_ROT_dec31_dec_sub27_cry_in = 2'h0; endcase @@ -20124,48 +22205,36 @@ module SHIFT_ROT_dec31_dec_sub27(SHIFT_ROT_dec31_dec_sub27_function_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT_dec31_dec_sub27_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: SHIFT_ROT_dec31_dec_sub27_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: SHIFT_ROT_dec31_dec_sub27_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: SHIFT_ROT_dec31_dec_sub27_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: SHIFT_ROT_dec31_dec_sub27_inv_a = 1'h0; endcase end - always @* begin - if (\initial ) begin end - SHIFT_ROT_dec31_dec_sub27_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) - casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h1b: - SHIFT_ROT_dec31_dec_sub27_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h00: - SHIFT_ROT_dec31_dec_sub27_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h19: - SHIFT_ROT_dec31_dec_sub27_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h10: - SHIFT_ROT_dec31_dec_sub27_cry_out = 1'h0; - endcase - end assign opcode_switch = opcode_in[10:6]; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_SPR.dec.SPR_dec31" *) (* generator = "nMigen" *) -module SPR_dec31(SPR_dec31_function_unit, SPR_dec31_internal_op, SPR_dec31_cr_in, SPR_dec31_cr_out, SPR_dec31_rc_sel, SPR_dec31_is_32b, opcode_in); +module SPR_dec31(SPR_dec31_function_unit, SPR_dec31_internal_op, SPR_dec31_SV_Ptype, SPR_dec31_cr_in, SPR_dec31_cr_out, SPR_dec31_rc_sel, SPR_dec31_is_32b, opcode_in); reg \initial = 0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] SPR_dec31_SV_Ptype; + reg [1:0] SPR_dec31_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -20175,7 +22244,7 @@ module SPR_dec31(SPR_dec31_function_unit, SPR_dec31_internal_op, SPR_dec31_cr_in (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SPR_dec31_cr_in; reg [2:0] SPR_dec31_cr_in; (* enum_base_type = "CROutSel" *) @@ -20185,9 +22254,15 @@ module SPR_dec31(SPR_dec31_function_unit, SPR_dec31_internal_op, SPR_dec31_cr_in (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SPR_dec31_cr_out; reg [2:0] SPR_dec31_cr_out; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -20197,7 +22272,7 @@ module SPR_dec31(SPR_dec31_function_unit, SPR_dec31_internal_op, SPR_dec31_cr_in (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -20206,25 +22281,26 @@ module SPR_dec31(SPR_dec31_function_unit, SPR_dec31_internal_op, SPR_dec31_cr_in (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -20300,36 +22376,39 @@ module SPR_dec31(SPR_dec31_function_unit, SPR_dec31_internal_op, SPR_dec31_cr_in (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] SPR_dec31_dec_sub19_opcode_in; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] SPR_dec31_function_unit; - reg [13:0] SPR_dec31_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] SPR_dec31_function_unit; + reg [14:0] SPR_dec31_function_unit; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -20405,26 +22484,29 @@ module SPR_dec31(SPR_dec31_function_unit, SPR_dec31_internal_op, SPR_dec31_cr_in (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] SPR_dec31_internal_op; reg [6:0] SPR_dec31_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SPR_dec31_is_32b; reg SPR_dec31_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] SPR_dec31_rc_sel; reg [1:0] SPR_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:355" *) wire [4:0] opc_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [9:0] opcode_switch; SPR_dec31_dec_sub19 SPR_dec31_dec_sub19 ( + .SPR_dec31_dec_sub19_SV_Ptype(SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_SV_Ptype), .SPR_dec31_dec_sub19_cr_in(SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in), .SPR_dec31_dec_sub19_cr_out(SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out), .SPR_dec31_dec_sub19_function_unit(SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit), @@ -20435,10 +22517,10 @@ module SPR_dec31(SPR_dec31_function_unit, SPR_dec31_internal_op, SPR_dec31_cr_in ); always @* begin if (\initial ) begin end - SPR_dec31_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + SPR_dec31_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: SPR_dec31_function_unit = SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit; endcase @@ -20446,19 +22528,29 @@ module SPR_dec31(SPR_dec31_function_unit, SPR_dec31_internal_op, SPR_dec31_cr_in always @* begin if (\initial ) begin end SPR_dec31_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: SPR_dec31_internal_op = SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op; endcase end + always @* begin + if (\initial ) begin end + SPR_dec31_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opc_in) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + SPR_dec31_SV_Ptype = SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_SV_Ptype; + endcase + end always @* begin if (\initial ) begin end SPR_dec31_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: SPR_dec31_cr_in = SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in; endcase @@ -20466,9 +22558,9 @@ module SPR_dec31(SPR_dec31_function_unit, SPR_dec31_internal_op, SPR_dec31_cr_in always @* begin if (\initial ) begin end SPR_dec31_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: SPR_dec31_cr_out = SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out; endcase @@ -20476,9 +22568,9 @@ module SPR_dec31(SPR_dec31_function_unit, SPR_dec31_internal_op, SPR_dec31_cr_in always @* begin if (\initial ) begin end SPR_dec31_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: SPR_dec31_rc_sel = SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel; endcase @@ -20486,9 +22578,9 @@ module SPR_dec31(SPR_dec31_function_unit, SPR_dec31_internal_op, SPR_dec31_cr_in always @* begin if (\initial ) begin end SPR_dec31_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: SPR_dec31_is_32b = SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b; endcase @@ -20500,8 +22592,15 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_SPR.dec.SPR_dec31.SPR_dec31_dec_sub19" *) (* generator = "nMigen" *) -module SPR_dec31_dec_sub19(SPR_dec31_dec_sub19_function_unit, SPR_dec31_dec_sub19_internal_op, SPR_dec31_dec_sub19_cr_in, SPR_dec31_dec_sub19_cr_out, SPR_dec31_dec_sub19_rc_sel, SPR_dec31_dec_sub19_is_32b, opcode_in); +module SPR_dec31_dec_sub19(SPR_dec31_dec_sub19_function_unit, SPR_dec31_dec_sub19_internal_op, SPR_dec31_dec_sub19_SV_Ptype, SPR_dec31_dec_sub19_cr_in, SPR_dec31_dec_sub19_cr_out, SPR_dec31_dec_sub19_rc_sel, SPR_dec31_dec_sub19_is_32b, opcode_in); reg \initial = 0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [1:0] SPR_dec31_dec_sub19_SV_Ptype; + reg [1:0] SPR_dec31_dec_sub19_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -20511,7 +22610,7 @@ module SPR_dec31_dec_sub19(SPR_dec31_dec_sub19_function_unit, SPR_dec31_dec_sub1 (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SPR_dec31_dec_sub19_cr_in; reg [2:0] SPR_dec31_dec_sub19_cr_in; (* enum_base_type = "CROutSel" *) @@ -20521,27 +22620,28 @@ module SPR_dec31_dec_sub19(SPR_dec31_dec_sub19_function_unit, SPR_dec31_dec_sub1 (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SPR_dec31_dec_sub19_cr_out; reg [2:0] SPR_dec31_dec_sub19_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] SPR_dec31_dec_sub19_function_unit; - reg [13:0] SPR_dec31_dec_sub19_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] SPR_dec31_dec_sub19_function_unit; + reg [14:0] SPR_dec31_dec_sub19_function_unit; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -20617,58 +22717,73 @@ module SPR_dec31_dec_sub19(SPR_dec31_dec_sub19_function_unit, SPR_dec31_dec_sub1 (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] SPR_dec31_dec_sub19_internal_op; reg [6:0] SPR_dec31_dec_sub19_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SPR_dec31_dec_sub19_is_32b; reg SPR_dec31_dec_sub19_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] SPR_dec31_dec_sub19_rc_sel; reg [1:0] SPR_dec31_dec_sub19_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - SPR_dec31_dec_sub19_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + SPR_dec31_dec_sub19_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: - SPR_dec31_dec_sub19_function_unit = 14'h0400; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + SPR_dec31_dec_sub19_function_unit = 15'h0400; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: - SPR_dec31_dec_sub19_function_unit = 14'h0400; + SPR_dec31_dec_sub19_function_unit = 15'h0400; endcase end always @* begin if (\initial ) begin end SPR_dec31_dec_sub19_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: SPR_dec31_dec_sub19_internal_op = 7'h2e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: SPR_dec31_dec_sub19_internal_op = 7'h31; endcase end + always @* begin + if (\initial ) begin end + SPR_dec31_dec_sub19_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0a: + SPR_dec31_dec_sub19_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0e: + SPR_dec31_dec_sub19_SV_Ptype = 2'h2; + endcase + end always @* begin if (\initial ) begin end SPR_dec31_dec_sub19_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: SPR_dec31_dec_sub19_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: SPR_dec31_dec_sub19_cr_in = 3'h0; endcase @@ -20676,12 +22791,12 @@ module SPR_dec31_dec_sub19(SPR_dec31_dec_sub19_function_unit, SPR_dec31_dec_sub1 always @* begin if (\initial ) begin end SPR_dec31_dec_sub19_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: SPR_dec31_dec_sub19_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: SPR_dec31_dec_sub19_cr_out = 3'h0; endcase @@ -20689,12 +22804,12 @@ module SPR_dec31_dec_sub19(SPR_dec31_dec_sub19_function_unit, SPR_dec31_dec_sub1 always @* begin if (\initial ) begin end SPR_dec31_dec_sub19_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: SPR_dec31_dec_sub19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: SPR_dec31_dec_sub19_rc_sel = 2'h0; endcase @@ -20702,12 +22817,12 @@ module SPR_dec31_dec_sub19(SPR_dec31_dec_sub19_function_unit, SPR_dec31_dec_sub1 always @* begin if (\initial ) begin end SPR_dec31_dec_sub19_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: SPR_dec31_dec_sub19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: SPR_dec31_dec_sub19_is_32b = 1'h0; endcase @@ -20735,9 +22850,9 @@ module adr_l(coresync_rst, s_adr, r_adr, q_adr, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_adr; @@ -20766,7 +22881,7 @@ module adr_l(coresync_rst, s_adr, r_adr, q_adr, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -20797,9 +22912,9 @@ module adrok_l(coresync_rst, s_addr_acked, r_addr_acked, qn_addr_acked, q_addr_a wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_addr_acked; @@ -20828,7 +22943,7 @@ module adrok_l(coresync_rst, s_addr_acked, r_addr_acked, qn_addr_acked, q_addr_a always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -20841,7 +22956,7 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0" *) (* generator = "nMigen" *) -module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, oper_i_alu_alu0__imm_data__data, oper_i_alu_alu0__imm_data__ok, oper_i_alu_alu0__rc__rc, oper_i_alu_alu0__rc__ok, oper_i_alu_alu0__oe__oe, oper_i_alu_alu0__oe__ok, oper_i_alu_alu0__invert_in, oper_i_alu_alu0__zero_a, oper_i_alu_alu0__invert_out, oper_i_alu_alu0__write_cr0, oper_i_alu_alu0__input_carry, oper_i_alu_alu0__output_carry, oper_i_alu_alu0__is_32bit, oper_i_alu_alu0__is_signed, oper_i_alu_alu0__data_len, oper_i_alu_alu0__insn, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, src4_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, cr_a_ok, dest2_o, xer_ca_ok, dest3_o, xer_ov_ok, dest4_o, xer_so_ok, dest5_o, coresync_clk); +module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, oper_i_alu_alu0__imm_data__data, oper_i_alu_alu0__imm_data__ok, oper_i_alu_alu0__rc__rc, oper_i_alu_alu0__rc__ok, oper_i_alu_alu0__oe__oe, oper_i_alu_alu0__oe__ok, oper_i_alu_alu0__invert_in, oper_i_alu_alu0__zero_a, oper_i_alu_alu0__invert_out, oper_i_alu_alu0__write_cr0, oper_i_alu_alu0__input_carry, oper_i_alu_alu0__output_carry, oper_i_alu_alu0__is_32bit, oper_i_alu_alu0__is_signed, oper_i_alu_alu0__data_len, oper_i_alu_alu0__insn, oper_i_alu_alu0__sv_pred_sz, oper_i_alu_alu0__sv_pred_dz, oper_i_alu_alu0__sv_saturate, oper_i_alu_alu0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, src4_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, cr_a_ok, dest2_o, xer_ca_ok, dest3_o, xer_ov_ok, dest4_o, xer_so_ok, dest5_o, coresync_clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) wire \$101 ; @@ -20987,48 +23102,57 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, wire all_rd_pulse; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) wire all_rd_rise; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] alu_alu0_alu_op__SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \alu_alu0_alu_op__SV_Ptype$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [3:0] alu_alu0_alu_op__data_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [3:0] \alu_alu0_alu_op__data_len$next ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] alu_alu0_alu_op__fn_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] \alu_alu0_alu_op__fn_unit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] alu_alu0_alu_op__fn_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] \alu_alu0_alu_op__fn_unit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] alu_alu0_alu_op__imm_data__data = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] \alu_alu0_alu_op__imm_data__data$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_alu0_alu_op__imm_data__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_alu0_alu_op__imm_data__ok$next ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [1:0] alu_alu0_alu_op__input_carry = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [1:0] \alu_alu0_alu_op__input_carry$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] alu_alu0_alu_op__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] \alu_alu0_alu_op__insn$next ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -21105,79 +23229,97 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] alu_alu0_alu_op__insn_type = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] \alu_alu0_alu_op__insn_type$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_alu0_alu_op__invert_in = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_alu0_alu_op__invert_in$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_alu0_alu_op__invert_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_alu0_alu_op__invert_out$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_alu0_alu_op__is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_alu0_alu_op__is_32bit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_alu0_alu_op__is_signed = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_alu0_alu_op__is_signed$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_alu0_alu_op__oe__oe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_alu0_alu_op__oe__oe$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_alu0_alu_op__oe__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_alu0_alu_op__oe__ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_alu0_alu_op__output_carry = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_alu0_alu_op__output_carry$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_alu0_alu_op__rc__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_alu0_alu_op__rc__ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_alu0_alu_op__rc__rc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_alu0_alu_op__rc__rc$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg alu_alu0_alu_op__sv_pred_dz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \alu_alu0_alu_op__sv_pred_dz$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg alu_alu0_alu_op__sv_pred_sz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \alu_alu0_alu_op__sv_pred_sz$next ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] alu_alu0_alu_op__sv_saturate = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \alu_alu0_alu_op__sv_saturate$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_alu0_alu_op__write_cr0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_alu0_alu_op__write_cr0$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_alu0_alu_op__zero_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_alu0_alu_op__zero_a$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [3:0] alu_alu0_cr_a; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) wire alu_alu0_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire alu_alu0_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] alu_alu0_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire alu_alu0_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) wire alu_alu0_p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] alu_alu0_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] alu_alu0_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [1:0] alu_alu0_xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [1:0] \alu_alu0_xer_ca$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [1:0] alu_alu0_xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire alu_alu0_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire \alu_alu0_xer_so$1 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" *) wire alu_done; @@ -21207,11 +23349,11 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_a_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) output cu_busy_o; @@ -21290,7 +23432,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) output dest5_o; reg dest5_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire opc_l_q_opc; @@ -21302,36 +23444,43 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, reg opc_l_s_opc = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) reg \opc_l_s_opc$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_alu0__SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [3:0] oper_i_alu_alu0__data_len; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] oper_i_alu_alu0__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] oper_i_alu_alu0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] oper_i_alu_alu0__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_alu0__imm_data__ok; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] oper_i_alu_alu0__input_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] oper_i_alu_alu0__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -21408,29 +23557,41 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] oper_i_alu_alu0__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_alu0__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_alu0__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_alu0__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_alu0__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_alu0__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_alu0__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_alu0__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_alu0__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_alu0__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_alu0__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_alu0__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_alu0__sv_saturate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_alu0__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_alu0__zero_a; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *) reg [4:0] prev_wr_go = 5'h00; @@ -21518,11 +23679,11 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, wire \src_sel$85 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" *) wire wr_any; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_so_ok; assign \$5 = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$8 ; assign \$99 = alu_alu0_p_ready_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *) alui_l_q_alui; @@ -21659,6 +23820,14 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, alu_alu0_alu_op__data_len <= \alu_alu0_alu_op__data_len$next ; always @(posedge coresync_clk) alu_alu0_alu_op__insn <= \alu_alu0_alu_op__insn$next ; + always @(posedge coresync_clk) + alu_alu0_alu_op__sv_pred_sz <= \alu_alu0_alu_op__sv_pred_sz$next ; + always @(posedge coresync_clk) + alu_alu0_alu_op__sv_pred_dz <= \alu_alu0_alu_op__sv_pred_dz$next ; + always @(posedge coresync_clk) + alu_alu0_alu_op__sv_saturate <= \alu_alu0_alu_op__sv_saturate$next ; + always @(posedge coresync_clk) + alu_alu0_alu_op__SV_Ptype <= \alu_alu0_alu_op__SV_Ptype$next ; always @(posedge coresync_clk) req_l_r_req <= \req_l_r_req$next ; always @(posedge coresync_clk) @@ -21686,6 +23855,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @(posedge coresync_clk) all_rd_dly <= \$11 ; alu_alu0 alu_alu0 ( + .alu_op__SV_Ptype(alu_alu0_alu_op__SV_Ptype), .alu_op__data_len(alu_alu0_alu_op__data_len), .alu_op__fn_unit(alu_alu0_alu_op__fn_unit), .alu_op__imm_data__data(alu_alu0_alu_op__imm_data__data), @@ -21702,6 +23872,9 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, .alu_op__output_carry(alu_alu0_alu_op__output_carry), .alu_op__rc__ok(alu_alu0_alu_op__rc__ok), .alu_op__rc__rc(alu_alu0_alu_op__rc__rc), + .alu_op__sv_pred_dz(alu_alu0_alu_op__sv_pred_dz), + .alu_op__sv_pred_sz(alu_alu0_alu_op__sv_pred_sz), + .alu_op__sv_saturate(alu_alu0_alu_op__sv_saturate), .alu_op__write_cr0(alu_alu0_alu_op__write_cr0), .alu_op__zero_a(alu_alu0_alu_op__zero_a), .coresync_clk(coresync_clk), @@ -21786,7 +23959,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \rok_l_s_rdok$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_s_rdok$next = 1'h0; @@ -21795,7 +23968,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \rok_l_r_rdok$next = \$65 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_r_rdok$next = 1'h1; @@ -21804,7 +23977,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \rst_l_s_rst$next = all_rd; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_s_rst$next = 1'h0; @@ -21813,7 +23986,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \rst_l_r_rst$next = rst_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_r_rst$next = 1'h1; @@ -21822,7 +23995,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \opc_l_s_opc$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_s_opc$next = 1'h0; @@ -21831,7 +24004,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \opc_l_r_opc$next = req_done; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_r_opc$next = 1'h1; @@ -21840,7 +24013,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_s_src$next = 4'h0; @@ -21849,7 +24022,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \src_l_r_src$next = reset_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_r_src$next = 4'hf; @@ -21858,7 +24031,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \req_l_s_req$next = \$67 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_s_req$next = 5'h00; @@ -21867,7 +24040,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \req_l_r_req$next = \$69 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_r_req$next = 5'h1f; @@ -21893,13 +24066,17 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, \alu_alu0_alu_op__is_signed$next = alu_alu0_alu_op__is_signed; \alu_alu0_alu_op__data_len$next = alu_alu0_alu_op__data_len; \alu_alu0_alu_op__insn$next = alu_alu0_alu_op__insn; + \alu_alu0_alu_op__sv_pred_sz$next = alu_alu0_alu_op__sv_pred_sz; + \alu_alu0_alu_op__sv_pred_dz$next = alu_alu0_alu_op__sv_pred_dz; + \alu_alu0_alu_op__sv_saturate$next = alu_alu0_alu_op__sv_saturate; + \alu_alu0_alu_op__SV_Ptype$next = alu_alu0_alu_op__SV_Ptype; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *) casez (cu_issue_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" */ 1'h1: - { \alu_alu0_alu_op__insn$next , \alu_alu0_alu_op__data_len$next , \alu_alu0_alu_op__is_signed$next , \alu_alu0_alu_op__is_32bit$next , \alu_alu0_alu_op__output_carry$next , \alu_alu0_alu_op__input_carry$next , \alu_alu0_alu_op__write_cr0$next , \alu_alu0_alu_op__invert_out$next , \alu_alu0_alu_op__zero_a$next , \alu_alu0_alu_op__invert_in$next , \alu_alu0_alu_op__oe__ok$next , \alu_alu0_alu_op__oe__oe$next , \alu_alu0_alu_op__rc__ok$next , \alu_alu0_alu_op__rc__rc$next , \alu_alu0_alu_op__imm_data__ok$next , \alu_alu0_alu_op__imm_data__data$next , \alu_alu0_alu_op__fn_unit$next , \alu_alu0_alu_op__insn_type$next } = { oper_i_alu_alu0__insn, oper_i_alu_alu0__data_len, oper_i_alu_alu0__is_signed, oper_i_alu_alu0__is_32bit, oper_i_alu_alu0__output_carry, oper_i_alu_alu0__input_carry, oper_i_alu_alu0__write_cr0, oper_i_alu_alu0__invert_out, oper_i_alu_alu0__zero_a, oper_i_alu_alu0__invert_in, oper_i_alu_alu0__oe__ok, oper_i_alu_alu0__oe__oe, oper_i_alu_alu0__rc__ok, oper_i_alu_alu0__rc__rc, oper_i_alu_alu0__imm_data__ok, oper_i_alu_alu0__imm_data__data, oper_i_alu_alu0__fn_unit, oper_i_alu_alu0__insn_type }; + { \alu_alu0_alu_op__SV_Ptype$next , \alu_alu0_alu_op__sv_saturate$next , \alu_alu0_alu_op__sv_pred_dz$next , \alu_alu0_alu_op__sv_pred_sz$next , \alu_alu0_alu_op__insn$next , \alu_alu0_alu_op__data_len$next , \alu_alu0_alu_op__is_signed$next , \alu_alu0_alu_op__is_32bit$next , \alu_alu0_alu_op__output_carry$next , \alu_alu0_alu_op__input_carry$next , \alu_alu0_alu_op__write_cr0$next , \alu_alu0_alu_op__invert_out$next , \alu_alu0_alu_op__zero_a$next , \alu_alu0_alu_op__invert_in$next , \alu_alu0_alu_op__oe__ok$next , \alu_alu0_alu_op__oe__oe$next , \alu_alu0_alu_op__rc__ok$next , \alu_alu0_alu_op__rc__rc$next , \alu_alu0_alu_op__imm_data__ok$next , \alu_alu0_alu_op__imm_data__data$next , \alu_alu0_alu_op__fn_unit$next , \alu_alu0_alu_op__insn_type$next } = { oper_i_alu_alu0__SV_Ptype, oper_i_alu_alu0__sv_saturate, oper_i_alu_alu0__sv_pred_dz, oper_i_alu_alu0__sv_pred_sz, oper_i_alu_alu0__insn, oper_i_alu_alu0__data_len, oper_i_alu_alu0__is_signed, oper_i_alu_alu0__is_32bit, oper_i_alu_alu0__output_carry, oper_i_alu_alu0__input_carry, oper_i_alu_alu0__write_cr0, oper_i_alu_alu0__invert_out, oper_i_alu_alu0__zero_a, oper_i_alu_alu0__invert_in, oper_i_alu_alu0__oe__ok, oper_i_alu_alu0__oe__oe, oper_i_alu_alu0__rc__ok, oper_i_alu_alu0__rc__rc, oper_i_alu_alu0__imm_data__ok, oper_i_alu_alu0__imm_data__data, oper_i_alu_alu0__fn_unit, oper_i_alu_alu0__insn_type }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -21928,7 +24105,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, 1'h1: { \data_r0__o_ok$next , \data_r0__o$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r0__o_ok$next = 1'h0; @@ -21950,7 +24127,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, 1'h1: { \data_r1__cr_a_ok$next , \data_r1__cr_a$next } = 5'h00; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r1__cr_a_ok$next = 1'h0; @@ -21972,7 +24149,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, 1'h1: { \data_r2__xer_ca_ok$next , \data_r2__xer_ca$next } = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r2__xer_ca_ok$next = 1'h0; @@ -21994,7 +24171,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, 1'h1: { \data_r3__xer_ov_ok$next , \data_r3__xer_ov$next } = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r3__xer_ov_ok$next = 1'h0; @@ -22016,7 +24193,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, 1'h1: { \data_r4__xer_so_ok$next , \data_r4__xer_so$next } = 2'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r4__xer_so_ok$next = 1'h0; @@ -22065,7 +24242,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \alui_l_r_alui$next = \$99 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alui_l_r_alui$next = 1'h1; @@ -22074,7 +24251,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \alu_l_r_alu$next = \$101 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alu_l_r_alu$next = 1'h1; @@ -22133,7 +24310,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \prev_wr_go$next = \$21 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \prev_wr_go$next = 5'h00; @@ -22176,69 +24353,83 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.alu_alu0" *) (* generator = "nMigen" *) -module alu_alu0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ready_i, alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, o, cr_a, xer_ca, xer_ov, xer_so, ra, rb, \xer_so$1 , \xer_ca$2 , p_valid_i, p_ready_o, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) +module alu_alu0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ready_i, alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, alu_op__sv_pred_sz, alu_op__sv_pred_dz, alu_op__sv_saturate, alu_op__SV_Ptype, o, cr_a, xer_ca, xer_ov, xer_so, ra, rb, \xer_so$1 , \xer_ca$2 , p_valid_i, p_ready_o, coresync_clk); + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] alu_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \alu_op__SV_Ptype$83 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [3:0] alu_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [3:0] \alu_op__data_len$70 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [3:0] \alu_op__data_len$78 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] alu_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] alu_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \alu_op__fn_unit$55 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \alu_op__fn_unit$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] alu_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \alu_op__imm_data__data$56 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \alu_op__imm_data__data$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__imm_data__ok$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__imm_data__ok$65 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] alu_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [1:0] \alu_op__input_carry$66 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \alu_op__input_carry$74 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] alu_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \alu_op__insn$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \alu_op__insn$79 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -22314,7 +24505,9 @@ module alu_alu0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, n_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] alu_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -22391,137 +24584,173 @@ module alu_alu0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, n_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \alu_op__insn_type$54 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \alu_op__insn_type$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__invert_in$62 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__invert_in$70 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__invert_out$64 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__invert_out$72 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__is_32bit$68 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__is_32bit$76 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__is_signed$69 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__is_signed$77 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__oe__oe$60 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__oe__oe$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__oe__ok$61 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__oe__ok$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__output_carry$67 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__output_carry$75 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__rc__ok$59 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__rc__ok$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__rc__rc$58 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__rc__rc$66 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input alu_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__sv_pred_dz$81 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input alu_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__sv_pred_sz$80 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] alu_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \alu_op__sv_saturate$82 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__write_cr0$65 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__write_cr0$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__zero_a$63 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__zero_a$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_a_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \muxid$53 ; + wire [1:0] \muxid$61 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) input p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] pipe1_alu_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \pipe1_alu_op__SV_Ptype$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [3:0] pipe1_alu_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [3:0] \pipe1_alu_op__data_len$20 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] pipe1_alu_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] pipe1_alu_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \pipe1_alu_op__fn_unit$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \pipe1_alu_op__fn_unit$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] pipe1_alu_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] \pipe1_alu_op__imm_data__data$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe1_alu_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe1_alu_op__imm_data__ok$7 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [1:0] pipe1_alu_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [1:0] \pipe1_alu_op__input_carry$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] pipe1_alu_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] \pipe1_alu_op__insn$21 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -22598,7 +24827,9 @@ module alu_alu0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, n_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] pipe1_alu_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -22675,55 +24906,77 @@ module alu_alu0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, n_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] \pipe1_alu_op__insn_type$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe1_alu_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe1_alu_op__invert_in$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe1_alu_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe1_alu_op__invert_out$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe1_alu_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe1_alu_op__is_32bit$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe1_alu_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe1_alu_op__is_signed$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe1_alu_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe1_alu_op__oe__oe$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe1_alu_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe1_alu_op__oe__ok$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe1_alu_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe1_alu_op__output_carry$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe1_alu_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe1_alu_op__rc__ok$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe1_alu_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe1_alu_op__rc__rc$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire pipe1_alu_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe1_alu_op__sv_pred_dz$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire pipe1_alu_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe1_alu_op__sv_pred_sz$22 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] pipe1_alu_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \pipe1_alu_op__sv_saturate$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe1_alu_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe1_alu_op__write_cr0$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe1_alu_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe1_alu_op__zero_a$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [3:0] pipe1_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe1_cr_a_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] pipe1_muxid; @@ -22733,96 +24986,110 @@ module alu_alu0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, n_ wire pipe1_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire pipe1_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] pipe1_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe1_o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire pipe1_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) wire pipe1_p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] pipe1_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] pipe1_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [1:0] pipe1_xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [1:0] \pipe1_xer_ca$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [1:0] \pipe1_xer_ca$27 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe1_xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [1:0] pipe1_xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe1_xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe1_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire \pipe1_xer_so$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire \pipe1_xer_so$26 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe1_xer_so_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] pipe2_alu_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \pipe2_alu_op__SV_Ptype$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [3:0] pipe2_alu_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [3:0] \pipe2_alu_op__data_len$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [3:0] \pipe2_alu_op__data_len$45 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] pipe2_alu_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] pipe2_alu_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \pipe2_alu_op__fn_unit$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \pipe2_alu_op__fn_unit$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] pipe2_alu_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \pipe2_alu_op__imm_data__data$27 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \pipe2_alu_op__imm_data__data$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe2_alu_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe2_alu_op__imm_data__ok$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe2_alu_op__imm_data__ok$32 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [1:0] pipe2_alu_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [1:0] \pipe2_alu_op__input_carry$37 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \pipe2_alu_op__input_carry$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] pipe2_alu_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \pipe2_alu_op__insn$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \pipe2_alu_op__insn$46 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -22898,7 +25165,9 @@ module alu_alu0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, n_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] pipe2_alu_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -22975,123 +25244,145 @@ module alu_alu0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, n_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \pipe2_alu_op__insn_type$25 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \pipe2_alu_op__insn_type$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe2_alu_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe2_alu_op__invert_in$33 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe2_alu_op__invert_in$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe2_alu_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe2_alu_op__invert_out$35 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe2_alu_op__invert_out$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe2_alu_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe2_alu_op__is_32bit$39 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe2_alu_op__is_32bit$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe2_alu_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe2_alu_op__is_signed$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe2_alu_op__is_signed$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe2_alu_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe2_alu_op__oe__oe$31 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe2_alu_op__oe__oe$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe2_alu_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe2_alu_op__oe__ok$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe2_alu_op__oe__ok$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe2_alu_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe2_alu_op__output_carry$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe2_alu_op__output_carry$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe2_alu_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe2_alu_op__rc__ok$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe2_alu_op__rc__ok$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe2_alu_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe2_alu_op__rc__rc$29 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe2_alu_op__rc__rc$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire pipe2_alu_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe2_alu_op__sv_pred_dz$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire pipe2_alu_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe2_alu_op__sv_pred_sz$47 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] pipe2_alu_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \pipe2_alu_op__sv_saturate$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe2_alu_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe2_alu_op__write_cr0$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe2_alu_op__write_cr0$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe2_alu_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe2_alu_op__zero_a$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe2_alu_op__zero_a$38 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [3:0] pipe2_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [3:0] \pipe2_cr_a$45 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [3:0] \pipe2_cr_a$53 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe2_cr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \pipe2_cr_a_ok$46 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \pipe2_cr_a_ok$54 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] pipe2_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \pipe2_muxid$24 ; + wire [1:0] \pipe2_muxid$28 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) wire pipe2_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire pipe2_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] pipe2_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \pipe2_o$43 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \pipe2_o$51 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe2_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \pipe2_o_ok$44 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \pipe2_o_ok$52 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire pipe2_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) wire pipe2_p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [1:0] pipe2_xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [1:0] \pipe2_xer_ca$47 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [1:0] \pipe2_xer_ca$55 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe2_xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \pipe2_xer_ca_ok$48 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \pipe2_xer_ca_ok$56 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [1:0] pipe2_xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [1:0] \pipe2_xer_ov$49 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [1:0] \pipe2_xer_ov$57 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe2_xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \pipe2_xer_ov_ok$50 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \pipe2_xer_ov_ok$58 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe2_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \pipe2_xer_so$51 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \pipe2_xer_so$59 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe2_xer_so_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \pipe2_xer_so_ok$52 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \pipe2_xer_so_ok$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [1:0] xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [1:0] \xer_ca$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [1:0] xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input \xer_so$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_so_ok; n n ( .n_ready_i(n_ready_i), @@ -23102,6 +25393,8 @@ module alu_alu0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, n_ .p_valid_i(p_valid_i) ); pipe1 pipe1 ( + .alu_op__SV_Ptype(pipe1_alu_op__SV_Ptype), + .\alu_op__SV_Ptype$23 (\pipe1_alu_op__SV_Ptype$25 ), .alu_op__data_len(pipe1_alu_op__data_len), .\alu_op__data_len$18 (\pipe1_alu_op__data_len$20 ), .alu_op__fn_unit(pipe1_alu_op__fn_unit), @@ -23134,6 +25427,12 @@ module alu_alu0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, n_ .\alu_op__rc__ok$7 (\pipe1_alu_op__rc__ok$9 ), .alu_op__rc__rc(pipe1_alu_op__rc__rc), .\alu_op__rc__rc$6 (\pipe1_alu_op__rc__rc$8 ), + .alu_op__sv_pred_dz(pipe1_alu_op__sv_pred_dz), + .\alu_op__sv_pred_dz$21 (\pipe1_alu_op__sv_pred_dz$23 ), + .alu_op__sv_pred_sz(pipe1_alu_op__sv_pred_sz), + .\alu_op__sv_pred_sz$20 (\pipe1_alu_op__sv_pred_sz$22 ), + .alu_op__sv_saturate(pipe1_alu_op__sv_saturate), + .\alu_op__sv_saturate$22 (\pipe1_alu_op__sv_saturate$24 ), .alu_op__write_cr0(pipe1_alu_op__write_cr0), .\alu_op__write_cr0$13 (\pipe1_alu_op__write_cr0$15 ), .alu_op__zero_a(pipe1_alu_op__zero_a), @@ -23153,95 +25452,103 @@ module alu_alu0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, n_ .ra(pipe1_ra), .rb(pipe1_rb), .xer_ca(pipe1_xer_ca), - .\xer_ca$21 (\pipe1_xer_ca$23 ), + .\xer_ca$25 (\pipe1_xer_ca$27 ), .xer_ca_ok(pipe1_xer_ca_ok), .xer_ov(pipe1_xer_ov), .xer_ov_ok(pipe1_xer_ov_ok), .xer_so(pipe1_xer_so), - .\xer_so$20 (\pipe1_xer_so$22 ), + .\xer_so$24 (\pipe1_xer_so$26 ), .xer_so_ok(pipe1_xer_so_ok) ); pipe2 pipe2 ( + .alu_op__SV_Ptype(pipe2_alu_op__SV_Ptype), + .\alu_op__SV_Ptype$23 (\pipe2_alu_op__SV_Ptype$50 ), .alu_op__data_len(pipe2_alu_op__data_len), - .\alu_op__data_len$18 (\pipe2_alu_op__data_len$41 ), + .\alu_op__data_len$18 (\pipe2_alu_op__data_len$45 ), .alu_op__fn_unit(pipe2_alu_op__fn_unit), - .\alu_op__fn_unit$3 (\pipe2_alu_op__fn_unit$26 ), + .\alu_op__fn_unit$3 (\pipe2_alu_op__fn_unit$30 ), .alu_op__imm_data__data(pipe2_alu_op__imm_data__data), - .\alu_op__imm_data__data$4 (\pipe2_alu_op__imm_data__data$27 ), + .\alu_op__imm_data__data$4 (\pipe2_alu_op__imm_data__data$31 ), .alu_op__imm_data__ok(pipe2_alu_op__imm_data__ok), - .\alu_op__imm_data__ok$5 (\pipe2_alu_op__imm_data__ok$28 ), + .\alu_op__imm_data__ok$5 (\pipe2_alu_op__imm_data__ok$32 ), .alu_op__input_carry(pipe2_alu_op__input_carry), - .\alu_op__input_carry$14 (\pipe2_alu_op__input_carry$37 ), + .\alu_op__input_carry$14 (\pipe2_alu_op__input_carry$41 ), .alu_op__insn(pipe2_alu_op__insn), - .\alu_op__insn$19 (\pipe2_alu_op__insn$42 ), + .\alu_op__insn$19 (\pipe2_alu_op__insn$46 ), .alu_op__insn_type(pipe2_alu_op__insn_type), - .\alu_op__insn_type$2 (\pipe2_alu_op__insn_type$25 ), + .\alu_op__insn_type$2 (\pipe2_alu_op__insn_type$29 ), .alu_op__invert_in(pipe2_alu_op__invert_in), - .\alu_op__invert_in$10 (\pipe2_alu_op__invert_in$33 ), + .\alu_op__invert_in$10 (\pipe2_alu_op__invert_in$37 ), .alu_op__invert_out(pipe2_alu_op__invert_out), - .\alu_op__invert_out$12 (\pipe2_alu_op__invert_out$35 ), + .\alu_op__invert_out$12 (\pipe2_alu_op__invert_out$39 ), .alu_op__is_32bit(pipe2_alu_op__is_32bit), - .\alu_op__is_32bit$16 (\pipe2_alu_op__is_32bit$39 ), + .\alu_op__is_32bit$16 (\pipe2_alu_op__is_32bit$43 ), .alu_op__is_signed(pipe2_alu_op__is_signed), - .\alu_op__is_signed$17 (\pipe2_alu_op__is_signed$40 ), + .\alu_op__is_signed$17 (\pipe2_alu_op__is_signed$44 ), .alu_op__oe__oe(pipe2_alu_op__oe__oe), - .\alu_op__oe__oe$8 (\pipe2_alu_op__oe__oe$31 ), + .\alu_op__oe__oe$8 (\pipe2_alu_op__oe__oe$35 ), .alu_op__oe__ok(pipe2_alu_op__oe__ok), - .\alu_op__oe__ok$9 (\pipe2_alu_op__oe__ok$32 ), + .\alu_op__oe__ok$9 (\pipe2_alu_op__oe__ok$36 ), .alu_op__output_carry(pipe2_alu_op__output_carry), - .\alu_op__output_carry$15 (\pipe2_alu_op__output_carry$38 ), + .\alu_op__output_carry$15 (\pipe2_alu_op__output_carry$42 ), .alu_op__rc__ok(pipe2_alu_op__rc__ok), - .\alu_op__rc__ok$7 (\pipe2_alu_op__rc__ok$30 ), + .\alu_op__rc__ok$7 (\pipe2_alu_op__rc__ok$34 ), .alu_op__rc__rc(pipe2_alu_op__rc__rc), - .\alu_op__rc__rc$6 (\pipe2_alu_op__rc__rc$29 ), + .\alu_op__rc__rc$6 (\pipe2_alu_op__rc__rc$33 ), + .alu_op__sv_pred_dz(pipe2_alu_op__sv_pred_dz), + .\alu_op__sv_pred_dz$21 (\pipe2_alu_op__sv_pred_dz$48 ), + .alu_op__sv_pred_sz(pipe2_alu_op__sv_pred_sz), + .\alu_op__sv_pred_sz$20 (\pipe2_alu_op__sv_pred_sz$47 ), + .alu_op__sv_saturate(pipe2_alu_op__sv_saturate), + .\alu_op__sv_saturate$22 (\pipe2_alu_op__sv_saturate$49 ), .alu_op__write_cr0(pipe2_alu_op__write_cr0), - .\alu_op__write_cr0$13 (\pipe2_alu_op__write_cr0$36 ), + .\alu_op__write_cr0$13 (\pipe2_alu_op__write_cr0$40 ), .alu_op__zero_a(pipe2_alu_op__zero_a), - .\alu_op__zero_a$11 (\pipe2_alu_op__zero_a$34 ), + .\alu_op__zero_a$11 (\pipe2_alu_op__zero_a$38 ), .coresync_clk(coresync_clk), .coresync_rst(coresync_rst), .cr_a(pipe2_cr_a), - .\cr_a$22 (\pipe2_cr_a$45 ), + .\cr_a$26 (\pipe2_cr_a$53 ), .cr_a_ok(pipe2_cr_a_ok), - .\cr_a_ok$23 (\pipe2_cr_a_ok$46 ), + .\cr_a_ok$27 (\pipe2_cr_a_ok$54 ), .muxid(pipe2_muxid), - .\muxid$1 (\pipe2_muxid$24 ), + .\muxid$1 (\pipe2_muxid$28 ), .n_ready_i(pipe2_n_ready_i), .n_valid_o(pipe2_n_valid_o), .o(pipe2_o), - .\o$20 (\pipe2_o$43 ), + .\o$24 (\pipe2_o$51 ), .o_ok(pipe2_o_ok), - .\o_ok$21 (\pipe2_o_ok$44 ), + .\o_ok$25 (\pipe2_o_ok$52 ), .p_ready_o(pipe2_p_ready_o), .p_valid_i(pipe2_p_valid_i), .xer_ca(pipe2_xer_ca), - .\xer_ca$24 (\pipe2_xer_ca$47 ), + .\xer_ca$28 (\pipe2_xer_ca$55 ), .xer_ca_ok(pipe2_xer_ca_ok), - .\xer_ca_ok$25 (\pipe2_xer_ca_ok$48 ), + .\xer_ca_ok$29 (\pipe2_xer_ca_ok$56 ), .xer_ov(pipe2_xer_ov), - .\xer_ov$26 (\pipe2_xer_ov$49 ), + .\xer_ov$30 (\pipe2_xer_ov$57 ), .xer_ov_ok(pipe2_xer_ov_ok), - .\xer_ov_ok$27 (\pipe2_xer_ov_ok$50 ), + .\xer_ov_ok$31 (\pipe2_xer_ov_ok$58 ), .xer_so(pipe2_xer_so), - .\xer_so$28 (\pipe2_xer_so$51 ), + .\xer_so$32 (\pipe2_xer_so$59 ), .xer_so_ok(pipe2_xer_so_ok), - .\xer_so_ok$29 (\pipe2_xer_so_ok$52 ) + .\xer_so_ok$33 (\pipe2_xer_so_ok$60 ) ); assign muxid = 2'h0; - assign { xer_so_ok, xer_so } = { \pipe2_xer_so_ok$52 , \pipe2_xer_so$51 }; - assign { xer_ov_ok, xer_ov } = { \pipe2_xer_ov_ok$50 , \pipe2_xer_ov$49 }; - assign { xer_ca_ok, xer_ca } = { \pipe2_xer_ca_ok$48 , \pipe2_xer_ca$47 }; - assign { cr_a_ok, cr_a } = { \pipe2_cr_a_ok$46 , \pipe2_cr_a$45 }; - assign { o_ok, o } = { \pipe2_o_ok$44 , \pipe2_o$43 }; - assign { \alu_op__insn$71 , \alu_op__data_len$70 , \alu_op__is_signed$69 , \alu_op__is_32bit$68 , \alu_op__output_carry$67 , \alu_op__input_carry$66 , \alu_op__write_cr0$65 , \alu_op__invert_out$64 , \alu_op__zero_a$63 , \alu_op__invert_in$62 , \alu_op__oe__ok$61 , \alu_op__oe__oe$60 , \alu_op__rc__ok$59 , \alu_op__rc__rc$58 , \alu_op__imm_data__ok$57 , \alu_op__imm_data__data$56 , \alu_op__fn_unit$55 , \alu_op__insn_type$54 } = { \pipe2_alu_op__insn$42 , \pipe2_alu_op__data_len$41 , \pipe2_alu_op__is_signed$40 , \pipe2_alu_op__is_32bit$39 , \pipe2_alu_op__output_carry$38 , \pipe2_alu_op__input_carry$37 , \pipe2_alu_op__write_cr0$36 , \pipe2_alu_op__invert_out$35 , \pipe2_alu_op__zero_a$34 , \pipe2_alu_op__invert_in$33 , \pipe2_alu_op__oe__ok$32 , \pipe2_alu_op__oe__oe$31 , \pipe2_alu_op__rc__ok$30 , \pipe2_alu_op__rc__rc$29 , \pipe2_alu_op__imm_data__ok$28 , \pipe2_alu_op__imm_data__data$27 , \pipe2_alu_op__fn_unit$26 , \pipe2_alu_op__insn_type$25 }; - assign \muxid$53 = \pipe2_muxid$24 ; + assign { xer_so_ok, xer_so } = { \pipe2_xer_so_ok$60 , \pipe2_xer_so$59 }; + assign { xer_ov_ok, xer_ov } = { \pipe2_xer_ov_ok$58 , \pipe2_xer_ov$57 }; + assign { xer_ca_ok, xer_ca } = { \pipe2_xer_ca_ok$56 , \pipe2_xer_ca$55 }; + assign { cr_a_ok, cr_a } = { \pipe2_cr_a_ok$54 , \pipe2_cr_a$53 }; + assign { o_ok, o } = { \pipe2_o_ok$52 , \pipe2_o$51 }; + assign { \alu_op__SV_Ptype$83 , \alu_op__sv_saturate$82 , \alu_op__sv_pred_dz$81 , \alu_op__sv_pred_sz$80 , \alu_op__insn$79 , \alu_op__data_len$78 , \alu_op__is_signed$77 , \alu_op__is_32bit$76 , \alu_op__output_carry$75 , \alu_op__input_carry$74 , \alu_op__write_cr0$73 , \alu_op__invert_out$72 , \alu_op__zero_a$71 , \alu_op__invert_in$70 , \alu_op__oe__ok$69 , \alu_op__oe__oe$68 , \alu_op__rc__ok$67 , \alu_op__rc__rc$66 , \alu_op__imm_data__ok$65 , \alu_op__imm_data__data$64 , \alu_op__fn_unit$63 , \alu_op__insn_type$62 } = { \pipe2_alu_op__SV_Ptype$50 , \pipe2_alu_op__sv_saturate$49 , \pipe2_alu_op__sv_pred_dz$48 , \pipe2_alu_op__sv_pred_sz$47 , \pipe2_alu_op__insn$46 , \pipe2_alu_op__data_len$45 , \pipe2_alu_op__is_signed$44 , \pipe2_alu_op__is_32bit$43 , \pipe2_alu_op__output_carry$42 , \pipe2_alu_op__input_carry$41 , \pipe2_alu_op__write_cr0$40 , \pipe2_alu_op__invert_out$39 , \pipe2_alu_op__zero_a$38 , \pipe2_alu_op__invert_in$37 , \pipe2_alu_op__oe__ok$36 , \pipe2_alu_op__oe__oe$35 , \pipe2_alu_op__rc__ok$34 , \pipe2_alu_op__rc__rc$33 , \pipe2_alu_op__imm_data__ok$32 , \pipe2_alu_op__imm_data__data$31 , \pipe2_alu_op__fn_unit$30 , \pipe2_alu_op__insn_type$29 }; + assign \muxid$61 = \pipe2_muxid$28 ; assign pipe2_n_ready_i = n_ready_i; assign n_valid_o = pipe2_n_valid_o; - assign \pipe1_xer_ca$23 = \xer_ca$2 ; - assign \pipe1_xer_so$22 = \xer_so$1 ; + assign \pipe1_xer_ca$27 = \xer_ca$2 ; + assign \pipe1_xer_so$26 = \xer_so$1 ; assign pipe1_rb = rb; assign pipe1_ra = ra; - assign { \pipe1_alu_op__insn$21 , \pipe1_alu_op__data_len$20 , \pipe1_alu_op__is_signed$19 , \pipe1_alu_op__is_32bit$18 , \pipe1_alu_op__output_carry$17 , \pipe1_alu_op__input_carry$16 , \pipe1_alu_op__write_cr0$15 , \pipe1_alu_op__invert_out$14 , \pipe1_alu_op__zero_a$13 , \pipe1_alu_op__invert_in$12 , \pipe1_alu_op__oe__ok$11 , \pipe1_alu_op__oe__oe$10 , \pipe1_alu_op__rc__ok$9 , \pipe1_alu_op__rc__rc$8 , \pipe1_alu_op__imm_data__ok$7 , \pipe1_alu_op__imm_data__data$6 , \pipe1_alu_op__fn_unit$5 , \pipe1_alu_op__insn_type$4 } = { alu_op__insn, alu_op__data_len, alu_op__is_signed, alu_op__is_32bit, alu_op__output_carry, alu_op__input_carry, alu_op__write_cr0, alu_op__invert_out, alu_op__zero_a, alu_op__invert_in, alu_op__oe__ok, alu_op__oe__oe, alu_op__rc__ok, alu_op__rc__rc, alu_op__imm_data__ok, alu_op__imm_data__data, alu_op__fn_unit, alu_op__insn_type }; + assign { \pipe1_alu_op__SV_Ptype$25 , \pipe1_alu_op__sv_saturate$24 , \pipe1_alu_op__sv_pred_dz$23 , \pipe1_alu_op__sv_pred_sz$22 , \pipe1_alu_op__insn$21 , \pipe1_alu_op__data_len$20 , \pipe1_alu_op__is_signed$19 , \pipe1_alu_op__is_32bit$18 , \pipe1_alu_op__output_carry$17 , \pipe1_alu_op__input_carry$16 , \pipe1_alu_op__write_cr0$15 , \pipe1_alu_op__invert_out$14 , \pipe1_alu_op__zero_a$13 , \pipe1_alu_op__invert_in$12 , \pipe1_alu_op__oe__ok$11 , \pipe1_alu_op__oe__oe$10 , \pipe1_alu_op__rc__ok$9 , \pipe1_alu_op__rc__rc$8 , \pipe1_alu_op__imm_data__ok$7 , \pipe1_alu_op__imm_data__data$6 , \pipe1_alu_op__fn_unit$5 , \pipe1_alu_op__insn_type$4 } = { alu_op__SV_Ptype, alu_op__sv_saturate, alu_op__sv_pred_dz, alu_op__sv_pred_sz, alu_op__insn, alu_op__data_len, alu_op__is_signed, alu_op__is_32bit, alu_op__output_carry, alu_op__input_carry, alu_op__write_cr0, alu_op__invert_out, alu_op__zero_a, alu_op__invert_in, alu_op__oe__ok, alu_op__oe__oe, alu_op__rc__ok, alu_op__rc__rc, alu_op__imm_data__ok, alu_op__imm_data__data, alu_op__fn_unit, alu_op__insn_type }; assign \pipe1_muxid$3 = 2'h0; assign p_ready_o = pipe1_p_ready_o; assign pipe1_p_valid_i = p_valid_i; @@ -23250,7 +25557,7 @@ module alu_alu0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, n_ assign { pipe2_xer_ca_ok, pipe2_xer_ca } = { pipe1_xer_ca_ok, pipe1_xer_ca }; assign { pipe2_cr_a_ok, pipe2_cr_a } = { pipe1_cr_a_ok, pipe1_cr_a }; assign { pipe2_o_ok, pipe2_o } = { pipe1_o_ok, pipe1_o }; - assign { pipe2_alu_op__insn, pipe2_alu_op__data_len, pipe2_alu_op__is_signed, pipe2_alu_op__is_32bit, pipe2_alu_op__output_carry, pipe2_alu_op__input_carry, pipe2_alu_op__write_cr0, pipe2_alu_op__invert_out, pipe2_alu_op__zero_a, pipe2_alu_op__invert_in, pipe2_alu_op__oe__ok, pipe2_alu_op__oe__oe, pipe2_alu_op__rc__ok, pipe2_alu_op__rc__rc, pipe2_alu_op__imm_data__ok, pipe2_alu_op__imm_data__data, pipe2_alu_op__fn_unit, pipe2_alu_op__insn_type } = { pipe1_alu_op__insn, pipe1_alu_op__data_len, pipe1_alu_op__is_signed, pipe1_alu_op__is_32bit, pipe1_alu_op__output_carry, pipe1_alu_op__input_carry, pipe1_alu_op__write_cr0, pipe1_alu_op__invert_out, pipe1_alu_op__zero_a, pipe1_alu_op__invert_in, pipe1_alu_op__oe__ok, pipe1_alu_op__oe__oe, pipe1_alu_op__rc__ok, pipe1_alu_op__rc__rc, pipe1_alu_op__imm_data__ok, pipe1_alu_op__imm_data__data, pipe1_alu_op__fn_unit, pipe1_alu_op__insn_type }; + assign { pipe2_alu_op__SV_Ptype, pipe2_alu_op__sv_saturate, pipe2_alu_op__sv_pred_dz, pipe2_alu_op__sv_pred_sz, pipe2_alu_op__insn, pipe2_alu_op__data_len, pipe2_alu_op__is_signed, pipe2_alu_op__is_32bit, pipe2_alu_op__output_carry, pipe2_alu_op__input_carry, pipe2_alu_op__write_cr0, pipe2_alu_op__invert_out, pipe2_alu_op__zero_a, pipe2_alu_op__invert_in, pipe2_alu_op__oe__ok, pipe2_alu_op__oe__oe, pipe2_alu_op__rc__ok, pipe2_alu_op__rc__rc, pipe2_alu_op__imm_data__ok, pipe2_alu_op__imm_data__data, pipe2_alu_op__fn_unit, pipe2_alu_op__insn_type } = { pipe1_alu_op__SV_Ptype, pipe1_alu_op__sv_saturate, pipe1_alu_op__sv_pred_dz, pipe1_alu_op__sv_pred_sz, pipe1_alu_op__insn, pipe1_alu_op__data_len, pipe1_alu_op__is_signed, pipe1_alu_op__is_32bit, pipe1_alu_op__output_carry, pipe1_alu_op__input_carry, pipe1_alu_op__write_cr0, pipe1_alu_op__invert_out, pipe1_alu_op__zero_a, pipe1_alu_op__invert_in, pipe1_alu_op__oe__ok, pipe1_alu_op__oe__oe, pipe1_alu_op__rc__ok, pipe1_alu_op__rc__rc, pipe1_alu_op__imm_data__ok, pipe1_alu_op__imm_data__data, pipe1_alu_op__fn_unit, pipe1_alu_op__insn_type }; assign pipe2_muxid = pipe1_muxid; assign pipe1_n_ready_i = pipe2_p_ready_o; assign pipe2_p_valid_i = pipe1_n_valid_o; @@ -23258,57 +25565,71 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.branch0.alu_branch0" *) (* generator = "nMigen" *) -module alu_branch0(coresync_rst, fast1_ok, fast2_ok, nia_ok, n_valid_o, n_ready_i, br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_op__imm_data__data, br_op__imm_data__ok, br_op__lk, br_op__is_32bit, fast1, fast2, nia, \fast1$1 , \fast2$2 , cr_a, p_valid_i, p_ready_o, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) +module alu_branch0(coresync_rst, fast1_ok, fast2_ok, nia_ok, n_valid_o, n_ready_i, br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_op__imm_data__data, br_op__imm_data__ok, br_op__lk, br_op__is_32bit, br_op__sv_pred_sz, br_op__sv_pred_dz, br_op__sv_saturate, br_op__SV_Ptype, fast1, fast2, nia, \fast1$1 , \fast2$2 , cr_a, p_valid_i, p_ready_o, coresync_clk); + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] br_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \br_op__SV_Ptype$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] br_op__cia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \br_op__cia$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \br_op__cia$19 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] br_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] br_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \br_op__fn_unit$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \br_op__fn_unit$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] br_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \br_op__imm_data__data$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \br_op__imm_data__data$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input br_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \br_op__imm_data__ok$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \br_op__imm_data__ok$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] br_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \br_op__insn$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \br_op__insn$22 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -23384,7 +25705,9 @@ module alu_branch0(coresync_rst, fast1_ok, fast2_ok, nia_ok, n_valid_o, n_ready_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] br_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -23461,99 +25784,135 @@ module alu_branch0(coresync_rst, fast1_ok, fast2_ok, nia_ok, n_valid_o, n_ready_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \br_op__insn_type$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \br_op__insn_type$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input br_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \br_op__is_32bit$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \br_op__is_32bit$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input br_op__lk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \br_op__lk$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \br_op__lk$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input br_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \br_op__sv_pred_dz$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input br_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \br_op__sv_pred_sz$27 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] br_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \br_op__sv_saturate$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] \fast1$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output fast1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] fast2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] \fast2$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output fast2_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \muxid$14 ; + wire [1:0] \muxid$18 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] nia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output nia_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) input p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] pipe_br_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \pipe_br_op__SV_Ptype$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] pipe_br_op__cia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] \pipe_br_op__cia$4 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] pipe_br_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] pipe_br_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \pipe_br_op__fn_unit$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \pipe_br_op__fn_unit$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] pipe_br_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] \pipe_br_op__imm_data__data$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_br_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe_br_op__imm_data__ok$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] pipe_br_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] \pipe_br_op__insn$7 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -23630,7 +25989,9 @@ module alu_branch0(coresync_rst, fast1_ok, fast2_ok, nia_ok, n_valid_o, n_ready_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] pipe_br_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -23707,29 +26068,51 @@ module alu_branch0(coresync_rst, fast1_ok, fast2_ok, nia_ok, n_valid_o, n_ready_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] \pipe_br_op__insn_type$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_br_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe_br_op__is_32bit$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_br_op__lk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe_br_op__lk$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire pipe_br_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_br_op__sv_pred_dz$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire pipe_br_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_br_op__sv_pred_sz$12 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] pipe_br_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \pipe_br_op__sv_saturate$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [3:0] pipe_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] pipe_fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \pipe_fast1$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \pipe_fast1$16 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe_fast1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] pipe_fast2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \pipe_fast2$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \pipe_fast2$17 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe_fast2_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] pipe_muxid; @@ -23739,9 +26122,9 @@ module alu_branch0(coresync_rst, fast1_ok, fast2_ok, nia_ok, n_valid_o, n_ready_ wire pipe_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire pipe_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] pipe_nia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe_nia_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire pipe_p_ready_o; @@ -23756,6 +26139,8 @@ module alu_branch0(coresync_rst, fast1_ok, fast2_ok, nia_ok, n_valid_o, n_ready_ .p_valid_i(p_valid_i) ); \pipe$19 pipe ( + .br_op__SV_Ptype(pipe_br_op__SV_Ptype), + .\br_op__SV_Ptype$13 (\pipe_br_op__SV_Ptype$15 ), .br_op__cia(pipe_br_op__cia), .\br_op__cia$2 (\pipe_br_op__cia$4 ), .br_op__fn_unit(pipe_br_op__fn_unit), @@ -23772,14 +26157,20 @@ module alu_branch0(coresync_rst, fast1_ok, fast2_ok, nia_ok, n_valid_o, n_ready_ .\br_op__is_32bit$9 (\pipe_br_op__is_32bit$11 ), .br_op__lk(pipe_br_op__lk), .\br_op__lk$8 (\pipe_br_op__lk$10 ), + .br_op__sv_pred_dz(pipe_br_op__sv_pred_dz), + .\br_op__sv_pred_dz$11 (\pipe_br_op__sv_pred_dz$13 ), + .br_op__sv_pred_sz(pipe_br_op__sv_pred_sz), + .\br_op__sv_pred_sz$10 (\pipe_br_op__sv_pred_sz$12 ), + .br_op__sv_saturate(pipe_br_op__sv_saturate), + .\br_op__sv_saturate$12 (\pipe_br_op__sv_saturate$14 ), .coresync_clk(coresync_clk), .coresync_rst(coresync_rst), .cr_a(pipe_cr_a), .fast1(pipe_fast1), - .\fast1$10 (\pipe_fast1$12 ), + .\fast1$14 (\pipe_fast1$16 ), .fast1_ok(pipe_fast1_ok), .fast2(pipe_fast2), - .\fast2$11 (\pipe_fast2$13 ), + .\fast2$15 (\pipe_fast2$17 ), .fast2_ok(pipe_fast2_ok), .muxid(pipe_muxid), .\muxid$1 (\pipe_muxid$3 ), @@ -23792,16 +26183,16 @@ module alu_branch0(coresync_rst, fast1_ok, fast2_ok, nia_ok, n_valid_o, n_ready_ ); assign muxid = 2'h0; assign { nia_ok, nia } = { pipe_nia_ok, pipe_nia }; - assign { fast2_ok, fast2 } = { pipe_fast2_ok, \pipe_fast2$13 }; - assign { fast1_ok, fast1 } = { pipe_fast1_ok, \pipe_fast1$12 }; - assign { \br_op__is_32bit$22 , \br_op__lk$21 , \br_op__imm_data__ok$20 , \br_op__imm_data__data$19 , \br_op__insn$18 , \br_op__fn_unit$17 , \br_op__insn_type$16 , \br_op__cia$15 } = { \pipe_br_op__is_32bit$11 , \pipe_br_op__lk$10 , \pipe_br_op__imm_data__ok$9 , \pipe_br_op__imm_data__data$8 , \pipe_br_op__insn$7 , \pipe_br_op__fn_unit$6 , \pipe_br_op__insn_type$5 , \pipe_br_op__cia$4 }; - assign \muxid$14 = \pipe_muxid$3 ; + assign { fast2_ok, fast2 } = { pipe_fast2_ok, \pipe_fast2$17 }; + assign { fast1_ok, fast1 } = { pipe_fast1_ok, \pipe_fast1$16 }; + assign { \br_op__SV_Ptype$30 , \br_op__sv_saturate$29 , \br_op__sv_pred_dz$28 , \br_op__sv_pred_sz$27 , \br_op__is_32bit$26 , \br_op__lk$25 , \br_op__imm_data__ok$24 , \br_op__imm_data__data$23 , \br_op__insn$22 , \br_op__fn_unit$21 , \br_op__insn_type$20 , \br_op__cia$19 } = { \pipe_br_op__SV_Ptype$15 , \pipe_br_op__sv_saturate$14 , \pipe_br_op__sv_pred_dz$13 , \pipe_br_op__sv_pred_sz$12 , \pipe_br_op__is_32bit$11 , \pipe_br_op__lk$10 , \pipe_br_op__imm_data__ok$9 , \pipe_br_op__imm_data__data$8 , \pipe_br_op__insn$7 , \pipe_br_op__fn_unit$6 , \pipe_br_op__insn_type$5 , \pipe_br_op__cia$4 }; + assign \muxid$18 = \pipe_muxid$3 ; assign pipe_n_ready_i = n_ready_i; assign n_valid_o = pipe_n_valid_o; assign pipe_cr_a = cr_a; assign pipe_fast2 = \fast2$2 ; assign pipe_fast1 = \fast1$1 ; - assign { pipe_br_op__is_32bit, pipe_br_op__lk, pipe_br_op__imm_data__ok, pipe_br_op__imm_data__data, pipe_br_op__insn, pipe_br_op__fn_unit, pipe_br_op__insn_type, pipe_br_op__cia } = { br_op__is_32bit, br_op__lk, br_op__imm_data__ok, br_op__imm_data__data, br_op__insn, br_op__fn_unit, br_op__insn_type, br_op__cia }; + assign { pipe_br_op__SV_Ptype, pipe_br_op__sv_saturate, pipe_br_op__sv_pred_dz, pipe_br_op__sv_pred_sz, pipe_br_op__is_32bit, pipe_br_op__lk, pipe_br_op__imm_data__ok, pipe_br_op__imm_data__data, pipe_br_op__insn, pipe_br_op__fn_unit, pipe_br_op__insn_type, pipe_br_op__cia } = { br_op__SV_Ptype, br_op__sv_saturate, br_op__sv_pred_dz, br_op__sv_pred_sz, br_op__is_32bit, br_op__lk, br_op__imm_data__ok, br_op__imm_data__data, br_op__insn, br_op__fn_unit, br_op__insn_type, br_op__cia }; assign pipe_muxid = 2'h0; assign p_ready_o = pipe_p_ready_o; assign pipe_p_valid_i = p_valid_i; @@ -23809,59 +26200,73 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.cr0.alu_cr0" *) (* generator = "nMigen" *) -module alu_cr0(coresync_rst, o_ok, full_cr_ok, cr_a_ok, n_valid_o, n_ready_i, cr_op__insn_type, cr_op__fn_unit, cr_op__insn, o, full_cr, cr_a, ra, rb, \full_cr$1 , \cr_a$2 , cr_b, cr_c, p_valid_i, p_ready_o, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) +module alu_cr0(coresync_rst, o_ok, full_cr_ok, cr_a_ok, n_valid_o, n_ready_i, cr_op__insn_type, cr_op__fn_unit, cr_op__insn, cr_op__sv_pred_sz, cr_op__sv_pred_dz, cr_op__sv_saturate, cr_op__SV_Ptype, o, full_cr, cr_a, ra, rb, \full_cr$1 , \cr_a$2 , cr_b, cr_c, p_valid_i, p_ready_o, coresync_clk); + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [3:0] \cr_a$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [3:0] cr_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [3:0] cr_c; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] cr_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \cr_op__SV_Ptype$20 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] cr_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] cr_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \cr_op__fn_unit$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \cr_op__fn_unit$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] cr_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \cr_op__insn$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \cr_op__insn$16 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -23937,7 +26342,9 @@ module alu_cr0(coresync_rst, o_ok, full_cr_ok, cr_a_ok, n_valid_o, n_ready_i, cr (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] cr_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -24014,77 +26421,113 @@ module alu_cr0(coresync_rst, o_ok, full_cr_ok, cr_a_ok, n_valid_o, n_ready_i, cr (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \cr_op__insn_type$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \cr_op__insn_type$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input cr_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \cr_op__sv_pred_dz$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input cr_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \cr_op__sv_pred_sz$17 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] cr_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \cr_op__sv_saturate$19 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [31:0] full_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [31:0] \full_cr$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output full_cr_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \muxid$9 ; + wire [1:0] \muxid$13 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) input p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [3:0] pipe_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [3:0] \pipe_cr_a$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [3:0] \pipe_cr_a$12 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe_cr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [3:0] pipe_cr_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [3:0] pipe_cr_c; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] pipe_cr_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \pipe_cr_op__SV_Ptype$10 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] pipe_cr_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] pipe_cr_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \pipe_cr_op__fn_unit$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \pipe_cr_op__fn_unit$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] pipe_cr_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] \pipe_cr_op__insn$6 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -24161,7 +26604,9 @@ module alu_cr0(coresync_rst, o_ok, full_cr_ok, cr_a_ok, n_valid_o, n_ready_i, cr (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] pipe_cr_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -24238,13 +26683,35 @@ module alu_cr0(coresync_rst, o_ok, full_cr_ok, cr_a_ok, n_valid_o, n_ready_i, cr (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] \pipe_cr_op__insn_type$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire pipe_cr_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_cr_op__sv_pred_dz$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire pipe_cr_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_cr_op__sv_pred_sz$7 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] pipe_cr_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \pipe_cr_op__sv_saturate$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [31:0] pipe_full_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [31:0] \pipe_full_cr$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [31:0] \pipe_full_cr$11 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe_full_cr_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] pipe_muxid; @@ -24254,21 +26721,21 @@ module alu_cr0(coresync_rst, o_ok, full_cr_ok, cr_a_ok, n_valid_o, n_ready_i, cr wire pipe_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire pipe_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] pipe_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe_o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire pipe_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) wire pipe_p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] pipe_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] pipe_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] rb; \n$6 n ( .n_ready_i(n_ready_i), @@ -24282,18 +26749,26 @@ module alu_cr0(coresync_rst, o_ok, full_cr_ok, cr_a_ok, n_valid_o, n_ready_i, cr .coresync_clk(coresync_clk), .coresync_rst(coresync_rst), .cr_a(pipe_cr_a), - .\cr_a$6 (\pipe_cr_a$8 ), + .\cr_a$10 (\pipe_cr_a$12 ), .cr_a_ok(pipe_cr_a_ok), .cr_b(pipe_cr_b), .cr_c(pipe_cr_c), + .cr_op__SV_Ptype(pipe_cr_op__SV_Ptype), + .\cr_op__SV_Ptype$8 (\pipe_cr_op__SV_Ptype$10 ), .cr_op__fn_unit(pipe_cr_op__fn_unit), .\cr_op__fn_unit$3 (\pipe_cr_op__fn_unit$5 ), .cr_op__insn(pipe_cr_op__insn), .\cr_op__insn$4 (\pipe_cr_op__insn$6 ), .cr_op__insn_type(pipe_cr_op__insn_type), .\cr_op__insn_type$2 (\pipe_cr_op__insn_type$4 ), + .cr_op__sv_pred_dz(pipe_cr_op__sv_pred_dz), + .\cr_op__sv_pred_dz$6 (\pipe_cr_op__sv_pred_dz$8 ), + .cr_op__sv_pred_sz(pipe_cr_op__sv_pred_sz), + .\cr_op__sv_pred_sz$5 (\pipe_cr_op__sv_pred_sz$7 ), + .cr_op__sv_saturate(pipe_cr_op__sv_saturate), + .\cr_op__sv_saturate$7 (\pipe_cr_op__sv_saturate$9 ), .full_cr(pipe_full_cr), - .\full_cr$5 (\pipe_full_cr$7 ), + .\full_cr$9 (\pipe_full_cr$11 ), .full_cr_ok(pipe_full_cr_ok), .muxid(pipe_muxid), .\muxid$1 (\pipe_muxid$3 ), @@ -24307,11 +26782,11 @@ module alu_cr0(coresync_rst, o_ok, full_cr_ok, cr_a_ok, n_valid_o, n_ready_i, cr .rb(pipe_rb) ); assign muxid = 2'h0; - assign { cr_a_ok, cr_a } = { pipe_cr_a_ok, \pipe_cr_a$8 }; - assign { full_cr_ok, full_cr } = { pipe_full_cr_ok, \pipe_full_cr$7 }; + assign { cr_a_ok, cr_a } = { pipe_cr_a_ok, \pipe_cr_a$12 }; + assign { full_cr_ok, full_cr } = { pipe_full_cr_ok, \pipe_full_cr$11 }; assign { o_ok, o } = { pipe_o_ok, pipe_o }; - assign { \cr_op__insn$12 , \cr_op__fn_unit$11 , \cr_op__insn_type$10 } = { \pipe_cr_op__insn$6 , \pipe_cr_op__fn_unit$5 , \pipe_cr_op__insn_type$4 }; - assign \muxid$9 = \pipe_muxid$3 ; + assign { \cr_op__SV_Ptype$20 , \cr_op__sv_saturate$19 , \cr_op__sv_pred_dz$18 , \cr_op__sv_pred_sz$17 , \cr_op__insn$16 , \cr_op__fn_unit$15 , \cr_op__insn_type$14 } = { \pipe_cr_op__SV_Ptype$10 , \pipe_cr_op__sv_saturate$9 , \pipe_cr_op__sv_pred_dz$8 , \pipe_cr_op__sv_pred_sz$7 , \pipe_cr_op__insn$6 , \pipe_cr_op__fn_unit$5 , \pipe_cr_op__insn_type$4 }; + assign \muxid$13 = \pipe_muxid$3 ; assign pipe_n_ready_i = n_ready_i; assign n_valid_o = pipe_n_valid_o; assign pipe_cr_c = cr_c; @@ -24320,7 +26795,7 @@ module alu_cr0(coresync_rst, o_ok, full_cr_ok, cr_a_ok, n_valid_o, n_ready_i, cr assign pipe_full_cr = \full_cr$1 ; assign pipe_rb = rb; assign pipe_ra = ra; - assign { pipe_cr_op__insn, pipe_cr_op__fn_unit, pipe_cr_op__insn_type } = { cr_op__insn, cr_op__fn_unit, cr_op__insn_type }; + assign { pipe_cr_op__SV_Ptype, pipe_cr_op__sv_saturate, pipe_cr_op__sv_pred_dz, pipe_cr_op__sv_pred_sz, pipe_cr_op__insn, pipe_cr_op__fn_unit, pipe_cr_op__insn_type } = { cr_op__SV_Ptype, cr_op__sv_saturate, cr_op__sv_pred_dz, cr_op__sv_pred_sz, cr_op__insn, cr_op__fn_unit, cr_op__insn_type }; assign pipe_muxid = 2'h0; assign p_ready_o = pipe_p_ready_o; assign pipe_p_valid_i = p_valid_i; @@ -24328,77 +26803,91 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0" *) (* generator = "nMigen" *) -module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ready_i, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, o, cr_a, xer_ov, xer_so, ra, rb, \xer_so$1 , p_valid_i, p_ready_o, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) +module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ready_i, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__SV_Ptype, o, cr_a, xer_ov, xer_so, ra, rb, \xer_so$1 , p_valid_i, p_ready_o, coresync_clk); + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] logical_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \logical_op__SV_Ptype$105 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [3:0] logical_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [3:0] \logical_op__data_len$88 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [3:0] \logical_op__data_len$100 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] logical_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] logical_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \logical_op__fn_unit$73 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \logical_op__fn_unit$85 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] logical_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \logical_op__imm_data__data$74 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \logical_op__imm_data__data$86 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__imm_data__ok$75 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__imm_data__ok$87 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] logical_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [1:0] \logical_op__input_carry$82 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \logical_op__input_carry$94 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] logical_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \logical_op__insn$89 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \logical_op__insn$101 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -24474,7 +26963,9 @@ module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] logical_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -24551,71 +27042,93 @@ module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \logical_op__insn_type$72 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \logical_op__insn_type$84 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__invert_in$80 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__invert_in$92 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__invert_out$83 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__invert_out$95 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__is_32bit$86 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__is_32bit$98 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__is_signed$87 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__is_signed$99 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__oe__oe$78 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__oe__oe$90 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__oe__ok$79 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__oe__ok$91 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__output_carry$85 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__output_carry$97 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__rc__ok$77 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__rc__ok$89 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__rc__rc$76 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__rc__rc$88 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input logical_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__sv_pred_dz$103 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input logical_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__sv_pred_sz$102 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] logical_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \logical_op__sv_saturate$104 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__write_cr0$84 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__write_cr0$96 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__zero_a$81 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__zero_a$93 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \muxid$71 ; + wire [1:0] \muxid$83 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) input p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [3:0] pipe_end_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe_end_cr_a_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) wire pipe_end_div_by_zero; @@ -24627,68 +27140,82 @@ module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ wire pipe_end_dividend_neg; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *) wire pipe_end_divisor_neg; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] pipe_end_logical_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \pipe_end_logical_op__SV_Ptype$81 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [3:0] pipe_end_logical_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [3:0] \pipe_end_logical_op__data_len$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [3:0] \pipe_end_logical_op__data_len$76 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] pipe_end_logical_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] pipe_end_logical_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \pipe_end_logical_op__fn_unit$53 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \pipe_end_logical_op__fn_unit$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] pipe_end_logical_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \pipe_end_logical_op__imm_data__data$54 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \pipe_end_logical_op__imm_data__data$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_end_logical_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe_end_logical_op__imm_data__ok$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_end_logical_op__imm_data__ok$63 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [1:0] pipe_end_logical_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [1:0] \pipe_end_logical_op__input_carry$62 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \pipe_end_logical_op__input_carry$70 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] pipe_end_logical_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \pipe_end_logical_op__insn$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \pipe_end_logical_op__insn$77 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -24764,7 +27291,9 @@ module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] pipe_end_logical_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -24841,63 +27370,85 @@ module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \pipe_end_logical_op__insn_type$52 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \pipe_end_logical_op__insn_type$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_end_logical_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe_end_logical_op__invert_in$60 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_end_logical_op__invert_in$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_end_logical_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe_end_logical_op__invert_out$63 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_end_logical_op__invert_out$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_end_logical_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe_end_logical_op__is_32bit$66 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_end_logical_op__is_32bit$74 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_end_logical_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe_end_logical_op__is_signed$67 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_end_logical_op__is_signed$75 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_end_logical_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe_end_logical_op__oe__oe$58 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_end_logical_op__oe__oe$66 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_end_logical_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe_end_logical_op__oe__ok$59 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_end_logical_op__oe__ok$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_end_logical_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe_end_logical_op__output_carry$65 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_end_logical_op__output_carry$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_end_logical_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe_end_logical_op__rc__ok$57 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_end_logical_op__rc__ok$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_end_logical_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe_end_logical_op__rc__rc$56 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_end_logical_op__rc__rc$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire pipe_end_logical_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_end_logical_op__sv_pred_dz$79 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire pipe_end_logical_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_end_logical_op__sv_pred_sz$78 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] pipe_end_logical_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \pipe_end_logical_op__sv_saturate$80 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_end_logical_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe_end_logical_op__write_cr0$64 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_end_logical_op__write_cr0$72 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_end_logical_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe_end_logical_op__zero_a$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_end_logical_op__zero_a$69 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] pipe_end_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \pipe_end_muxid$51 ; + wire [1:0] \pipe_end_muxid$59 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) wire pipe_end_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire pipe_end_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] pipe_end_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe_end_o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire pipe_end_p_ready_o; @@ -24905,108 +27456,122 @@ module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ wire pipe_end_p_valid_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" *) wire [63:0] pipe_end_quotient_root; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] pipe_end_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] pipe_end_rb; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" *) wire [191:0] pipe_end_remainder; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [1:0] pipe_end_xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe_end_xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire pipe_end_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \pipe_end_xer_so$70 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \pipe_end_xer_so$82 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe_end_xer_so_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) wire pipe_middle_0_div_by_zero; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) - wire \pipe_middle_0_div_by_zero$50 ; + wire \pipe_middle_0_div_by_zero$58 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *) wire pipe_middle_0_dive_abs_ov32; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *) - wire \pipe_middle_0_dive_abs_ov32$48 ; + wire \pipe_middle_0_dive_abs_ov32$56 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *) wire pipe_middle_0_dive_abs_ov64; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *) - wire \pipe_middle_0_dive_abs_ov64$49 ; + wire \pipe_middle_0_dive_abs_ov64$57 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *) wire [127:0] pipe_middle_0_dividend; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *) wire pipe_middle_0_dividend_neg; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *) - wire \pipe_middle_0_dividend_neg$47 ; + wire \pipe_middle_0_dividend_neg$55 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *) wire pipe_middle_0_divisor_neg; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *) - wire \pipe_middle_0_divisor_neg$46 ; + wire \pipe_middle_0_divisor_neg$54 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *) wire [63:0] pipe_middle_0_divisor_radicand; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] pipe_middle_0_logical_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \pipe_middle_0_logical_op__SV_Ptype$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [3:0] pipe_middle_0_logical_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [3:0] \pipe_middle_0_logical_op__data_len$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [3:0] \pipe_middle_0_logical_op__data_len$45 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] pipe_middle_0_logical_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] pipe_middle_0_logical_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \pipe_middle_0_logical_op__fn_unit$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \pipe_middle_0_logical_op__fn_unit$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] pipe_middle_0_logical_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \pipe_middle_0_logical_op__imm_data__data$27 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \pipe_middle_0_logical_op__imm_data__data$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_middle_0_logical_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe_middle_0_logical_op__imm_data__ok$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_middle_0_logical_op__imm_data__ok$32 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [1:0] pipe_middle_0_logical_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [1:0] \pipe_middle_0_logical_op__input_carry$35 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \pipe_middle_0_logical_op__input_carry$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] pipe_middle_0_logical_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \pipe_middle_0_logical_op__insn$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \pipe_middle_0_logical_op__insn$46 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -25082,7 +27647,9 @@ module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] pipe_middle_0_logical_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -25159,56 +27726,78 @@ module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \pipe_middle_0_logical_op__insn_type$25 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \pipe_middle_0_logical_op__insn_type$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_middle_0_logical_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe_middle_0_logical_op__invert_in$33 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_middle_0_logical_op__invert_in$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_middle_0_logical_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe_middle_0_logical_op__invert_out$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_middle_0_logical_op__invert_out$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_middle_0_logical_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe_middle_0_logical_op__is_32bit$39 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_middle_0_logical_op__is_32bit$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_middle_0_logical_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe_middle_0_logical_op__is_signed$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_middle_0_logical_op__is_signed$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_middle_0_logical_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe_middle_0_logical_op__oe__oe$31 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_middle_0_logical_op__oe__oe$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_middle_0_logical_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe_middle_0_logical_op__oe__ok$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_middle_0_logical_op__oe__ok$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_middle_0_logical_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe_middle_0_logical_op__output_carry$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_middle_0_logical_op__output_carry$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_middle_0_logical_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe_middle_0_logical_op__rc__ok$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_middle_0_logical_op__rc__ok$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_middle_0_logical_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe_middle_0_logical_op__rc__rc$29 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_middle_0_logical_op__rc__rc$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire pipe_middle_0_logical_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_middle_0_logical_op__sv_pred_dz$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire pipe_middle_0_logical_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_middle_0_logical_op__sv_pred_sz$47 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] pipe_middle_0_logical_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \pipe_middle_0_logical_op__sv_saturate$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_middle_0_logical_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe_middle_0_logical_op__write_cr0$37 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_middle_0_logical_op__write_cr0$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_middle_0_logical_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe_middle_0_logical_op__zero_a$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_middle_0_logical_op__zero_a$38 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] pipe_middle_0_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \pipe_middle_0_muxid$24 ; + wire [1:0] \pipe_middle_0_muxid$28 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) wire pipe_middle_0_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) @@ -25221,20 +27810,20 @@ module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ wire pipe_middle_0_p_valid_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" *) wire [63:0] pipe_middle_0_quotient_root; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] pipe_middle_0_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \pipe_middle_0_ra$43 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \pipe_middle_0_ra$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] pipe_middle_0_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \pipe_middle_0_rb$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \pipe_middle_0_rb$52 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" *) wire [191:0] pipe_middle_0_remainder; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire pipe_middle_0_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire \pipe_middle_0_xer_so$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire \pipe_middle_0_xer_so$53 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) wire pipe_start_div_by_zero; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *) @@ -25249,67 +27838,81 @@ module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ wire pipe_start_divisor_neg; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *) wire [63:0] pipe_start_divisor_radicand; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] pipe_start_logical_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \pipe_start_logical_op__SV_Ptype$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [3:0] pipe_start_logical_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [3:0] \pipe_start_logical_op__data_len$19 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] pipe_start_logical_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] pipe_start_logical_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \pipe_start_logical_op__fn_unit$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \pipe_start_logical_op__fn_unit$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] pipe_start_logical_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] \pipe_start_logical_op__imm_data__data$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_start_logical_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe_start_logical_op__imm_data__ok$6 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [1:0] pipe_start_logical_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [1:0] \pipe_start_logical_op__input_carry$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] pipe_start_logical_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] \pipe_start_logical_op__insn$20 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -25386,7 +27989,9 @@ module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] pipe_start_logical_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -25463,51 +28068,73 @@ module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] \pipe_start_logical_op__insn_type$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_start_logical_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe_start_logical_op__invert_in$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_start_logical_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe_start_logical_op__invert_out$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_start_logical_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe_start_logical_op__is_32bit$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_start_logical_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe_start_logical_op__is_signed$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_start_logical_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe_start_logical_op__oe__oe$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_start_logical_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe_start_logical_op__oe__ok$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_start_logical_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe_start_logical_op__output_carry$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_start_logical_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe_start_logical_op__rc__ok$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_start_logical_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe_start_logical_op__rc__rc$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire pipe_start_logical_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_start_logical_op__sv_pred_dz$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire pipe_start_logical_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_start_logical_op__sv_pred_sz$21 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] pipe_start_logical_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \pipe_start_logical_op__sv_saturate$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_start_logical_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe_start_logical_op__write_cr0$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_start_logical_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe_start_logical_op__zero_a$12 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] pipe_start_muxid; @@ -25523,31 +28150,31 @@ module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ wire pipe_start_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) wire pipe_start_p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] pipe_start_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \pipe_start_ra$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \pipe_start_ra$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] pipe_start_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \pipe_start_rb$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \pipe_start_rb$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire pipe_start_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire \pipe_start_xer_so$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire \pipe_start_xer_so$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [1:0] xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input \xer_so$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_so_ok; \n$75 n ( .n_ready_i(n_ready_i), @@ -25567,44 +28194,52 @@ module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ .dive_abs_ov64(pipe_end_dive_abs_ov64), .dividend_neg(pipe_end_dividend_neg), .divisor_neg(pipe_end_divisor_neg), + .logical_op__SV_Ptype(pipe_end_logical_op__SV_Ptype), + .\logical_op__SV_Ptype$23 (\pipe_end_logical_op__SV_Ptype$81 ), .logical_op__data_len(pipe_end_logical_op__data_len), - .\logical_op__data_len$18 (\pipe_end_logical_op__data_len$68 ), + .\logical_op__data_len$18 (\pipe_end_logical_op__data_len$76 ), .logical_op__fn_unit(pipe_end_logical_op__fn_unit), - .\logical_op__fn_unit$3 (\pipe_end_logical_op__fn_unit$53 ), + .\logical_op__fn_unit$3 (\pipe_end_logical_op__fn_unit$61 ), .logical_op__imm_data__data(pipe_end_logical_op__imm_data__data), - .\logical_op__imm_data__data$4 (\pipe_end_logical_op__imm_data__data$54 ), + .\logical_op__imm_data__data$4 (\pipe_end_logical_op__imm_data__data$62 ), .logical_op__imm_data__ok(pipe_end_logical_op__imm_data__ok), - .\logical_op__imm_data__ok$5 (\pipe_end_logical_op__imm_data__ok$55 ), + .\logical_op__imm_data__ok$5 (\pipe_end_logical_op__imm_data__ok$63 ), .logical_op__input_carry(pipe_end_logical_op__input_carry), - .\logical_op__input_carry$12 (\pipe_end_logical_op__input_carry$62 ), + .\logical_op__input_carry$12 (\pipe_end_logical_op__input_carry$70 ), .logical_op__insn(pipe_end_logical_op__insn), - .\logical_op__insn$19 (\pipe_end_logical_op__insn$69 ), + .\logical_op__insn$19 (\pipe_end_logical_op__insn$77 ), .logical_op__insn_type(pipe_end_logical_op__insn_type), - .\logical_op__insn_type$2 (\pipe_end_logical_op__insn_type$52 ), + .\logical_op__insn_type$2 (\pipe_end_logical_op__insn_type$60 ), .logical_op__invert_in(pipe_end_logical_op__invert_in), - .\logical_op__invert_in$10 (\pipe_end_logical_op__invert_in$60 ), + .\logical_op__invert_in$10 (\pipe_end_logical_op__invert_in$68 ), .logical_op__invert_out(pipe_end_logical_op__invert_out), - .\logical_op__invert_out$13 (\pipe_end_logical_op__invert_out$63 ), + .\logical_op__invert_out$13 (\pipe_end_logical_op__invert_out$71 ), .logical_op__is_32bit(pipe_end_logical_op__is_32bit), - .\logical_op__is_32bit$16 (\pipe_end_logical_op__is_32bit$66 ), + .\logical_op__is_32bit$16 (\pipe_end_logical_op__is_32bit$74 ), .logical_op__is_signed(pipe_end_logical_op__is_signed), - .\logical_op__is_signed$17 (\pipe_end_logical_op__is_signed$67 ), + .\logical_op__is_signed$17 (\pipe_end_logical_op__is_signed$75 ), .logical_op__oe__oe(pipe_end_logical_op__oe__oe), - .\logical_op__oe__oe$8 (\pipe_end_logical_op__oe__oe$58 ), + .\logical_op__oe__oe$8 (\pipe_end_logical_op__oe__oe$66 ), .logical_op__oe__ok(pipe_end_logical_op__oe__ok), - .\logical_op__oe__ok$9 (\pipe_end_logical_op__oe__ok$59 ), + .\logical_op__oe__ok$9 (\pipe_end_logical_op__oe__ok$67 ), .logical_op__output_carry(pipe_end_logical_op__output_carry), - .\logical_op__output_carry$15 (\pipe_end_logical_op__output_carry$65 ), + .\logical_op__output_carry$15 (\pipe_end_logical_op__output_carry$73 ), .logical_op__rc__ok(pipe_end_logical_op__rc__ok), - .\logical_op__rc__ok$7 (\pipe_end_logical_op__rc__ok$57 ), + .\logical_op__rc__ok$7 (\pipe_end_logical_op__rc__ok$65 ), .logical_op__rc__rc(pipe_end_logical_op__rc__rc), - .\logical_op__rc__rc$6 (\pipe_end_logical_op__rc__rc$56 ), + .\logical_op__rc__rc$6 (\pipe_end_logical_op__rc__rc$64 ), + .logical_op__sv_pred_dz(pipe_end_logical_op__sv_pred_dz), + .\logical_op__sv_pred_dz$21 (\pipe_end_logical_op__sv_pred_dz$79 ), + .logical_op__sv_pred_sz(pipe_end_logical_op__sv_pred_sz), + .\logical_op__sv_pred_sz$20 (\pipe_end_logical_op__sv_pred_sz$78 ), + .logical_op__sv_saturate(pipe_end_logical_op__sv_saturate), + .\logical_op__sv_saturate$22 (\pipe_end_logical_op__sv_saturate$80 ), .logical_op__write_cr0(pipe_end_logical_op__write_cr0), - .\logical_op__write_cr0$14 (\pipe_end_logical_op__write_cr0$64 ), + .\logical_op__write_cr0$14 (\pipe_end_logical_op__write_cr0$72 ), .logical_op__zero_a(pipe_end_logical_op__zero_a), - .\logical_op__zero_a$11 (\pipe_end_logical_op__zero_a$61 ), + .\logical_op__zero_a$11 (\pipe_end_logical_op__zero_a$69 ), .muxid(pipe_end_muxid), - .\muxid$1 (\pipe_end_muxid$51 ), + .\muxid$1 (\pipe_end_muxid$59 ), .n_ready_i(pipe_end_n_ready_i), .n_valid_o(pipe_end_n_valid_o), .o(pipe_end_o), @@ -25618,62 +28253,70 @@ module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ .xer_ov(pipe_end_xer_ov), .xer_ov_ok(pipe_end_xer_ov_ok), .xer_so(pipe_end_xer_so), - .\xer_so$20 (\pipe_end_xer_so$70 ), + .\xer_so$24 (\pipe_end_xer_so$82 ), .xer_so_ok(pipe_end_xer_so_ok) ); pipe_middle_0 pipe_middle_0 ( .coresync_clk(coresync_clk), .coresync_rst(coresync_rst), .div_by_zero(pipe_middle_0_div_by_zero), - .\div_by_zero$27 (\pipe_middle_0_div_by_zero$50 ), + .\div_by_zero$31 (\pipe_middle_0_div_by_zero$58 ), .dive_abs_ov32(pipe_middle_0_dive_abs_ov32), - .\dive_abs_ov32$25 (\pipe_middle_0_dive_abs_ov32$48 ), + .\dive_abs_ov32$29 (\pipe_middle_0_dive_abs_ov32$56 ), .dive_abs_ov64(pipe_middle_0_dive_abs_ov64), - .\dive_abs_ov64$26 (\pipe_middle_0_dive_abs_ov64$49 ), + .\dive_abs_ov64$30 (\pipe_middle_0_dive_abs_ov64$57 ), .dividend(pipe_middle_0_dividend), .dividend_neg(pipe_middle_0_dividend_neg), - .\dividend_neg$24 (\pipe_middle_0_dividend_neg$47 ), + .\dividend_neg$28 (\pipe_middle_0_dividend_neg$55 ), .divisor_neg(pipe_middle_0_divisor_neg), - .\divisor_neg$23 (\pipe_middle_0_divisor_neg$46 ), + .\divisor_neg$27 (\pipe_middle_0_divisor_neg$54 ), .divisor_radicand(pipe_middle_0_divisor_radicand), + .logical_op__SV_Ptype(pipe_middle_0_logical_op__SV_Ptype), + .\logical_op__SV_Ptype$23 (\pipe_middle_0_logical_op__SV_Ptype$50 ), .logical_op__data_len(pipe_middle_0_logical_op__data_len), - .\logical_op__data_len$18 (\pipe_middle_0_logical_op__data_len$41 ), + .\logical_op__data_len$18 (\pipe_middle_0_logical_op__data_len$45 ), .logical_op__fn_unit(pipe_middle_0_logical_op__fn_unit), - .\logical_op__fn_unit$3 (\pipe_middle_0_logical_op__fn_unit$26 ), + .\logical_op__fn_unit$3 (\pipe_middle_0_logical_op__fn_unit$30 ), .logical_op__imm_data__data(pipe_middle_0_logical_op__imm_data__data), - .\logical_op__imm_data__data$4 (\pipe_middle_0_logical_op__imm_data__data$27 ), + .\logical_op__imm_data__data$4 (\pipe_middle_0_logical_op__imm_data__data$31 ), .logical_op__imm_data__ok(pipe_middle_0_logical_op__imm_data__ok), - .\logical_op__imm_data__ok$5 (\pipe_middle_0_logical_op__imm_data__ok$28 ), + .\logical_op__imm_data__ok$5 (\pipe_middle_0_logical_op__imm_data__ok$32 ), .logical_op__input_carry(pipe_middle_0_logical_op__input_carry), - .\logical_op__input_carry$12 (\pipe_middle_0_logical_op__input_carry$35 ), + .\logical_op__input_carry$12 (\pipe_middle_0_logical_op__input_carry$39 ), .logical_op__insn(pipe_middle_0_logical_op__insn), - .\logical_op__insn$19 (\pipe_middle_0_logical_op__insn$42 ), + .\logical_op__insn$19 (\pipe_middle_0_logical_op__insn$46 ), .logical_op__insn_type(pipe_middle_0_logical_op__insn_type), - .\logical_op__insn_type$2 (\pipe_middle_0_logical_op__insn_type$25 ), + .\logical_op__insn_type$2 (\pipe_middle_0_logical_op__insn_type$29 ), .logical_op__invert_in(pipe_middle_0_logical_op__invert_in), - .\logical_op__invert_in$10 (\pipe_middle_0_logical_op__invert_in$33 ), + .\logical_op__invert_in$10 (\pipe_middle_0_logical_op__invert_in$37 ), .logical_op__invert_out(pipe_middle_0_logical_op__invert_out), - .\logical_op__invert_out$13 (\pipe_middle_0_logical_op__invert_out$36 ), + .\logical_op__invert_out$13 (\pipe_middle_0_logical_op__invert_out$40 ), .logical_op__is_32bit(pipe_middle_0_logical_op__is_32bit), - .\logical_op__is_32bit$16 (\pipe_middle_0_logical_op__is_32bit$39 ), + .\logical_op__is_32bit$16 (\pipe_middle_0_logical_op__is_32bit$43 ), .logical_op__is_signed(pipe_middle_0_logical_op__is_signed), - .\logical_op__is_signed$17 (\pipe_middle_0_logical_op__is_signed$40 ), + .\logical_op__is_signed$17 (\pipe_middle_0_logical_op__is_signed$44 ), .logical_op__oe__oe(pipe_middle_0_logical_op__oe__oe), - .\logical_op__oe__oe$8 (\pipe_middle_0_logical_op__oe__oe$31 ), + .\logical_op__oe__oe$8 (\pipe_middle_0_logical_op__oe__oe$35 ), .logical_op__oe__ok(pipe_middle_0_logical_op__oe__ok), - .\logical_op__oe__ok$9 (\pipe_middle_0_logical_op__oe__ok$32 ), + .\logical_op__oe__ok$9 (\pipe_middle_0_logical_op__oe__ok$36 ), .logical_op__output_carry(pipe_middle_0_logical_op__output_carry), - .\logical_op__output_carry$15 (\pipe_middle_0_logical_op__output_carry$38 ), + .\logical_op__output_carry$15 (\pipe_middle_0_logical_op__output_carry$42 ), .logical_op__rc__ok(pipe_middle_0_logical_op__rc__ok), - .\logical_op__rc__ok$7 (\pipe_middle_0_logical_op__rc__ok$30 ), + .\logical_op__rc__ok$7 (\pipe_middle_0_logical_op__rc__ok$34 ), .logical_op__rc__rc(pipe_middle_0_logical_op__rc__rc), - .\logical_op__rc__rc$6 (\pipe_middle_0_logical_op__rc__rc$29 ), + .\logical_op__rc__rc$6 (\pipe_middle_0_logical_op__rc__rc$33 ), + .logical_op__sv_pred_dz(pipe_middle_0_logical_op__sv_pred_dz), + .\logical_op__sv_pred_dz$21 (\pipe_middle_0_logical_op__sv_pred_dz$48 ), + .logical_op__sv_pred_sz(pipe_middle_0_logical_op__sv_pred_sz), + .\logical_op__sv_pred_sz$20 (\pipe_middle_0_logical_op__sv_pred_sz$47 ), + .logical_op__sv_saturate(pipe_middle_0_logical_op__sv_saturate), + .\logical_op__sv_saturate$22 (\pipe_middle_0_logical_op__sv_saturate$49 ), .logical_op__write_cr0(pipe_middle_0_logical_op__write_cr0), - .\logical_op__write_cr0$14 (\pipe_middle_0_logical_op__write_cr0$37 ), + .\logical_op__write_cr0$14 (\pipe_middle_0_logical_op__write_cr0$41 ), .logical_op__zero_a(pipe_middle_0_logical_op__zero_a), - .\logical_op__zero_a$11 (\pipe_middle_0_logical_op__zero_a$34 ), + .\logical_op__zero_a$11 (\pipe_middle_0_logical_op__zero_a$38 ), .muxid(pipe_middle_0_muxid), - .\muxid$1 (\pipe_middle_0_muxid$24 ), + .\muxid$1 (\pipe_middle_0_muxid$28 ), .n_ready_i(pipe_middle_0_n_ready_i), .n_valid_o(pipe_middle_0_n_valid_o), .operation(pipe_middle_0_operation), @@ -25681,12 +28324,12 @@ module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ .p_valid_i(pipe_middle_0_p_valid_i), .quotient_root(pipe_middle_0_quotient_root), .ra(pipe_middle_0_ra), - .\ra$20 (\pipe_middle_0_ra$43 ), + .\ra$24 (\pipe_middle_0_ra$51 ), .rb(pipe_middle_0_rb), - .\rb$21 (\pipe_middle_0_rb$44 ), + .\rb$25 (\pipe_middle_0_rb$52 ), .remainder(pipe_middle_0_remainder), .xer_so(pipe_middle_0_xer_so), - .\xer_so$22 (\pipe_middle_0_xer_so$45 ) + .\xer_so$26 (\pipe_middle_0_xer_so$53 ) ); pipe_start pipe_start ( .coresync_clk(coresync_clk), @@ -25698,6 +28341,8 @@ module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ .dividend_neg(pipe_start_dividend_neg), .divisor_neg(pipe_start_divisor_neg), .divisor_radicand(pipe_start_divisor_radicand), + .logical_op__SV_Ptype(pipe_start_logical_op__SV_Ptype), + .\logical_op__SV_Ptype$23 (\pipe_start_logical_op__SV_Ptype$24 ), .logical_op__data_len(pipe_start_logical_op__data_len), .\logical_op__data_len$18 (\pipe_start_logical_op__data_len$19 ), .logical_op__fn_unit(pipe_start_logical_op__fn_unit), @@ -25730,6 +28375,12 @@ module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ .\logical_op__rc__ok$7 (\pipe_start_logical_op__rc__ok$8 ), .logical_op__rc__rc(pipe_start_logical_op__rc__rc), .\logical_op__rc__rc$6 (\pipe_start_logical_op__rc__rc$7 ), + .logical_op__sv_pred_dz(pipe_start_logical_op__sv_pred_dz), + .\logical_op__sv_pred_dz$21 (\pipe_start_logical_op__sv_pred_dz$22 ), + .logical_op__sv_pred_sz(pipe_start_logical_op__sv_pred_sz), + .\logical_op__sv_pred_sz$20 (\pipe_start_logical_op__sv_pred_sz$21 ), + .logical_op__sv_saturate(pipe_start_logical_op__sv_saturate), + .\logical_op__sv_saturate$22 (\pipe_start_logical_op__sv_saturate$23 ), .logical_op__write_cr0(pipe_start_logical_op__write_cr0), .\logical_op__write_cr0$14 (\pipe_start_logical_op__write_cr0$15 ), .logical_op__zero_a(pipe_start_logical_op__zero_a), @@ -25742,40 +28393,40 @@ module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ .p_ready_o(pipe_start_p_ready_o), .p_valid_i(pipe_start_p_valid_i), .ra(pipe_start_ra), - .\ra$20 (\pipe_start_ra$21 ), + .\ra$24 (\pipe_start_ra$25 ), .rb(pipe_start_rb), - .\rb$21 (\pipe_start_rb$22 ), + .\rb$25 (\pipe_start_rb$26 ), .xer_so(pipe_start_xer_so), - .\xer_so$22 (\pipe_start_xer_so$23 ) + .\xer_so$26 (\pipe_start_xer_so$27 ) ); assign muxid = 2'h0; - assign { xer_so_ok, xer_so } = { pipe_end_xer_so_ok, \pipe_end_xer_so$70 }; + assign { xer_so_ok, xer_so } = { pipe_end_xer_so_ok, \pipe_end_xer_so$82 }; assign { xer_ov_ok, xer_ov } = { pipe_end_xer_ov_ok, pipe_end_xer_ov }; assign { cr_a_ok, cr_a } = { pipe_end_cr_a_ok, pipe_end_cr_a }; assign { o_ok, o } = { pipe_end_o_ok, pipe_end_o }; - assign { \logical_op__insn$89 , \logical_op__data_len$88 , \logical_op__is_signed$87 , \logical_op__is_32bit$86 , \logical_op__output_carry$85 , \logical_op__write_cr0$84 , \logical_op__invert_out$83 , \logical_op__input_carry$82 , \logical_op__zero_a$81 , \logical_op__invert_in$80 , \logical_op__oe__ok$79 , \logical_op__oe__oe$78 , \logical_op__rc__ok$77 , \logical_op__rc__rc$76 , \logical_op__imm_data__ok$75 , \logical_op__imm_data__data$74 , \logical_op__fn_unit$73 , \logical_op__insn_type$72 } = { \pipe_end_logical_op__insn$69 , \pipe_end_logical_op__data_len$68 , \pipe_end_logical_op__is_signed$67 , \pipe_end_logical_op__is_32bit$66 , \pipe_end_logical_op__output_carry$65 , \pipe_end_logical_op__write_cr0$64 , \pipe_end_logical_op__invert_out$63 , \pipe_end_logical_op__input_carry$62 , \pipe_end_logical_op__zero_a$61 , \pipe_end_logical_op__invert_in$60 , \pipe_end_logical_op__oe__ok$59 , \pipe_end_logical_op__oe__oe$58 , \pipe_end_logical_op__rc__ok$57 , \pipe_end_logical_op__rc__rc$56 , \pipe_end_logical_op__imm_data__ok$55 , \pipe_end_logical_op__imm_data__data$54 , \pipe_end_logical_op__fn_unit$53 , \pipe_end_logical_op__insn_type$52 }; - assign \muxid$71 = \pipe_end_muxid$51 ; + assign { \logical_op__SV_Ptype$105 , \logical_op__sv_saturate$104 , \logical_op__sv_pred_dz$103 , \logical_op__sv_pred_sz$102 , \logical_op__insn$101 , \logical_op__data_len$100 , \logical_op__is_signed$99 , \logical_op__is_32bit$98 , \logical_op__output_carry$97 , \logical_op__write_cr0$96 , \logical_op__invert_out$95 , \logical_op__input_carry$94 , \logical_op__zero_a$93 , \logical_op__invert_in$92 , \logical_op__oe__ok$91 , \logical_op__oe__oe$90 , \logical_op__rc__ok$89 , \logical_op__rc__rc$88 , \logical_op__imm_data__ok$87 , \logical_op__imm_data__data$86 , \logical_op__fn_unit$85 , \logical_op__insn_type$84 } = { \pipe_end_logical_op__SV_Ptype$81 , \pipe_end_logical_op__sv_saturate$80 , \pipe_end_logical_op__sv_pred_dz$79 , \pipe_end_logical_op__sv_pred_sz$78 , \pipe_end_logical_op__insn$77 , \pipe_end_logical_op__data_len$76 , \pipe_end_logical_op__is_signed$75 , \pipe_end_logical_op__is_32bit$74 , \pipe_end_logical_op__output_carry$73 , \pipe_end_logical_op__write_cr0$72 , \pipe_end_logical_op__invert_out$71 , \pipe_end_logical_op__input_carry$70 , \pipe_end_logical_op__zero_a$69 , \pipe_end_logical_op__invert_in$68 , \pipe_end_logical_op__oe__ok$67 , \pipe_end_logical_op__oe__oe$66 , \pipe_end_logical_op__rc__ok$65 , \pipe_end_logical_op__rc__rc$64 , \pipe_end_logical_op__imm_data__ok$63 , \pipe_end_logical_op__imm_data__data$62 , \pipe_end_logical_op__fn_unit$61 , \pipe_end_logical_op__insn_type$60 }; + assign \muxid$83 = \pipe_end_muxid$59 ; assign pipe_end_n_ready_i = n_ready_i; assign n_valid_o = pipe_end_n_valid_o; - assign \pipe_start_xer_so$23 = \xer_so$1 ; - assign \pipe_start_rb$22 = rb; - assign \pipe_start_ra$21 = ra; - assign { \pipe_start_logical_op__insn$20 , \pipe_start_logical_op__data_len$19 , \pipe_start_logical_op__is_signed$18 , \pipe_start_logical_op__is_32bit$17 , \pipe_start_logical_op__output_carry$16 , \pipe_start_logical_op__write_cr0$15 , \pipe_start_logical_op__invert_out$14 , \pipe_start_logical_op__input_carry$13 , \pipe_start_logical_op__zero_a$12 , \pipe_start_logical_op__invert_in$11 , \pipe_start_logical_op__oe__ok$10 , \pipe_start_logical_op__oe__oe$9 , \pipe_start_logical_op__rc__ok$8 , \pipe_start_logical_op__rc__rc$7 , \pipe_start_logical_op__imm_data__ok$6 , \pipe_start_logical_op__imm_data__data$5 , \pipe_start_logical_op__fn_unit$4 , \pipe_start_logical_op__insn_type$3 } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; + assign \pipe_start_xer_so$27 = \xer_so$1 ; + assign \pipe_start_rb$26 = rb; + assign \pipe_start_ra$25 = ra; + assign { \pipe_start_logical_op__SV_Ptype$24 , \pipe_start_logical_op__sv_saturate$23 , \pipe_start_logical_op__sv_pred_dz$22 , \pipe_start_logical_op__sv_pred_sz$21 , \pipe_start_logical_op__insn$20 , \pipe_start_logical_op__data_len$19 , \pipe_start_logical_op__is_signed$18 , \pipe_start_logical_op__is_32bit$17 , \pipe_start_logical_op__output_carry$16 , \pipe_start_logical_op__write_cr0$15 , \pipe_start_logical_op__invert_out$14 , \pipe_start_logical_op__input_carry$13 , \pipe_start_logical_op__zero_a$12 , \pipe_start_logical_op__invert_in$11 , \pipe_start_logical_op__oe__ok$10 , \pipe_start_logical_op__oe__oe$9 , \pipe_start_logical_op__rc__ok$8 , \pipe_start_logical_op__rc__rc$7 , \pipe_start_logical_op__imm_data__ok$6 , \pipe_start_logical_op__imm_data__data$5 , \pipe_start_logical_op__fn_unit$4 , \pipe_start_logical_op__insn_type$3 } = { logical_op__SV_Ptype, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; assign \pipe_start_muxid$2 = 2'h0; assign p_ready_o = pipe_start_p_ready_o; assign pipe_start_p_valid_i = p_valid_i; assign pipe_end_remainder = pipe_middle_0_remainder; assign pipe_end_quotient_root = pipe_middle_0_quotient_root; - assign pipe_end_div_by_zero = \pipe_middle_0_div_by_zero$50 ; - assign pipe_end_dive_abs_ov64 = \pipe_middle_0_dive_abs_ov64$49 ; - assign pipe_end_dive_abs_ov32 = \pipe_middle_0_dive_abs_ov32$48 ; - assign pipe_end_dividend_neg = \pipe_middle_0_dividend_neg$47 ; - assign pipe_end_divisor_neg = \pipe_middle_0_divisor_neg$46 ; - assign pipe_end_xer_so = \pipe_middle_0_xer_so$45 ; - assign pipe_end_rb = \pipe_middle_0_rb$44 ; - assign pipe_end_ra = \pipe_middle_0_ra$43 ; - assign { pipe_end_logical_op__insn, pipe_end_logical_op__data_len, pipe_end_logical_op__is_signed, pipe_end_logical_op__is_32bit, pipe_end_logical_op__output_carry, pipe_end_logical_op__write_cr0, pipe_end_logical_op__invert_out, pipe_end_logical_op__input_carry, pipe_end_logical_op__zero_a, pipe_end_logical_op__invert_in, pipe_end_logical_op__oe__ok, pipe_end_logical_op__oe__oe, pipe_end_logical_op__rc__ok, pipe_end_logical_op__rc__rc, pipe_end_logical_op__imm_data__ok, pipe_end_logical_op__imm_data__data, pipe_end_logical_op__fn_unit, pipe_end_logical_op__insn_type } = { \pipe_middle_0_logical_op__insn$42 , \pipe_middle_0_logical_op__data_len$41 , \pipe_middle_0_logical_op__is_signed$40 , \pipe_middle_0_logical_op__is_32bit$39 , \pipe_middle_0_logical_op__output_carry$38 , \pipe_middle_0_logical_op__write_cr0$37 , \pipe_middle_0_logical_op__invert_out$36 , \pipe_middle_0_logical_op__input_carry$35 , \pipe_middle_0_logical_op__zero_a$34 , \pipe_middle_0_logical_op__invert_in$33 , \pipe_middle_0_logical_op__oe__ok$32 , \pipe_middle_0_logical_op__oe__oe$31 , \pipe_middle_0_logical_op__rc__ok$30 , \pipe_middle_0_logical_op__rc__rc$29 , \pipe_middle_0_logical_op__imm_data__ok$28 , \pipe_middle_0_logical_op__imm_data__data$27 , \pipe_middle_0_logical_op__fn_unit$26 , \pipe_middle_0_logical_op__insn_type$25 }; - assign pipe_end_muxid = \pipe_middle_0_muxid$24 ; + assign pipe_end_div_by_zero = \pipe_middle_0_div_by_zero$58 ; + assign pipe_end_dive_abs_ov64 = \pipe_middle_0_dive_abs_ov64$57 ; + assign pipe_end_dive_abs_ov32 = \pipe_middle_0_dive_abs_ov32$56 ; + assign pipe_end_dividend_neg = \pipe_middle_0_dividend_neg$55 ; + assign pipe_end_divisor_neg = \pipe_middle_0_divisor_neg$54 ; + assign pipe_end_xer_so = \pipe_middle_0_xer_so$53 ; + assign pipe_end_rb = \pipe_middle_0_rb$52 ; + assign pipe_end_ra = \pipe_middle_0_ra$51 ; + assign { pipe_end_logical_op__SV_Ptype, pipe_end_logical_op__sv_saturate, pipe_end_logical_op__sv_pred_dz, pipe_end_logical_op__sv_pred_sz, pipe_end_logical_op__insn, pipe_end_logical_op__data_len, pipe_end_logical_op__is_signed, pipe_end_logical_op__is_32bit, pipe_end_logical_op__output_carry, pipe_end_logical_op__write_cr0, pipe_end_logical_op__invert_out, pipe_end_logical_op__input_carry, pipe_end_logical_op__zero_a, pipe_end_logical_op__invert_in, pipe_end_logical_op__oe__ok, pipe_end_logical_op__oe__oe, pipe_end_logical_op__rc__ok, pipe_end_logical_op__rc__rc, pipe_end_logical_op__imm_data__ok, pipe_end_logical_op__imm_data__data, pipe_end_logical_op__fn_unit, pipe_end_logical_op__insn_type } = { \pipe_middle_0_logical_op__SV_Ptype$50 , \pipe_middle_0_logical_op__sv_saturate$49 , \pipe_middle_0_logical_op__sv_pred_dz$48 , \pipe_middle_0_logical_op__sv_pred_sz$47 , \pipe_middle_0_logical_op__insn$46 , \pipe_middle_0_logical_op__data_len$45 , \pipe_middle_0_logical_op__is_signed$44 , \pipe_middle_0_logical_op__is_32bit$43 , \pipe_middle_0_logical_op__output_carry$42 , \pipe_middle_0_logical_op__write_cr0$41 , \pipe_middle_0_logical_op__invert_out$40 , \pipe_middle_0_logical_op__input_carry$39 , \pipe_middle_0_logical_op__zero_a$38 , \pipe_middle_0_logical_op__invert_in$37 , \pipe_middle_0_logical_op__oe__ok$36 , \pipe_middle_0_logical_op__oe__oe$35 , \pipe_middle_0_logical_op__rc__ok$34 , \pipe_middle_0_logical_op__rc__rc$33 , \pipe_middle_0_logical_op__imm_data__ok$32 , \pipe_middle_0_logical_op__imm_data__data$31 , \pipe_middle_0_logical_op__fn_unit$30 , \pipe_middle_0_logical_op__insn_type$29 }; + assign pipe_end_muxid = \pipe_middle_0_muxid$28 ; assign pipe_middle_0_n_ready_i = pipe_end_p_ready_o; assign pipe_end_p_valid_i = pipe_middle_0_n_valid_o; assign pipe_middle_0_operation = pipe_start_operation; @@ -25789,7 +28440,7 @@ module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ assign pipe_middle_0_xer_so = pipe_start_xer_so; assign pipe_middle_0_rb = pipe_start_rb; assign pipe_middle_0_ra = pipe_start_ra; - assign { pipe_middle_0_logical_op__insn, pipe_middle_0_logical_op__data_len, pipe_middle_0_logical_op__is_signed, pipe_middle_0_logical_op__is_32bit, pipe_middle_0_logical_op__output_carry, pipe_middle_0_logical_op__write_cr0, pipe_middle_0_logical_op__invert_out, pipe_middle_0_logical_op__input_carry, pipe_middle_0_logical_op__zero_a, pipe_middle_0_logical_op__invert_in, pipe_middle_0_logical_op__oe__ok, pipe_middle_0_logical_op__oe__oe, pipe_middle_0_logical_op__rc__ok, pipe_middle_0_logical_op__rc__rc, pipe_middle_0_logical_op__imm_data__ok, pipe_middle_0_logical_op__imm_data__data, pipe_middle_0_logical_op__fn_unit, pipe_middle_0_logical_op__insn_type } = { pipe_start_logical_op__insn, pipe_start_logical_op__data_len, pipe_start_logical_op__is_signed, pipe_start_logical_op__is_32bit, pipe_start_logical_op__output_carry, pipe_start_logical_op__write_cr0, pipe_start_logical_op__invert_out, pipe_start_logical_op__input_carry, pipe_start_logical_op__zero_a, pipe_start_logical_op__invert_in, pipe_start_logical_op__oe__ok, pipe_start_logical_op__oe__oe, pipe_start_logical_op__rc__ok, pipe_start_logical_op__rc__rc, pipe_start_logical_op__imm_data__ok, pipe_start_logical_op__imm_data__data, pipe_start_logical_op__fn_unit, pipe_start_logical_op__insn_type }; + assign { pipe_middle_0_logical_op__SV_Ptype, pipe_middle_0_logical_op__sv_saturate, pipe_middle_0_logical_op__sv_pred_dz, pipe_middle_0_logical_op__sv_pred_sz, pipe_middle_0_logical_op__insn, pipe_middle_0_logical_op__data_len, pipe_middle_0_logical_op__is_signed, pipe_middle_0_logical_op__is_32bit, pipe_middle_0_logical_op__output_carry, pipe_middle_0_logical_op__write_cr0, pipe_middle_0_logical_op__invert_out, pipe_middle_0_logical_op__input_carry, pipe_middle_0_logical_op__zero_a, pipe_middle_0_logical_op__invert_in, pipe_middle_0_logical_op__oe__ok, pipe_middle_0_logical_op__oe__oe, pipe_middle_0_logical_op__rc__ok, pipe_middle_0_logical_op__rc__rc, pipe_middle_0_logical_op__imm_data__ok, pipe_middle_0_logical_op__imm_data__data, pipe_middle_0_logical_op__fn_unit, pipe_middle_0_logical_op__insn_type } = { pipe_start_logical_op__SV_Ptype, pipe_start_logical_op__sv_saturate, pipe_start_logical_op__sv_pred_dz, pipe_start_logical_op__sv_pred_sz, pipe_start_logical_op__insn, pipe_start_logical_op__data_len, pipe_start_logical_op__is_signed, pipe_start_logical_op__is_32bit, pipe_start_logical_op__output_carry, pipe_start_logical_op__write_cr0, pipe_start_logical_op__invert_out, pipe_start_logical_op__input_carry, pipe_start_logical_op__zero_a, pipe_start_logical_op__invert_in, pipe_start_logical_op__oe__ok, pipe_start_logical_op__oe__oe, pipe_start_logical_op__rc__ok, pipe_start_logical_op__rc__rc, pipe_start_logical_op__imm_data__ok, pipe_start_logical_op__imm_data__data, pipe_start_logical_op__fn_unit, pipe_start_logical_op__insn_type }; assign pipe_middle_0_muxid = pipe_start_muxid; assign pipe_start_n_ready_i = pipe_middle_0_p_ready_o; assign pipe_middle_0_p_valid_i = pipe_start_n_valid_o; @@ -25815,9 +28466,9 @@ module alu_l(coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -25846,7 +28497,7 @@ module alu_l(coresync_rst, q_alu, r_alu, s_alu, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -25877,9 +28528,9 @@ module \alu_l$107 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -25908,7 +28559,7 @@ module \alu_l$107 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -25939,9 +28590,9 @@ module \alu_l$125 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -25970,7 +28621,7 @@ module \alu_l$125 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -26001,9 +28652,9 @@ module \alu_l$128 (coresync_rst, s_alu, r_alu, q_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -26032,7 +28683,7 @@ module \alu_l$128 (coresync_rst, s_alu, r_alu, q_alu, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -26063,9 +28714,9 @@ module \alu_l$16 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -26094,7 +28745,7 @@ module \alu_l$16 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -26125,9 +28776,9 @@ module \alu_l$29 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -26156,7 +28807,7 @@ module \alu_l$29 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -26187,9 +28838,9 @@ module \alu_l$45 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -26218,7 +28869,7 @@ module \alu_l$45 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -26249,9 +28900,9 @@ module \alu_l$61 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -26280,7 +28931,7 @@ module \alu_l$61 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -26311,9 +28962,9 @@ module \alu_l$73 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -26342,7 +28993,7 @@ module \alu_l$73 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -26373,9 +29024,9 @@ module \alu_l$90 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -26404,7 +29055,7 @@ module \alu_l$90 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -26417,77 +29068,91 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0" *) (* generator = "nMigen" *) -module alu_logical0(coresync_rst, o_ok, cr_a_ok, n_valid_o, n_ready_i, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, o, cr_a, ra, rb, xer_so, p_valid_i, p_ready_o, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) +module alu_logical0(coresync_rst, o_ok, cr_a_ok, n_valid_o, n_ready_i, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__SV_Ptype, o, cr_a, ra, rb, xer_so, p_valid_i, p_ready_o, coresync_clk); + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] logical_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \logical_op__SV_Ptype$74 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [3:0] logical_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [3:0] \logical_op__data_len$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [3:0] \logical_op__data_len$69 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] logical_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] logical_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \logical_op__fn_unit$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \logical_op__fn_unit$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] logical_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \logical_op__imm_data__data$47 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \logical_op__imm_data__data$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__imm_data__ok$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__imm_data__ok$56 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] logical_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [1:0] \logical_op__input_carry$55 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \logical_op__input_carry$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] logical_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \logical_op__insn$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \logical_op__insn$70 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -26563,7 +29228,9 @@ module alu_logical0(coresync_rst, o_ok, cr_a_ok, n_valid_o, n_ready_i, logical_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] logical_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -26640,117 +29307,153 @@ module alu_logical0(coresync_rst, o_ok, cr_a_ok, n_valid_o, n_ready_i, logical_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \logical_op__insn_type$45 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \logical_op__insn_type$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__invert_in$53 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__invert_in$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__invert_out$56 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__invert_out$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__is_32bit$59 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__is_32bit$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__is_signed$60 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__is_signed$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__oe__oe$51 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__oe__oe$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__oe__ok$52 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__oe__ok$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__output_carry$58 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__output_carry$66 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__rc__ok$50 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__rc__ok$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__rc__rc$49 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__rc__rc$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input logical_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__sv_pred_dz$72 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input logical_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__sv_pred_sz$71 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] logical_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \logical_op__sv_saturate$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__write_cr0$57 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__write_cr0$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__zero_a$54 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__zero_a$62 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [3:0] logical_pipe1_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire logical_pipe1_cr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] logical_pipe1_logical_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \logical_pipe1_logical_op__SV_Ptype$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [3:0] logical_pipe1_logical_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [3:0] \logical_pipe1_logical_op__data_len$18 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] logical_pipe1_logical_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] logical_pipe1_logical_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \logical_pipe1_logical_op__fn_unit$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \logical_pipe1_logical_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] logical_pipe1_logical_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] \logical_pipe1_logical_op__imm_data__data$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire logical_pipe1_logical_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \logical_pipe1_logical_op__imm_data__ok$5 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [1:0] logical_pipe1_logical_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [1:0] \logical_pipe1_logical_op__input_carry$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] logical_pipe1_logical_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] \logical_pipe1_logical_op__insn$19 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -26827,7 +29530,9 @@ module alu_logical0(coresync_rst, o_ok, cr_a_ok, n_valid_o, n_ready_i, logical_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] logical_pipe1_logical_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -26904,51 +29609,73 @@ module alu_logical0(coresync_rst, o_ok, cr_a_ok, n_valid_o, n_ready_i, logical_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] \logical_pipe1_logical_op__insn_type$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire logical_pipe1_logical_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \logical_pipe1_logical_op__invert_in$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire logical_pipe1_logical_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \logical_pipe1_logical_op__invert_out$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire logical_pipe1_logical_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \logical_pipe1_logical_op__is_32bit$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire logical_pipe1_logical_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \logical_pipe1_logical_op__is_signed$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire logical_pipe1_logical_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \logical_pipe1_logical_op__oe__oe$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire logical_pipe1_logical_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \logical_pipe1_logical_op__oe__ok$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire logical_pipe1_logical_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \logical_pipe1_logical_op__output_carry$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire logical_pipe1_logical_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \logical_pipe1_logical_op__rc__ok$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire logical_pipe1_logical_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \logical_pipe1_logical_op__rc__rc$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire logical_pipe1_logical_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_pipe1_logical_op__sv_pred_dz$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire logical_pipe1_logical_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_pipe1_logical_op__sv_pred_sz$20 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] logical_pipe1_logical_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \logical_pipe1_logical_op__sv_saturate$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire logical_pipe1_logical_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \logical_pipe1_logical_op__write_cr0$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire logical_pipe1_logical_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \logical_pipe1_logical_op__zero_a$11 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] logical_pipe1_muxid; @@ -26958,94 +29685,108 @@ module alu_logical0(coresync_rst, o_ok, cr_a_ok, n_valid_o, n_ready_i, logical_o wire logical_pipe1_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire logical_pipe1_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] logical_pipe1_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire logical_pipe1_o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire logical_pipe1_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) wire logical_pipe1_p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] logical_pipe1_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] logical_pipe1_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire logical_pipe1_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire \logical_pipe1_xer_so$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire \logical_pipe1_xer_so$24 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire logical_pipe1_xer_so_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [3:0] logical_pipe2_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [3:0] \logical_pipe2_cr_a$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [3:0] \logical_pipe2_cr_a$50 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire logical_pipe2_cr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \logical_pipe2_cr_a_ok$43 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \logical_pipe2_cr_a_ok$51 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] logical_pipe2_logical_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \logical_pipe2_logical_op__SV_Ptype$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [3:0] logical_pipe2_logical_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [3:0] \logical_pipe2_logical_op__data_len$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [3:0] \logical_pipe2_logical_op__data_len$42 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] logical_pipe2_logical_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] logical_pipe2_logical_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \logical_pipe2_logical_op__fn_unit$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \logical_pipe2_logical_op__fn_unit$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] logical_pipe2_logical_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \logical_pipe2_logical_op__imm_data__data$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \logical_pipe2_logical_op__imm_data__data$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire logical_pipe2_logical_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_pipe2_logical_op__imm_data__ok$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_pipe2_logical_op__imm_data__ok$29 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [1:0] logical_pipe2_logical_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [1:0] \logical_pipe2_logical_op__input_carry$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \logical_pipe2_logical_op__input_carry$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] logical_pipe2_logical_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \logical_pipe2_logical_op__insn$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \logical_pipe2_logical_op__insn$43 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -27121,7 +29862,9 @@ module alu_logical0(coresync_rst, o_ok, cr_a_ok, n_valid_o, n_ready_i, logical_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] logical_pipe2_logical_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -27198,103 +29941,127 @@ module alu_logical0(coresync_rst, o_ok, cr_a_ok, n_valid_o, n_ready_i, logical_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \logical_pipe2_logical_op__insn_type$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \logical_pipe2_logical_op__insn_type$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire logical_pipe2_logical_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_pipe2_logical_op__invert_in$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_pipe2_logical_op__invert_in$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire logical_pipe2_logical_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_pipe2_logical_op__invert_out$33 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_pipe2_logical_op__invert_out$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire logical_pipe2_logical_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_pipe2_logical_op__is_32bit$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_pipe2_logical_op__is_32bit$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire logical_pipe2_logical_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_pipe2_logical_op__is_signed$37 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_pipe2_logical_op__is_signed$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire logical_pipe2_logical_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_pipe2_logical_op__oe__oe$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_pipe2_logical_op__oe__oe$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire logical_pipe2_logical_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_pipe2_logical_op__oe__ok$29 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_pipe2_logical_op__oe__ok$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire logical_pipe2_logical_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_pipe2_logical_op__output_carry$35 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_pipe2_logical_op__output_carry$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire logical_pipe2_logical_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_pipe2_logical_op__rc__ok$27 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_pipe2_logical_op__rc__ok$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire logical_pipe2_logical_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_pipe2_logical_op__rc__rc$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_pipe2_logical_op__rc__rc$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire logical_pipe2_logical_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_pipe2_logical_op__sv_pred_dz$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire logical_pipe2_logical_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_pipe2_logical_op__sv_pred_sz$44 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] logical_pipe2_logical_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \logical_pipe2_logical_op__sv_saturate$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire logical_pipe2_logical_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_pipe2_logical_op__write_cr0$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_pipe2_logical_op__write_cr0$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire logical_pipe2_logical_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_pipe2_logical_op__zero_a$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_pipe2_logical_op__zero_a$35 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] logical_pipe2_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \logical_pipe2_muxid$21 ; + wire [1:0] \logical_pipe2_muxid$25 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) wire logical_pipe2_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire logical_pipe2_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] logical_pipe2_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \logical_pipe2_o$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \logical_pipe2_o$48 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire logical_pipe2_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \logical_pipe2_o_ok$41 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \logical_pipe2_o_ok$49 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire logical_pipe2_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) wire logical_pipe2_p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire logical_pipe2_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire logical_pipe2_xer_so_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \muxid$44 ; + wire [1:0] \muxid$52 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) input p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input xer_so; logical_pipe1 logical_pipe1 ( .coresync_clk(coresync_clk), .coresync_rst(coresync_rst), .cr_a(logical_pipe1_cr_a), .cr_a_ok(logical_pipe1_cr_a_ok), + .logical_op__SV_Ptype(logical_pipe1_logical_op__SV_Ptype), + .\logical_op__SV_Ptype$23 (\logical_pipe1_logical_op__SV_Ptype$23 ), .logical_op__data_len(logical_pipe1_logical_op__data_len), .\logical_op__data_len$18 (\logical_pipe1_logical_op__data_len$18 ), .logical_op__fn_unit(logical_pipe1_logical_op__fn_unit), @@ -27327,6 +30094,12 @@ module alu_logical0(coresync_rst, o_ok, cr_a_ok, n_valid_o, n_ready_i, logical_o .\logical_op__rc__ok$7 (\logical_pipe1_logical_op__rc__ok$7 ), .logical_op__rc__rc(logical_pipe1_logical_op__rc__rc), .\logical_op__rc__rc$6 (\logical_pipe1_logical_op__rc__rc$6 ), + .logical_op__sv_pred_dz(logical_pipe1_logical_op__sv_pred_dz), + .\logical_op__sv_pred_dz$21 (\logical_pipe1_logical_op__sv_pred_dz$21 ), + .logical_op__sv_pred_sz(logical_pipe1_logical_op__sv_pred_sz), + .\logical_op__sv_pred_sz$20 (\logical_pipe1_logical_op__sv_pred_sz$20 ), + .logical_op__sv_saturate(logical_pipe1_logical_op__sv_saturate), + .\logical_op__sv_saturate$22 (\logical_pipe1_logical_op__sv_saturate$22 ), .logical_op__write_cr0(logical_pipe1_logical_op__write_cr0), .\logical_op__write_cr0$14 (\logical_pipe1_logical_op__write_cr0$14 ), .logical_op__zero_a(logical_pipe1_logical_op__zero_a), @@ -27342,60 +30115,68 @@ module alu_logical0(coresync_rst, o_ok, cr_a_ok, n_valid_o, n_ready_i, logical_o .ra(logical_pipe1_ra), .rb(logical_pipe1_rb), .xer_so(logical_pipe1_xer_so), - .\xer_so$20 (\logical_pipe1_xer_so$20 ), + .\xer_so$24 (\logical_pipe1_xer_so$24 ), .xer_so_ok(logical_pipe1_xer_so_ok) ); logical_pipe2 logical_pipe2 ( .coresync_clk(coresync_clk), .coresync_rst(coresync_rst), .cr_a(logical_pipe2_cr_a), - .\cr_a$22 (\logical_pipe2_cr_a$42 ), + .\cr_a$26 (\logical_pipe2_cr_a$50 ), .cr_a_ok(logical_pipe2_cr_a_ok), - .\cr_a_ok$23 (\logical_pipe2_cr_a_ok$43 ), + .\cr_a_ok$27 (\logical_pipe2_cr_a_ok$51 ), + .logical_op__SV_Ptype(logical_pipe2_logical_op__SV_Ptype), + .\logical_op__SV_Ptype$23 (\logical_pipe2_logical_op__SV_Ptype$47 ), .logical_op__data_len(logical_pipe2_logical_op__data_len), - .\logical_op__data_len$18 (\logical_pipe2_logical_op__data_len$38 ), + .\logical_op__data_len$18 (\logical_pipe2_logical_op__data_len$42 ), .logical_op__fn_unit(logical_pipe2_logical_op__fn_unit), - .\logical_op__fn_unit$3 (\logical_pipe2_logical_op__fn_unit$23 ), + .\logical_op__fn_unit$3 (\logical_pipe2_logical_op__fn_unit$27 ), .logical_op__imm_data__data(logical_pipe2_logical_op__imm_data__data), - .\logical_op__imm_data__data$4 (\logical_pipe2_logical_op__imm_data__data$24 ), + .\logical_op__imm_data__data$4 (\logical_pipe2_logical_op__imm_data__data$28 ), .logical_op__imm_data__ok(logical_pipe2_logical_op__imm_data__ok), - .\logical_op__imm_data__ok$5 (\logical_pipe2_logical_op__imm_data__ok$25 ), + .\logical_op__imm_data__ok$5 (\logical_pipe2_logical_op__imm_data__ok$29 ), .logical_op__input_carry(logical_pipe2_logical_op__input_carry), - .\logical_op__input_carry$12 (\logical_pipe2_logical_op__input_carry$32 ), + .\logical_op__input_carry$12 (\logical_pipe2_logical_op__input_carry$36 ), .logical_op__insn(logical_pipe2_logical_op__insn), - .\logical_op__insn$19 (\logical_pipe2_logical_op__insn$39 ), + .\logical_op__insn$19 (\logical_pipe2_logical_op__insn$43 ), .logical_op__insn_type(logical_pipe2_logical_op__insn_type), - .\logical_op__insn_type$2 (\logical_pipe2_logical_op__insn_type$22 ), + .\logical_op__insn_type$2 (\logical_pipe2_logical_op__insn_type$26 ), .logical_op__invert_in(logical_pipe2_logical_op__invert_in), - .\logical_op__invert_in$10 (\logical_pipe2_logical_op__invert_in$30 ), + .\logical_op__invert_in$10 (\logical_pipe2_logical_op__invert_in$34 ), .logical_op__invert_out(logical_pipe2_logical_op__invert_out), - .\logical_op__invert_out$13 (\logical_pipe2_logical_op__invert_out$33 ), + .\logical_op__invert_out$13 (\logical_pipe2_logical_op__invert_out$37 ), .logical_op__is_32bit(logical_pipe2_logical_op__is_32bit), - .\logical_op__is_32bit$16 (\logical_pipe2_logical_op__is_32bit$36 ), + .\logical_op__is_32bit$16 (\logical_pipe2_logical_op__is_32bit$40 ), .logical_op__is_signed(logical_pipe2_logical_op__is_signed), - .\logical_op__is_signed$17 (\logical_pipe2_logical_op__is_signed$37 ), + .\logical_op__is_signed$17 (\logical_pipe2_logical_op__is_signed$41 ), .logical_op__oe__oe(logical_pipe2_logical_op__oe__oe), - .\logical_op__oe__oe$8 (\logical_pipe2_logical_op__oe__oe$28 ), + .\logical_op__oe__oe$8 (\logical_pipe2_logical_op__oe__oe$32 ), .logical_op__oe__ok(logical_pipe2_logical_op__oe__ok), - .\logical_op__oe__ok$9 (\logical_pipe2_logical_op__oe__ok$29 ), + .\logical_op__oe__ok$9 (\logical_pipe2_logical_op__oe__ok$33 ), .logical_op__output_carry(logical_pipe2_logical_op__output_carry), - .\logical_op__output_carry$15 (\logical_pipe2_logical_op__output_carry$35 ), + .\logical_op__output_carry$15 (\logical_pipe2_logical_op__output_carry$39 ), .logical_op__rc__ok(logical_pipe2_logical_op__rc__ok), - .\logical_op__rc__ok$7 (\logical_pipe2_logical_op__rc__ok$27 ), + .\logical_op__rc__ok$7 (\logical_pipe2_logical_op__rc__ok$31 ), .logical_op__rc__rc(logical_pipe2_logical_op__rc__rc), - .\logical_op__rc__rc$6 (\logical_pipe2_logical_op__rc__rc$26 ), + .\logical_op__rc__rc$6 (\logical_pipe2_logical_op__rc__rc$30 ), + .logical_op__sv_pred_dz(logical_pipe2_logical_op__sv_pred_dz), + .\logical_op__sv_pred_dz$21 (\logical_pipe2_logical_op__sv_pred_dz$45 ), + .logical_op__sv_pred_sz(logical_pipe2_logical_op__sv_pred_sz), + .\logical_op__sv_pred_sz$20 (\logical_pipe2_logical_op__sv_pred_sz$44 ), + .logical_op__sv_saturate(logical_pipe2_logical_op__sv_saturate), + .\logical_op__sv_saturate$22 (\logical_pipe2_logical_op__sv_saturate$46 ), .logical_op__write_cr0(logical_pipe2_logical_op__write_cr0), - .\logical_op__write_cr0$14 (\logical_pipe2_logical_op__write_cr0$34 ), + .\logical_op__write_cr0$14 (\logical_pipe2_logical_op__write_cr0$38 ), .logical_op__zero_a(logical_pipe2_logical_op__zero_a), - .\logical_op__zero_a$11 (\logical_pipe2_logical_op__zero_a$31 ), + .\logical_op__zero_a$11 (\logical_pipe2_logical_op__zero_a$35 ), .muxid(logical_pipe2_muxid), - .\muxid$1 (\logical_pipe2_muxid$21 ), + .\muxid$1 (\logical_pipe2_muxid$25 ), .n_ready_i(logical_pipe2_n_ready_i), .n_valid_o(logical_pipe2_n_valid_o), .o(logical_pipe2_o), - .\o$20 (\logical_pipe2_o$40 ), + .\o$24 (\logical_pipe2_o$48 ), .o_ok(logical_pipe2_o_ok), - .\o_ok$21 (\logical_pipe2_o_ok$41 ), + .\o_ok$25 (\logical_pipe2_o_ok$49 ), .p_ready_o(logical_pipe2_p_ready_o), .p_valid_i(logical_pipe2_p_valid_i), .xer_so(logical_pipe2_xer_so), @@ -27410,23 +30191,23 @@ module alu_logical0(coresync_rst, o_ok, cr_a_ok, n_valid_o, n_ready_i, logical_o .p_valid_i(p_valid_i) ); assign muxid = 2'h0; - assign { cr_a_ok, cr_a } = { \logical_pipe2_cr_a_ok$43 , \logical_pipe2_cr_a$42 }; - assign { o_ok, o } = { \logical_pipe2_o_ok$41 , \logical_pipe2_o$40 }; - assign { \logical_op__insn$62 , \logical_op__data_len$61 , \logical_op__is_signed$60 , \logical_op__is_32bit$59 , \logical_op__output_carry$58 , \logical_op__write_cr0$57 , \logical_op__invert_out$56 , \logical_op__input_carry$55 , \logical_op__zero_a$54 , \logical_op__invert_in$53 , \logical_op__oe__ok$52 , \logical_op__oe__oe$51 , \logical_op__rc__ok$50 , \logical_op__rc__rc$49 , \logical_op__imm_data__ok$48 , \logical_op__imm_data__data$47 , \logical_op__fn_unit$46 , \logical_op__insn_type$45 } = { \logical_pipe2_logical_op__insn$39 , \logical_pipe2_logical_op__data_len$38 , \logical_pipe2_logical_op__is_signed$37 , \logical_pipe2_logical_op__is_32bit$36 , \logical_pipe2_logical_op__output_carry$35 , \logical_pipe2_logical_op__write_cr0$34 , \logical_pipe2_logical_op__invert_out$33 , \logical_pipe2_logical_op__input_carry$32 , \logical_pipe2_logical_op__zero_a$31 , \logical_pipe2_logical_op__invert_in$30 , \logical_pipe2_logical_op__oe__ok$29 , \logical_pipe2_logical_op__oe__oe$28 , \logical_pipe2_logical_op__rc__ok$27 , \logical_pipe2_logical_op__rc__rc$26 , \logical_pipe2_logical_op__imm_data__ok$25 , \logical_pipe2_logical_op__imm_data__data$24 , \logical_pipe2_logical_op__fn_unit$23 , \logical_pipe2_logical_op__insn_type$22 }; - assign \muxid$44 = \logical_pipe2_muxid$21 ; + assign { cr_a_ok, cr_a } = { \logical_pipe2_cr_a_ok$51 , \logical_pipe2_cr_a$50 }; + assign { o_ok, o } = { \logical_pipe2_o_ok$49 , \logical_pipe2_o$48 }; + assign { \logical_op__SV_Ptype$74 , \logical_op__sv_saturate$73 , \logical_op__sv_pred_dz$72 , \logical_op__sv_pred_sz$71 , \logical_op__insn$70 , \logical_op__data_len$69 , \logical_op__is_signed$68 , \logical_op__is_32bit$67 , \logical_op__output_carry$66 , \logical_op__write_cr0$65 , \logical_op__invert_out$64 , \logical_op__input_carry$63 , \logical_op__zero_a$62 , \logical_op__invert_in$61 , \logical_op__oe__ok$60 , \logical_op__oe__oe$59 , \logical_op__rc__ok$58 , \logical_op__rc__rc$57 , \logical_op__imm_data__ok$56 , \logical_op__imm_data__data$55 , \logical_op__fn_unit$54 , \logical_op__insn_type$53 } = { \logical_pipe2_logical_op__SV_Ptype$47 , \logical_pipe2_logical_op__sv_saturate$46 , \logical_pipe2_logical_op__sv_pred_dz$45 , \logical_pipe2_logical_op__sv_pred_sz$44 , \logical_pipe2_logical_op__insn$43 , \logical_pipe2_logical_op__data_len$42 , \logical_pipe2_logical_op__is_signed$41 , \logical_pipe2_logical_op__is_32bit$40 , \logical_pipe2_logical_op__output_carry$39 , \logical_pipe2_logical_op__write_cr0$38 , \logical_pipe2_logical_op__invert_out$37 , \logical_pipe2_logical_op__input_carry$36 , \logical_pipe2_logical_op__zero_a$35 , \logical_pipe2_logical_op__invert_in$34 , \logical_pipe2_logical_op__oe__ok$33 , \logical_pipe2_logical_op__oe__oe$32 , \logical_pipe2_logical_op__rc__ok$31 , \logical_pipe2_logical_op__rc__rc$30 , \logical_pipe2_logical_op__imm_data__ok$29 , \logical_pipe2_logical_op__imm_data__data$28 , \logical_pipe2_logical_op__fn_unit$27 , \logical_pipe2_logical_op__insn_type$26 }; + assign \muxid$52 = \logical_pipe2_muxid$25 ; assign logical_pipe2_n_ready_i = n_ready_i; assign n_valid_o = logical_pipe2_n_valid_o; - assign \logical_pipe1_xer_so$20 = xer_so; + assign \logical_pipe1_xer_so$24 = xer_so; assign logical_pipe1_rb = rb; assign logical_pipe1_ra = ra; - assign { \logical_pipe1_logical_op__insn$19 , \logical_pipe1_logical_op__data_len$18 , \logical_pipe1_logical_op__is_signed$17 , \logical_pipe1_logical_op__is_32bit$16 , \logical_pipe1_logical_op__output_carry$15 , \logical_pipe1_logical_op__write_cr0$14 , \logical_pipe1_logical_op__invert_out$13 , \logical_pipe1_logical_op__input_carry$12 , \logical_pipe1_logical_op__zero_a$11 , \logical_pipe1_logical_op__invert_in$10 , \logical_pipe1_logical_op__oe__ok$9 , \logical_pipe1_logical_op__oe__oe$8 , \logical_pipe1_logical_op__rc__ok$7 , \logical_pipe1_logical_op__rc__rc$6 , \logical_pipe1_logical_op__imm_data__ok$5 , \logical_pipe1_logical_op__imm_data__data$4 , \logical_pipe1_logical_op__fn_unit$3 , \logical_pipe1_logical_op__insn_type$2 } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; + assign { \logical_pipe1_logical_op__SV_Ptype$23 , \logical_pipe1_logical_op__sv_saturate$22 , \logical_pipe1_logical_op__sv_pred_dz$21 , \logical_pipe1_logical_op__sv_pred_sz$20 , \logical_pipe1_logical_op__insn$19 , \logical_pipe1_logical_op__data_len$18 , \logical_pipe1_logical_op__is_signed$17 , \logical_pipe1_logical_op__is_32bit$16 , \logical_pipe1_logical_op__output_carry$15 , \logical_pipe1_logical_op__write_cr0$14 , \logical_pipe1_logical_op__invert_out$13 , \logical_pipe1_logical_op__input_carry$12 , \logical_pipe1_logical_op__zero_a$11 , \logical_pipe1_logical_op__invert_in$10 , \logical_pipe1_logical_op__oe__ok$9 , \logical_pipe1_logical_op__oe__oe$8 , \logical_pipe1_logical_op__rc__ok$7 , \logical_pipe1_logical_op__rc__rc$6 , \logical_pipe1_logical_op__imm_data__ok$5 , \logical_pipe1_logical_op__imm_data__data$4 , \logical_pipe1_logical_op__fn_unit$3 , \logical_pipe1_logical_op__insn_type$2 } = { logical_op__SV_Ptype, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; assign \logical_pipe1_muxid$1 = 2'h0; assign p_ready_o = logical_pipe1_p_ready_o; assign logical_pipe1_p_valid_i = p_valid_i; assign { logical_pipe2_xer_so_ok, logical_pipe2_xer_so } = { logical_pipe1_xer_so_ok, logical_pipe1_xer_so }; assign { logical_pipe2_cr_a_ok, logical_pipe2_cr_a } = { logical_pipe1_cr_a_ok, logical_pipe1_cr_a }; assign { logical_pipe2_o_ok, logical_pipe2_o } = { logical_pipe1_o_ok, logical_pipe1_o }; - assign { logical_pipe2_logical_op__insn, logical_pipe2_logical_op__data_len, logical_pipe2_logical_op__is_signed, logical_pipe2_logical_op__is_32bit, logical_pipe2_logical_op__output_carry, logical_pipe2_logical_op__write_cr0, logical_pipe2_logical_op__invert_out, logical_pipe2_logical_op__input_carry, logical_pipe2_logical_op__zero_a, logical_pipe2_logical_op__invert_in, logical_pipe2_logical_op__oe__ok, logical_pipe2_logical_op__oe__oe, logical_pipe2_logical_op__rc__ok, logical_pipe2_logical_op__rc__rc, logical_pipe2_logical_op__imm_data__ok, logical_pipe2_logical_op__imm_data__data, logical_pipe2_logical_op__fn_unit, logical_pipe2_logical_op__insn_type } = { logical_pipe1_logical_op__insn, logical_pipe1_logical_op__data_len, logical_pipe1_logical_op__is_signed, logical_pipe1_logical_op__is_32bit, logical_pipe1_logical_op__output_carry, logical_pipe1_logical_op__write_cr0, logical_pipe1_logical_op__invert_out, logical_pipe1_logical_op__input_carry, logical_pipe1_logical_op__zero_a, logical_pipe1_logical_op__invert_in, logical_pipe1_logical_op__oe__ok, logical_pipe1_logical_op__oe__oe, logical_pipe1_logical_op__rc__ok, logical_pipe1_logical_op__rc__rc, logical_pipe1_logical_op__imm_data__ok, logical_pipe1_logical_op__imm_data__data, logical_pipe1_logical_op__fn_unit, logical_pipe1_logical_op__insn_type }; + assign { logical_pipe2_logical_op__SV_Ptype, logical_pipe2_logical_op__sv_saturate, logical_pipe2_logical_op__sv_pred_dz, logical_pipe2_logical_op__sv_pred_sz, logical_pipe2_logical_op__insn, logical_pipe2_logical_op__data_len, logical_pipe2_logical_op__is_signed, logical_pipe2_logical_op__is_32bit, logical_pipe2_logical_op__output_carry, logical_pipe2_logical_op__write_cr0, logical_pipe2_logical_op__invert_out, logical_pipe2_logical_op__input_carry, logical_pipe2_logical_op__zero_a, logical_pipe2_logical_op__invert_in, logical_pipe2_logical_op__oe__ok, logical_pipe2_logical_op__oe__oe, logical_pipe2_logical_op__rc__ok, logical_pipe2_logical_op__rc__rc, logical_pipe2_logical_op__imm_data__ok, logical_pipe2_logical_op__imm_data__data, logical_pipe2_logical_op__fn_unit, logical_pipe2_logical_op__insn_type } = { logical_pipe1_logical_op__SV_Ptype, logical_pipe1_logical_op__sv_saturate, logical_pipe1_logical_op__sv_pred_dz, logical_pipe1_logical_op__sv_pred_sz, logical_pipe1_logical_op__insn, logical_pipe1_logical_op__data_len, logical_pipe1_logical_op__is_signed, logical_pipe1_logical_op__is_32bit, logical_pipe1_logical_op__output_carry, logical_pipe1_logical_op__write_cr0, logical_pipe1_logical_op__invert_out, logical_pipe1_logical_op__input_carry, logical_pipe1_logical_op__zero_a, logical_pipe1_logical_op__invert_in, logical_pipe1_logical_op__oe__ok, logical_pipe1_logical_op__oe__oe, logical_pipe1_logical_op__rc__ok, logical_pipe1_logical_op__rc__rc, logical_pipe1_logical_op__imm_data__ok, logical_pipe1_logical_op__imm_data__data, logical_pipe1_logical_op__fn_unit, logical_pipe1_logical_op__insn_type }; assign logical_pipe2_muxid = logical_pipe1_muxid; assign logical_pipe1_n_ready_i = logical_pipe2_p_ready_o; assign logical_pipe2_p_valid_i = logical_pipe1_n_valid_o; @@ -27434,61 +30215,75 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0" *) (* generator = "nMigen" *) -module alu_mul0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ready_i, mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, o, cr_a, xer_ov, xer_so, ra, rb, \xer_so$1 , p_valid_i, p_ready_o, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) +module alu_mul0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ready_i, mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, mul_op__sv_pred_sz, mul_op__sv_pred_dz, mul_op__sv_saturate, mul_op__SV_Ptype, o, cr_a, xer_ov, xer_so, ra, rb, \xer_so$1 , p_valid_i, p_ready_o, coresync_clk); + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_a_ok; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] mul_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \mul_op__SV_Ptype$77 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] mul_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] mul_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \mul_op__fn_unit$51 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \mul_op__fn_unit$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] mul_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \mul_op__imm_data__data$52 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \mul_op__imm_data__data$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_op__imm_data__ok$53 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__imm_data__ok$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] mul_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \mul_op__insn$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \mul_op__insn$73 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -27564,7 +30359,9 @@ module alu_mul0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] mul_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -27641,81 +30438,117 @@ module alu_mul0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \mul_op__insn_type$50 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \mul_op__insn_type$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_op__is_32bit$59 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__is_32bit$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_op__is_signed$60 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__is_signed$72 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_op__oe__oe$56 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__oe__oe$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_op__oe__ok$57 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__oe__ok$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_op__rc__ok$55 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__rc__ok$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_op__rc__rc$54 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__rc__rc$66 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input mul_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__sv_pred_dz$75 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input mul_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__sv_pred_sz$74 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] mul_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \mul_op__sv_saturate$76 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_op__write_cr0$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__write_cr0$70 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] mul_pipe1_mul_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \mul_pipe1_mul_op__SV_Ptype$18 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] mul_pipe1_mul_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] mul_pipe1_mul_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \mul_pipe1_mul_op__fn_unit$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \mul_pipe1_mul_op__fn_unit$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] mul_pipe1_mul_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] \mul_pipe1_mul_op__imm_data__data$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul_pipe1_mul_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \mul_pipe1_mul_op__imm_data__ok$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] mul_pipe1_mul_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] \mul_pipe1_mul_op__insn$14 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -27792,7 +30625,9 @@ module alu_mul0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] mul_pipe1_mul_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -27869,35 +30704,57 @@ module alu_mul0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] \mul_pipe1_mul_op__insn_type$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul_pipe1_mul_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \mul_pipe1_mul_op__is_32bit$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul_pipe1_mul_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \mul_pipe1_mul_op__is_signed$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul_pipe1_mul_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \mul_pipe1_mul_op__oe__oe$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul_pipe1_mul_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \mul_pipe1_mul_op__oe__ok$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul_pipe1_mul_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \mul_pipe1_mul_op__rc__ok$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul_pipe1_mul_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \mul_pipe1_mul_op__rc__rc$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire mul_pipe1_mul_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_pipe1_mul_op__sv_pred_dz$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire mul_pipe1_mul_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_pipe1_mul_op__sv_pred_sz$15 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] mul_pipe1_mul_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \mul_pipe1_mul_op__sv_saturate$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul_pipe1_mul_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \mul_pipe1_mul_op__write_cr0$11 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] mul_pipe1_muxid; @@ -27915,64 +30772,78 @@ module alu_mul0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ wire mul_pipe1_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) wire mul_pipe1_p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] mul_pipe1_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \mul_pipe1_ra$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \mul_pipe1_ra$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] mul_pipe1_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \mul_pipe1_rb$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \mul_pipe1_rb$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire mul_pipe1_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire \mul_pipe1_xer_so$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire \mul_pipe1_xer_so$21 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] mul_pipe2_mul_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \mul_pipe2_mul_op__SV_Ptype$38 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] mul_pipe2_mul_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] mul_pipe2_mul_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \mul_pipe2_mul_op__fn_unit$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \mul_pipe2_mul_op__fn_unit$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] mul_pipe2_mul_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \mul_pipe2_mul_op__imm_data__data$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \mul_pipe2_mul_op__imm_data__data$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul_pipe2_mul_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_pipe2_mul_op__imm_data__ok$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_pipe2_mul_op__imm_data__ok$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] mul_pipe2_mul_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \mul_pipe2_mul_op__insn$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \mul_pipe2_mul_op__insn$34 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -28048,7 +30919,9 @@ module alu_mul0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] mul_pipe2_mul_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -28125,40 +30998,62 @@ module alu_mul0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \mul_pipe2_mul_op__insn_type$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \mul_pipe2_mul_op__insn_type$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul_pipe2_mul_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_pipe2_mul_op__is_32bit$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_pipe2_mul_op__is_32bit$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul_pipe2_mul_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_pipe2_mul_op__is_signed$29 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_pipe2_mul_op__is_signed$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul_pipe2_mul_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_pipe2_mul_op__oe__oe$25 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_pipe2_mul_op__oe__oe$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul_pipe2_mul_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_pipe2_mul_op__oe__ok$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_pipe2_mul_op__oe__ok$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul_pipe2_mul_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_pipe2_mul_op__rc__ok$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_pipe2_mul_op__rc__ok$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul_pipe2_mul_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_pipe2_mul_op__rc__rc$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_pipe2_mul_op__rc__rc$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire mul_pipe2_mul_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_pipe2_mul_op__sv_pred_dz$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire mul_pipe2_mul_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_pipe2_mul_op__sv_pred_sz$35 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] mul_pipe2_mul_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \mul_pipe2_mul_op__sv_saturate$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul_pipe2_mul_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_pipe2_mul_op__write_cr0$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_pipe2_mul_op__write_cr0$31 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] mul_pipe2_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \mul_pipe2_muxid$18 ; + wire [1:0] \mul_pipe2_muxid$22 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) wire mul_pipe2_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) @@ -28166,75 +31061,89 @@ module alu_mul0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *) wire mul_pipe2_neg_res; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *) - wire \mul_pipe2_neg_res$32 ; + wire \mul_pipe2_neg_res$40 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *) wire mul_pipe2_neg_res32; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *) - wire \mul_pipe2_neg_res32$33 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire \mul_pipe2_neg_res32$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [128:0] mul_pipe2_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire mul_pipe2_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) wire mul_pipe2_p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] mul_pipe2_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] mul_pipe2_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire mul_pipe2_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire \mul_pipe2_xer_so$31 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire \mul_pipe2_xer_so$39 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [3:0] mul_pipe3_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire mul_pipe3_cr_a_ok; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] mul_pipe3_mul_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \mul_pipe3_mul_op__SV_Ptype$58 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] mul_pipe3_mul_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] mul_pipe3_mul_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \mul_pipe3_mul_op__fn_unit$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \mul_pipe3_mul_op__fn_unit$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] mul_pipe3_mul_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \mul_pipe3_mul_op__imm_data__data$37 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \mul_pipe3_mul_op__imm_data__data$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul_pipe3_mul_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_pipe3_mul_op__imm_data__ok$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_pipe3_mul_op__imm_data__ok$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] mul_pipe3_mul_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \mul_pipe3_mul_op__insn$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \mul_pipe3_mul_op__insn$54 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -28310,7 +31219,9 @@ module alu_mul0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] mul_pipe3_mul_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -28387,40 +31298,62 @@ module alu_mul0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \mul_pipe3_mul_op__insn_type$35 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \mul_pipe3_mul_op__insn_type$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul_pipe3_mul_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_pipe3_mul_op__is_32bit$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_pipe3_mul_op__is_32bit$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul_pipe3_mul_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_pipe3_mul_op__is_signed$45 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_pipe3_mul_op__is_signed$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul_pipe3_mul_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_pipe3_mul_op__oe__oe$41 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_pipe3_mul_op__oe__oe$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul_pipe3_mul_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_pipe3_mul_op__oe__ok$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_pipe3_mul_op__oe__ok$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul_pipe3_mul_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_pipe3_mul_op__rc__ok$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_pipe3_mul_op__rc__ok$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul_pipe3_mul_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_pipe3_mul_op__rc__rc$39 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_pipe3_mul_op__rc__rc$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire mul_pipe3_mul_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_pipe3_mul_op__sv_pred_dz$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire mul_pipe3_mul_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_pipe3_mul_op__sv_pred_sz$55 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] mul_pipe3_mul_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \mul_pipe3_mul_op__sv_saturate$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul_pipe3_mul_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_pipe3_mul_op__write_cr0$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_pipe3_mul_op__write_cr0$51 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] mul_pipe3_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \mul_pipe3_muxid$34 ; + wire [1:0] \mul_pipe3_muxid$42 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) wire mul_pipe3_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) @@ -28429,59 +31362,61 @@ module alu_mul0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ wire mul_pipe3_neg_res; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *) wire mul_pipe3_neg_res32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [128:0] mul_pipe3_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \mul_pipe3_o$47 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \mul_pipe3_o$59 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire mul_pipe3_o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire mul_pipe3_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) wire mul_pipe3_p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [1:0] mul_pipe3_xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire mul_pipe3_xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire mul_pipe3_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \mul_pipe3_xer_so$48 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \mul_pipe3_xer_so$60 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire mul_pipe3_xer_so_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \muxid$49 ; + wire [1:0] \muxid$61 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) input p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [1:0] xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input \xer_so$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_so_ok; mul_pipe1 mul_pipe1 ( .coresync_clk(coresync_clk), .coresync_rst(coresync_rst), + .mul_op__SV_Ptype(mul_pipe1_mul_op__SV_Ptype), + .\mul_op__SV_Ptype$17 (\mul_pipe1_mul_op__SV_Ptype$18 ), .mul_op__fn_unit(mul_pipe1_mul_op__fn_unit), .\mul_op__fn_unit$3 (\mul_pipe1_mul_op__fn_unit$4 ), .mul_op__imm_data__data(mul_pipe1_mul_op__imm_data__data), @@ -28504,6 +31439,12 @@ module alu_mul0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ .\mul_op__rc__ok$7 (\mul_pipe1_mul_op__rc__ok$8 ), .mul_op__rc__rc(mul_pipe1_mul_op__rc__rc), .\mul_op__rc__rc$6 (\mul_pipe1_mul_op__rc__rc$7 ), + .mul_op__sv_pred_dz(mul_pipe1_mul_op__sv_pred_dz), + .\mul_op__sv_pred_dz$15 (\mul_pipe1_mul_op__sv_pred_dz$16 ), + .mul_op__sv_pred_sz(mul_pipe1_mul_op__sv_pred_sz), + .\mul_op__sv_pred_sz$14 (\mul_pipe1_mul_op__sv_pred_sz$15 ), + .mul_op__sv_saturate(mul_pipe1_mul_op__sv_saturate), + .\mul_op__sv_saturate$16 (\mul_pipe1_mul_op__sv_saturate$17 ), .mul_op__write_cr0(mul_pipe1_mul_op__write_cr0), .\mul_op__write_cr0$10 (\mul_pipe1_mul_op__write_cr0$11 ), .muxid(mul_pipe1_muxid), @@ -28515,99 +31456,115 @@ module alu_mul0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ .p_ready_o(mul_pipe1_p_ready_o), .p_valid_i(mul_pipe1_p_valid_i), .ra(mul_pipe1_ra), - .\ra$14 (\mul_pipe1_ra$15 ), + .\ra$18 (\mul_pipe1_ra$19 ), .rb(mul_pipe1_rb), - .\rb$15 (\mul_pipe1_rb$16 ), + .\rb$19 (\mul_pipe1_rb$20 ), .xer_so(mul_pipe1_xer_so), - .\xer_so$16 (\mul_pipe1_xer_so$17 ) + .\xer_so$20 (\mul_pipe1_xer_so$21 ) ); mul_pipe2 mul_pipe2 ( .coresync_clk(coresync_clk), .coresync_rst(coresync_rst), + .mul_op__SV_Ptype(mul_pipe2_mul_op__SV_Ptype), + .\mul_op__SV_Ptype$17 (\mul_pipe2_mul_op__SV_Ptype$38 ), .mul_op__fn_unit(mul_pipe2_mul_op__fn_unit), - .\mul_op__fn_unit$3 (\mul_pipe2_mul_op__fn_unit$20 ), + .\mul_op__fn_unit$3 (\mul_pipe2_mul_op__fn_unit$24 ), .mul_op__imm_data__data(mul_pipe2_mul_op__imm_data__data), - .\mul_op__imm_data__data$4 (\mul_pipe2_mul_op__imm_data__data$21 ), + .\mul_op__imm_data__data$4 (\mul_pipe2_mul_op__imm_data__data$25 ), .mul_op__imm_data__ok(mul_pipe2_mul_op__imm_data__ok), - .\mul_op__imm_data__ok$5 (\mul_pipe2_mul_op__imm_data__ok$22 ), + .\mul_op__imm_data__ok$5 (\mul_pipe2_mul_op__imm_data__ok$26 ), .mul_op__insn(mul_pipe2_mul_op__insn), - .\mul_op__insn$13 (\mul_pipe2_mul_op__insn$30 ), + .\mul_op__insn$13 (\mul_pipe2_mul_op__insn$34 ), .mul_op__insn_type(mul_pipe2_mul_op__insn_type), - .\mul_op__insn_type$2 (\mul_pipe2_mul_op__insn_type$19 ), + .\mul_op__insn_type$2 (\mul_pipe2_mul_op__insn_type$23 ), .mul_op__is_32bit(mul_pipe2_mul_op__is_32bit), - .\mul_op__is_32bit$11 (\mul_pipe2_mul_op__is_32bit$28 ), + .\mul_op__is_32bit$11 (\mul_pipe2_mul_op__is_32bit$32 ), .mul_op__is_signed(mul_pipe2_mul_op__is_signed), - .\mul_op__is_signed$12 (\mul_pipe2_mul_op__is_signed$29 ), + .\mul_op__is_signed$12 (\mul_pipe2_mul_op__is_signed$33 ), .mul_op__oe__oe(mul_pipe2_mul_op__oe__oe), - .\mul_op__oe__oe$8 (\mul_pipe2_mul_op__oe__oe$25 ), + .\mul_op__oe__oe$8 (\mul_pipe2_mul_op__oe__oe$29 ), .mul_op__oe__ok(mul_pipe2_mul_op__oe__ok), - .\mul_op__oe__ok$9 (\mul_pipe2_mul_op__oe__ok$26 ), + .\mul_op__oe__ok$9 (\mul_pipe2_mul_op__oe__ok$30 ), .mul_op__rc__ok(mul_pipe2_mul_op__rc__ok), - .\mul_op__rc__ok$7 (\mul_pipe2_mul_op__rc__ok$24 ), + .\mul_op__rc__ok$7 (\mul_pipe2_mul_op__rc__ok$28 ), .mul_op__rc__rc(mul_pipe2_mul_op__rc__rc), - .\mul_op__rc__rc$6 (\mul_pipe2_mul_op__rc__rc$23 ), + .\mul_op__rc__rc$6 (\mul_pipe2_mul_op__rc__rc$27 ), + .mul_op__sv_pred_dz(mul_pipe2_mul_op__sv_pred_dz), + .\mul_op__sv_pred_dz$15 (\mul_pipe2_mul_op__sv_pred_dz$36 ), + .mul_op__sv_pred_sz(mul_pipe2_mul_op__sv_pred_sz), + .\mul_op__sv_pred_sz$14 (\mul_pipe2_mul_op__sv_pred_sz$35 ), + .mul_op__sv_saturate(mul_pipe2_mul_op__sv_saturate), + .\mul_op__sv_saturate$16 (\mul_pipe2_mul_op__sv_saturate$37 ), .mul_op__write_cr0(mul_pipe2_mul_op__write_cr0), - .\mul_op__write_cr0$10 (\mul_pipe2_mul_op__write_cr0$27 ), + .\mul_op__write_cr0$10 (\mul_pipe2_mul_op__write_cr0$31 ), .muxid(mul_pipe2_muxid), - .\muxid$1 (\mul_pipe2_muxid$18 ), + .\muxid$1 (\mul_pipe2_muxid$22 ), .n_ready_i(mul_pipe2_n_ready_i), .n_valid_o(mul_pipe2_n_valid_o), .neg_res(mul_pipe2_neg_res), - .\neg_res$15 (\mul_pipe2_neg_res$32 ), + .\neg_res$19 (\mul_pipe2_neg_res$40 ), .neg_res32(mul_pipe2_neg_res32), - .\neg_res32$16 (\mul_pipe2_neg_res32$33 ), + .\neg_res32$20 (\mul_pipe2_neg_res32$41 ), .o(mul_pipe2_o), .p_ready_o(mul_pipe2_p_ready_o), .p_valid_i(mul_pipe2_p_valid_i), .ra(mul_pipe2_ra), .rb(mul_pipe2_rb), .xer_so(mul_pipe2_xer_so), - .\xer_so$14 (\mul_pipe2_xer_so$31 ) + .\xer_so$18 (\mul_pipe2_xer_so$39 ) ); mul_pipe3 mul_pipe3 ( .coresync_clk(coresync_clk), .coresync_rst(coresync_rst), .cr_a(mul_pipe3_cr_a), .cr_a_ok(mul_pipe3_cr_a_ok), + .mul_op__SV_Ptype(mul_pipe3_mul_op__SV_Ptype), + .\mul_op__SV_Ptype$17 (\mul_pipe3_mul_op__SV_Ptype$58 ), .mul_op__fn_unit(mul_pipe3_mul_op__fn_unit), - .\mul_op__fn_unit$3 (\mul_pipe3_mul_op__fn_unit$36 ), + .\mul_op__fn_unit$3 (\mul_pipe3_mul_op__fn_unit$44 ), .mul_op__imm_data__data(mul_pipe3_mul_op__imm_data__data), - .\mul_op__imm_data__data$4 (\mul_pipe3_mul_op__imm_data__data$37 ), + .\mul_op__imm_data__data$4 (\mul_pipe3_mul_op__imm_data__data$45 ), .mul_op__imm_data__ok(mul_pipe3_mul_op__imm_data__ok), - .\mul_op__imm_data__ok$5 (\mul_pipe3_mul_op__imm_data__ok$38 ), + .\mul_op__imm_data__ok$5 (\mul_pipe3_mul_op__imm_data__ok$46 ), .mul_op__insn(mul_pipe3_mul_op__insn), - .\mul_op__insn$13 (\mul_pipe3_mul_op__insn$46 ), + .\mul_op__insn$13 (\mul_pipe3_mul_op__insn$54 ), .mul_op__insn_type(mul_pipe3_mul_op__insn_type), - .\mul_op__insn_type$2 (\mul_pipe3_mul_op__insn_type$35 ), + .\mul_op__insn_type$2 (\mul_pipe3_mul_op__insn_type$43 ), .mul_op__is_32bit(mul_pipe3_mul_op__is_32bit), - .\mul_op__is_32bit$11 (\mul_pipe3_mul_op__is_32bit$44 ), + .\mul_op__is_32bit$11 (\mul_pipe3_mul_op__is_32bit$52 ), .mul_op__is_signed(mul_pipe3_mul_op__is_signed), - .\mul_op__is_signed$12 (\mul_pipe3_mul_op__is_signed$45 ), + .\mul_op__is_signed$12 (\mul_pipe3_mul_op__is_signed$53 ), .mul_op__oe__oe(mul_pipe3_mul_op__oe__oe), - .\mul_op__oe__oe$8 (\mul_pipe3_mul_op__oe__oe$41 ), + .\mul_op__oe__oe$8 (\mul_pipe3_mul_op__oe__oe$49 ), .mul_op__oe__ok(mul_pipe3_mul_op__oe__ok), - .\mul_op__oe__ok$9 (\mul_pipe3_mul_op__oe__ok$42 ), + .\mul_op__oe__ok$9 (\mul_pipe3_mul_op__oe__ok$50 ), .mul_op__rc__ok(mul_pipe3_mul_op__rc__ok), - .\mul_op__rc__ok$7 (\mul_pipe3_mul_op__rc__ok$40 ), + .\mul_op__rc__ok$7 (\mul_pipe3_mul_op__rc__ok$48 ), .mul_op__rc__rc(mul_pipe3_mul_op__rc__rc), - .\mul_op__rc__rc$6 (\mul_pipe3_mul_op__rc__rc$39 ), + .\mul_op__rc__rc$6 (\mul_pipe3_mul_op__rc__rc$47 ), + .mul_op__sv_pred_dz(mul_pipe3_mul_op__sv_pred_dz), + .\mul_op__sv_pred_dz$15 (\mul_pipe3_mul_op__sv_pred_dz$56 ), + .mul_op__sv_pred_sz(mul_pipe3_mul_op__sv_pred_sz), + .\mul_op__sv_pred_sz$14 (\mul_pipe3_mul_op__sv_pred_sz$55 ), + .mul_op__sv_saturate(mul_pipe3_mul_op__sv_saturate), + .\mul_op__sv_saturate$16 (\mul_pipe3_mul_op__sv_saturate$57 ), .mul_op__write_cr0(mul_pipe3_mul_op__write_cr0), - .\mul_op__write_cr0$10 (\mul_pipe3_mul_op__write_cr0$43 ), + .\mul_op__write_cr0$10 (\mul_pipe3_mul_op__write_cr0$51 ), .muxid(mul_pipe3_muxid), - .\muxid$1 (\mul_pipe3_muxid$34 ), + .\muxid$1 (\mul_pipe3_muxid$42 ), .n_ready_i(mul_pipe3_n_ready_i), .n_valid_o(mul_pipe3_n_valid_o), .neg_res(mul_pipe3_neg_res), .neg_res32(mul_pipe3_neg_res32), .o(mul_pipe3_o), - .\o$14 (\mul_pipe3_o$47 ), + .\o$18 (\mul_pipe3_o$59 ), .o_ok(mul_pipe3_o_ok), .p_ready_o(mul_pipe3_p_ready_o), .p_valid_i(mul_pipe3_p_valid_i), .xer_ov(mul_pipe3_xer_ov), .xer_ov_ok(mul_pipe3_xer_ov_ok), .xer_so(mul_pipe3_xer_so), - .\xer_so$15 (\mul_pipe3_xer_so$48 ), + .\xer_so$19 (\mul_pipe3_xer_so$60 ), .xer_so_ok(mul_pipe3_xer_so_ok) ); \n$92 n ( @@ -28619,27 +31576,27 @@ module alu_mul0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ .p_valid_i(p_valid_i) ); assign muxid = 2'h0; - assign { xer_so_ok, xer_so } = { mul_pipe3_xer_so_ok, \mul_pipe3_xer_so$48 }; + assign { xer_so_ok, xer_so } = { mul_pipe3_xer_so_ok, \mul_pipe3_xer_so$60 }; assign { xer_ov_ok, xer_ov } = { mul_pipe3_xer_ov_ok, mul_pipe3_xer_ov }; assign { cr_a_ok, cr_a } = { mul_pipe3_cr_a_ok, mul_pipe3_cr_a }; - assign { o_ok, o } = { mul_pipe3_o_ok, \mul_pipe3_o$47 }; - assign { \mul_op__insn$61 , \mul_op__is_signed$60 , \mul_op__is_32bit$59 , \mul_op__write_cr0$58 , \mul_op__oe__ok$57 , \mul_op__oe__oe$56 , \mul_op__rc__ok$55 , \mul_op__rc__rc$54 , \mul_op__imm_data__ok$53 , \mul_op__imm_data__data$52 , \mul_op__fn_unit$51 , \mul_op__insn_type$50 } = { \mul_pipe3_mul_op__insn$46 , \mul_pipe3_mul_op__is_signed$45 , \mul_pipe3_mul_op__is_32bit$44 , \mul_pipe3_mul_op__write_cr0$43 , \mul_pipe3_mul_op__oe__ok$42 , \mul_pipe3_mul_op__oe__oe$41 , \mul_pipe3_mul_op__rc__ok$40 , \mul_pipe3_mul_op__rc__rc$39 , \mul_pipe3_mul_op__imm_data__ok$38 , \mul_pipe3_mul_op__imm_data__data$37 , \mul_pipe3_mul_op__fn_unit$36 , \mul_pipe3_mul_op__insn_type$35 }; - assign \muxid$49 = \mul_pipe3_muxid$34 ; + assign { o_ok, o } = { mul_pipe3_o_ok, \mul_pipe3_o$59 }; + assign { \mul_op__SV_Ptype$77 , \mul_op__sv_saturate$76 , \mul_op__sv_pred_dz$75 , \mul_op__sv_pred_sz$74 , \mul_op__insn$73 , \mul_op__is_signed$72 , \mul_op__is_32bit$71 , \mul_op__write_cr0$70 , \mul_op__oe__ok$69 , \mul_op__oe__oe$68 , \mul_op__rc__ok$67 , \mul_op__rc__rc$66 , \mul_op__imm_data__ok$65 , \mul_op__imm_data__data$64 , \mul_op__fn_unit$63 , \mul_op__insn_type$62 } = { \mul_pipe3_mul_op__SV_Ptype$58 , \mul_pipe3_mul_op__sv_saturate$57 , \mul_pipe3_mul_op__sv_pred_dz$56 , \mul_pipe3_mul_op__sv_pred_sz$55 , \mul_pipe3_mul_op__insn$54 , \mul_pipe3_mul_op__is_signed$53 , \mul_pipe3_mul_op__is_32bit$52 , \mul_pipe3_mul_op__write_cr0$51 , \mul_pipe3_mul_op__oe__ok$50 , \mul_pipe3_mul_op__oe__oe$49 , \mul_pipe3_mul_op__rc__ok$48 , \mul_pipe3_mul_op__rc__rc$47 , \mul_pipe3_mul_op__imm_data__ok$46 , \mul_pipe3_mul_op__imm_data__data$45 , \mul_pipe3_mul_op__fn_unit$44 , \mul_pipe3_mul_op__insn_type$43 }; + assign \muxid$61 = \mul_pipe3_muxid$42 ; assign mul_pipe3_n_ready_i = n_ready_i; assign n_valid_o = mul_pipe3_n_valid_o; - assign \mul_pipe1_xer_so$17 = \xer_so$1 ; - assign \mul_pipe1_rb$16 = rb; - assign \mul_pipe1_ra$15 = ra; - assign { \mul_pipe1_mul_op__insn$14 , \mul_pipe1_mul_op__is_signed$13 , \mul_pipe1_mul_op__is_32bit$12 , \mul_pipe1_mul_op__write_cr0$11 , \mul_pipe1_mul_op__oe__ok$10 , \mul_pipe1_mul_op__oe__oe$9 , \mul_pipe1_mul_op__rc__ok$8 , \mul_pipe1_mul_op__rc__rc$7 , \mul_pipe1_mul_op__imm_data__ok$6 , \mul_pipe1_mul_op__imm_data__data$5 , \mul_pipe1_mul_op__fn_unit$4 , \mul_pipe1_mul_op__insn_type$3 } = { mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type }; + assign \mul_pipe1_xer_so$21 = \xer_so$1 ; + assign \mul_pipe1_rb$20 = rb; + assign \mul_pipe1_ra$19 = ra; + assign { \mul_pipe1_mul_op__SV_Ptype$18 , \mul_pipe1_mul_op__sv_saturate$17 , \mul_pipe1_mul_op__sv_pred_dz$16 , \mul_pipe1_mul_op__sv_pred_sz$15 , \mul_pipe1_mul_op__insn$14 , \mul_pipe1_mul_op__is_signed$13 , \mul_pipe1_mul_op__is_32bit$12 , \mul_pipe1_mul_op__write_cr0$11 , \mul_pipe1_mul_op__oe__ok$10 , \mul_pipe1_mul_op__oe__oe$9 , \mul_pipe1_mul_op__rc__ok$8 , \mul_pipe1_mul_op__rc__rc$7 , \mul_pipe1_mul_op__imm_data__ok$6 , \mul_pipe1_mul_op__imm_data__data$5 , \mul_pipe1_mul_op__fn_unit$4 , \mul_pipe1_mul_op__insn_type$3 } = { mul_op__SV_Ptype, mul_op__sv_saturate, mul_op__sv_pred_dz, mul_op__sv_pred_sz, mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type }; assign \mul_pipe1_muxid$2 = 2'h0; assign p_ready_o = mul_pipe1_p_ready_o; assign mul_pipe1_p_valid_i = p_valid_i; - assign mul_pipe3_neg_res32 = \mul_pipe2_neg_res32$33 ; - assign mul_pipe3_neg_res = \mul_pipe2_neg_res$32 ; - assign mul_pipe3_xer_so = \mul_pipe2_xer_so$31 ; + assign mul_pipe3_neg_res32 = \mul_pipe2_neg_res32$41 ; + assign mul_pipe3_neg_res = \mul_pipe2_neg_res$40 ; + assign mul_pipe3_xer_so = \mul_pipe2_xer_so$39 ; assign mul_pipe3_o = mul_pipe2_o; - assign { mul_pipe3_mul_op__insn, mul_pipe3_mul_op__is_signed, mul_pipe3_mul_op__is_32bit, mul_pipe3_mul_op__write_cr0, mul_pipe3_mul_op__oe__ok, mul_pipe3_mul_op__oe__oe, mul_pipe3_mul_op__rc__ok, mul_pipe3_mul_op__rc__rc, mul_pipe3_mul_op__imm_data__ok, mul_pipe3_mul_op__imm_data__data, mul_pipe3_mul_op__fn_unit, mul_pipe3_mul_op__insn_type } = { \mul_pipe2_mul_op__insn$30 , \mul_pipe2_mul_op__is_signed$29 , \mul_pipe2_mul_op__is_32bit$28 , \mul_pipe2_mul_op__write_cr0$27 , \mul_pipe2_mul_op__oe__ok$26 , \mul_pipe2_mul_op__oe__oe$25 , \mul_pipe2_mul_op__rc__ok$24 , \mul_pipe2_mul_op__rc__rc$23 , \mul_pipe2_mul_op__imm_data__ok$22 , \mul_pipe2_mul_op__imm_data__data$21 , \mul_pipe2_mul_op__fn_unit$20 , \mul_pipe2_mul_op__insn_type$19 }; - assign mul_pipe3_muxid = \mul_pipe2_muxid$18 ; + assign { mul_pipe3_mul_op__SV_Ptype, mul_pipe3_mul_op__sv_saturate, mul_pipe3_mul_op__sv_pred_dz, mul_pipe3_mul_op__sv_pred_sz, mul_pipe3_mul_op__insn, mul_pipe3_mul_op__is_signed, mul_pipe3_mul_op__is_32bit, mul_pipe3_mul_op__write_cr0, mul_pipe3_mul_op__oe__ok, mul_pipe3_mul_op__oe__oe, mul_pipe3_mul_op__rc__ok, mul_pipe3_mul_op__rc__rc, mul_pipe3_mul_op__imm_data__ok, mul_pipe3_mul_op__imm_data__data, mul_pipe3_mul_op__fn_unit, mul_pipe3_mul_op__insn_type } = { \mul_pipe2_mul_op__SV_Ptype$38 , \mul_pipe2_mul_op__sv_saturate$37 , \mul_pipe2_mul_op__sv_pred_dz$36 , \mul_pipe2_mul_op__sv_pred_sz$35 , \mul_pipe2_mul_op__insn$34 , \mul_pipe2_mul_op__is_signed$33 , \mul_pipe2_mul_op__is_32bit$32 , \mul_pipe2_mul_op__write_cr0$31 , \mul_pipe2_mul_op__oe__ok$30 , \mul_pipe2_mul_op__oe__oe$29 , \mul_pipe2_mul_op__rc__ok$28 , \mul_pipe2_mul_op__rc__rc$27 , \mul_pipe2_mul_op__imm_data__ok$26 , \mul_pipe2_mul_op__imm_data__data$25 , \mul_pipe2_mul_op__fn_unit$24 , \mul_pipe2_mul_op__insn_type$23 }; + assign mul_pipe3_muxid = \mul_pipe2_muxid$22 ; assign mul_pipe2_n_ready_i = mul_pipe3_p_ready_o; assign mul_pipe3_p_valid_i = mul_pipe2_n_valid_o; assign mul_pipe2_neg_res32 = mul_pipe1_neg_res32; @@ -28647,7 +31604,7 @@ module alu_mul0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ assign mul_pipe2_xer_so = mul_pipe1_xer_so; assign mul_pipe2_rb = mul_pipe1_rb; assign mul_pipe2_ra = mul_pipe1_ra; - assign { mul_pipe2_mul_op__insn, mul_pipe2_mul_op__is_signed, mul_pipe2_mul_op__is_32bit, mul_pipe2_mul_op__write_cr0, mul_pipe2_mul_op__oe__ok, mul_pipe2_mul_op__oe__oe, mul_pipe2_mul_op__rc__ok, mul_pipe2_mul_op__rc__rc, mul_pipe2_mul_op__imm_data__ok, mul_pipe2_mul_op__imm_data__data, mul_pipe2_mul_op__fn_unit, mul_pipe2_mul_op__insn_type } = { mul_pipe1_mul_op__insn, mul_pipe1_mul_op__is_signed, mul_pipe1_mul_op__is_32bit, mul_pipe1_mul_op__write_cr0, mul_pipe1_mul_op__oe__ok, mul_pipe1_mul_op__oe__oe, mul_pipe1_mul_op__rc__ok, mul_pipe1_mul_op__rc__rc, mul_pipe1_mul_op__imm_data__ok, mul_pipe1_mul_op__imm_data__data, mul_pipe1_mul_op__fn_unit, mul_pipe1_mul_op__insn_type }; + assign { mul_pipe2_mul_op__SV_Ptype, mul_pipe2_mul_op__sv_saturate, mul_pipe2_mul_op__sv_pred_dz, mul_pipe2_mul_op__sv_pred_sz, mul_pipe2_mul_op__insn, mul_pipe2_mul_op__is_signed, mul_pipe2_mul_op__is_32bit, mul_pipe2_mul_op__write_cr0, mul_pipe2_mul_op__oe__ok, mul_pipe2_mul_op__oe__oe, mul_pipe2_mul_op__rc__ok, mul_pipe2_mul_op__rc__rc, mul_pipe2_mul_op__imm_data__ok, mul_pipe2_mul_op__imm_data__data, mul_pipe2_mul_op__fn_unit, mul_pipe2_mul_op__insn_type } = { mul_pipe1_mul_op__SV_Ptype, mul_pipe1_mul_op__sv_saturate, mul_pipe1_mul_op__sv_pred_dz, mul_pipe1_mul_op__sv_pred_sz, mul_pipe1_mul_op__insn, mul_pipe1_mul_op__is_signed, mul_pipe1_mul_op__is_32bit, mul_pipe1_mul_op__write_cr0, mul_pipe1_mul_op__oe__ok, mul_pipe1_mul_op__oe__oe, mul_pipe1_mul_op__rc__ok, mul_pipe1_mul_op__rc__rc, mul_pipe1_mul_op__imm_data__ok, mul_pipe1_mul_op__imm_data__data, mul_pipe1_mul_op__fn_unit, mul_pipe1_mul_op__insn_type }; assign mul_pipe2_muxid = mul_pipe1_muxid; assign mul_pipe1_n_ready_i = mul_pipe2_p_ready_o; assign mul_pipe2_p_valid_i = mul_pipe1_n_valid_o; @@ -28655,34 +31612,34 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0" *) (* generator = "nMigen" *) -module alu_shift_rot0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, n_valid_o, n_ready_i, sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, o, cr_a, xer_ca, ra, rb, rc, xer_so, \xer_ca$1 , p_valid_i, p_ready_o, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) +module alu_shift_rot0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, n_valid_o, n_ready_i, sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, sr_op__sv_pred_sz, sr_op__sv_pred_dz, sr_op__sv_saturate, sr_op__SV_Ptype, o, cr_a, xer_ca, ra, rb, rc, xer_so, \xer_ca$1 , p_valid_i, p_ready_o, coresync_clk); + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_a_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \muxid$46 ; + wire [1:0] \muxid$54 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) input p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [3:0] pipe1_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe1_cr_a_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] pipe1_muxid; @@ -28692,81 +31649,95 @@ module alu_shift_rot0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, n_valid_o, n_ready wire pipe1_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire pipe1_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] pipe1_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe1_o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire pipe1_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) wire pipe1_p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] pipe1_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] pipe1_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] pipe1_rc; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] pipe1_sr_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \pipe1_sr_op__SV_Ptype$23 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] pipe1_sr_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] pipe1_sr_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \pipe1_sr_op__fn_unit$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \pipe1_sr_op__fn_unit$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] pipe1_sr_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] \pipe1_sr_op__imm_data__data$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe1_sr_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe1_sr_op__imm_data__ok$6 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [1:0] pipe1_sr_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [1:0] \pipe1_sr_op__input_carry$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe1_sr_op__input_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe1_sr_op__input_cr$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] pipe1_sr_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] \pipe1_sr_op__insn$19 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -28843,7 +31814,9 @@ module alu_shift_rot0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, n_valid_o, n_ready (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] pipe1_sr_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -28920,150 +31893,186 @@ module alu_shift_rot0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, n_valid_o, n_ready (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] \pipe1_sr_op__insn_type$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe1_sr_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe1_sr_op__invert_in$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe1_sr_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe1_sr_op__is_32bit$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe1_sr_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe1_sr_op__is_signed$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe1_sr_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe1_sr_op__oe__oe$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe1_sr_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe1_sr_op__oe__ok$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe1_sr_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe1_sr_op__output_carry$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe1_sr_op__output_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe1_sr_op__output_cr$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe1_sr_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe1_sr_op__rc__ok$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe1_sr_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe1_sr_op__rc__rc$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire pipe1_sr_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe1_sr_op__sv_pred_dz$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire pipe1_sr_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe1_sr_op__sv_pred_sz$20 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] pipe1_sr_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \pipe1_sr_op__sv_saturate$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe1_sr_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe1_sr_op__write_cr0$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [1:0] pipe1_xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [1:0] \pipe1_xer_ca$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [1:0] \pipe1_xer_ca$25 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe1_xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe1_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire \pipe1_xer_so$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire \pipe1_xer_so$24 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe1_xer_so_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [3:0] pipe2_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [3:0] \pipe2_cr_a$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [3:0] \pipe2_cr_a$50 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe2_cr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \pipe2_cr_a_ok$43 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \pipe2_cr_a_ok$51 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] pipe2_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \pipe2_muxid$22 ; + wire [1:0] \pipe2_muxid$26 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) wire pipe2_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire pipe2_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] pipe2_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \pipe2_o$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \pipe2_o$48 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe2_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \pipe2_o_ok$41 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \pipe2_o_ok$49 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire pipe2_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) wire pipe2_p_valid_i; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] pipe2_sr_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \pipe2_sr_op__SV_Ptype$47 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] pipe2_sr_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] pipe2_sr_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \pipe2_sr_op__fn_unit$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \pipe2_sr_op__fn_unit$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] pipe2_sr_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \pipe2_sr_op__imm_data__data$25 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \pipe2_sr_op__imm_data__data$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe2_sr_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe2_sr_op__imm_data__ok$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe2_sr_op__imm_data__ok$30 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [1:0] pipe2_sr_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [1:0] \pipe2_sr_op__input_carry$33 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \pipe2_sr_op__input_carry$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe2_sr_op__input_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe2_sr_op__input_cr$35 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe2_sr_op__input_cr$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] pipe2_sr_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \pipe2_sr_op__insn$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \pipe2_sr_op__insn$43 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -29139,7 +32148,9 @@ module alu_shift_rot0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, n_valid_o, n_ready (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] pipe2_sr_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -29216,128 +32227,164 @@ module alu_shift_rot0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, n_valid_o, n_ready (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \pipe2_sr_op__insn_type$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \pipe2_sr_op__insn_type$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe2_sr_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe2_sr_op__invert_in$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe2_sr_op__invert_in$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe2_sr_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe2_sr_op__is_32bit$37 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe2_sr_op__is_32bit$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe2_sr_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe2_sr_op__is_signed$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe2_sr_op__is_signed$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe2_sr_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe2_sr_op__oe__oe$29 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe2_sr_op__oe__oe$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe2_sr_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe2_sr_op__oe__ok$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe2_sr_op__oe__ok$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe2_sr_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe2_sr_op__output_carry$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe2_sr_op__output_carry$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe2_sr_op__output_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe2_sr_op__output_cr$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe2_sr_op__output_cr$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe2_sr_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe2_sr_op__rc__ok$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe2_sr_op__rc__ok$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe2_sr_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe2_sr_op__rc__rc$27 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe2_sr_op__rc__rc$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire pipe2_sr_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe2_sr_op__sv_pred_dz$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire pipe2_sr_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe2_sr_op__sv_pred_sz$44 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] pipe2_sr_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \pipe2_sr_op__sv_saturate$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe2_sr_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe2_sr_op__write_cr0$31 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe2_sr_op__write_cr0$35 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [1:0] pipe2_xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [1:0] \pipe2_xer_ca$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [1:0] \pipe2_xer_ca$52 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe2_xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \pipe2_xer_ca_ok$45 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \pipe2_xer_ca_ok$53 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe2_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe2_xer_so_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] rc; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] sr_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \sr_op__SV_Ptype$75 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] sr_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] sr_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \sr_op__fn_unit$48 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \sr_op__fn_unit$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] sr_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \sr_op__imm_data__data$49 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \sr_op__imm_data__data$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__imm_data__ok$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__imm_data__ok$58 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] sr_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [1:0] \sr_op__input_carry$57 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \sr_op__input_carry$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__input_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__input_cr$59 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__input_cr$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] sr_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \sr_op__insn$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \sr_op__insn$71 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -29413,7 +32460,9 @@ module alu_shift_rot0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, n_valid_o, n_ready (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] sr_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -29490,55 +32539,77 @@ module alu_shift_rot0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, n_valid_o, n_ready (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \sr_op__insn_type$47 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \sr_op__insn_type$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__invert_in$56 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__invert_in$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__is_32bit$61 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__is_32bit$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__is_signed$62 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__is_signed$70 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__oe__oe$53 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__oe__oe$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__oe__ok$54 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__oe__ok$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__output_carry$58 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__output_carry$66 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__output_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__output_cr$60 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__output_cr$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__rc__ok$52 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__rc__ok$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__rc__rc$51 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__rc__rc$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input sr_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__sv_pred_dz$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input sr_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__sv_pred_sz$72 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] sr_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \sr_op__sv_saturate$74 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__write_cr0$55 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__write_cr0$63 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [1:0] xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [1:0] \xer_ca$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input xer_so; \n$109 n ( .n_ready_i(n_ready_i), @@ -29564,6 +32635,8 @@ module alu_shift_rot0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, n_valid_o, n_ready .ra(pipe1_ra), .rb(pipe1_rb), .rc(pipe1_rc), + .sr_op__SV_Ptype(pipe1_sr_op__SV_Ptype), + .\sr_op__SV_Ptype$22 (\pipe1_sr_op__SV_Ptype$23 ), .sr_op__fn_unit(pipe1_sr_op__fn_unit), .\sr_op__fn_unit$3 (\pipe1_sr_op__fn_unit$4 ), .sr_op__imm_data__data(pipe1_sr_op__imm_data__data), @@ -29596,87 +32669,101 @@ module alu_shift_rot0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, n_valid_o, n_ready .\sr_op__rc__ok$7 (\pipe1_sr_op__rc__ok$8 ), .sr_op__rc__rc(pipe1_sr_op__rc__rc), .\sr_op__rc__rc$6 (\pipe1_sr_op__rc__rc$7 ), + .sr_op__sv_pred_dz(pipe1_sr_op__sv_pred_dz), + .\sr_op__sv_pred_dz$20 (\pipe1_sr_op__sv_pred_dz$21 ), + .sr_op__sv_pred_sz(pipe1_sr_op__sv_pred_sz), + .\sr_op__sv_pred_sz$19 (\pipe1_sr_op__sv_pred_sz$20 ), + .sr_op__sv_saturate(pipe1_sr_op__sv_saturate), + .\sr_op__sv_saturate$21 (\pipe1_sr_op__sv_saturate$22 ), .sr_op__write_cr0(pipe1_sr_op__write_cr0), .\sr_op__write_cr0$10 (\pipe1_sr_op__write_cr0$11 ), .xer_ca(pipe1_xer_ca), - .\xer_ca$20 (\pipe1_xer_ca$21 ), + .\xer_ca$24 (\pipe1_xer_ca$25 ), .xer_ca_ok(pipe1_xer_ca_ok), .xer_so(pipe1_xer_so), - .\xer_so$19 (\pipe1_xer_so$20 ), + .\xer_so$23 (\pipe1_xer_so$24 ), .xer_so_ok(pipe1_xer_so_ok) ); \pipe2$115 pipe2 ( .coresync_clk(coresync_clk), .coresync_rst(coresync_rst), .cr_a(pipe2_cr_a), - .\cr_a$21 (\pipe2_cr_a$42 ), + .\cr_a$25 (\pipe2_cr_a$50 ), .cr_a_ok(pipe2_cr_a_ok), - .\cr_a_ok$22 (\pipe2_cr_a_ok$43 ), + .\cr_a_ok$26 (\pipe2_cr_a_ok$51 ), .muxid(pipe2_muxid), - .\muxid$1 (\pipe2_muxid$22 ), + .\muxid$1 (\pipe2_muxid$26 ), .n_ready_i(pipe2_n_ready_i), .n_valid_o(pipe2_n_valid_o), .o(pipe2_o), - .\o$19 (\pipe2_o$40 ), + .\o$23 (\pipe2_o$48 ), .o_ok(pipe2_o_ok), - .\o_ok$20 (\pipe2_o_ok$41 ), + .\o_ok$24 (\pipe2_o_ok$49 ), .p_ready_o(pipe2_p_ready_o), .p_valid_i(pipe2_p_valid_i), + .sr_op__SV_Ptype(pipe2_sr_op__SV_Ptype), + .\sr_op__SV_Ptype$22 (\pipe2_sr_op__SV_Ptype$47 ), .sr_op__fn_unit(pipe2_sr_op__fn_unit), - .\sr_op__fn_unit$3 (\pipe2_sr_op__fn_unit$24 ), + .\sr_op__fn_unit$3 (\pipe2_sr_op__fn_unit$28 ), .sr_op__imm_data__data(pipe2_sr_op__imm_data__data), - .\sr_op__imm_data__data$4 (\pipe2_sr_op__imm_data__data$25 ), + .\sr_op__imm_data__data$4 (\pipe2_sr_op__imm_data__data$29 ), .sr_op__imm_data__ok(pipe2_sr_op__imm_data__ok), - .\sr_op__imm_data__ok$5 (\pipe2_sr_op__imm_data__ok$26 ), + .\sr_op__imm_data__ok$5 (\pipe2_sr_op__imm_data__ok$30 ), .sr_op__input_carry(pipe2_sr_op__input_carry), - .\sr_op__input_carry$12 (\pipe2_sr_op__input_carry$33 ), + .\sr_op__input_carry$12 (\pipe2_sr_op__input_carry$37 ), .sr_op__input_cr(pipe2_sr_op__input_cr), - .\sr_op__input_cr$14 (\pipe2_sr_op__input_cr$35 ), + .\sr_op__input_cr$14 (\pipe2_sr_op__input_cr$39 ), .sr_op__insn(pipe2_sr_op__insn), - .\sr_op__insn$18 (\pipe2_sr_op__insn$39 ), + .\sr_op__insn$18 (\pipe2_sr_op__insn$43 ), .sr_op__insn_type(pipe2_sr_op__insn_type), - .\sr_op__insn_type$2 (\pipe2_sr_op__insn_type$23 ), + .\sr_op__insn_type$2 (\pipe2_sr_op__insn_type$27 ), .sr_op__invert_in(pipe2_sr_op__invert_in), - .\sr_op__invert_in$11 (\pipe2_sr_op__invert_in$32 ), + .\sr_op__invert_in$11 (\pipe2_sr_op__invert_in$36 ), .sr_op__is_32bit(pipe2_sr_op__is_32bit), - .\sr_op__is_32bit$16 (\pipe2_sr_op__is_32bit$37 ), + .\sr_op__is_32bit$16 (\pipe2_sr_op__is_32bit$41 ), .sr_op__is_signed(pipe2_sr_op__is_signed), - .\sr_op__is_signed$17 (\pipe2_sr_op__is_signed$38 ), + .\sr_op__is_signed$17 (\pipe2_sr_op__is_signed$42 ), .sr_op__oe__oe(pipe2_sr_op__oe__oe), - .\sr_op__oe__oe$8 (\pipe2_sr_op__oe__oe$29 ), + .\sr_op__oe__oe$8 (\pipe2_sr_op__oe__oe$33 ), .sr_op__oe__ok(pipe2_sr_op__oe__ok), - .\sr_op__oe__ok$9 (\pipe2_sr_op__oe__ok$30 ), + .\sr_op__oe__ok$9 (\pipe2_sr_op__oe__ok$34 ), .sr_op__output_carry(pipe2_sr_op__output_carry), - .\sr_op__output_carry$13 (\pipe2_sr_op__output_carry$34 ), + .\sr_op__output_carry$13 (\pipe2_sr_op__output_carry$38 ), .sr_op__output_cr(pipe2_sr_op__output_cr), - .\sr_op__output_cr$15 (\pipe2_sr_op__output_cr$36 ), + .\sr_op__output_cr$15 (\pipe2_sr_op__output_cr$40 ), .sr_op__rc__ok(pipe2_sr_op__rc__ok), - .\sr_op__rc__ok$7 (\pipe2_sr_op__rc__ok$28 ), + .\sr_op__rc__ok$7 (\pipe2_sr_op__rc__ok$32 ), .sr_op__rc__rc(pipe2_sr_op__rc__rc), - .\sr_op__rc__rc$6 (\pipe2_sr_op__rc__rc$27 ), + .\sr_op__rc__rc$6 (\pipe2_sr_op__rc__rc$31 ), + .sr_op__sv_pred_dz(pipe2_sr_op__sv_pred_dz), + .\sr_op__sv_pred_dz$20 (\pipe2_sr_op__sv_pred_dz$45 ), + .sr_op__sv_pred_sz(pipe2_sr_op__sv_pred_sz), + .\sr_op__sv_pred_sz$19 (\pipe2_sr_op__sv_pred_sz$44 ), + .sr_op__sv_saturate(pipe2_sr_op__sv_saturate), + .\sr_op__sv_saturate$21 (\pipe2_sr_op__sv_saturate$46 ), .sr_op__write_cr0(pipe2_sr_op__write_cr0), - .\sr_op__write_cr0$10 (\pipe2_sr_op__write_cr0$31 ), + .\sr_op__write_cr0$10 (\pipe2_sr_op__write_cr0$35 ), .xer_ca(pipe2_xer_ca), - .\xer_ca$23 (\pipe2_xer_ca$44 ), + .\xer_ca$27 (\pipe2_xer_ca$52 ), .xer_ca_ok(pipe2_xer_ca_ok), - .\xer_ca_ok$24 (\pipe2_xer_ca_ok$45 ), + .\xer_ca_ok$28 (\pipe2_xer_ca_ok$53 ), .xer_so(pipe2_xer_so), .xer_so_ok(pipe2_xer_so_ok) ); assign muxid = 2'h0; - assign { xer_ca_ok, xer_ca } = { \pipe2_xer_ca_ok$45 , \pipe2_xer_ca$44 }; - assign { cr_a_ok, cr_a } = { \pipe2_cr_a_ok$43 , \pipe2_cr_a$42 }; - assign { o_ok, o } = { \pipe2_o_ok$41 , \pipe2_o$40 }; - assign { \sr_op__insn$63 , \sr_op__is_signed$62 , \sr_op__is_32bit$61 , \sr_op__output_cr$60 , \sr_op__input_cr$59 , \sr_op__output_carry$58 , \sr_op__input_carry$57 , \sr_op__invert_in$56 , \sr_op__write_cr0$55 , \sr_op__oe__ok$54 , \sr_op__oe__oe$53 , \sr_op__rc__ok$52 , \sr_op__rc__rc$51 , \sr_op__imm_data__ok$50 , \sr_op__imm_data__data$49 , \sr_op__fn_unit$48 , \sr_op__insn_type$47 } = { \pipe2_sr_op__insn$39 , \pipe2_sr_op__is_signed$38 , \pipe2_sr_op__is_32bit$37 , \pipe2_sr_op__output_cr$36 , \pipe2_sr_op__input_cr$35 , \pipe2_sr_op__output_carry$34 , \pipe2_sr_op__input_carry$33 , \pipe2_sr_op__invert_in$32 , \pipe2_sr_op__write_cr0$31 , \pipe2_sr_op__oe__ok$30 , \pipe2_sr_op__oe__oe$29 , \pipe2_sr_op__rc__ok$28 , \pipe2_sr_op__rc__rc$27 , \pipe2_sr_op__imm_data__ok$26 , \pipe2_sr_op__imm_data__data$25 , \pipe2_sr_op__fn_unit$24 , \pipe2_sr_op__insn_type$23 }; - assign \muxid$46 = \pipe2_muxid$22 ; + assign { xer_ca_ok, xer_ca } = { \pipe2_xer_ca_ok$53 , \pipe2_xer_ca$52 }; + assign { cr_a_ok, cr_a } = { \pipe2_cr_a_ok$51 , \pipe2_cr_a$50 }; + assign { o_ok, o } = { \pipe2_o_ok$49 , \pipe2_o$48 }; + assign { \sr_op__SV_Ptype$75 , \sr_op__sv_saturate$74 , \sr_op__sv_pred_dz$73 , \sr_op__sv_pred_sz$72 , \sr_op__insn$71 , \sr_op__is_signed$70 , \sr_op__is_32bit$69 , \sr_op__output_cr$68 , \sr_op__input_cr$67 , \sr_op__output_carry$66 , \sr_op__input_carry$65 , \sr_op__invert_in$64 , \sr_op__write_cr0$63 , \sr_op__oe__ok$62 , \sr_op__oe__oe$61 , \sr_op__rc__ok$60 , \sr_op__rc__rc$59 , \sr_op__imm_data__ok$58 , \sr_op__imm_data__data$57 , \sr_op__fn_unit$56 , \sr_op__insn_type$55 } = { \pipe2_sr_op__SV_Ptype$47 , \pipe2_sr_op__sv_saturate$46 , \pipe2_sr_op__sv_pred_dz$45 , \pipe2_sr_op__sv_pred_sz$44 , \pipe2_sr_op__insn$43 , \pipe2_sr_op__is_signed$42 , \pipe2_sr_op__is_32bit$41 , \pipe2_sr_op__output_cr$40 , \pipe2_sr_op__input_cr$39 , \pipe2_sr_op__output_carry$38 , \pipe2_sr_op__input_carry$37 , \pipe2_sr_op__invert_in$36 , \pipe2_sr_op__write_cr0$35 , \pipe2_sr_op__oe__ok$34 , \pipe2_sr_op__oe__oe$33 , \pipe2_sr_op__rc__ok$32 , \pipe2_sr_op__rc__rc$31 , \pipe2_sr_op__imm_data__ok$30 , \pipe2_sr_op__imm_data__data$29 , \pipe2_sr_op__fn_unit$28 , \pipe2_sr_op__insn_type$27 }; + assign \muxid$54 = \pipe2_muxid$26 ; assign pipe2_n_ready_i = n_ready_i; assign n_valid_o = pipe2_n_valid_o; - assign \pipe1_xer_ca$21 = \xer_ca$1 ; - assign \pipe1_xer_so$20 = xer_so; + assign \pipe1_xer_ca$25 = \xer_ca$1 ; + assign \pipe1_xer_so$24 = xer_so; assign pipe1_rc = rc; assign pipe1_rb = rb; assign pipe1_ra = ra; - assign { \pipe1_sr_op__insn$19 , \pipe1_sr_op__is_signed$18 , \pipe1_sr_op__is_32bit$17 , \pipe1_sr_op__output_cr$16 , \pipe1_sr_op__input_cr$15 , \pipe1_sr_op__output_carry$14 , \pipe1_sr_op__input_carry$13 , \pipe1_sr_op__invert_in$12 , \pipe1_sr_op__write_cr0$11 , \pipe1_sr_op__oe__ok$10 , \pipe1_sr_op__oe__oe$9 , \pipe1_sr_op__rc__ok$8 , \pipe1_sr_op__rc__rc$7 , \pipe1_sr_op__imm_data__ok$6 , \pipe1_sr_op__imm_data__data$5 , \pipe1_sr_op__fn_unit$4 , \pipe1_sr_op__insn_type$3 } = { sr_op__insn, sr_op__is_signed, sr_op__is_32bit, sr_op__output_cr, sr_op__input_cr, sr_op__output_carry, sr_op__input_carry, sr_op__invert_in, sr_op__write_cr0, sr_op__oe__ok, sr_op__oe__oe, sr_op__rc__ok, sr_op__rc__rc, sr_op__imm_data__ok, sr_op__imm_data__data, sr_op__fn_unit, sr_op__insn_type }; + assign { \pipe1_sr_op__SV_Ptype$23 , \pipe1_sr_op__sv_saturate$22 , \pipe1_sr_op__sv_pred_dz$21 , \pipe1_sr_op__sv_pred_sz$20 , \pipe1_sr_op__insn$19 , \pipe1_sr_op__is_signed$18 , \pipe1_sr_op__is_32bit$17 , \pipe1_sr_op__output_cr$16 , \pipe1_sr_op__input_cr$15 , \pipe1_sr_op__output_carry$14 , \pipe1_sr_op__input_carry$13 , \pipe1_sr_op__invert_in$12 , \pipe1_sr_op__write_cr0$11 , \pipe1_sr_op__oe__ok$10 , \pipe1_sr_op__oe__oe$9 , \pipe1_sr_op__rc__ok$8 , \pipe1_sr_op__rc__rc$7 , \pipe1_sr_op__imm_data__ok$6 , \pipe1_sr_op__imm_data__data$5 , \pipe1_sr_op__fn_unit$4 , \pipe1_sr_op__insn_type$3 } = { sr_op__SV_Ptype, sr_op__sv_saturate, sr_op__sv_pred_dz, sr_op__sv_pred_sz, sr_op__insn, sr_op__is_signed, sr_op__is_32bit, sr_op__output_cr, sr_op__input_cr, sr_op__output_carry, sr_op__input_carry, sr_op__invert_in, sr_op__write_cr0, sr_op__oe__ok, sr_op__oe__oe, sr_op__rc__ok, sr_op__rc__rc, sr_op__imm_data__ok, sr_op__imm_data__data, sr_op__fn_unit, sr_op__insn_type }; assign \pipe1_muxid$2 = 2'h0; assign p_ready_o = pipe1_p_ready_o; assign pipe1_p_valid_i = p_valid_i; @@ -29684,7 +32771,7 @@ module alu_shift_rot0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, n_valid_o, n_ready assign { pipe2_xer_so_ok, pipe2_xer_so } = { pipe1_xer_so_ok, pipe1_xer_so }; assign { pipe2_cr_a_ok, pipe2_cr_a } = { pipe1_cr_a_ok, pipe1_cr_a }; assign { pipe2_o_ok, pipe2_o } = { pipe1_o_ok, pipe1_o }; - assign { pipe2_sr_op__insn, pipe2_sr_op__is_signed, pipe2_sr_op__is_32bit, pipe2_sr_op__output_cr, pipe2_sr_op__input_cr, pipe2_sr_op__output_carry, pipe2_sr_op__input_carry, pipe2_sr_op__invert_in, pipe2_sr_op__write_cr0, pipe2_sr_op__oe__ok, pipe2_sr_op__oe__oe, pipe2_sr_op__rc__ok, pipe2_sr_op__rc__rc, pipe2_sr_op__imm_data__ok, pipe2_sr_op__imm_data__data, pipe2_sr_op__fn_unit, pipe2_sr_op__insn_type } = { pipe1_sr_op__insn, pipe1_sr_op__is_signed, pipe1_sr_op__is_32bit, pipe1_sr_op__output_cr, pipe1_sr_op__input_cr, pipe1_sr_op__output_carry, pipe1_sr_op__input_carry, pipe1_sr_op__invert_in, pipe1_sr_op__write_cr0, pipe1_sr_op__oe__ok, pipe1_sr_op__oe__oe, pipe1_sr_op__rc__ok, pipe1_sr_op__rc__rc, pipe1_sr_op__imm_data__ok, pipe1_sr_op__imm_data__data, pipe1_sr_op__fn_unit, pipe1_sr_op__insn_type }; + assign { pipe2_sr_op__SV_Ptype, pipe2_sr_op__sv_saturate, pipe2_sr_op__sv_pred_dz, pipe2_sr_op__sv_pred_sz, pipe2_sr_op__insn, pipe2_sr_op__is_signed, pipe2_sr_op__is_32bit, pipe2_sr_op__output_cr, pipe2_sr_op__input_cr, pipe2_sr_op__output_carry, pipe2_sr_op__input_carry, pipe2_sr_op__invert_in, pipe2_sr_op__write_cr0, pipe2_sr_op__oe__ok, pipe2_sr_op__oe__oe, pipe2_sr_op__rc__ok, pipe2_sr_op__rc__rc, pipe2_sr_op__imm_data__ok, pipe2_sr_op__imm_data__data, pipe2_sr_op__fn_unit, pipe2_sr_op__insn_type } = { pipe1_sr_op__SV_Ptype, pipe1_sr_op__sv_saturate, pipe1_sr_op__sv_pred_dz, pipe1_sr_op__sv_pred_sz, pipe1_sr_op__insn, pipe1_sr_op__is_signed, pipe1_sr_op__is_32bit, pipe1_sr_op__output_cr, pipe1_sr_op__input_cr, pipe1_sr_op__output_carry, pipe1_sr_op__input_carry, pipe1_sr_op__invert_in, pipe1_sr_op__write_cr0, pipe1_sr_op__oe__ok, pipe1_sr_op__oe__oe, pipe1_sr_op__rc__ok, pipe1_sr_op__rc__rc, pipe1_sr_op__imm_data__ok, pipe1_sr_op__imm_data__data, pipe1_sr_op__fn_unit, pipe1_sr_op__insn_type }; assign pipe2_muxid = pipe1_muxid; assign pipe1_n_ready_i = pipe2_p_ready_o; assign pipe2_p_valid_i = pipe1_n_valid_o; @@ -29692,38 +32779,38 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.spr0.alu_spr0" *) (* generator = "nMigen" *) -module alu_spr0(coresync_rst, o_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, fast1_ok, spr1_ok, n_valid_o, n_ready_i, spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32bit, o, spr1, fast1, xer_so, xer_ov, xer_ca, ra, \spr1$1 , \fast1$2 , \xer_so$3 , \xer_ov$4 , \xer_ca$5 , p_valid_i, p_ready_o, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) +module alu_spr0(coresync_rst, o_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, fast1_ok, spr1_ok, n_valid_o, n_ready_i, spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32bit, spr_op__sv_pred_sz, spr_op__sv_pred_dz, spr_op__sv_saturate, spr_op__SV_Ptype, o, spr1, fast1, xer_so, xer_ov, xer_ca, ra, \spr1$1 , \fast1$2 , \xer_so$3 , \xer_ov$4 , \xer_ca$5 , p_valid_i, p_ready_o, coresync_clk); + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] \fast1$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output fast1_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \muxid$16 ; + wire [1:0] \muxid$20 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) input p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] pipe_fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \pipe_fast1$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \pipe_fast1$16 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe_fast1_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] pipe_muxid; @@ -29733,59 +32820,73 @@ module alu_spr0(coresync_rst, o_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, fast1_ok, s wire pipe_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire pipe_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] pipe_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe_o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire pipe_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) wire pipe_p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] pipe_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] pipe_spr1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \pipe_spr1$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \pipe_spr1$15 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe_spr1_ok; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] pipe_spr_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \pipe_spr_op__SV_Ptype$14 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] pipe_spr_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] pipe_spr_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \pipe_spr_op__fn_unit$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \pipe_spr_op__fn_unit$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] pipe_spr_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] \pipe_spr_op__insn$9 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -29862,7 +32963,9 @@ module alu_spr0(coresync_rst, o_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, fast1_ok, s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] pipe_spr_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -29939,76 +33042,112 @@ module alu_spr0(coresync_rst, o_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, fast1_ok, s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] \pipe_spr_op__insn_type$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe_spr_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \pipe_spr_op__is_32bit$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire pipe_spr_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_spr_op__sv_pred_dz$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire pipe_spr_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe_spr_op__sv_pred_sz$11 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] pipe_spr_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \pipe_spr_op__sv_saturate$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [1:0] pipe_xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [1:0] \pipe_xer_ca$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [1:0] \pipe_xer_ca$19 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe_xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [1:0] pipe_xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [1:0] \pipe_xer_ov$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [1:0] \pipe_xer_ov$18 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe_xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire pipe_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \pipe_xer_so$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \pipe_xer_so$17 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe_xer_so_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] spr1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] \spr1$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output spr1_ok; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] spr_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \spr_op__SV_Ptype$28 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] spr_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] spr_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \spr_op__fn_unit$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \spr_op__fn_unit$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] spr_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \spr_op__insn$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \spr_op__insn$23 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -30084,7 +33223,9 @@ module alu_spr0(coresync_rst, o_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, fast1_ok, s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] spr_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -30161,29 +33302,51 @@ module alu_spr0(coresync_rst, o_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, fast1_ok, s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \spr_op__insn_type$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \spr_op__insn_type$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input spr_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \spr_op__is_32bit$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \spr_op__is_32bit$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input spr_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \spr_op__sv_pred_dz$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input spr_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \spr_op__sv_pred_sz$25 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] spr_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \spr_op__sv_saturate$27 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [1:0] xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [1:0] \xer_ca$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [1:0] xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [1:0] \xer_ov$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input \xer_so$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_so_ok; \n$63 n ( .n_ready_i(n_ready_i), @@ -30197,7 +33360,7 @@ module alu_spr0(coresync_rst, o_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, fast1_ok, s .coresync_clk(coresync_clk), .coresync_rst(coresync_rst), .fast1(pipe_fast1), - .\fast1$7 (\pipe_fast1$12 ), + .\fast1$11 (\pipe_fast1$16 ), .fast1_ok(pipe_fast1_ok), .muxid(pipe_muxid), .\muxid$1 (\pipe_muxid$6 ), @@ -30209,8 +33372,10 @@ module alu_spr0(coresync_rst, o_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, fast1_ok, s .p_valid_i(pipe_p_valid_i), .ra(pipe_ra), .spr1(pipe_spr1), - .\spr1$6 (\pipe_spr1$11 ), + .\spr1$10 (\pipe_spr1$15 ), .spr1_ok(pipe_spr1_ok), + .spr_op__SV_Ptype(pipe_spr_op__SV_Ptype), + .\spr_op__SV_Ptype$9 (\pipe_spr_op__SV_Ptype$14 ), .spr_op__fn_unit(pipe_spr_op__fn_unit), .\spr_op__fn_unit$3 (\pipe_spr_op__fn_unit$8 ), .spr_op__insn(pipe_spr_op__insn), @@ -30219,25 +33384,31 @@ module alu_spr0(coresync_rst, o_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, fast1_ok, s .\spr_op__insn_type$2 (\pipe_spr_op__insn_type$7 ), .spr_op__is_32bit(pipe_spr_op__is_32bit), .\spr_op__is_32bit$5 (\pipe_spr_op__is_32bit$10 ), + .spr_op__sv_pred_dz(pipe_spr_op__sv_pred_dz), + .\spr_op__sv_pred_dz$7 (\pipe_spr_op__sv_pred_dz$12 ), + .spr_op__sv_pred_sz(pipe_spr_op__sv_pred_sz), + .\spr_op__sv_pred_sz$6 (\pipe_spr_op__sv_pred_sz$11 ), + .spr_op__sv_saturate(pipe_spr_op__sv_saturate), + .\spr_op__sv_saturate$8 (\pipe_spr_op__sv_saturate$13 ), .xer_ca(pipe_xer_ca), - .\xer_ca$10 (\pipe_xer_ca$15 ), + .\xer_ca$14 (\pipe_xer_ca$19 ), .xer_ca_ok(pipe_xer_ca_ok), .xer_ov(pipe_xer_ov), - .\xer_ov$9 (\pipe_xer_ov$14 ), + .\xer_ov$13 (\pipe_xer_ov$18 ), .xer_ov_ok(pipe_xer_ov_ok), .xer_so(pipe_xer_so), - .\xer_so$8 (\pipe_xer_so$13 ), + .\xer_so$12 (\pipe_xer_so$17 ), .xer_so_ok(pipe_xer_so_ok) ); assign muxid = 2'h0; - assign { xer_ca_ok, xer_ca } = { pipe_xer_ca_ok, \pipe_xer_ca$15 }; - assign { xer_ov_ok, xer_ov } = { pipe_xer_ov_ok, \pipe_xer_ov$14 }; - assign { xer_so_ok, xer_so } = { pipe_xer_so_ok, \pipe_xer_so$13 }; - assign { fast1_ok, fast1 } = { pipe_fast1_ok, \pipe_fast1$12 }; - assign { spr1_ok, spr1 } = { pipe_spr1_ok, \pipe_spr1$11 }; + assign { xer_ca_ok, xer_ca } = { pipe_xer_ca_ok, \pipe_xer_ca$19 }; + assign { xer_ov_ok, xer_ov } = { pipe_xer_ov_ok, \pipe_xer_ov$18 }; + assign { xer_so_ok, xer_so } = { pipe_xer_so_ok, \pipe_xer_so$17 }; + assign { fast1_ok, fast1 } = { pipe_fast1_ok, \pipe_fast1$16 }; + assign { spr1_ok, spr1 } = { pipe_spr1_ok, \pipe_spr1$15 }; assign { o_ok, o } = { pipe_o_ok, pipe_o }; - assign { \spr_op__is_32bit$20 , \spr_op__insn$19 , \spr_op__fn_unit$18 , \spr_op__insn_type$17 } = { \pipe_spr_op__is_32bit$10 , \pipe_spr_op__insn$9 , \pipe_spr_op__fn_unit$8 , \pipe_spr_op__insn_type$7 }; - assign \muxid$16 = \pipe_muxid$6 ; + assign { \spr_op__SV_Ptype$28 , \spr_op__sv_saturate$27 , \spr_op__sv_pred_dz$26 , \spr_op__sv_pred_sz$25 , \spr_op__is_32bit$24 , \spr_op__insn$23 , \spr_op__fn_unit$22 , \spr_op__insn_type$21 } = { \pipe_spr_op__SV_Ptype$14 , \pipe_spr_op__sv_saturate$13 , \pipe_spr_op__sv_pred_dz$12 , \pipe_spr_op__sv_pred_sz$11 , \pipe_spr_op__is_32bit$10 , \pipe_spr_op__insn$9 , \pipe_spr_op__fn_unit$8 , \pipe_spr_op__insn_type$7 }; + assign \muxid$20 = \pipe_muxid$6 ; assign pipe_n_ready_i = n_ready_i; assign n_valid_o = pipe_n_valid_o; assign pipe_xer_ca = \xer_ca$5 ; @@ -30246,7 +33417,7 @@ module alu_spr0(coresync_rst, o_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, fast1_ok, s assign pipe_fast1 = \fast1$2 ; assign pipe_spr1 = \spr1$1 ; assign pipe_ra = ra; - assign { pipe_spr_op__is_32bit, pipe_spr_op__insn, pipe_spr_op__fn_unit, pipe_spr_op__insn_type } = { spr_op__is_32bit, spr_op__insn, spr_op__fn_unit, spr_op__insn_type }; + assign { pipe_spr_op__SV_Ptype, pipe_spr_op__sv_saturate, pipe_spr_op__sv_pred_dz, pipe_spr_op__sv_pred_sz, pipe_spr_op__is_32bit, pipe_spr_op__insn, pipe_spr_op__fn_unit, pipe_spr_op__insn_type } = { spr_op__SV_Ptype, spr_op__sv_saturate, spr_op__sv_pred_dz, spr_op__sv_pred_sz, spr_op__is_32bit, spr_op__insn, spr_op__fn_unit, spr_op__insn_type }; assign pipe_muxid = 2'h0; assign p_ready_o = pipe_p_ready_o; assign pipe_p_valid_i = p_valid_i; @@ -30254,59 +33425,69 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0.alu_trap0" *) (* generator = "nMigen" *) -module alu_trap0(coresync_rst, o_ok, fast1_ok, fast2_ok, nia_ok, msr_ok, n_valid_o, n_ready_i, trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, o, fast1, fast2, nia, msr, ra, rb, \fast1$1 , \fast2$2 , p_valid_i, p_ready_o, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) +module alu_trap0(coresync_rst, o_ok, fast1_ok, fast2_ok, fast3_ok, nia_ok, msr_ok, svstate_ok, n_valid_o, n_ready_i, trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__svstate, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, trap_op__sv_pred_sz, trap_op__sv_pred_dz, trap_op__sv_saturate, trap_op__SV_Ptype, o, fast1, fast2, fast3, nia, msr, svstate, ra, rb, \fast1$1 , \fast2$2 , \fast3$3 , p_valid_i, p_ready_o, coresync_clk); + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] \fast1$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output fast1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] fast2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] \fast2$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output fast2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [63:0] fast3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + input [63:0] \fast3$3 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output fast3_ok; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] msr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output msr_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \muxid$29 ; + wire [1:0] \muxid$42 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] nia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output nia_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) input p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] pipe1_fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \pipe1_fast1$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \pipe1_fast1$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] pipe1_fast2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \pipe1_fast2$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \pipe1_fast2$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] pipe1_fast3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \pipe1_fast3$23 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] pipe1_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \pipe1_muxid$3 ; + wire [1:0] \pipe1_muxid$4 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) wire pipe1_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) @@ -30315,56 +33496,70 @@ module alu_trap0(coresync_rst, o_ok, fast1_ok, fast2_ok, nia_ok, msr_ok, n_valid wire pipe1_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) wire pipe1_p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] pipe1_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \pipe1_ra$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \pipe1_ra$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] pipe1_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \pipe1_rb$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \pipe1_rb$20 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] pipe1_trap_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \pipe1_trap_op__SV_Ptype$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] pipe1_trap_op__cia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \pipe1_trap_op__cia$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \pipe1_trap_op__cia$9 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] pipe1_trap_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] pipe1_trap_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \pipe1_trap_op__fn_unit$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \pipe1_trap_op__fn_unit$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] pipe1_trap_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \pipe1_trap_op__insn$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \pipe1_trap_op__insn$7 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -30440,7 +33635,9 @@ module alu_trap0(coresync_rst, o_ok, fast1_ok, fast2_ok, nia_ok, msr_ok, n_valid (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] pipe1_trap_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -30517,110 +33714,160 @@ module alu_trap0(coresync_rst, o_ok, fast1_ok, fast2_ok, nia_ok, msr_ok, n_valid (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \pipe1_trap_op__insn_type$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \pipe1_trap_op__insn_type$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe1_trap_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe1_trap_op__is_32bit$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe1_trap_op__is_32bit$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [7:0] pipe1_trap_op__ldst_exc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [7:0] \pipe1_trap_op__ldst_exc$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [7:0] \pipe1_trap_op__ldst_exc$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] pipe1_trap_op__msr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \pipe1_trap_op__msr$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \pipe1_trap_op__msr$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire pipe1_trap_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe1_trap_op__sv_pred_dz$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire pipe1_trap_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe1_trap_op__sv_pred_sz$15 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] pipe1_trap_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \pipe1_trap_op__sv_saturate$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] pipe1_trap_op__svstate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \pipe1_trap_op__svstate$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [12:0] pipe1_trap_op__trapaddr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [12:0] \pipe1_trap_op__trapaddr$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [12:0] \pipe1_trap_op__trapaddr$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [7:0] pipe1_trap_op__traptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [7:0] \pipe1_trap_op__traptype$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [7:0] \pipe1_trap_op__traptype$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] pipe2_fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \pipe2_fast1$27 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \pipe2_fast1$39 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe2_fast1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] pipe2_fast2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \pipe2_fast2$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \pipe2_fast2$40 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe2_fast2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] pipe2_fast3; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \pipe2_fast3$41 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire pipe2_fast3_ok; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] pipe2_msr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe2_msr_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] pipe2_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \pipe2_muxid$17 ; + wire [1:0] \pipe2_muxid$24 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) wire pipe2_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire pipe2_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] pipe2_nia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe2_nia_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] pipe2_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pipe2_o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire pipe2_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) wire pipe2_p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] pipe2_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] pipe2_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [31:0] pipe2_svstate; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire pipe2_svstate_ok; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] pipe2_trap_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \pipe2_trap_op__SV_Ptype$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] pipe2_trap_op__cia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \pipe2_trap_op__cia$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \pipe2_trap_op__cia$29 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] pipe2_trap_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] pipe2_trap_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \pipe2_trap_op__fn_unit$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \pipe2_trap_op__fn_unit$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] pipe2_trap_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \pipe2_trap_op__insn$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \pipe2_trap_op__insn$27 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -30696,7 +33943,9 @@ module alu_trap0(coresync_rst, o_ok, fast1_ok, fast2_ok, nia_ok, msr_ok, n_valid (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] pipe2_trap_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -30773,74 +34022,118 @@ module alu_trap0(coresync_rst, o_ok, fast1_ok, fast2_ok, nia_ok, msr_ok, n_valid (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \pipe2_trap_op__insn_type$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \pipe2_trap_op__insn_type$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire pipe2_trap_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \pipe2_trap_op__is_32bit$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe2_trap_op__is_32bit$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [7:0] pipe2_trap_op__ldst_exc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [7:0] \pipe2_trap_op__ldst_exc$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [7:0] \pipe2_trap_op__ldst_exc$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] pipe2_trap_op__msr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \pipe2_trap_op__msr$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \pipe2_trap_op__msr$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire pipe2_trap_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe2_trap_op__sv_pred_dz$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire pipe2_trap_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \pipe2_trap_op__sv_pred_sz$35 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] pipe2_trap_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \pipe2_trap_op__sv_saturate$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] pipe2_trap_op__svstate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \pipe2_trap_op__svstate$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [12:0] pipe2_trap_op__trapaddr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [12:0] \pipe2_trap_op__trapaddr$25 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [12:0] \pipe2_trap_op__trapaddr$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [7:0] pipe2_trap_op__traptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [7:0] \pipe2_trap_op__traptype$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [7:0] \pipe2_trap_op__traptype$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [31:0] svstate; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output svstate_ok; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] trap_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \trap_op__SV_Ptype$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] trap_op__cia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \trap_op__cia$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \trap_op__cia$47 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] trap_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] trap_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \trap_op__fn_unit$31 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \trap_op__fn_unit$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] trap_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \trap_op__insn$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \trap_op__insn$45 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -30916,7 +34209,9 @@ module alu_trap0(coresync_rst, o_ok, fast1_ok, fast2_ok, nia_ok, msr_ok, n_valid (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] trap_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -30993,28 +34288,54 @@ module alu_trap0(coresync_rst, o_ok, fast1_ok, fast2_ok, nia_ok, msr_ok, n_valid (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \trap_op__insn_type$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \trap_op__insn_type$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input trap_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \trap_op__is_32bit$35 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \trap_op__is_32bit$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [7:0] trap_op__ldst_exc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [7:0] \trap_op__ldst_exc$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [7:0] \trap_op__ldst_exc$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] trap_op__msr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \trap_op__msr$33 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \trap_op__msr$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input trap_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \trap_op__sv_pred_dz$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input trap_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \trap_op__sv_pred_sz$53 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] trap_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \trap_op__sv_saturate$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [31:0] trap_op__svstate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \trap_op__svstate$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [12:0] trap_op__trapaddr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [12:0] \trap_op__trapaddr$37 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [12:0] \trap_op__trapaddr$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [7:0] trap_op__traptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [7:0] \trap_op__traptype$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [7:0] \trap_op__traptype$50 ; \n$31 n ( .n_ready_i(n_ready_i), .n_valid_o(n_valid_o) @@ -31027,51 +34348,66 @@ module alu_trap0(coresync_rst, o_ok, fast1_ok, fast2_ok, nia_ok, msr_ok, n_valid .coresync_clk(coresync_clk), .coresync_rst(coresync_rst), .fast1(pipe1_fast1), - .\fast1$13 (\pipe1_fast1$15 ), + .\fast1$18 (\pipe1_fast1$21 ), .fast2(pipe1_fast2), - .\fast2$14 (\pipe1_fast2$16 ), + .\fast2$19 (\pipe1_fast2$22 ), + .fast3(pipe1_fast3), + .\fast3$20 (\pipe1_fast3$23 ), .muxid(pipe1_muxid), - .\muxid$1 (\pipe1_muxid$3 ), + .\muxid$1 (\pipe1_muxid$4 ), .n_ready_i(pipe1_n_ready_i), .n_valid_o(pipe1_n_valid_o), .p_ready_o(pipe1_p_ready_o), .p_valid_i(pipe1_p_valid_i), .ra(pipe1_ra), - .\ra$11 (\pipe1_ra$13 ), + .\ra$16 (\pipe1_ra$19 ), .rb(pipe1_rb), - .\rb$12 (\pipe1_rb$14 ), + .\rb$17 (\pipe1_rb$20 ), + .trap_op__SV_Ptype(pipe1_trap_op__SV_Ptype), + .\trap_op__SV_Ptype$15 (\pipe1_trap_op__SV_Ptype$18 ), .trap_op__cia(pipe1_trap_op__cia), - .\trap_op__cia$6 (\pipe1_trap_op__cia$8 ), + .\trap_op__cia$6 (\pipe1_trap_op__cia$9 ), .trap_op__fn_unit(pipe1_trap_op__fn_unit), - .\trap_op__fn_unit$3 (\pipe1_trap_op__fn_unit$5 ), + .\trap_op__fn_unit$3 (\pipe1_trap_op__fn_unit$6 ), .trap_op__insn(pipe1_trap_op__insn), - .\trap_op__insn$4 (\pipe1_trap_op__insn$6 ), + .\trap_op__insn$4 (\pipe1_trap_op__insn$7 ), .trap_op__insn_type(pipe1_trap_op__insn_type), - .\trap_op__insn_type$2 (\pipe1_trap_op__insn_type$4 ), + .\trap_op__insn_type$2 (\pipe1_trap_op__insn_type$5 ), .trap_op__is_32bit(pipe1_trap_op__is_32bit), - .\trap_op__is_32bit$7 (\pipe1_trap_op__is_32bit$9 ), + .\trap_op__is_32bit$8 (\pipe1_trap_op__is_32bit$11 ), .trap_op__ldst_exc(pipe1_trap_op__ldst_exc), - .\trap_op__ldst_exc$10 (\pipe1_trap_op__ldst_exc$12 ), + .\trap_op__ldst_exc$11 (\pipe1_trap_op__ldst_exc$14 ), .trap_op__msr(pipe1_trap_op__msr), - .\trap_op__msr$5 (\pipe1_trap_op__msr$7 ), + .\trap_op__msr$5 (\pipe1_trap_op__msr$8 ), + .trap_op__sv_pred_dz(pipe1_trap_op__sv_pred_dz), + .\trap_op__sv_pred_dz$13 (\pipe1_trap_op__sv_pred_dz$16 ), + .trap_op__sv_pred_sz(pipe1_trap_op__sv_pred_sz), + .\trap_op__sv_pred_sz$12 (\pipe1_trap_op__sv_pred_sz$15 ), + .trap_op__sv_saturate(pipe1_trap_op__sv_saturate), + .\trap_op__sv_saturate$14 (\pipe1_trap_op__sv_saturate$17 ), + .trap_op__svstate(pipe1_trap_op__svstate), + .\trap_op__svstate$7 (\pipe1_trap_op__svstate$10 ), .trap_op__trapaddr(pipe1_trap_op__trapaddr), - .\trap_op__trapaddr$9 (\pipe1_trap_op__trapaddr$11 ), + .\trap_op__trapaddr$10 (\pipe1_trap_op__trapaddr$13 ), .trap_op__traptype(pipe1_trap_op__traptype), - .\trap_op__traptype$8 (\pipe1_trap_op__traptype$10 ) + .\trap_op__traptype$9 (\pipe1_trap_op__traptype$12 ) ); \pipe2$35 pipe2 ( .coresync_clk(coresync_clk), .coresync_rst(coresync_rst), .fast1(pipe2_fast1), - .\fast1$11 (\pipe2_fast1$27 ), + .\fast1$16 (\pipe2_fast1$39 ), .fast1_ok(pipe2_fast1_ok), .fast2(pipe2_fast2), - .\fast2$12 (\pipe2_fast2$28 ), + .\fast2$17 (\pipe2_fast2$40 ), .fast2_ok(pipe2_fast2_ok), + .fast3(pipe2_fast3), + .\fast3$18 (\pipe2_fast3$41 ), + .fast3_ok(pipe2_fast3_ok), .msr(pipe2_msr), .msr_ok(pipe2_msr_ok), .muxid(pipe2_muxid), - .\muxid$1 (\pipe2_muxid$17 ), + .\muxid$1 (\pipe2_muxid$24 ), .n_ready_i(pipe2_n_ready_i), .n_valid_o(pipe2_n_valid_o), .nia(pipe2_nia), @@ -31082,48 +34418,64 @@ module alu_trap0(coresync_rst, o_ok, fast1_ok, fast2_ok, nia_ok, msr_ok, n_valid .p_valid_i(pipe2_p_valid_i), .ra(pipe2_ra), .rb(pipe2_rb), + .svstate(pipe2_svstate), + .svstate_ok(pipe2_svstate_ok), + .trap_op__SV_Ptype(pipe2_trap_op__SV_Ptype), + .\trap_op__SV_Ptype$15 (\pipe2_trap_op__SV_Ptype$38 ), .trap_op__cia(pipe2_trap_op__cia), - .\trap_op__cia$6 (\pipe2_trap_op__cia$22 ), + .\trap_op__cia$6 (\pipe2_trap_op__cia$29 ), .trap_op__fn_unit(pipe2_trap_op__fn_unit), - .\trap_op__fn_unit$3 (\pipe2_trap_op__fn_unit$19 ), + .\trap_op__fn_unit$3 (\pipe2_trap_op__fn_unit$26 ), .trap_op__insn(pipe2_trap_op__insn), - .\trap_op__insn$4 (\pipe2_trap_op__insn$20 ), + .\trap_op__insn$4 (\pipe2_trap_op__insn$27 ), .trap_op__insn_type(pipe2_trap_op__insn_type), - .\trap_op__insn_type$2 (\pipe2_trap_op__insn_type$18 ), + .\trap_op__insn_type$2 (\pipe2_trap_op__insn_type$25 ), .trap_op__is_32bit(pipe2_trap_op__is_32bit), - .\trap_op__is_32bit$7 (\pipe2_trap_op__is_32bit$23 ), + .\trap_op__is_32bit$8 (\pipe2_trap_op__is_32bit$31 ), .trap_op__ldst_exc(pipe2_trap_op__ldst_exc), - .\trap_op__ldst_exc$10 (\pipe2_trap_op__ldst_exc$26 ), + .\trap_op__ldst_exc$11 (\pipe2_trap_op__ldst_exc$34 ), .trap_op__msr(pipe2_trap_op__msr), - .\trap_op__msr$5 (\pipe2_trap_op__msr$21 ), + .\trap_op__msr$5 (\pipe2_trap_op__msr$28 ), + .trap_op__sv_pred_dz(pipe2_trap_op__sv_pred_dz), + .\trap_op__sv_pred_dz$13 (\pipe2_trap_op__sv_pred_dz$36 ), + .trap_op__sv_pred_sz(pipe2_trap_op__sv_pred_sz), + .\trap_op__sv_pred_sz$12 (\pipe2_trap_op__sv_pred_sz$35 ), + .trap_op__sv_saturate(pipe2_trap_op__sv_saturate), + .\trap_op__sv_saturate$14 (\pipe2_trap_op__sv_saturate$37 ), + .trap_op__svstate(pipe2_trap_op__svstate), + .\trap_op__svstate$7 (\pipe2_trap_op__svstate$30 ), .trap_op__trapaddr(pipe2_trap_op__trapaddr), - .\trap_op__trapaddr$9 (\pipe2_trap_op__trapaddr$25 ), + .\trap_op__trapaddr$10 (\pipe2_trap_op__trapaddr$33 ), .trap_op__traptype(pipe2_trap_op__traptype), - .\trap_op__traptype$8 (\pipe2_trap_op__traptype$24 ) + .\trap_op__traptype$9 (\pipe2_trap_op__traptype$32 ) ); assign muxid = 2'h0; + assign { svstate_ok, svstate } = { pipe2_svstate_ok, pipe2_svstate }; assign { msr_ok, msr } = { pipe2_msr_ok, pipe2_msr }; assign { nia_ok, nia } = { pipe2_nia_ok, pipe2_nia }; - assign { fast2_ok, fast2 } = { pipe2_fast2_ok, \pipe2_fast2$28 }; - assign { fast1_ok, fast1 } = { pipe2_fast1_ok, \pipe2_fast1$27 }; + assign { fast3_ok, fast3 } = { pipe2_fast3_ok, \pipe2_fast3$41 }; + assign { fast2_ok, fast2 } = { pipe2_fast2_ok, \pipe2_fast2$40 }; + assign { fast1_ok, fast1 } = { pipe2_fast1_ok, \pipe2_fast1$39 }; assign { o_ok, o } = { pipe2_o_ok, pipe2_o }; - assign { \trap_op__ldst_exc$38 , \trap_op__trapaddr$37 , \trap_op__traptype$36 , \trap_op__is_32bit$35 , \trap_op__cia$34 , \trap_op__msr$33 , \trap_op__insn$32 , \trap_op__fn_unit$31 , \trap_op__insn_type$30 } = { \pipe2_trap_op__ldst_exc$26 , \pipe2_trap_op__trapaddr$25 , \pipe2_trap_op__traptype$24 , \pipe2_trap_op__is_32bit$23 , \pipe2_trap_op__cia$22 , \pipe2_trap_op__msr$21 , \pipe2_trap_op__insn$20 , \pipe2_trap_op__fn_unit$19 , \pipe2_trap_op__insn_type$18 }; - assign \muxid$29 = \pipe2_muxid$17 ; + assign { \trap_op__SV_Ptype$56 , \trap_op__sv_saturate$55 , \trap_op__sv_pred_dz$54 , \trap_op__sv_pred_sz$53 , \trap_op__ldst_exc$52 , \trap_op__trapaddr$51 , \trap_op__traptype$50 , \trap_op__is_32bit$49 , \trap_op__svstate$48 , \trap_op__cia$47 , \trap_op__msr$46 , \trap_op__insn$45 , \trap_op__fn_unit$44 , \trap_op__insn_type$43 } = { \pipe2_trap_op__SV_Ptype$38 , \pipe2_trap_op__sv_saturate$37 , \pipe2_trap_op__sv_pred_dz$36 , \pipe2_trap_op__sv_pred_sz$35 , \pipe2_trap_op__ldst_exc$34 , \pipe2_trap_op__trapaddr$33 , \pipe2_trap_op__traptype$32 , \pipe2_trap_op__is_32bit$31 , \pipe2_trap_op__svstate$30 , \pipe2_trap_op__cia$29 , \pipe2_trap_op__msr$28 , \pipe2_trap_op__insn$27 , \pipe2_trap_op__fn_unit$26 , \pipe2_trap_op__insn_type$25 }; + assign \muxid$42 = \pipe2_muxid$24 ; assign pipe2_n_ready_i = n_ready_i; assign n_valid_o = pipe2_n_valid_o; - assign \pipe1_fast2$16 = \fast2$2 ; - assign \pipe1_fast1$15 = \fast1$1 ; - assign \pipe1_rb$14 = rb; - assign \pipe1_ra$13 = ra; - assign { \pipe1_trap_op__ldst_exc$12 , \pipe1_trap_op__trapaddr$11 , \pipe1_trap_op__traptype$10 , \pipe1_trap_op__is_32bit$9 , \pipe1_trap_op__cia$8 , \pipe1_trap_op__msr$7 , \pipe1_trap_op__insn$6 , \pipe1_trap_op__fn_unit$5 , \pipe1_trap_op__insn_type$4 } = { trap_op__ldst_exc, trap_op__trapaddr, trap_op__traptype, trap_op__is_32bit, trap_op__cia, trap_op__msr, trap_op__insn, trap_op__fn_unit, trap_op__insn_type }; - assign \pipe1_muxid$3 = 2'h0; + assign \pipe1_fast3$23 = \fast3$3 ; + assign \pipe1_fast2$22 = \fast2$2 ; + assign \pipe1_fast1$21 = \fast1$1 ; + assign \pipe1_rb$20 = rb; + assign \pipe1_ra$19 = ra; + assign { \pipe1_trap_op__SV_Ptype$18 , \pipe1_trap_op__sv_saturate$17 , \pipe1_trap_op__sv_pred_dz$16 , \pipe1_trap_op__sv_pred_sz$15 , \pipe1_trap_op__ldst_exc$14 , \pipe1_trap_op__trapaddr$13 , \pipe1_trap_op__traptype$12 , \pipe1_trap_op__is_32bit$11 , \pipe1_trap_op__svstate$10 , \pipe1_trap_op__cia$9 , \pipe1_trap_op__msr$8 , \pipe1_trap_op__insn$7 , \pipe1_trap_op__fn_unit$6 , \pipe1_trap_op__insn_type$5 } = { trap_op__SV_Ptype, trap_op__sv_saturate, trap_op__sv_pred_dz, trap_op__sv_pred_sz, trap_op__ldst_exc, trap_op__trapaddr, trap_op__traptype, trap_op__is_32bit, trap_op__svstate, trap_op__cia, trap_op__msr, trap_op__insn, trap_op__fn_unit, trap_op__insn_type }; + assign \pipe1_muxid$4 = 2'h0; assign p_ready_o = pipe1_p_ready_o; assign pipe1_p_valid_i = p_valid_i; + assign pipe2_fast3 = pipe1_fast3; assign pipe2_fast2 = pipe1_fast2; assign pipe2_fast1 = pipe1_fast1; assign pipe2_rb = pipe1_rb; assign pipe2_ra = pipe1_ra; - assign { pipe2_trap_op__ldst_exc, pipe2_trap_op__trapaddr, pipe2_trap_op__traptype, pipe2_trap_op__is_32bit, pipe2_trap_op__cia, pipe2_trap_op__msr, pipe2_trap_op__insn, pipe2_trap_op__fn_unit, pipe2_trap_op__insn_type } = { pipe1_trap_op__ldst_exc, pipe1_trap_op__trapaddr, pipe1_trap_op__traptype, pipe1_trap_op__is_32bit, pipe1_trap_op__cia, pipe1_trap_op__msr, pipe1_trap_op__insn, pipe1_trap_op__fn_unit, pipe1_trap_op__insn_type }; + assign { pipe2_trap_op__SV_Ptype, pipe2_trap_op__sv_saturate, pipe2_trap_op__sv_pred_dz, pipe2_trap_op__sv_pred_sz, pipe2_trap_op__ldst_exc, pipe2_trap_op__trapaddr, pipe2_trap_op__traptype, pipe2_trap_op__is_32bit, pipe2_trap_op__svstate, pipe2_trap_op__cia, pipe2_trap_op__msr, pipe2_trap_op__insn, pipe2_trap_op__fn_unit, pipe2_trap_op__insn_type } = { pipe1_trap_op__SV_Ptype, pipe1_trap_op__sv_saturate, pipe1_trap_op__sv_pred_dz, pipe1_trap_op__sv_pred_sz, pipe1_trap_op__ldst_exc, pipe1_trap_op__trapaddr, pipe1_trap_op__traptype, pipe1_trap_op__is_32bit, pipe1_trap_op__svstate, pipe1_trap_op__cia, pipe1_trap_op__msr, pipe1_trap_op__insn, pipe1_trap_op__fn_unit, pipe1_trap_op__insn_type }; assign pipe2_muxid = pipe1_muxid; assign pipe1_n_ready_i = pipe2_p_ready_o; assign pipe2_p_valid_i = pipe1_n_valid_o; @@ -31149,9 +34501,9 @@ module alui_l(coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -31180,7 +34532,7 @@ module alui_l(coresync_rst, q_alui, r_alui, s_alui, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -31211,9 +34563,9 @@ module \alui_l$106 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -31242,7 +34594,7 @@ module \alui_l$106 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -31273,9 +34625,9 @@ module \alui_l$124 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -31304,7 +34656,7 @@ module \alui_l$124 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -31335,9 +34687,9 @@ module \alui_l$15 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -31366,7 +34718,7 @@ module \alui_l$15 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -31397,9 +34749,9 @@ module \alui_l$28 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -31428,7 +34780,7 @@ module \alui_l$28 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -31459,9 +34811,9 @@ module \alui_l$44 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -31490,7 +34842,7 @@ module \alui_l$44 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -31521,9 +34873,9 @@ module \alui_l$60 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -31552,7 +34904,7 @@ module \alui_l$60 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -31583,9 +34935,9 @@ module \alui_l$72 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -31614,7 +34966,7 @@ module \alui_l$72 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -31645,9 +34997,9 @@ module \alui_l$89 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -31676,7 +35028,7 @@ module \alui_l$89 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -33045,7 +36397,7 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.branch0" *) (* generator = "nMigen" *) -module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_type, oper_i_alu_branch0__fn_unit, oper_i_alu_branch0__insn, oper_i_alu_branch0__imm_data__data, oper_i_alu_branch0__imm_data__ok, oper_i_alu_branch0__lk, oper_i_alu_branch0__is_32bit, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src3_i, src1_i, src2_i, fast1_ok, cu_wr__rel_o, cu_wr__go_i, fast2_ok, dest1_o, dest2_o, nia_ok, dest3_o, coresync_clk); +module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_type, oper_i_alu_branch0__fn_unit, oper_i_alu_branch0__insn, oper_i_alu_branch0__imm_data__data, oper_i_alu_branch0__imm_data__ok, oper_i_alu_branch0__lk, oper_i_alu_branch0__is_32bit, oper_i_alu_branch0__sv_pred_sz, oper_i_alu_branch0__sv_pred_dz, oper_i_alu_branch0__sv_saturate, oper_i_alu_branch0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src3_i, src1_i, src2_i, fast1_ok, cu_wr__rel_o, cu_wr__go_i, fast2_ok, dest1_o, dest2_o, nia_ok, dest3_o, coresync_clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) wire \$101 ; @@ -33171,40 +36523,49 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t wire all_rd_pulse; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) wire all_rd_rise; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] alu_branch0_br_op__SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \alu_branch0_br_op__SV_Ptype$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] alu_branch0_br_op__cia = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] \alu_branch0_br_op__cia$next ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] alu_branch0_br_op__fn_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] \alu_branch0_br_op__fn_unit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] alu_branch0_br_op__fn_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] \alu_branch0_br_op__fn_unit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] alu_branch0_br_op__imm_data__data = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] \alu_branch0_br_op__imm_data__data$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_branch0_br_op__imm_data__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_branch0_br_op__imm_data__ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] alu_branch0_br_op__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] \alu_branch0_br_op__insn$next ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -33281,33 +36642,51 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] alu_branch0_br_op__insn_type = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] \alu_branch0_br_op__insn_type$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_branch0_br_op__is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_branch0_br_op__is_32bit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_branch0_br_op__lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_branch0_br_op__lk$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg alu_branch0_br_op__sv_pred_dz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \alu_branch0_br_op__sv_pred_dz$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg alu_branch0_br_op__sv_pred_sz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \alu_branch0_br_op__sv_pred_sz$next ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] alu_branch0_br_op__sv_saturate = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \alu_branch0_br_op__sv_saturate$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [3:0] alu_branch0_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] alu_branch0_fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] \alu_branch0_fast1$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] alu_branch0_fast2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] \alu_branch0_fast2$2 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) wire alu_branch0_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire alu_branch0_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] alu_branch0_nia; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire alu_branch0_p_ready_o; @@ -33341,9 +36720,9 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) output cu_busy_o; @@ -33400,11 +36779,11 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) output [63:0] dest3_o; reg [63:0] dest3_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output fast1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output fast2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output nia_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire opc_l_q_opc; @@ -33416,30 +36795,37 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t reg opc_l_s_opc = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) reg \opc_l_s_opc$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_branch0__SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] oper_i_alu_branch0__cia; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] oper_i_alu_branch0__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] oper_i_alu_branch0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] oper_i_alu_branch0__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_branch0__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] oper_i_alu_branch0__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -33516,12 +36902,24 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] oper_i_alu_branch0__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_branch0__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_branch0__lk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_branch0__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_branch0__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_branch0__sv_saturate; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *) reg [2:0] prev_wr_go = 3'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *) @@ -33693,6 +37091,14 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t alu_branch0_br_op__lk <= \alu_branch0_br_op__lk$next ; always @(posedge coresync_clk) alu_branch0_br_op__is_32bit <= \alu_branch0_br_op__is_32bit$next ; + always @(posedge coresync_clk) + alu_branch0_br_op__sv_pred_sz <= \alu_branch0_br_op__sv_pred_sz$next ; + always @(posedge coresync_clk) + alu_branch0_br_op__sv_pred_dz <= \alu_branch0_br_op__sv_pred_dz$next ; + always @(posedge coresync_clk) + alu_branch0_br_op__sv_saturate <= \alu_branch0_br_op__sv_saturate$next ; + always @(posedge coresync_clk) + alu_branch0_br_op__SV_Ptype <= \alu_branch0_br_op__SV_Ptype$next ; always @(posedge coresync_clk) req_l_r_req <= \req_l_r_req$next ; always @(posedge coresync_clk) @@ -33720,6 +37126,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @(posedge coresync_clk) all_rd_dly <= \$11 ; alu_branch0 alu_branch0 ( + .br_op__SV_Ptype(alu_branch0_br_op__SV_Ptype), .br_op__cia(alu_branch0_br_op__cia), .br_op__fn_unit(alu_branch0_br_op__fn_unit), .br_op__imm_data__data(alu_branch0_br_op__imm_data__data), @@ -33728,6 +37135,9 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t .br_op__insn_type(alu_branch0_br_op__insn_type), .br_op__is_32bit(alu_branch0_br_op__is_32bit), .br_op__lk(alu_branch0_br_op__lk), + .br_op__sv_pred_dz(alu_branch0_br_op__sv_pred_dz), + .br_op__sv_pred_sz(alu_branch0_br_op__sv_pred_sz), + .br_op__sv_saturate(alu_branch0_br_op__sv_saturate), .coresync_clk(coresync_clk), .coresync_rst(coresync_rst), .cr_a(alu_branch0_cr_a), @@ -33805,7 +37215,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \rok_l_s_rdok$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_s_rdok$next = 1'h0; @@ -33814,7 +37224,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \rok_l_r_rdok$next = \$65 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_r_rdok$next = 1'h1; @@ -33823,7 +37233,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \rst_l_s_rst$next = all_rd; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_s_rst$next = 1'h0; @@ -33832,7 +37242,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \rst_l_r_rst$next = rst_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_r_rst$next = 1'h1; @@ -33841,7 +37251,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \opc_l_s_opc$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_s_opc$next = 1'h0; @@ -33850,7 +37260,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \opc_l_r_opc$next = req_done; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_r_opc$next = 1'h1; @@ -33859,7 +37269,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_s_src$next = 3'h0; @@ -33868,7 +37278,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \src_l_r_src$next = reset_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_r_src$next = 3'h7; @@ -33877,7 +37287,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \req_l_s_req$next = \$67 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_s_req$next = 3'h0; @@ -33886,7 +37296,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \req_l_r_req$next = \$69 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_r_req$next = 3'h7; @@ -33902,13 +37312,17 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t \alu_branch0_br_op__imm_data__ok$next = alu_branch0_br_op__imm_data__ok; \alu_branch0_br_op__lk$next = alu_branch0_br_op__lk; \alu_branch0_br_op__is_32bit$next = alu_branch0_br_op__is_32bit; + \alu_branch0_br_op__sv_pred_sz$next = alu_branch0_br_op__sv_pred_sz; + \alu_branch0_br_op__sv_pred_dz$next = alu_branch0_br_op__sv_pred_dz; + \alu_branch0_br_op__sv_saturate$next = alu_branch0_br_op__sv_saturate; + \alu_branch0_br_op__SV_Ptype$next = alu_branch0_br_op__SV_Ptype; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *) casez (cu_issue_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" */ 1'h1: - { \alu_branch0_br_op__is_32bit$next , \alu_branch0_br_op__lk$next , \alu_branch0_br_op__imm_data__ok$next , \alu_branch0_br_op__imm_data__data$next , \alu_branch0_br_op__insn$next , \alu_branch0_br_op__fn_unit$next , \alu_branch0_br_op__insn_type$next , \alu_branch0_br_op__cia$next } = { oper_i_alu_branch0__is_32bit, oper_i_alu_branch0__lk, oper_i_alu_branch0__imm_data__ok, oper_i_alu_branch0__imm_data__data, oper_i_alu_branch0__insn, oper_i_alu_branch0__fn_unit, oper_i_alu_branch0__insn_type, oper_i_alu_branch0__cia }; + { \alu_branch0_br_op__SV_Ptype$next , \alu_branch0_br_op__sv_saturate$next , \alu_branch0_br_op__sv_pred_dz$next , \alu_branch0_br_op__sv_pred_sz$next , \alu_branch0_br_op__is_32bit$next , \alu_branch0_br_op__lk$next , \alu_branch0_br_op__imm_data__ok$next , \alu_branch0_br_op__imm_data__data$next , \alu_branch0_br_op__insn$next , \alu_branch0_br_op__fn_unit$next , \alu_branch0_br_op__insn_type$next , \alu_branch0_br_op__cia$next } = { oper_i_alu_branch0__SV_Ptype, oper_i_alu_branch0__sv_saturate, oper_i_alu_branch0__sv_pred_dz, oper_i_alu_branch0__sv_pred_sz, oper_i_alu_branch0__is_32bit, oper_i_alu_branch0__lk, oper_i_alu_branch0__imm_data__ok, oper_i_alu_branch0__imm_data__data, oper_i_alu_branch0__insn, oper_i_alu_branch0__fn_unit, oper_i_alu_branch0__insn_type, oper_i_alu_branch0__cia }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -33933,7 +37347,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t 1'h1: { \data_r0__fast1_ok$next , \data_r0__fast1$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r0__fast1_ok$next = 1'h0; @@ -33955,7 +37369,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t 1'h1: { \data_r1__fast2_ok$next , \data_r1__fast2$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r1__fast2_ok$next = 1'h0; @@ -33977,7 +37391,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t 1'h1: { \data_r2__nia_ok$next , \data_r2__nia$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r2__nia_ok$next = 1'h0; @@ -34016,7 +37430,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \alui_l_r_alui$next = \$87 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alui_l_r_alui$next = 1'h1; @@ -34025,7 +37439,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \alu_l_r_alu$next = \$89 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alu_l_r_alu$next = 1'h1; @@ -34064,7 +37478,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \prev_wr_go$next = \$21 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \prev_wr_go$next = 3'h0; @@ -34122,9 +37536,9 @@ module busy_l(coresync_rst, s_busy, r_busy, q_busy, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_busy; @@ -34153,7 +37567,7 @@ module busy_l(coresync_rst, s_busy, r_busy, q_busy, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -35872,1678 +39286,1899 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core" *) (* generator = "nMigen" *) -module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data_i, msr__ren, core_terminate_o, msr__data_o, core_rego, core_ea, core_reg1, core_reg1_ok, core_reg2, core_reg2_ok, core_reg3, core_reg3_ok, core_spro, core_spr1, core_spr1_ok, core_xer_in, core_fast1, core_fast1_ok, core_fast2, core_fast2_ok, core_fasto1, core_fasto2, core_cr_in1, core_cr_in1_ok, core_cr_in2, core_cr_in2_ok, \core_cr_in2$1 , \core_cr_in2_ok$2 , core_cr_out, core_core_msr, core_core_cia, core_core_insn, core_core_insn_type, core_core_fn_unit, core_core_rc, core_core_rc_ok, core_core_oe, core_core_oe_ok, core_core_input_carry, core_core_traptype, \core_core_exc_$signal , \core_core_exc_$signal$3 , \core_core_exc_$signal$4 , \core_core_exc_$signal$5 , \core_core_exc_$signal$6 , \core_core_exc_$signal$7 , \core_core_exc_$signal$8 , \core_core_exc_$signal$9 , core_core_trapaddr, core_core_cr_rd, core_core_cr_rd_ok, core_core_cr_wr, core_core_is_32bit, core_pc, raw_insn_i, bigendian_i, sv_a_nz, \wen$10 , \data_i$11 , ivalid_i, issue_i, state_nia_wen, dmi__addr, dmi__ren, dmi__data_o, full_rd2__ren, full_rd2__data_o, full_rd__ren, full_rd__data_o, issue__addr, issue__ren, issue__data_o, \issue__addr$12 , issue__wen, issue__data_i, wb_dcache_en, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, coresync_clk); +module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data_i, msr__ren, core_terminate_o, msr__data_o, \exc_o_$signal , core_rego, core_ea, core_reg1, core_reg1_ok, core_reg2, core_reg2_ok, core_reg3, core_reg3_ok, core_spro, core_spr1, core_spr1_ok, core_xer_in, core_fast1, core_fast1_ok, core_fast2, core_fast2_ok, core_fast3, core_fast3_ok, core_fasto1, core_fasto2, core_fasto3, core_cr_in1, core_cr_in1_ok, core_cr_in2, core_cr_in2_ok, \core_cr_in2$1 , \core_cr_in2_ok$2 , core_cr_out, core_core__sv_pred_sz, core_core__sv_pred_dz, core_core__sv_saturate, core_core__SV_Ptype, core_core_msr, core_core_cia, core_core_svstate, core_core_insn, core_core_insn_type, core_core_fn_unit, core_core_rc, core_core_rc_ok, core_core_oe, core_core_oe_ok, core_core_input_carry, core_core_traptype, \core_core_exc_$signal , \core_core_exc_$signal$3 , \core_core_exc_$signal$4 , \core_core_exc_$signal$5 , \core_core_exc_$signal$6 , \core_core_exc_$signal$7 , \core_core_exc_$signal$8 , \core_core_exc_$signal$9 , core_core_trapaddr, core_core_cr_rd, core_core_cr_rd_ok, core_core_cr_wr, core_core_is_32bit, core_pc, core_msr, raw_insn_i, bigendian_i, \wen$10 , \data_i$11 , ivalid_i, issue_i, state_nia_wen, dmi__addr, dmi__ren, dmi__data_o, full_rd2__ren, full_rd2__data_o, full_rd__ren, full_rd__data_o, issue__addr, issue__ren, issue__data_o, \issue__addr$12 , issue__wen, issue__data_i, wb_dcache_en, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, coresync_clk); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) - wire [6:0] \$1001 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) - wire \$1003 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$1006 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1010 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1000 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire [6:0] \$1002 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) + wire \$1004 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) + wire \$1007 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1012 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) - wire \$1019 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) - wire [6:0] \$1022 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) - wire \$1024 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$1027 ; + wire \$1011 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1031 ; + wire \$1013 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1018 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire [6:0] \$1021 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) + wire \$1023 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) + wire \$1026 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1033 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) - wire \$1037 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) - wire [6:0] \$1040 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) - wire \$1042 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$1045 ; + wire \$1030 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1032 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1041 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire [6:0] \$1044 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) + wire \$1046 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wire \$1049 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1051 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + wire \$1053 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1055 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wire \$1059 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) wire [6:0] \$1062 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) wire \$1064 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wire \$1067 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1071 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1073 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) - wire \$1079 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) - wire [6:0] \$1082 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) - wire \$1084 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$1087 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1091 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1081 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire [6:0] \$1084 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) + wire \$1086 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) + wire \$1089 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1093 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) - wire \$1099 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) - wire [6:0] \$1102 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) - wire \$1104 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$1107 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1111 ; + wire \$1095 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1101 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire [6:0] \$1104 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) + wire \$1106 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) + wire \$1109 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1113 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) - wire \$1118 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) - wire [6:0] \$1121 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) - wire \$1123 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$1126 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1130 ; + wire \$1115 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1121 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire [6:0] \$1124 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) + wire \$1126 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) + wire \$1129 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1132 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) - wire \$1136 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) - wire [6:0] \$1139 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) - wire \$1141 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$1144 ; + wire \$1133 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1147 ; + wire \$1135 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1140 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire [6:0] \$1143 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) + wire \$1145 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) + wire \$1148 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1149 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wire \$1152 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) - wire [6:0] \$1155 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1154 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1158 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire [6:0] \$1161 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) + wire \$1163 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) + wire \$1166 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1169 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1171 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1174 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire [6:0] \$1177 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [64:0] \$1157 ; + wire [64:0] \$1179 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [63:0] \$1158 ; + wire [63:0] \$1180 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [63:0] \$1160 ; + wire [63:0] \$1182 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [63:0] \$1162 ; + wire [63:0] \$1184 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [63:0] \$1164 ; + wire [63:0] \$1186 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [63:0] \$1166 ; + wire [63:0] \$1188 ; (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:258" *) - wire [64:0] \$1168 ; + wire [64:0] \$1190 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [64:0] \$1170 ; + wire [64:0] \$1192 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [64:0] \$1172 ; + wire [64:0] \$1194 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [64:0] \$1174 ; + wire [64:0] \$1196 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [6:0] \$1176 ; + wire [6:0] \$1198 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [6:0] \$1177 ; + wire [6:0] \$1199 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [6:0] \$1179 ; + wire [6:0] \$1201 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [6:0] \$1181 ; + wire [6:0] \$1203 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [6:0] \$1183 ; + wire [6:0] \$1205 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [6:0] \$1185 ; + wire [6:0] \$1207 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [6:0] \$1187 ; + wire [6:0] \$1209 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [6:0] \$1189 ; + wire [6:0] \$1211 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [6:0] \$1191 ; + wire [6:0] \$1213 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [6:0] \$1193 ; + wire [6:0] \$1215 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire \$1195 ; + wire \$1217 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire \$1197 ; + wire \$1219 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire \$1199 ; + wire \$1221 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire \$1201 ; + wire \$1223 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire \$1203 ; + wire \$1225 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire \$1205 ; + wire \$1227 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire \$1207 ; + wire \$1229 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire \$1209 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire \$1211 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) - wire \$1213 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) - wire \$1215 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$1218 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1221 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1223 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) - wire \$1226 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) - wire [7:0] \$1229 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) wire \$1231 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) wire \$1233 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) wire \$1235 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) wire \$1237 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) - wire \$1239 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) - wire \$1241 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) - wire \$1243 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$1246 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) + wire \$1240 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1249 ; + wire \$1243 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1251 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) - wire \$1254 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) - wire [7:0] \$1257 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) - wire [255:0] \$1259 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) - wire [255:0] \$1261 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire \$1245 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1248 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire [7:0] \$1251 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) + wire \$1253 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) + wire \$1255 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) + wire \$1257 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) + wire \$1259 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) + wire \$1261 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) wire \$1263 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$1266 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1269 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) + wire \$1265 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) + wire \$1268 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1271 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) - wire \$1274 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) - wire [7:0] \$1277 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) - wire [255:0] \$1279 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) - wire [255:0] \$1281 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) - wire \$1283 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$1286 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1289 ; + wire \$1273 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1276 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) + wire [7:0] \$1279 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) + wire [255:0] \$1281 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire [255:0] \$1283 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) + wire \$1285 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) + wire \$1288 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1291 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) - wire \$1294 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) - wire [7:0] \$1297 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) - wire [255:0] \$1299 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) - wire [255:0] \$1301 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) - wire \$1303 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$1306 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1309 ; + wire \$1293 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1296 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) + wire [7:0] \$1299 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) + wire [255:0] \$1301 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire [255:0] \$1303 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) + wire \$1305 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) + wire \$1308 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1311 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) - wire \$1314 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) - wire [7:0] \$1317 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) - wire [255:0] \$1319 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) - wire [255:0] \$1321 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) - wire \$1323 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$1326 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1329 ; + wire \$1313 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1316 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) + wire [7:0] \$1319 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) + wire [255:0] \$1321 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire [255:0] \$1323 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) + wire \$1325 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) + wire \$1328 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1331 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) - wire \$1334 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) - wire [7:0] \$1337 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) - wire [255:0] \$1339 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) - wire [255:0] \$1341 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) - wire \$1343 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$1346 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1349 ; + wire \$1333 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1336 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) + wire [7:0] \$1339 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) + wire [255:0] \$1341 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire [255:0] \$1343 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) + wire \$1345 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) + wire \$1348 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1351 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) - wire \$1354 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) - wire [7:0] \$1357 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) - wire [255:0] \$1359 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1353 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1356 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) + wire [7:0] \$1359 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) wire [255:0] \$1361 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire [255:0] \$1363 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) + wire \$1365 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) + wire \$1368 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1371 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1373 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1376 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) + wire [7:0] \$1379 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) + wire [255:0] \$1381 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire [255:0] \$1383 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [3:0] \$1363 ; + wire [3:0] \$1385 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [3:0] \$1365 ; + wire [3:0] \$1387 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [3:0] \$1367 ; + wire [3:0] \$1389 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [3:0] \$1369 ; + wire [3:0] \$1391 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [3:0] \$1371 ; + wire [3:0] \$1393 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [255:0] \$1373 ; + wire [255:0] \$1395 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [255:0] \$1374 ; + wire [255:0] \$1396 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [255:0] \$1376 ; + wire [255:0] \$1398 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [255:0] \$1378 ; + wire [255:0] \$1400 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [255:0] \$1380 ; + wire [255:0] \$1402 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [255:0] \$1382 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) - wire \$1384 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) - wire \$1386 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) - wire \$1388 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) - wire \$1390 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$1393 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1396 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1398 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) - wire \$1401 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) - wire [1:0] \$1404 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire [255:0] \$1404 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) wire \$1406 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$1409 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) + wire \$1408 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) + wire \$1410 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) wire \$1412 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) + wire \$1415 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1414 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) - wire \$1417 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) - wire [1:0] \$1420 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) - wire \$1422 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$1425 ; + wire \$1418 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1420 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1423 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire [1:0] \$1426 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) wire \$1428 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) + wire \$1431 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1434 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1436 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1439 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire [1:0] \$1442 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) + wire \$1444 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) + wire \$1447 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1430 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) - wire \$1433 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) - wire [1:0] \$1436 ; + wire \$1450 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1452 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1455 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire [1:0] \$1458 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [1:0] \$1438 ; + wire [1:0] \$1460 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [1:0] \$1440 ; + wire [1:0] \$1462 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [2:0] \$1442 ; + wire [2:0] \$1464 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [1:0] \$1443 ; + wire [1:0] \$1465 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [1:0] \$1445 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) - wire \$1448 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) - wire \$1450 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) - wire \$1452 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) - wire \$1454 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) - wire \$1456 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$1459 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1462 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1464 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) - wire \$1467 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) - wire [2:0] \$1470 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + wire [1:0] \$1467 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) + wire \$1470 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) wire \$1472 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$1475 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) + wire \$1474 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) + wire \$1476 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) wire \$1478 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) + wire \$1481 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1480 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) - wire \$1483 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) - wire [2:0] \$1486 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) - wire \$1488 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$1491 ; + wire \$1484 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1486 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1489 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire [2:0] \$1492 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) wire \$1494 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) + wire \$1497 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1496 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) - wire \$1499 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) - wire [2:0] \$1502 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) - wire \$1504 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$1507 ; + wire \$1500 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1502 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1505 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire [2:0] \$1508 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) wire \$1510 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) + wire \$1513 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1512 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) - wire \$1515 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) - wire [2:0] \$1518 ; + wire \$1516 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1518 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1521 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire [2:0] \$1524 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) + wire \$1526 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) + wire \$1529 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1532 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1534 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1537 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire [2:0] \$1540 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [1:0] \$1520 ; + wire [1:0] \$1542 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [1:0] \$1522 ; + wire [1:0] \$1544 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [1:0] \$1524 ; + wire [1:0] \$1546 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [2:0] \$1526 ; + wire [2:0] \$1548 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [2:0] \$1528 ; + wire [2:0] \$1550 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [2:0] \$1530 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) - wire \$1532 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) - wire \$1534 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) - wire \$1536 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) - wire \$1538 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) - wire \$1540 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$1543 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1546 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1548 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) - wire \$1551 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) + wire [2:0] \$1552 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) wire \$1554 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) wire \$1556 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$1559 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) + wire \$1558 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) + wire \$1560 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) wire \$1562 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) + wire \$1565 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1564 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) - wire \$1567 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) - wire \$1570 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) - wire \$1572 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$1575 ; + wire \$1568 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1570 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1573 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire \$1576 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) wire \$1578 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) + wire \$1581 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1580 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) - wire \$1583 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) - wire \$1586 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) - wire \$1588 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$1591 ; + wire \$1584 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1586 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1589 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire \$1592 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) wire \$1594 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) + wire \$1597 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1600 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1596 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) - wire \$1599 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wire \$1602 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1605 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire \$1608 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) + wire \$1610 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) + wire \$1613 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1616 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1618 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1621 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire \$1624 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [1:0] \$1604 ; + wire [1:0] \$1626 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire \$1605 ; + wire \$1627 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire \$1607 ; + wire \$1629 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire \$1609 ; + wire \$1631 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [2:0] \$1612 ; + wire [2:0] \$1634 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire \$1613 ; + wire \$1635 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire \$1615 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire \$1617 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) - wire \$1620 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) - wire \$1622 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) - wire \$1624 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) - wire \$1626 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) - wire \$1628 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) - wire \$1630 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$1633 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$1637 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) wire \$1639 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) + wire \$1642 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) wire \$1644 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) - wire [2:0] \$1647 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) - wire \$1649 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) + wire \$1646 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) + wire \$1648 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) + wire \$1650 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) wire \$1652 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1655 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) + wire \$1654 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wire \$1657 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) - wire \$1660 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) - wire [2:0] \$1663 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) - wire \$1665 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$1668 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1671 ; + wire \$1661 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1663 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1668 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire [2:0] \$1671 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) wire \$1673 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wire \$1676 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) - wire [2:0] \$1679 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) - wire \$1681 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$1684 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1687 ; + wire \$1679 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1681 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1684 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire [2:0] \$1687 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) wire \$1689 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wire \$1692 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) - wire [2:0] \$1695 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) - wire \$1697 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$1700 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1703 ; + wire \$1695 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1697 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1700 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire [2:0] \$1703 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) wire \$1705 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wire \$1708 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) - wire [2:0] \$1711 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1711 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1713 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1716 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire [2:0] \$1719 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) + wire \$1721 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) + wire \$1724 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1727 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1729 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1732 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire [2:0] \$1735 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) + wire \$1737 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) + wire \$1740 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1743 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1745 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1748 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire [2:0] \$1751 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [63:0] \$1713 ; + wire [63:0] \$1753 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [63:0] \$1755 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [63:0] \$1715 ; + wire [63:0] \$1757 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [63:0] \$1759 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [63:0] \$1717 ; + wire [63:0] \$1761 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [63:0] \$1719 ; + wire [3:0] \$1763 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [2:0] \$1721 ; + wire [2:0] \$1764 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [2:0] \$1766 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [2:0] \$1723 ; + wire [2:0] \$1768 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [2:0] \$1725 ; + wire [2:0] \$1770 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [2:0] \$1727 ; + wire [2:0] \$1772 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire \$1729 ; + wire \$1775 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire \$1777 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire \$1731 ; + wire \$1779 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire \$1733 ; + wire \$1781 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire \$1735 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) - wire \$1737 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) - wire \$1739 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) - wire \$1741 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$1744 ; + wire \$1783 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) + wire \$1785 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) + wire \$1787 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) + wire \$1789 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) + wire \$1792 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1747 ; + wire \$1795 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1749 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) - wire \$1752 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) - wire \$1755 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) - wire \$1757 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$1760 ; + wire \$1797 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1800 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire \$1803 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) + wire \$1805 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) + wire \$1808 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1763 ; + wire \$1811 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1765 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) - wire \$1768 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) - wire \$1771 ; + wire \$1813 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1816 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire \$1819 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [63:0] \$1773 ; + wire [63:0] \$1821 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [2:0] \$1775 ; + wire [2:0] \$1823 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire \$1776 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) - wire \$1779 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) - wire \$1781 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$1784 ; + wire \$1824 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) + wire \$1827 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) + wire \$1829 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) + wire \$1832 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1787 ; + wire \$1835 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1789 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) - wire \$1792 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) - wire [1:0] \$1795 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire [2:0] \$1797 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) - wire \$1799 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) - wire \$1801 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$1804 ; + wire \$1837 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1840 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire [1:0] \$1843 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire [2:0] \$1845 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) + wire \$1847 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) + wire \$1849 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) + wire \$185 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) + wire \$1852 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1807 ; + wire \$1855 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$1809 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) - wire \$181 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) - wire \$1812 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) - wire [9:0] \$1815 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) - wire [13:0] \$182 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) - wire \$185 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) - wire [13:0] \$186 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) + wire \$1857 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) + wire [14:0] \$186 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1860 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire [2:0] \$1863 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [63:0] \$1865 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) + wire \$1867 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) + wire \$1869 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) + wire \$1872 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1875 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$1877 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) + wire \$1880 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) + wire [9:0] \$1883 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) wire \$189 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) - wire [13:0] \$190 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) + wire [14:0] \$190 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) wire \$193 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) - wire [13:0] \$194 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) + wire [14:0] \$194 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) wire \$197 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) - wire [13:0] \$198 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) + wire [14:0] \$198 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) wire \$201 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) - wire [13:0] \$202 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) + wire [14:0] \$202 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) wire \$205 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) - wire [13:0] \$206 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) + wire [14:0] \$206 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) wire \$209 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) - wire [13:0] \$210 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) + wire [14:0] \$210 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) wire \$213 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) - wire [13:0] \$214 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) + wire [14:0] \$214 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) wire \$217 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) - wire [13:0] \$218 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) + wire [14:0] \$218 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) wire \$221 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" *) - wire [2:0] \$223 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" *) - wire [2:0] \$224 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" *) - wire \$226 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) - wire [3:0] \$228 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) - wire \$229 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) - wire [2:0] \$231 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) + wire [14:0] \$222 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216" *) + wire \$225 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" *) + wire [2:0] \$227 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" *) + wire [2:0] \$228 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216" *) + wire \$230 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) + wire [3:0] \$232 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$233 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) - wire \$235 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) + wire [2:0] \$235 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$237 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$239 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) wire \$241 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) - wire [2:0] \$243 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) + wire \$243 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:86" *) wire \$245 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) - wire \$247 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) - wire [5:0] \$250 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) - wire [2:0] \$252 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) - wire [3:0] \$254 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) + wire [2:0] \$247 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) + wire \$249 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) + wire \$251 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) + wire [5:0] \$254 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) wire [2:0] \$256 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) - wire \$257 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) - wire [2:0] \$259 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) + wire [4:0] \$258 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) + wire [2:0] \$260 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$261 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) - wire \$263 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) + wire [2:0] \$263 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$265 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$267 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) - wire [5:0] \$270 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) + wire \$269 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) wire \$271 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) - wire [2:0] \$273 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) + wire [5:0] \$274 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$275 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) - wire \$277 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) + wire [2:0] \$277 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$279 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$281 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) wire \$283 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) - wire [2:0] \$285 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) + wire \$285 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:83" *) wire \$287 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) - wire \$289 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) + wire [2:0] \$289 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) wire \$291 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) - wire [2:0] \$293 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) + wire \$293 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:86" *) wire \$295 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) - wire \$297 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) - wire [2:0] \$300 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) + wire [2:0] \$297 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) + wire \$299 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) wire \$301 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) - wire [2:0] \$303 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) + wire [2:0] \$304 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$305 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) - wire \$307 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) + wire [2:0] \$307 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$309 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$311 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) - wire [2:0] \$314 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) + wire \$313 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) wire \$315 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) - wire [2:0] \$317 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) + wire [2:0] \$318 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$319 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) - wire \$321 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) + wire [2:0] \$321 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$323 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$325 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) - wire [4:0] \$328 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) + wire \$327 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) wire \$329 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) - wire [2:0] \$331 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) + wire [4:0] \$332 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$333 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) - wire \$335 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) + wire [2:0] \$335 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$337 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$339 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) wire \$341 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) - wire [2:0] \$343 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) + wire \$343 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:86" *) wire \$345 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) - wire \$347 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) - wire [2:0] \$350 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$352 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$354 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) + wire [2:0] \$347 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) + wire \$349 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) + wire \$351 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) + wire [2:0] \$354 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$356 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$358 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$360 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [6:0] \$362 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + wire \$362 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) wire \$364 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$366 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [6:0] \$366 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$368 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$370 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$372 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [6:0] \$374 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + wire \$374 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) wire \$376 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$378 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [6:0] \$378 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$380 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$382 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$384 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [6:0] \$386 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + wire \$386 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) wire \$388 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$390 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [6:0] \$390 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$392 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$394 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$396 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [6:0] \$398 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + wire \$398 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) wire \$400 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$402 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [6:0] \$402 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$404 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$406 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$408 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [6:0] \$410 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + wire \$410 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) wire \$412 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$414 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [6:0] \$414 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$416 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$418 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$420 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [6:0] \$422 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + wire \$422 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) wire \$424 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$426 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [6:0] \$426 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$428 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$430 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$432 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [6:0] \$434 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + wire \$434 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) wire \$436 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$438 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [6:0] \$438 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$440 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$442 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$444 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [6:0] \$446 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + wire \$446 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) wire \$448 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$450 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [6:0] \$450 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$452 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$454 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$456 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [6:0] \$458 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + wire \$458 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) wire \$460 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$462 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [6:0] \$462 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$464 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$466 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$468 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [6:0] \$470 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + wire \$470 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) wire \$472 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$474 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [6:0] \$474 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$476 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$478 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$480 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [6:0] \$482 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + wire \$482 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) wire \$484 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$486 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [6:0] \$486 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$488 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$490 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$492 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [6:0] \$494 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + wire \$494 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) wire \$496 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$498 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [6:0] \$498 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$500 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$502 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$504 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [6:0] \$506 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + wire \$506 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) wire \$508 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$510 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [6:0] \$510 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$512 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$514 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$516 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [6:0] \$518 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + wire \$518 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) wire \$520 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$522 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [6:0] \$522 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$524 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$526 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$528 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [6:0] \$530 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + wire \$530 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) wire \$532 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$534 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [6:0] \$534 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$536 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$538 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$540 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [6:0] \$542 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + wire \$542 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) wire \$544 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$546 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [6:0] \$546 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$548 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$550 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$552 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [6:0] \$554 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + wire \$554 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) wire \$556 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$558 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [6:0] \$558 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$560 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$562 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$564 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [6:0] \$566 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + wire \$566 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) wire \$568 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$570 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [6:0] \$570 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$572 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$574 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$576 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [6:0] \$578 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + wire \$578 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) + wire \$580 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [6:0] \$582 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [6:0] \$580 ; + wire [6:0] \$584 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [6:0] \$581 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [6:0] \$583 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) wire [6:0] \$585 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) wire [6:0] \$587 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [6:0] \$589 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [6:0] \$589 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) wire [6:0] \$591 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) wire [6:0] \$593 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) wire [6:0] \$595 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) wire [6:0] \$597 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [6:0] \$599 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [6:0] \$599 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) wire [6:0] \$601 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [6:0] \$603 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire [6:0] \$603 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) wire [6:0] \$605 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [6:0] \$607 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [6:0] \$607 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) wire [6:0] \$609 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) wire [6:0] \$611 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) wire [6:0] \$613 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) wire [6:0] \$615 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:325" *) - wire \$617 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) - wire \$619 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) - wire [2:0] \$621 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [6:0] \$617 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [6:0] \$619 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:343" *) + wire \$621 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$623 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) - wire \$625 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) + wire [2:0] \$625 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$627 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) wire \$629 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) wire \$631 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) wire \$633 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$635 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$637 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$639 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$641 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) wire \$643 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) wire \$645 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$647 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$649 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$651 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$653 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) wire \$655 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) wire \$657 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$659 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$661 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$663 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$665 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) wire \$667 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) wire \$669 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$671 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$673 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$675 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$677 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) wire \$679 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) wire \$681 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$683 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$685 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$687 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$689 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) wire \$691 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) wire \$693 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$695 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$697 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$699 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$701 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) + wire \$703 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire \$705 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [2:0] \$703 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire \$704 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire \$706 ; + wire [2:0] \$707 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) wire \$708 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) wire \$710 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) wire \$712 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" *) - wire \$715 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) - wire [2:0] \$717 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire \$714 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire \$716 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:86" *) wire \$719 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) - wire \$721 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) + wire [2:0] \$721 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) wire \$723 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) wire \$725 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$727 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$729 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$731 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [1:0] \$733 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + wire \$733 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) wire \$735 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$737 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [1:0] \$737 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$739 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$741 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$743 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [1:0] \$745 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + wire \$745 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) wire \$747 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$749 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [1:0] \$749 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$751 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$753 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$755 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [1:0] \$757 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + wire \$757 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) + wire \$759 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [1:0] \$761 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [2:0] \$759 ; + wire [2:0] \$763 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [1:0] \$760 ; + wire [1:0] \$764 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [1:0] \$762 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" *) - wire \$765 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) - wire [2:0] \$767 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) + wire [1:0] \$766 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:83" *) wire \$769 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) - wire \$771 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) + wire [2:0] \$771 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) wire \$773 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) wire \$775 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$777 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$779 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$781 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [2:0] \$783 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + wire \$783 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) wire \$785 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$787 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [2:0] \$787 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$789 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$791 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$793 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [7:0] \$795 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + wire \$795 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) wire \$797 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$799 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [7:0] \$799 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$801 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$803 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$805 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *) - wire [7:0] \$807 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *) - wire [255:0] \$809 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [255:0] \$811 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$813 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$815 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + wire \$807 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) + wire \$809 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:64" *) + wire [7:0] \$811 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:64" *) + wire [255:0] \$813 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [255:0] \$815 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$817 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$819 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$821 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *) - wire [7:0] \$823 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *) - wire [255:0] \$825 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [255:0] \$827 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + wire \$823 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) + wire \$825 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:64" *) + wire [7:0] \$827 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:64" *) wire [255:0] \$829 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [255:0] \$831 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire [255:0] \$833 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [255:0] \$830 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$832 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$834 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + wire [255:0] \$834 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$836 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$838 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$840 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" *) - wire [7:0] \$842 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" *) - wire [255:0] \$844 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [255:0] \$846 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$848 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$850 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + wire \$842 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) + wire \$844 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:66" *) + wire [7:0] \$846 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:66" *) + wire [255:0] \$848 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [255:0] \$850 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$852 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$854 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$856 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" *) - wire [7:0] \$858 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" *) - wire [255:0] \$860 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [255:0] \$862 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$864 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$866 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + wire \$858 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) + wire \$860 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:68" *) + wire [7:0] \$862 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:68" *) + wire [255:0] \$864 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [255:0] \$866 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$868 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$870 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$872 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [2:0] \$874 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + wire \$874 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) wire \$876 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$878 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [2:0] \$878 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$880 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$882 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$884 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [2:0] \$886 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + wire \$886 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) wire \$888 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$890 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [2:0] \$890 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$892 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$894 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$896 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [2:0] \$898 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + wire \$898 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) wire \$900 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$902 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [2:0] \$902 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$904 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$906 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$908 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [2:0] \$910 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + wire \$910 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) wire \$912 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) - wire \$914 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [2:0] \$914 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$916 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$918 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$920 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [2:0] \$922 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [2:0] \$924 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + wire \$922 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) + wire \$924 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) wire [2:0] \$926 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [2:0] \$928 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) - wire [2:0] \$930 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:325" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) + wire \$928 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) + wire \$930 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$932 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$934 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) wire \$936 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) - wire \$938 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) - wire \$940 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) - wire \$942 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) - wire [9:0] \$944 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:325" *) - wire \$946 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) - wire \$948 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) - wire \$950 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [2:0] \$938 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [3:0] \$940 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire [2:0] \$941 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [2:0] \$943 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + wire [2:0] \$945 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [2:0] \$947 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [2:0] \$949 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:343" *) wire \$952 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$954 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) wire \$956 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$958 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) wire \$960 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) wire \$962 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) - wire \$964 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) + wire [9:0] \$964 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:343" *) wire \$966 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) wire \$968 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) wire \$970 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) wire \$972 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) wire \$974 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) + wire \$976 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) + wire \$978 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) wire \$980 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) - wire [6:0] \$982 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) + wire \$982 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) wire \$984 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) - wire \$987 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) + wire \$986 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) + wire \$988 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) + wire \$990 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$991 ; + wire \$992 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$993 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) - wire \$998 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) + wire \$994 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] ALU__SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire ALU__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire ALU__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] ALU__sv_saturate; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] BRANCH__SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire BRANCH__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire BRANCH__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] BRANCH__sv_saturate; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] CR__SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire CR__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire CR__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] CR__sv_saturate; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] DIV__SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire DIV__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire DIV__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] DIV__sv_saturate; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] LDST__SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire LDST__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire LDST__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] LDST__sv_saturate; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] LOGICAL__SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire LOGICAL__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire LOGICAL__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] LOGICAL__sv_saturate; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] MUL__SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire MUL__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire MUL__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] MUL__sv_saturate; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] SHIFT_ROT__SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire SHIFT_ROT__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire SHIFT_ROT__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] SHIFT_ROT__sv_saturate; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] SPR__SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire SPR__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire SPR__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] SPR__sv_saturate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) wire [6:0] addr_en; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire [6:0] \addr_en$1000 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire [6:0] \addr_en$1021 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire [6:0] \addr_en$1039 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire [6:0] \addr_en$1020 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire [6:0] \addr_en$1043 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) wire [6:0] \addr_en$1061 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire [6:0] \addr_en$1081 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire [6:0] \addr_en$1101 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire [6:0] \addr_en$1120 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire [6:0] \addr_en$1138 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire [6:0] \addr_en$1154 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire [7:0] \addr_en$1228 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire [255:0] \addr_en$1256 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire [255:0] \addr_en$1276 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire [255:0] \addr_en$1296 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire [255:0] \addr_en$1316 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire [255:0] \addr_en$1336 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire [255:0] \addr_en$1356 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire [1:0] \addr_en$1403 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire [1:0] \addr_en$1419 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire [1:0] \addr_en$1435 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire [2:0] \addr_en$1469 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire [2:0] \addr_en$1485 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire [2:0] \addr_en$1501 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire [2:0] \addr_en$1517 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire \addr_en$1553 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire \addr_en$1569 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire \addr_en$1585 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire \addr_en$1601 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire [2:0] \addr_en$1646 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire [2:0] \addr_en$1662 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire [2:0] \addr_en$1678 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire [2:0] \addr_en$1694 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire [2:0] \addr_en$1710 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire \addr_en$1754 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire \addr_en$1770 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire [1:0] \addr_en$1794 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) - wire [9:0] \addr_en$1814 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire [6:0] \addr_en$1083 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire [6:0] \addr_en$1103 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire [6:0] \addr_en$1123 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire [6:0] \addr_en$1142 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire [6:0] \addr_en$1160 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire [6:0] \addr_en$1176 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire [7:0] \addr_en$1250 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire [255:0] \addr_en$1278 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire [255:0] \addr_en$1298 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire [255:0] \addr_en$1318 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire [255:0] \addr_en$1338 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire [255:0] \addr_en$1358 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire [255:0] \addr_en$1378 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire [1:0] \addr_en$1425 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire [1:0] \addr_en$1441 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire [1:0] \addr_en$1457 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire [2:0] \addr_en$1491 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire [2:0] \addr_en$1507 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire [2:0] \addr_en$1523 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire [2:0] \addr_en$1539 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire \addr_en$1575 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire \addr_en$1591 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire \addr_en$1607 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire \addr_en$1623 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire [2:0] \addr_en$1670 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire [2:0] \addr_en$1686 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire [2:0] \addr_en$1702 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire [2:0] \addr_en$1718 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire [2:0] \addr_en$1734 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire [2:0] \addr_en$1750 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire \addr_en$1802 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire \addr_en$1818 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire [1:0] \addr_en$1842 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire [2:0] \addr_en$1862 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) + wire [9:0] \addr_en$1882 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [255:0] addr_en_CR_cr_a_branch0_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [255:0] addr_en_CR_cr_a_cr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [255:0] addr_en_CR_cr_b_cr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [255:0] addr_en_CR_cr_c_cr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [7:0] addr_en_CR_full_cr_cr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [2:0] addr_en_FAST_fast1_branch0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [2:0] addr_en_FAST_fast1_branch0_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [2:0] addr_en_FAST_fast1_spr0_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [2:0] addr_en_FAST_fast1_trap0_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [2:0] addr_en_FAST_fast1_trap0_4; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) + wire [2:0] addr_en_FAST_fast1_trap0_5; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [6:0] addr_en_INT_rabc_alu0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [6:0] addr_en_INT_rabc_alu0_10; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [6:0] addr_en_INT_rabc_cr0_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [6:0] addr_en_INT_rabc_cr0_11; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [6:0] addr_en_INT_rabc_div0_15; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [6:0] addr_en_INT_rabc_div0_4; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [6:0] addr_en_INT_rabc_ldst0_18; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [6:0] addr_en_INT_rabc_ldst0_7; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [6:0] addr_en_INT_rabc_ldst0_9; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [6:0] addr_en_INT_rabc_logical0_13; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [6:0] addr_en_INT_rabc_logical0_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [6:0] addr_en_INT_rabc_mul0_16; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [6:0] addr_en_INT_rabc_mul0_5; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [6:0] addr_en_INT_rabc_shiftrot0_17; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [6:0] addr_en_INT_rabc_shiftrot0_6; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [6:0] addr_en_INT_rabc_shiftrot0_8; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [6:0] addr_en_INT_rabc_spr0_14; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [6:0] addr_en_INT_rabc_trap0_12; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [6:0] addr_en_INT_rabc_trap0_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [9:0] addr_en_SPR_spr1_spr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [1:0] addr_en_XER_xer_ca_alu0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [1:0] addr_en_XER_xer_ca_shiftrot0_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [1:0] addr_en_XER_xer_ca_spr0_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire [2:0] addr_en_XER_xer_ov_spr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire addr_en_XER_xer_so_alu0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire addr_en_XER_xer_so_div0_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire addr_en_XER_xer_so_logical0_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire addr_en_XER_xer_so_mul0_4; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire addr_en_XER_xer_so_shiftrot0_5; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302" *) wire addr_en_XER_xer_so_spr0_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" *) input bigendian_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) output [63:0] cia__data_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [2:0] cia__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [1:0] core_core__SV_Ptype; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input core_core__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input core_core__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [1:0] core_core__sv_saturate; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:46" *) input [63:0] core_core_cia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [7:0] core_core_cr_rd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input core_core_cr_rd_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [7:0] core_core_cr_wr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) input \core_core_exc_$signal ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) input \core_core_exc_$signal$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) input \core_core_exc_$signal$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) input \core_core_exc_$signal$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) input \core_core_exc_$signal$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) input \core_core_exc_$signal$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) input \core_core_exc_$signal$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) input \core_core_exc_$signal$9 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" *) - input [13:0] core_core_fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:52" *) + input [14:0] core_core_fn_unit; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:56" *) input [1:0] core_core_input_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:50" *) input [31:0] core_core_insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -37620,67 +41255,79 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:51" *) input [6:0] core_core_insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:62" *) input core_core_is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:45" *) input [63:0] core_core_msr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input core_core_oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input core_core_oe_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input core_core_rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input core_core_rc_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:47" *) + input [31:0] core_core_svstate; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:59" *) input [12:0] core_core_trapaddr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:57" *) input [7:0] core_core_traptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [6:0] core_cr_in1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input core_cr_in1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [6:0] core_cr_in2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [6:0] \core_cr_in2$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input core_cr_in2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input \core_cr_in2_ok$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [6:0] core_cr_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [6:0] core_ea; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [2:0] core_fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input core_fast1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [2:0] core_fast2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input core_fast2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + input [2:0] core_fast3; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + input core_fast3_ok; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [2:0] core_fasto1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [2:0] core_fasto2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + input [2:0] core_fasto3; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:17" *) + input [63:0] core_msr; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:16" *) input [63:0] core_pc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [6:0] core_reg1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input core_reg1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [6:0] core_reg2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input core_reg2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [6:0] core_reg3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input core_reg3_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [6:0] core_rego; (* enum_base_type = "SPR" *) (* enum_value_0000010010 = "DSISR" *) @@ -37694,9 +41341,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* enum_value_1011000000 = "SVSTATE" *) (* enum_value_1011010000 = "PRTBL" *) (* enum_value_1011010001 = "SVSRR0" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [9:0] core_spr1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input core_spr1_ok; (* enum_base_type = "SPR" *) (* enum_value_0000010010 = "DSISR" *) @@ -37710,25 +41357,25 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* enum_value_1011000000 = "SVSTATE" *) (* enum_value_1011010000 = "PRTBL" *) (* enum_value_1011010001 = "SVSRR0" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [9:0] core_spro; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:110" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:123" *) output core_terminate_o; reg core_terminate_o = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:110" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:123" *) reg \core_terminate_o$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:114" *) input [2:0] core_xer_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:107" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:120" *) output corebusy_o; reg corebusy_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" *) reg [1:0] counter = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" *) reg [1:0] \counter$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [3:0] cr_data_i; @@ -37784,36 +41431,37 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c output dbus__stb; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) output dbus__we; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [3:0] dec_ALU_ALU__data_len; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] dec_ALU_ALU__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] dec_ALU_ALU__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] dec_ALU_ALU__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_ALU_ALU__imm_data__ok; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [1:0] dec_ALU_ALU__input_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] dec_ALU_ALU__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -37890,60 +41538,63 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] dec_ALU_ALU__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_ALU_ALU__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_ALU_ALU__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_ALU_ALU__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_ALU_ALU__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_ALU_ALU__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_ALU_ALU__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_ALU_ALU__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_ALU_ALU__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_ALU_ALU__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_ALU_ALU__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_ALU_ALU__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:479" *) wire dec_ALU_bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:478" *) wire [31:0] dec_ALU_raw_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:747" *) wire dec_ALU_sv_a_nz; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] dec_BRANCH_BRANCH__cia; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] dec_BRANCH_BRANCH__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] dec_BRANCH_BRANCH__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] dec_BRANCH_BRANCH__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_BRANCH_BRANCH__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] dec_BRANCH_BRANCH__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -38020,34 +41671,37 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] dec_BRANCH_BRANCH__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_BRANCH_BRANCH__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_BRANCH_BRANCH__lk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:479" *) wire dec_BRANCH_bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:478" *) wire [31:0] dec_BRANCH_raw_opcode_in; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] dec_CR_CR__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] dec_CR_CR__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] dec_CR_CR__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -38124,42 +41778,45 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] dec_CR_CR__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:479" *) wire dec_CR_bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:478" *) wire [31:0] dec_CR_raw_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [3:0] dec_DIV_DIV__data_len; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] dec_DIV_DIV__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] dec_DIV_DIV__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] dec_DIV_DIV__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_DIV_DIV__imm_data__ok; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [1:0] dec_DIV_DIV__input_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] dec_DIV_DIV__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -38236,62 +41893,65 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] dec_DIV_DIV__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_DIV_DIV__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_DIV_DIV__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_DIV_DIV__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_DIV_DIV__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_DIV_DIV__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_DIV_DIV__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_DIV_DIV__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_DIV_DIV__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_DIV_DIV__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_DIV_DIV__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_DIV_DIV__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:479" *) wire dec_DIV_bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:478" *) wire [31:0] dec_DIV_raw_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:747" *) wire dec_DIV_sv_a_nz; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_LDST_LDST__byte_reverse; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [3:0] dec_LDST_LDST__data_len; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] dec_LDST_LDST__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] dec_LDST_LDST__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] dec_LDST_LDST__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_LDST_LDST__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] dec_LDST_LDST__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -38368,67 +42028,72 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] dec_LDST_LDST__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_LDST_LDST__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_LDST_LDST__is_signed; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [1:0] dec_LDST_LDST__ldst_mode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] dec_LDST_LDST__msr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_LDST_LDST__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_LDST_LDST__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_LDST_LDST__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_LDST_LDST__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_LDST_LDST__sign_extend; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_LDST_LDST__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:479" *) wire dec_LDST_bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:478" *) wire [31:0] dec_LDST_raw_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:747" *) wire dec_LDST_sv_a_nz; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [3:0] dec_LOGICAL_LOGICAL__data_len; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] dec_LOGICAL_LOGICAL__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] dec_LOGICAL_LOGICAL__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] dec_LOGICAL_LOGICAL__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_LOGICAL_LOGICAL__imm_data__ok; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [1:0] dec_LOGICAL_LOGICAL__input_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] dec_LOGICAL_LOGICAL__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -38505,58 +42170,61 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] dec_LOGICAL_LOGICAL__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_LOGICAL_LOGICAL__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_LOGICAL_LOGICAL__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_LOGICAL_LOGICAL__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_LOGICAL_LOGICAL__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_LOGICAL_LOGICAL__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_LOGICAL_LOGICAL__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_LOGICAL_LOGICAL__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_LOGICAL_LOGICAL__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_LOGICAL_LOGICAL__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_LOGICAL_LOGICAL__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_LOGICAL_LOGICAL__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:479" *) wire dec_LOGICAL_bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:478" *) wire [31:0] dec_LOGICAL_raw_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:747" *) wire dec_LOGICAL_sv_a_nz; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] dec_MUL_MUL__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] dec_MUL_MUL__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] dec_MUL_MUL__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_MUL_MUL__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] dec_MUL_MUL__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -38633,56 +42301,59 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] dec_MUL_MUL__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_MUL_MUL__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_MUL_MUL__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_MUL_MUL__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_MUL_MUL__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_MUL_MUL__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_MUL_MUL__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_MUL_MUL__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:479" *) wire dec_MUL_bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:478" *) wire [31:0] dec_MUL_raw_opcode_in; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] dec_SHIFT_ROT_SHIFT_ROT__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] dec_SHIFT_ROT_SHIFT_ROT__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] dec_SHIFT_ROT_SHIFT_ROT__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_SHIFT_ROT_SHIFT_ROT__imm_data__ok; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [1:0] dec_SHIFT_ROT_SHIFT_ROT__input_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_SHIFT_ROT_SHIFT_ROT__input_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] dec_SHIFT_ROT_SHIFT_ROT__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -38759,50 +42430,53 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] dec_SHIFT_ROT_SHIFT_ROT__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_SHIFT_ROT_SHIFT_ROT__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_SHIFT_ROT_SHIFT_ROT__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_SHIFT_ROT_SHIFT_ROT__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_SHIFT_ROT_SHIFT_ROT__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_SHIFT_ROT_SHIFT_ROT__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_SHIFT_ROT_SHIFT_ROT__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_SHIFT_ROT_SHIFT_ROT__output_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_SHIFT_ROT_SHIFT_ROT__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_SHIFT_ROT_SHIFT_ROT__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_SHIFT_ROT_SHIFT_ROT__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:479" *) wire dec_SHIFT_ROT_bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:478" *) wire [31:0] dec_SHIFT_ROT_raw_opcode_in; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] dec_SPR_SPR__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] dec_SPR_SPR__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] dec_SPR_SPR__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -38879,13 +42553,15 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] dec_SPR_SPR__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dec_SPR_SPR__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:479" *) wire dec_SPR_bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:478" *) wire [31:0] dec_SPR_raw_opcode_in; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [4:0] dmi__addr; @@ -38893,201 +42569,207 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c output [63:0] dmi__data_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input dmi__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_CR_cr_a_branch0_1 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_CR_cr_a_branch0_1$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_CR_cr_a_cr0_0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_CR_cr_a_cr0_0$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_CR_cr_b_cr0_0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_CR_cr_b_cr0_0$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_CR_cr_c_cr0_0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_CR_cr_c_cr0_0$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_CR_full_cr_cr0_0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_CR_full_cr_cr0_0$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_FAST_fast1_branch0_0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_FAST_fast1_branch0_0$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_FAST_fast1_branch0_3 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_FAST_fast1_branch0_3$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_FAST_fast1_spr0_2 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_FAST_fast1_spr0_2$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_FAST_fast1_trap0_1 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_FAST_fast1_trap0_1$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_FAST_fast1_trap0_4 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_FAST_fast1_trap0_4$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) + reg dp_FAST_fast1_trap0_5 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) + reg \dp_FAST_fast1_trap0_5$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_INT_rabc_alu0_0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_INT_rabc_alu0_0$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_INT_rabc_alu0_10 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_INT_rabc_alu0_10$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_INT_rabc_cr0_1 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_INT_rabc_cr0_1$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_INT_rabc_cr0_11 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_INT_rabc_cr0_11$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_INT_rabc_div0_15 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_INT_rabc_div0_15$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_INT_rabc_div0_4 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_INT_rabc_div0_4$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_INT_rabc_ldst0_18 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_INT_rabc_ldst0_18$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_INT_rabc_ldst0_7 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_INT_rabc_ldst0_7$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_INT_rabc_ldst0_9 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_INT_rabc_ldst0_9$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_INT_rabc_logical0_13 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_INT_rabc_logical0_13$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_INT_rabc_logical0_3 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_INT_rabc_logical0_3$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_INT_rabc_mul0_16 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_INT_rabc_mul0_16$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_INT_rabc_mul0_5 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_INT_rabc_mul0_5$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_INT_rabc_shiftrot0_17 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_INT_rabc_shiftrot0_17$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_INT_rabc_shiftrot0_6 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_INT_rabc_shiftrot0_6$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_INT_rabc_shiftrot0_8 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_INT_rabc_shiftrot0_8$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_INT_rabc_spr0_14 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_INT_rabc_spr0_14$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_INT_rabc_trap0_12 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_INT_rabc_trap0_12$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_INT_rabc_trap0_2 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_INT_rabc_trap0_2$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_SPR_spr1_spr0_0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_SPR_spr1_spr0_0$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_XER_xer_ca_alu0_0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_XER_xer_ca_alu0_0$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_XER_xer_ca_shiftrot0_2 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_XER_xer_ca_shiftrot0_2$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_XER_xer_ca_spr0_1 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_XER_xer_ca_spr0_1$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_XER_xer_ov_spr0_0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_XER_xer_ov_spr0_0$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_XER_xer_so_alu0_0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_XER_xer_so_alu0_0$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_XER_xer_so_div0_3 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_XER_xer_so_div0_3$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_XER_xer_so_logical0_1 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_XER_xer_so_logical0_1$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_XER_xer_so_mul0_4 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_XER_xer_so_mul0_4$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_XER_xer_so_shiftrot0_5 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_XER_xer_so_shiftrot0_5$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg dp_XER_xer_so_spr0_2 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:305" *) reg \dp_XER_xer_so_spr0_2$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire ea_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:210" *) wire en_alu0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:210" *) wire en_branch0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:210" *) wire en_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:210" *) wire en_div0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:210" *) wire en_ldst0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:210" *) wire en_logical0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:210" *) wire en_mul0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:210" *) wire en_shiftrot0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:210" *) wire en_spr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:210" *) wire en_trap0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) + output \exc_o_$signal ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) - wire [2:0] fast_dest1__addr; + wire [3:0] fast_dest1__addr; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [63:0] fast_dest1__data_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire fast_dest1__wen; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) - wire [2:0] fast_src1__addr; + wire [3:0] fast_src1__addr; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [63:0] fast_src1__data_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire fast_src1__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:200" *) wire [9:0] fu_enable; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) output [31:0] full_rd2__data_o; @@ -39097,18 +42779,18 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c output [5:0] full_rd__data_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [2:0] full_rd__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire fus_cr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \fus_cr_a_ok$122 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire \fus_cr_a_ok$123 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire \fus_cr_a_ok$124 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire \fus_cr_a_ok$125 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire \fus_cr_a_ok$126 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \fus_cr_a_ok$127 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) wire fus_cu_busy_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) @@ -39154,7 +42836,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) wire [5:0] \fus_cu_rd__go_i$41 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - wire [3:0] \fus_cu_rd__go_i$44 ; + wire [4:0] \fus_cu_rd__go_i$44 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) wire [2:0] \fus_cu_rd__go_i$47 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) @@ -39174,7 +42856,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) wire [5:0] \fus_cu_rd__rel_o$40 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - wire [3:0] \fus_cu_rd__rel_o$43 ; + wire [4:0] \fus_cu_rd__rel_o$43 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) wire [2:0] \fus_cu_rd__rel_o$46 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) @@ -39196,7 +42878,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) reg [2:0] \fus_cu_rdmaskn_i$18 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) - reg [3:0] \fus_cu_rdmaskn_i$21 ; + reg [4:0] \fus_cu_rdmaskn_i$21 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) reg [2:0] \fus_cu_rdmaskn_i$24 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) @@ -39212,48 +42894,46 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) wire [4:0] fus_cu_wr__go_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - wire [1:0] \fus_cu_wr__go_i$100 ; + wire [1:0] \fus_cu_wr__go_i$101 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - wire [5:0] \fus_cu_wr__go_i$103 ; + wire [5:0] \fus_cu_wr__go_i$104 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - wire [3:0] \fus_cu_wr__go_i$106 ; + wire [3:0] \fus_cu_wr__go_i$107 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - wire [3:0] \fus_cu_wr__go_i$109 ; + wire [3:0] \fus_cu_wr__go_i$110 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - wire [2:0] \fus_cu_wr__go_i$112 ; + wire [2:0] \fus_cu_wr__go_i$113 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - wire [1:0] \fus_cu_wr__go_i$114 ; + wire [1:0] \fus_cu_wr__go_i$115 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - wire [2:0] \fus_cu_wr__go_i$149 ; + wire [2:0] \fus_cu_wr__go_i$150 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - wire [2:0] \fus_cu_wr__go_i$94 ; + wire [2:0] \fus_cu_wr__go_i$95 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - wire [4:0] \fus_cu_wr__go_i$97 ; + wire [6:0] \fus_cu_wr__go_i$98 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) wire [4:0] fus_cu_wr__rel_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - wire [5:0] \fus_cu_wr__rel_o$102 ; + wire [1:0] \fus_cu_wr__rel_o$100 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - wire [3:0] \fus_cu_wr__rel_o$105 ; + wire [5:0] \fus_cu_wr__rel_o$103 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - wire [3:0] \fus_cu_wr__rel_o$108 ; + wire [3:0] \fus_cu_wr__rel_o$106 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - wire [2:0] \fus_cu_wr__rel_o$111 ; + wire [3:0] \fus_cu_wr__rel_o$109 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - wire [1:0] \fus_cu_wr__rel_o$113 ; + wire [2:0] \fus_cu_wr__rel_o$112 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - wire [2:0] \fus_cu_wr__rel_o$148 ; + wire [1:0] \fus_cu_wr__rel_o$114 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - wire [2:0] \fus_cu_wr__rel_o$93 ; + wire [2:0] \fus_cu_wr__rel_o$149 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - wire [4:0] \fus_cu_wr__rel_o$96 ; + wire [2:0] \fus_cu_wr__rel_o$94 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - wire [1:0] \fus_cu_wr__rel_o$99 ; + wire [6:0] \fus_cu_wr__rel_o$97 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) wire [63:0] fus_dest1_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - wire [63:0] \fus_dest1_o$115 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) wire [63:0] \fus_dest1_o$116 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) wire [63:0] \fus_dest1_o$117 ; @@ -39266,11 +42946,11 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) wire [63:0] \fus_dest1_o$121 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - wire [63:0] \fus_dest1_o$153 ; + wire [63:0] \fus_dest1_o$122 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - wire [31:0] fus_dest2_o; + wire [63:0] \fus_dest1_o$154 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - wire [3:0] \fus_dest2_o$127 ; + wire [31:0] fus_dest2_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) wire [3:0] \fus_dest2_o$128 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) @@ -39280,151 +42960,168 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) wire [3:0] \fus_dest2_o$131 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - wire [63:0] \fus_dest2_o$154 ; + wire [3:0] \fus_dest2_o$132 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - wire [63:0] \fus_dest2_o$156 ; + wire [63:0] \fus_dest2_o$155 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - wire [63:0] \fus_dest2_o$162 ; + wire [63:0] \fus_dest2_o$157 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - wire [3:0] fus_dest3_o; + wire [63:0] \fus_dest2_o$164 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - wire [1:0] \fus_dest3_o$134 ; + wire [3:0] fus_dest3_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) wire [1:0] \fus_dest3_o$135 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - wire [1:0] \fus_dest3_o$139 ; + wire [1:0] \fus_dest3_o$136 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) wire [1:0] \fus_dest3_o$140 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - wire [63:0] \fus_dest3_o$155 ; + wire [1:0] \fus_dest3_o$141 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - wire [63:0] \fus_dest3_o$157 ; + wire [63:0] \fus_dest3_o$156 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - wire [63:0] \fus_dest3_o$159 ; + wire [63:0] \fus_dest3_o$158 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - wire [1:0] fus_dest4_o; + wire [63:0] \fus_dest3_o$161 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - wire \fus_dest4_o$145 ; + wire [1:0] fus_dest4_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) wire \fus_dest4_o$146 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) wire \fus_dest4_o$147 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - wire [63:0] \fus_dest4_o$160 ; + wire \fus_dest4_o$148 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [63:0] \fus_dest4_o$159 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) wire [1:0] fus_dest5_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - wire \fus_dest5_o$144 ; + wire \fus_dest5_o$145 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - wire [63:0] \fus_dest5_o$161 ; + wire [63:0] \fus_dest5_o$162 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) wire [1:0] fus_dest6_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [63:0] \fus_dest6_o$163 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + wire [31:0] fus_dest7_o; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] fus_ea; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire fus_fast1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \fus_fast1_ok$150 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire \fus_fast1_ok$151 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \fus_fast1_ok$152 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire fus_fast2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \fus_fast2_ok$152 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \fus_fast2_ok$153 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire fus_fast3_ok; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire fus_full_cr_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [95:0] fus_ldst_port0_addr_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire fus_ldst_port0_addr_i_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" *) wire fus_ldst_port0_addr_ok_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" *) wire fus_ldst_port0_busy_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103" *) wire [3:0] fus_ldst_port0_data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \fus_ldst_port0_exc_$signal ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) - wire \fus_ldst_port0_exc_$signal$163 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) - wire \fus_ldst_port0_exc_$signal$164 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \fus_ldst_port0_exc_$signal$165 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \fus_ldst_port0_exc_$signal$166 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \fus_ldst_port0_exc_$signal$167 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \fus_ldst_port0_exc_$signal$168 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \fus_ldst_port0_exc_$signal$169 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" *) - wire fus_ldst_port0_is_ld_i; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) + wire \fus_ldst_port0_exc_$signal$170 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) + wire \fus_ldst_port0_exc_$signal$171 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *) + wire fus_ldst_port0_is_ld_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:100" *) wire fus_ldst_port0_is_st_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] fus_ldst_port0_ld_data_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire fus_ldst_port0_ld_data_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:120" *) + wire fus_ldst_port0_msr_pr; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] fus_ldst_port0_st_data_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire fus_ldst_port0_st_data_i_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire fus_msr_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire fus_nia_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \fus_nia_ok$158 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \fus_nia_ok$160 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] fus_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire fus_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \fus_o_ok$101 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \fus_o_ok$104 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \fus_o_ok$107 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \fus_o_ok$110 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \fus_o_ok$92 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \fus_o_ok$95 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \fus_o_ok$98 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \fus_o_ok$102 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \fus_o_ok$105 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \fus_o_ok$108 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \fus_o_ok$111 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \fus_o_ok$93 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \fus_o_ok$96 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \fus_o_ok$99 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] fus_oper_i_alu_alu0__SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [3:0] fus_oper_i_alu_alu0__data_len; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] fus_oper_i_alu_alu0__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] fus_oper_i_alu_alu0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] fus_oper_i_alu_alu0__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_alu0__imm_data__ok; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [1:0] fus_oper_i_alu_alu0__input_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] fus_oper_i_alu_alu0__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -39501,54 +43198,73 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] fus_oper_i_alu_alu0__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_alu0__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_alu0__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_alu0__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_alu0__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_alu0__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_alu0__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_alu0__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_alu0__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_alu0__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg fus_oper_i_alu_alu0__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg fus_oper_i_alu_alu0__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] fus_oper_i_alu_alu0__sv_saturate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_alu0__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_alu0__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] fus_oper_i_alu_branch0__SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] fus_oper_i_alu_branch0__cia; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] fus_oper_i_alu_branch0__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] fus_oper_i_alu_branch0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] fus_oper_i_alu_branch0__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_branch0__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] fus_oper_i_alu_branch0__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -39625,30 +43341,49 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] fus_oper_i_alu_branch0__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_branch0__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_branch0__lk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg fus_oper_i_alu_branch0__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg fus_oper_i_alu_branch0__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] fus_oper_i_alu_branch0__sv_saturate; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] fus_oper_i_alu_cr0__SV_Ptype; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] fus_oper_i_alu_cr0__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] fus_oper_i_alu_cr0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] fus_oper_i_alu_cr0__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -39725,38 +43460,57 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] fus_oper_i_alu_cr0__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg fus_oper_i_alu_cr0__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg fus_oper_i_alu_cr0__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] fus_oper_i_alu_cr0__sv_saturate; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] fus_oper_i_alu_div0__SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [3:0] fus_oper_i_alu_div0__data_len; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] fus_oper_i_alu_div0__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] fus_oper_i_alu_div0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] fus_oper_i_alu_div0__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_div0__imm_data__ok; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [1:0] fus_oper_i_alu_div0__input_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] fus_oper_i_alu_div0__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -39833,60 +43587,79 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] fus_oper_i_alu_div0__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_div0__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_div0__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_div0__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_div0__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_div0__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_div0__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_div0__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_div0__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_div0__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg fus_oper_i_alu_div0__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg fus_oper_i_alu_div0__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] fus_oper_i_alu_div0__sv_saturate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_div0__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_div0__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] fus_oper_i_alu_logical0__SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [3:0] fus_oper_i_alu_logical0__data_len; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] fus_oper_i_alu_logical0__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] fus_oper_i_alu_logical0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] fus_oper_i_alu_logical0__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_logical0__imm_data__ok; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [1:0] fus_oper_i_alu_logical0__input_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] fus_oper_i_alu_logical0__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -39963,52 +43736,71 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] fus_oper_i_alu_logical0__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_logical0__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_logical0__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_logical0__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_logical0__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_logical0__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_logical0__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_logical0__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_logical0__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_logical0__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg fus_oper_i_alu_logical0__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg fus_oper_i_alu_logical0__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] fus_oper_i_alu_logical0__sv_saturate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_logical0__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_logical0__zero_a; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] fus_oper_i_alu_mul0__SV_Ptype; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] fus_oper_i_alu_mul0__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] fus_oper_i_alu_mul0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] fus_oper_i_alu_mul0__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_mul0__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] fus_oper_i_alu_mul0__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -40085,52 +43877,71 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] fus_oper_i_alu_mul0__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_mul0__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_mul0__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_mul0__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_mul0__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_mul0__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_mul0__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg fus_oper_i_alu_mul0__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg fus_oper_i_alu_mul0__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] fus_oper_i_alu_mul0__sv_saturate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_mul0__write_cr0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] fus_oper_i_alu_shift_rot0__SV_Ptype; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] fus_oper_i_alu_shift_rot0__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] fus_oper_i_alu_shift_rot0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] fus_oper_i_alu_shift_rot0__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_shift_rot0__imm_data__ok; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [1:0] fus_oper_i_alu_shift_rot0__input_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_shift_rot0__input_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] fus_oper_i_alu_shift_rot0__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -40207,46 +44018,65 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] fus_oper_i_alu_shift_rot0__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_shift_rot0__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_shift_rot0__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_shift_rot0__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_shift_rot0__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_shift_rot0__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_shift_rot0__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_shift_rot0__output_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_shift_rot0__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_shift_rot0__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg fus_oper_i_alu_shift_rot0__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg fus_oper_i_alu_shift_rot0__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] fus_oper_i_alu_shift_rot0__sv_saturate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_shift_rot0__write_cr0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] fus_oper_i_alu_spr0__SV_Ptype; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] fus_oper_i_alu_spr0__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] fus_oper_i_alu_spr0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] fus_oper_i_alu_spr0__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -40323,30 +44153,49 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] fus_oper_i_alu_spr0__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_spr0__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg fus_oper_i_alu_spr0__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg fus_oper_i_alu_spr0__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] fus_oper_i_alu_spr0__sv_saturate; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] fus_oper_i_alu_trap0__SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] fus_oper_i_alu_trap0__cia; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] fus_oper_i_alu_trap0__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] fus_oper_i_alu_trap0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] fus_oper_i_alu_trap0__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -40423,44 +44272,65 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] fus_oper_i_alu_trap0__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_alu_trap0__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [7:0] fus_oper_i_alu_trap0__ldst_exc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] fus_oper_i_alu_trap0__msr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg fus_oper_i_alu_trap0__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg fus_oper_i_alu_trap0__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] fus_oper_i_alu_trap0__sv_saturate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [31:0] fus_oper_i_alu_trap0__svstate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [12:0] fus_oper_i_alu_trap0__trapaddr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [7:0] fus_oper_i_alu_trap0__traptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] fus_oper_i_ldst_ldst0__SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_ldst_ldst0__byte_reverse; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [3:0] fus_oper_i_ldst_ldst0__data_len; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] fus_oper_i_ldst_ldst0__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] fus_oper_i_ldst_ldst0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] fus_oper_i_ldst_ldst0__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_ldst_ldst0__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] fus_oper_i_ldst_ldst0__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -40537,32 +44407,46 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] fus_oper_i_ldst_ldst0__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_ldst_ldst0__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_ldst_ldst0__is_signed; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [1:0] fus_oper_i_ldst_ldst0__ldst_mode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [63:0] fus_oper_i_ldst_ldst0__msr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_ldst_ldst0__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_ldst_ldst0__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_ldst_ldst0__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_ldst_ldst0__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_ldst_ldst0__sign_extend; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg fus_oper_i_ldst_ldst0__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg fus_oper_i_ldst_ldst0__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] fus_oper_i_ldst_ldst0__sv_saturate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg fus_oper_i_ldst_ldst0__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire fus_spr1_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) reg [63:0] fus_src1_i; @@ -40603,7 +44487,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) reg [63:0] \fus_src2_i$89 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) - reg [63:0] \fus_src2_i$91 ; + reg [63:0] \fus_src2_i$92 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) reg [63:0] fus_src3_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) @@ -40641,31 +44525,35 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) reg [3:0] \fus_src5_i$84 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + reg [63:0] \fus_src5_i$91 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) reg [1:0] fus_src6_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) reg [3:0] \fus_src6_i$85 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire fus_svstate_ok; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire fus_xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \fus_xer_ca_ok$132 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire \fus_xer_ca_ok$133 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \fus_xer_ca_ok$134 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire fus_xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \fus_xer_ov_ok$136 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire \fus_xer_ov_ok$137 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire \fus_xer_ov_ok$138 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \fus_xer_ov_ok$139 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire fus_xer_so_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \fus_xer_so_ok$141 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire \fus_xer_so_ok$142 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire \fus_xer_so_ok$143 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \fus_xer_so_ok$144 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [4:0] int_dest1__addr; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) @@ -40679,9 +44567,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire int_src1__ren; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) - input [2:0] issue__addr; + input [3:0] issue__addr; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) - input [2:0] \issue__addr$12 ; + input [3:0] \issue__addr$12 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [63:0] issue__data_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) @@ -40690,123 +44578,127 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c input issue__ren; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input issue__wen; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:106" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119" *) input issue_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:105" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118" *) input ivalid_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) output [63:0] msr__data_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [2:0] msr__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_CR_cr_a_branch0_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_CR_cr_a_cr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_CR_cr_b_cr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_CR_cr_c_cr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_CR_full_cr_cr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_FAST_fast1_branch0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_FAST_fast1_branch0_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_FAST_fast1_spr0_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_FAST_fast1_trap0_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_FAST_fast1_trap0_4; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) + wire pick_FAST_fast1_trap0_5; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_INT_rabc_alu0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_INT_rabc_alu0_10; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_INT_rabc_cr0_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_INT_rabc_cr0_11; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_INT_rabc_div0_15; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_INT_rabc_div0_4; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_INT_rabc_ldst0_18; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_INT_rabc_ldst0_7; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_INT_rabc_ldst0_9; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_INT_rabc_logical0_13; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_INT_rabc_logical0_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_INT_rabc_mul0_16; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_INT_rabc_mul0_5; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_INT_rabc_shiftrot0_17; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_INT_rabc_shiftrot0_6; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_INT_rabc_shiftrot0_8; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_INT_rabc_spr0_14; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_INT_rabc_trap0_12; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_INT_rabc_trap0_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_SPR_spr1_spr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_XER_xer_ca_alu0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_XER_xer_ca_shiftrot0_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_XER_xer_ca_spr0_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_XER_xer_ov_spr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_XER_xer_so_alu0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_XER_xer_so_div0_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_XER_xer_so_logical0_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_XER_xer_so_mul0_4; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_XER_xer_so_shiftrot0_5; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303" *) wire pick_XER_xer_so_spr0_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:101" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:110" *) input [31:0] raw_insn_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" *) wire rdflag_CR_cr_a_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" *) wire rdflag_CR_cr_b_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" *) wire rdflag_CR_cr_c_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" *) wire rdflag_CR_full_cr_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" *) wire rdflag_FAST_fast1_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" *) wire rdflag_FAST_fast1_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" *) + wire rdflag_FAST_fast1_2; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" *) wire rdflag_INT_rabc_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" *) wire rdflag_INT_rabc_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" *) wire rdflag_INT_rabc_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" *) wire rdflag_SPR_spr1_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" *) wire rdflag_XER_xer_ca_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" *) wire rdflag_XER_xer_ov_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" *) wire rdflag_XER_xer_so_0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) wire rdpick_CR_cr_a_en_o; @@ -40835,9 +44727,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) wire rdpick_FAST_fast1_en_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) - wire [4:0] rdpick_FAST_fast1_i; + wire [5:0] rdpick_FAST_fast1_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) - wire [4:0] rdpick_FAST_fast1_o; + wire [5:0] rdpick_FAST_fast1_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) wire rdpick_INT_rabc_en_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) @@ -40868,90 +44760,92 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c wire [5:0] rdpick_XER_xer_so_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) wire [5:0] rdpick_XER_xer_so_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_CR_cr_a_branch0_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_CR_cr_a_cr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_CR_cr_b_cr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_CR_cr_c_cr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_CR_full_cr_cr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_FAST_fast1_branch0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_FAST_fast1_branch0_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_FAST_fast1_spr0_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_FAST_fast1_trap0_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_FAST_fast1_trap0_4; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) + wire rp_FAST_fast1_trap0_5; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_INT_rabc_alu0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_INT_rabc_alu0_10; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_INT_rabc_cr0_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_INT_rabc_cr0_11; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_INT_rabc_div0_15; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_INT_rabc_div0_4; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_INT_rabc_ldst0_18; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_INT_rabc_ldst0_7; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_INT_rabc_ldst0_9; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_INT_rabc_logical0_13; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_INT_rabc_logical0_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_INT_rabc_mul0_16; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_INT_rabc_mul0_5; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_INT_rabc_shiftrot0_17; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_INT_rabc_shiftrot0_6; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_INT_rabc_shiftrot0_8; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_INT_rabc_spr0_14; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_INT_rabc_trap0_12; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_INT_rabc_trap0_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_SPR_spr1_spr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_XER_xer_ca_alu0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_XER_xer_ca_shiftrot0_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_XER_xer_ca_spr0_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_XER_xer_ov_spr0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_XER_xer_so_alu0_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_XER_xer_so_div0_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_XER_xer_so_logical0_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_XER_xer_so_mul0_4; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_XER_xer_so_shiftrot0_5; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" *) wire rp_XER_xer_so_spr0_2; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [3:0] spr_spr1__addr; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) - wire [3:0] \spr_spr1__addr$175 ; + wire [3:0] \spr_spr1__addr$179 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [63:0] spr_spr1__data_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) @@ -40963,355 +44857,373 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [63:0] state_data_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) - wire [63:0] \state_data_i$174 ; + wire [63:0] \state_data_i$176 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] \state_data_i$177 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) output [2:0] state_nia_wen; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [2:0] state_wen; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [2:0] \state_wen$178 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) output [63:0] sv__data_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [2:0] sv__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" *) - input sv_a_nz; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) - wire \sv_a_nz$176 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) - wire \sv_a_nz$177 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) - wire \sv_a_nz$178 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) - wire \sv_a_nz$179 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:106" *) + wire sv_a_nz; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:747" *) wire \sv_a_nz$180 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:747" *) + wire \sv_a_nz$181 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:747" *) + wire \sv_a_nz$182 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:747" *) + wire \sv_a_nz$183 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:747" *) + wire \sv_a_nz$184 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" *) input wb_dcache_en; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [2:0] wen; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [2:0] \wen$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) wire wp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1018 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1036 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1017 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1040 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) wire \wp$1058 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1078 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1098 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1117 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1135 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1151 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1225 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1253 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1273 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1293 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1313 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1333 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1353 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1400 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1416 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1432 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1466 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1482 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1498 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1514 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1550 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1566 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1582 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1598 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1643 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1659 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1675 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1691 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1707 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1751 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1767 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1791 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$1811 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) - wire \wp$997 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1080 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1100 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1120 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1139 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1157 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1173 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1247 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1275 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1295 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1315 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1335 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1355 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1375 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1422 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1438 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1454 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1488 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1504 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1520 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1536 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1572 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1588 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1604 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1620 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1667 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1683 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1699 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1715 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1731 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1747 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1799 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1815 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1839 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1859 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:448" *) + wire \wp$1879 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) wire wr_pick; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1005 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1026 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1044 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1006 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1025 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1048 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) wire \wr_pick$1066 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1086 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1106 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1125 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1143 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1217 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1245 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1265 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1285 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1305 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1325 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1345 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1392 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1408 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1424 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1458 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1474 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1490 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1506 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1542 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1558 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1574 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1590 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1632 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1651 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1667 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1683 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1699 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1743 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1759 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1783 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$1803 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *) - wire \wr_pick$986 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1088 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1108 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1128 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1147 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1165 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1239 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1267 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1287 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1307 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1327 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1347 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1367 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1414 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1430 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1446 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1480 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1496 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1512 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1528 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1564 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1580 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1596 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1612 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1656 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1675 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1691 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1707 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1723 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1739 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1791 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1807 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1831 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1851 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:440" *) + wire \wr_pick$1871 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) reg wr_pick_dly = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1008 = 1'h0; + reg \wr_pick_dly$1009 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1008$next ; + reg \wr_pick_dly$1009$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1029 = 1'h0; + reg \wr_pick_dly$1028 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1029$next ; + reg \wr_pick_dly$1028$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1047 = 1'h0; + reg \wr_pick_dly$1051 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1047$next ; + reg \wr_pick_dly$1051$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) reg \wr_pick_dly$1069 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) reg \wr_pick_dly$1069$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1089 = 1'h0; + reg \wr_pick_dly$1091 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1091$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1089$next ; + reg \wr_pick_dly$1111 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1109 = 1'h0; + reg \wr_pick_dly$1111$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1109$next ; + reg \wr_pick_dly$1131 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1128 = 1'h0; + reg \wr_pick_dly$1131$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1128$next ; + reg \wr_pick_dly$1150 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1146 = 1'h0; + reg \wr_pick_dly$1150$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1146$next ; + reg \wr_pick_dly$1168 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1220 = 1'h0; + reg \wr_pick_dly$1168$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1220$next ; + reg \wr_pick_dly$1242 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1248 = 1'h0; + reg \wr_pick_dly$1242$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1248$next ; + reg \wr_pick_dly$1270 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1268 = 1'h0; + reg \wr_pick_dly$1270$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1268$next ; + reg \wr_pick_dly$1290 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1288 = 1'h0; + reg \wr_pick_dly$1290$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1288$next ; + reg \wr_pick_dly$1310 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1308 = 1'h0; + reg \wr_pick_dly$1310$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1308$next ; + reg \wr_pick_dly$1330 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1328 = 1'h0; + reg \wr_pick_dly$1330$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1328$next ; + reg \wr_pick_dly$1350 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1348 = 1'h0; + reg \wr_pick_dly$1350$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1348$next ; + reg \wr_pick_dly$1370 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1395 = 1'h0; + reg \wr_pick_dly$1370$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1395$next ; + reg \wr_pick_dly$1417 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1411 = 1'h0; + reg \wr_pick_dly$1417$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1411$next ; + reg \wr_pick_dly$1433 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1427 = 1'h0; + reg \wr_pick_dly$1433$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1427$next ; + reg \wr_pick_dly$1449 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1461 = 1'h0; + reg \wr_pick_dly$1449$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1461$next ; + reg \wr_pick_dly$1483 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1477 = 1'h0; + reg \wr_pick_dly$1483$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1477$next ; + reg \wr_pick_dly$1499 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1493 = 1'h0; + reg \wr_pick_dly$1499$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1493$next ; + reg \wr_pick_dly$1515 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1509 = 1'h0; + reg \wr_pick_dly$1515$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1509$next ; + reg \wr_pick_dly$1531 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1545 = 1'h0; + reg \wr_pick_dly$1531$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1545$next ; + reg \wr_pick_dly$1567 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1561 = 1'h0; + reg \wr_pick_dly$1567$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1561$next ; + reg \wr_pick_dly$1583 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1577 = 1'h0; + reg \wr_pick_dly$1583$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1577$next ; + reg \wr_pick_dly$1599 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1593 = 1'h0; + reg \wr_pick_dly$1599$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1593$next ; + reg \wr_pick_dly$1615 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1635 = 1'h0; + reg \wr_pick_dly$1615$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1635$next ; + reg \wr_pick_dly$1659 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1654 = 1'h0; + reg \wr_pick_dly$1659$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1654$next ; + reg \wr_pick_dly$1678 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1670 = 1'h0; + reg \wr_pick_dly$1678$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1670$next ; + reg \wr_pick_dly$1694 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1686 = 1'h0; + reg \wr_pick_dly$1694$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1686$next ; + reg \wr_pick_dly$1710 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1702 = 1'h0; + reg \wr_pick_dly$1710$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1702$next ; + reg \wr_pick_dly$1726 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1746 = 1'h0; + reg \wr_pick_dly$1726$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1746$next ; + reg \wr_pick_dly$1742 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1762 = 1'h0; + reg \wr_pick_dly$1742$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1762$next ; + reg \wr_pick_dly$1794 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1786 = 1'h0; + reg \wr_pick_dly$1794$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1786$next ; + reg \wr_pick_dly$1810 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1806 = 1'h0; + reg \wr_pick_dly$1810$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$1806$next ; + reg \wr_pick_dly$1834 = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$989 = 1'h0; + reg \wr_pick_dly$1834$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) - reg \wr_pick_dly$989$next ; + reg \wr_pick_dly$1854 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1854$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1874 = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) + reg \wr_pick_dly$1874$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) reg \wr_pick_dly$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) wire wr_pick_rise; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) - wire \wr_pick_rise$1009 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) - wire \wr_pick_rise$1014 ; + wire \wr_pick_rise$1010 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) wire \wr_pick_rise$1015 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) wire \wr_pick_rise$1016 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) - wire \wr_pick_rise$1017 ; + wire \wr_pick_rise$1029 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) - wire \wr_pick_rise$1030 ; + wire \wr_pick_rise$1034 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) wire \wr_pick_rise$1035 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) - wire \wr_pick_rise$1048 ; + wire \wr_pick_rise$1036 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) - wire \wr_pick_rise$1053 ; + wire \wr_pick_rise$1037 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) - wire \wr_pick_rise$1054 ; + wire \wr_pick_rise$1038 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) - wire \wr_pick_rise$1055 ; + wire \wr_pick_rise$1039 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) - wire \wr_pick_rise$1056 ; + wire \wr_pick_rise$1052 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) wire \wr_pick_rise$1057 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) @@ -41323,117 +45235,127 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) wire \wr_pick_rise$1077 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) - wire \wr_pick_rise$1090 ; + wire \wr_pick_rise$1078 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) - wire \wr_pick_rise$1095 ; + wire \wr_pick_rise$1079 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) - wire \wr_pick_rise$1096 ; + wire \wr_pick_rise$1092 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) wire \wr_pick_rise$1097 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) - wire \wr_pick_rise$1110 ; + wire \wr_pick_rise$1098 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) - wire \wr_pick_rise$1115 ; + wire \wr_pick_rise$1099 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) - wire \wr_pick_rise$1116 ; + wire \wr_pick_rise$1112 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) - wire \wr_pick_rise$1129 ; + wire \wr_pick_rise$1117 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) - wire \wr_pick_rise$1134 ; + wire \wr_pick_rise$1118 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) - wire \wr_pick_rise$1636 ; + wire \wr_pick_rise$1119 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) - wire \wr_pick_rise$1641 ; + wire \wr_pick_rise$1132 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) - wire \wr_pick_rise$1642 ; + wire \wr_pick_rise$1137 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) - wire \wr_pick_rise$976 ; + wire \wr_pick_rise$1138 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) - wire \wr_pick_rise$977 ; + wire \wr_pick_rise$1151 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) - wire \wr_pick_rise$978 ; + wire \wr_pick_rise$1156 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) - wire \wr_pick_rise$979 ; + wire \wr_pick_rise$1660 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) - wire \wr_pick_rise$990 ; + wire \wr_pick_rise$1665 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) - wire \wr_pick_rise$995 ; + wire \wr_pick_rise$1666 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) wire \wr_pick_rise$996 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$997 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$998 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) + wire \wr_pick_rise$999 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_alu0_cr_a_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_alu0_o_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_alu0_xer_ca_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_alu0_xer_ov_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_alu0_xer_so_4; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_branch0_fast1_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_branch0_fast1_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_branch0_nia_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_cr0_cr_a_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_cr0_full_cr_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_cr0_o_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_div0_cr_a_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_div0_o_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_div0_xer_ov_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_div0_xer_so_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_ldst0_o_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_ldst0_o_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_logical0_cr_a_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_logical0_o_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_mul0_cr_a_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_mul0_o_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_mul0_xer_ov_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_mul0_xer_so_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_shiftrot0_cr_a_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_shiftrot0_o_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_shiftrot0_xer_ca_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_spr0_fast1_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_spr0_o_0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_spr0_spr1_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_spr0_xer_ca_5; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_spr0_xer_ov_4; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_spr0_xer_so_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_trap0_fast1_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_trap0_fast1_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) - wire wrflag_trap0_msr_4; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) - wire wrflag_trap0_nia_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) + wire wrflag_trap0_fast1_3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) + wire wrflag_trap0_msr_5; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) + wire wrflag_trap0_nia_4; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) wire wrflag_trap0_o_0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:432" *) + wire wrflag_trap0_svstate_6; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) wire wrpick_CR_cr_a_en_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) @@ -41449,9 +45371,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) wire wrpick_FAST_fast1_en_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) - wire [4:0] wrpick_FAST_fast1_i; + wire [5:0] wrpick_FAST_fast1_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) - wire [4:0] wrpick_FAST_fast1_o; + wire [5:0] wrpick_FAST_fast1_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) wire wrpick_INT_o_en_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) @@ -41477,6 +45399,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) wire [1:0] wrpick_STATE_nia_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + wire wrpick_STATE_svstate_en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + wire wrpick_STATE_svstate_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + wire wrpick_STATE_svstate_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) wire wrpick_XER_xer_ca_en_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) wire [2:0] wrpick_XER_xer_ca_i; @@ -41497,10 +45425,10 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [1:0] xer_data_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) - wire [1:0] \xer_data_i$170 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [1:0] \xer_data_i$172 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] \xer_data_i$174 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [1:0] xer_src1__data_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [2:0] xer_src1__ren; @@ -41515,810 +45443,843 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [2:0] xer_wen; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) - wire [2:0] \xer_wen$171 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [2:0] \xer_wen$173 ; - assign \$1001 = \wp$997 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_rego : 7'h00; - assign \$1003 = \fus_o_ok$95 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$20 ; - assign \$1006 = wrpick_INT_o_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_INT_o_en_o; - assign \$1010 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1008 ; - assign \$1012 = \wr_pick$1005 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1010 ; - assign \$1019 = \wr_pick$1005 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_INT_o_en_o; - assign \$1022 = \wp$1018 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_rego : 7'h00; - assign \$1024 = \fus_o_ok$98 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$23 ; - assign \$1027 = wrpick_INT_o_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_INT_o_en_o; - assign \$1031 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1029 ; - assign \$1033 = \wr_pick$1026 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1031 ; - assign \$1037 = \wr_pick$1026 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_INT_o_en_o; - assign \$1040 = \wp$1036 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_rego : 7'h00; - assign \$1042 = \fus_o_ok$101 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$26 ; - assign \$1045 = wrpick_INT_o_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_INT_o_en_o; - assign \$1049 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1047 ; - assign \$1051 = \wr_pick$1044 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1049 ; - assign \$1059 = \wr_pick$1044 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_INT_o_en_o; - assign \$1062 = \wp$1058 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_rego : 7'h00; - assign \$1064 = \fus_o_ok$104 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$29 ; - assign \$1067 = wrpick_INT_o_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_INT_o_en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [2:0] \xer_wen$175 ; + assign \$1000 = wr_pick & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_INT_o_en_o; + assign \$1002 = wp ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_rego : 7'h00; + assign \$1004 = \fus_o_ok$93 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$14 ; + assign \$1007 = wrpick_INT_o_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_INT_o_en_o; + assign \$1011 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1009 ; + assign \$1013 = \wr_pick$1006 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1011 ; + assign \$1018 = \wr_pick$1006 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_INT_o_en_o; + assign \$1021 = \wp$1017 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_rego : 7'h00; + assign \$1023 = \fus_o_ok$96 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$20 ; + assign \$1026 = wrpick_INT_o_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_INT_o_en_o; + assign \$1030 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1028 ; + assign \$1032 = \wr_pick$1025 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1030 ; + assign \$1041 = \wr_pick$1025 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_INT_o_en_o; + assign \$1044 = \wp$1040 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_rego : 7'h00; + assign \$1046 = \fus_o_ok$99 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$23 ; + assign \$1049 = wrpick_INT_o_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_INT_o_en_o; + assign \$1053 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1051 ; + assign \$1055 = \wr_pick$1048 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1053 ; + assign \$1059 = \wr_pick$1048 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_INT_o_en_o; + assign \$1062 = \wp$1058 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_rego : 7'h00; + assign \$1064 = \fus_o_ok$102 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$26 ; + assign \$1067 = wrpick_INT_o_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_INT_o_en_o; assign \$1071 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1069 ; assign \$1073 = \wr_pick$1066 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1071 ; - assign \$1079 = \wr_pick$1066 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_INT_o_en_o; - assign \$1082 = \wp$1078 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_rego : 7'h00; - assign \$1084 = \fus_o_ok$107 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$32 ; - assign \$1087 = wrpick_INT_o_o[6] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_INT_o_en_o; - assign \$1091 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1089 ; - assign \$1093 = \wr_pick$1086 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1091 ; - assign \$1099 = \wr_pick$1086 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_INT_o_en_o; - assign \$1102 = \wp$1098 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_rego : 7'h00; - assign \$1104 = \fus_o_ok$110 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$35 ; - assign \$1107 = wrpick_INT_o_o[7] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_INT_o_en_o; - assign \$1111 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1109 ; - assign \$1113 = \wr_pick$1106 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1111 ; - assign \$1118 = \wr_pick$1106 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_INT_o_en_o; - assign \$1121 = \wp$1117 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_rego : 7'h00; - assign \$1123 = o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$38 ; - assign \$1126 = wrpick_INT_o_o[8] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_INT_o_en_o; - assign \$1130 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1128 ; - assign \$1132 = \wr_pick$1125 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1130 ; - assign \$1136 = \wr_pick$1125 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_INT_o_en_o; - assign \$1139 = \wp$1135 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_rego : 7'h00; - assign \$1141 = ea_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$38 ; - assign \$1144 = wrpick_INT_o_o[9] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_INT_o_en_o; - assign \$1147 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1146 ; - assign \$1149 = \wr_pick$1143 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1147 ; - assign \$1152 = \wr_pick$1143 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_INT_o_en_o; - assign \$1155 = \wp$1151 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_ea : 7'h00; - assign \$1158 = fus_dest1_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest1_o$115 ; - assign \$1160 = \fus_dest1_o$117 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest1_o$118 ; - assign \$1162 = \fus_dest1_o$116 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1160 ; - assign \$1164 = \$1158 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1162 ; - assign \$1166 = \fus_dest1_o$119 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest1_o$120 ; - assign \$1168 = { o_ok, fus_o } | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:258" *) { ea_ok, fus_ea }; - assign \$1170 = \fus_dest1_o$121 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1168 ; - assign \$1172 = \$1166 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1170 ; - assign \$1174 = \$1164 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1172 ; - assign \$1177 = addr_en | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1000 ; - assign \$1179 = \addr_en$1039 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1061 ; - assign \$1181 = \addr_en$1021 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1179 ; - assign \$1183 = \$1177 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1181 ; - assign \$1185 = \addr_en$1081 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1101 ; - assign \$1187 = \addr_en$1138 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1154 ; - assign \$1189 = \addr_en$1120 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1187 ; - assign \$1191 = \$1185 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1189 ; - assign \$1193 = \$1183 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1191 ; - assign \$1195 = wp | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$997 ; - assign \$1197 = \wp$1036 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1058 ; - assign \$1199 = \wp$1018 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1197 ; - assign \$1201 = \$1195 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1199 ; - assign \$1203 = \wp$1078 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1098 ; - assign \$1205 = \wp$1135 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1151 ; - assign \$1207 = \wp$1117 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1205 ; - assign \$1209 = \$1203 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1207 ; - assign \$1211 = \$1201 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1209 ; - assign \$1213 = fus_full_cr_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$14 ; - assign \$1215 = \fus_cu_wr__rel_o$93 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[1]; - assign \$1218 = wrpick_CR_full_cr_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_CR_full_cr_en_o; - assign \$1221 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1220 ; - assign \$1223 = \wr_pick$1217 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1221 ; - assign \$1226 = \wr_pick$1217 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_CR_full_cr_en_o; - assign \$1229 = \wp$1225 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_core_cr_wr : 8'h00; - assign \$1231 = fus_cr_a_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) fus_cu_busy_o; - assign \$1233 = fus_cu_wr__rel_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[0]; - assign \$1235 = \fus_cu_wr__rel_o$93 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[1]; - assign \$1237 = \fus_cu_wr__rel_o$99 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[4]; - assign \$1239 = \fus_cu_wr__rel_o$105 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[6]; - assign \$1241 = \fus_cu_wr__rel_o$108 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[7]; - assign \$1243 = \fus_cu_wr__rel_o$111 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[8]; - assign \$1246 = wrpick_CR_cr_a_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_CR_cr_a_en_o; - assign \$1249 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1248 ; - assign \$1251 = \wr_pick$1245 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1249 ; - assign \$1254 = \wr_pick$1245 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_CR_cr_a_en_o; - assign \$1257 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) core_cr_out; - assign \$1259 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) \$1257 ; - assign \$1261 = \wp$1253 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) \$1259 : 256'h0000000000000000000000000000000000000000000000000000000000000000; - assign \$1263 = \fus_cr_a_ok$122 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$14 ; - assign \$1266 = wrpick_CR_cr_a_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_CR_cr_a_en_o; - assign \$1269 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1268 ; - assign \$1271 = \wr_pick$1265 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1269 ; - assign \$1274 = \wr_pick$1265 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_CR_cr_a_en_o; - assign \$1277 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) core_cr_out; - assign \$1279 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) \$1277 ; - assign \$1281 = \wp$1273 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) \$1279 : 256'h0000000000000000000000000000000000000000000000000000000000000000; - assign \$1283 = \fus_cr_a_ok$123 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$23 ; - assign \$1286 = wrpick_CR_cr_a_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_CR_cr_a_en_o; - assign \$1289 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1288 ; - assign \$1291 = \wr_pick$1285 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1289 ; - assign \$1294 = \wr_pick$1285 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_CR_cr_a_en_o; - assign \$1297 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) core_cr_out; - assign \$1299 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) \$1297 ; - assign \$1301 = \wp$1293 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) \$1299 : 256'h0000000000000000000000000000000000000000000000000000000000000000; - assign \$1303 = \fus_cr_a_ok$124 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$29 ; - assign \$1306 = wrpick_CR_cr_a_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_CR_cr_a_en_o; - assign \$1309 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1308 ; - assign \$1311 = \wr_pick$1305 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1309 ; - assign \$1314 = \wr_pick$1305 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_CR_cr_a_en_o; - assign \$1317 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) core_cr_out; - assign \$1319 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) \$1317 ; - assign \$1321 = \wp$1313 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) \$1319 : 256'h0000000000000000000000000000000000000000000000000000000000000000; - assign \$1323 = \fus_cr_a_ok$125 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$32 ; - assign \$1326 = wrpick_CR_cr_a_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_CR_cr_a_en_o; - assign \$1329 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1328 ; - assign \$1331 = \wr_pick$1325 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1329 ; - assign \$1334 = \wr_pick$1325 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_CR_cr_a_en_o; - assign \$1337 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) core_cr_out; - assign \$1339 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) \$1337 ; - assign \$1341 = \wp$1333 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) \$1339 : 256'h0000000000000000000000000000000000000000000000000000000000000000; - assign \$1343 = \fus_cr_a_ok$126 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$35 ; - assign \$1346 = wrpick_CR_cr_a_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_CR_cr_a_en_o; - assign \$1349 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1348 ; - assign \$1351 = \wr_pick$1345 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1349 ; - assign \$1354 = \wr_pick$1345 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_CR_cr_a_en_o; - assign \$1357 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) core_cr_out; - assign \$1359 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) \$1357 ; - assign \$1361 = \wp$1353 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) \$1359 : 256'h0000000000000000000000000000000000000000000000000000000000000000; - assign \$1363 = fus_dest3_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest2_o$128 ; - assign \$1365 = \fus_dest2_o$127 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1363 ; - assign \$1367 = \fus_dest2_o$130 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest2_o$131 ; - assign \$1369 = \fus_dest2_o$129 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1367 ; - assign \$1371 = \$1365 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1369 ; - assign \$1374 = \addr_en$1276 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1296 ; - assign \$1376 = \addr_en$1256 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1374 ; - assign \$1378 = \addr_en$1336 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1356 ; - assign \$1380 = \addr_en$1316 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1378 ; - assign \$1382 = \$1376 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1380 ; - assign \$1384 = fus_xer_ca_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) fus_cu_busy_o; - assign \$1386 = fus_cu_wr__rel_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[0]; - assign \$1388 = \fus_cu_wr__rel_o$102 [5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[5]; - assign \$1390 = \fus_cu_wr__rel_o$111 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[8]; - assign \$1393 = wrpick_XER_xer_ca_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_XER_xer_ca_en_o; - assign \$1396 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1395 ; - assign \$1398 = \wr_pick$1392 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1396 ; - assign \$1401 = \wr_pick$1392 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_XER_xer_ca_en_o; - assign \$1404 = \wp$1400 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 2'h2 : 2'h0; - assign \$1406 = \fus_xer_ca_ok$132 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$26 ; - assign \$1409 = wrpick_XER_xer_ca_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_XER_xer_ca_en_o; - assign \$1412 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1411 ; - assign \$1414 = \wr_pick$1408 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1412 ; - assign \$1417 = \wr_pick$1408 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_XER_xer_ca_en_o; - assign \$1420 = \wp$1416 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 2'h2 : 2'h0; - assign \$1422 = \fus_xer_ca_ok$133 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$35 ; - assign \$1425 = wrpick_XER_xer_ca_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_XER_xer_ca_en_o; - assign \$1428 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1427 ; - assign \$1430 = \wr_pick$1424 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1428 ; - assign \$1433 = \wr_pick$1424 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_XER_xer_ca_en_o; - assign \$1436 = \wp$1432 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 2'h2 : 2'h0; - assign \$1438 = fus_dest6_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest3_o$135 ; - assign \$1440 = \fus_dest3_o$134 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1438 ; - assign \$1443 = \addr_en$1419 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1435 ; - assign \$1445 = \addr_en$1403 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1443 ; - assign \$1442 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1445 ; - assign \$1448 = fus_xer_ov_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) fus_cu_busy_o; - assign \$1450 = fus_cu_wr__rel_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[0]; - assign \$1452 = \fus_cu_wr__rel_o$102 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[5]; - assign \$1454 = \fus_cu_wr__rel_o$105 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[6]; - assign \$1456 = \fus_cu_wr__rel_o$108 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[7]; - assign \$1459 = wrpick_XER_xer_ov_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_XER_xer_ov_en_o; - assign \$1462 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1461 ; - assign \$1464 = \wr_pick$1458 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1462 ; - assign \$1467 = \wr_pick$1458 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_XER_xer_ov_en_o; - assign \$1470 = \wp$1466 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 3'h4 : 3'h0; - assign \$1472 = \fus_xer_ov_ok$136 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$26 ; - assign \$1475 = wrpick_XER_xer_ov_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_XER_xer_ov_en_o; - assign \$1478 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1477 ; - assign \$1480 = \wr_pick$1474 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1478 ; - assign \$1483 = \wr_pick$1474 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_XER_xer_ov_en_o; - assign \$1486 = \wp$1482 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 3'h4 : 3'h0; - assign \$1488 = \fus_xer_ov_ok$137 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$29 ; - assign \$1491 = wrpick_XER_xer_ov_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_XER_xer_ov_en_o; - assign \$1494 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1493 ; - assign \$1496 = \wr_pick$1490 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1494 ; - assign \$1499 = \wr_pick$1490 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_XER_xer_ov_en_o; - assign \$1502 = \wp$1498 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 3'h4 : 3'h0; - assign \$1504 = \fus_xer_ov_ok$138 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$32 ; - assign \$1507 = wrpick_XER_xer_ov_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_XER_xer_ov_en_o; - assign \$1510 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1509 ; - assign \$1512 = \wr_pick$1506 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1510 ; - assign \$1515 = \wr_pick$1506 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_XER_xer_ov_en_o; - assign \$1518 = \wp$1514 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 3'h4 : 3'h0; - assign \$1520 = fus_dest4_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) fus_dest5_o; - assign \$1522 = \fus_dest3_o$139 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest3_o$140 ; - assign \$1524 = \$1520 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1522 ; - assign \$1526 = \addr_en$1469 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1485 ; - assign \$1528 = \addr_en$1501 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1517 ; - assign \$1530 = \$1526 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1528 ; - assign \$1532 = fus_xer_so_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) fus_cu_busy_o; - assign \$1534 = fus_cu_wr__rel_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[0]; - assign \$1536 = \fus_cu_wr__rel_o$102 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[5]; - assign \$1538 = \fus_cu_wr__rel_o$105 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[6]; - assign \$1540 = \fus_cu_wr__rel_o$108 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[7]; - assign \$1543 = wrpick_XER_xer_so_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_XER_xer_so_en_o; - assign \$1546 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1545 ; - assign \$1548 = \wr_pick$1542 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1546 ; - assign \$1551 = \wr_pick$1542 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_XER_xer_so_en_o; - assign \$1554 = \wp$1550 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 1'h1 : 1'h0; - assign \$1556 = \fus_xer_so_ok$141 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$26 ; - assign \$1559 = wrpick_XER_xer_so_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_XER_xer_so_en_o; - assign \$1562 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1561 ; - assign \$1564 = \wr_pick$1558 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1562 ; - assign \$1567 = \wr_pick$1558 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_XER_xer_so_en_o; - assign \$1570 = \wp$1566 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 1'h1 : 1'h0; - assign \$1572 = \fus_xer_so_ok$142 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$29 ; - assign \$1575 = wrpick_XER_xer_so_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_XER_xer_so_en_o; - assign \$1578 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1577 ; - assign \$1580 = \wr_pick$1574 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1578 ; - assign \$1583 = \wr_pick$1574 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_XER_xer_so_en_o; - assign \$1586 = \wp$1582 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 1'h1 : 1'h0; - assign \$1588 = \fus_xer_so_ok$143 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$32 ; - assign \$1591 = wrpick_XER_xer_so_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_XER_xer_so_en_o; - assign \$1594 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1593 ; - assign \$1596 = \wr_pick$1590 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1594 ; - assign \$1599 = \wr_pick$1590 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_XER_xer_so_en_o; - assign \$1602 = \wp$1598 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 1'h1 : 1'h0; - assign \$1605 = \fus_dest5_o$144 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest4_o$145 ; - assign \$1607 = \fus_dest4_o$146 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest4_o$147 ; - assign \$1609 = \$1605 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1607 ; - assign \$1604 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1609 ; - assign \$1613 = \addr_en$1553 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1569 ; - assign \$1615 = \addr_en$1585 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1601 ; - assign \$1617 = \$1613 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1615 ; - assign \$1612 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1617 ; - assign \$1620 = fus_fast1_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$17 ; - assign \$1622 = \fus_cu_wr__rel_o$148 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[2]; - assign \$1624 = \fus_cu_wr__rel_o$96 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[3]; - assign \$1626 = \fus_cu_wr__rel_o$102 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[5]; - assign \$1628 = \fus_cu_wr__rel_o$148 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[2]; - assign \$1630 = \fus_cu_wr__rel_o$96 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[3]; - assign \$1633 = wrpick_FAST_fast1_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_FAST_fast1_en_o; - assign \$1637 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1635 ; - assign \$1639 = \wr_pick$1632 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1637 ; - assign \$1644 = \wr_pick$1632 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_FAST_fast1_en_o; - assign \$1647 = \wp$1643 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_fasto1 : 3'h0; - assign \$1649 = \fus_fast1_ok$150 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$20 ; - assign \$1652 = wrpick_FAST_fast1_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_FAST_fast1_en_o; - assign \$1655 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1654 ; - assign \$1657 = \wr_pick$1651 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1655 ; - assign \$1660 = \wr_pick$1651 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_FAST_fast1_en_o; - assign \$1663 = \wp$1659 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_fasto1 : 3'h0; - assign \$1665 = \fus_fast1_ok$151 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$26 ; - assign \$1668 = wrpick_FAST_fast1_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_FAST_fast1_en_o; - assign \$1671 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1670 ; - assign \$1673 = \wr_pick$1667 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1671 ; - assign \$1676 = \wr_pick$1667 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_FAST_fast1_en_o; - assign \$1679 = \wp$1675 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_fasto1 : 3'h0; - assign \$1681 = fus_fast2_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$17 ; - assign \$1684 = wrpick_FAST_fast1_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_FAST_fast1_en_o; - assign \$1687 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1686 ; - assign \$1689 = \wr_pick$1683 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1687 ; - assign \$1692 = \wr_pick$1683 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_FAST_fast1_en_o; - assign \$1695 = \wp$1691 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_fasto2 : 3'h0; - assign \$1697 = \fus_fast2_ok$152 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$20 ; - assign \$1700 = wrpick_FAST_fast1_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_FAST_fast1_en_o; - assign \$1703 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1702 ; - assign \$1705 = \wr_pick$1699 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1703 ; - assign \$1708 = \wr_pick$1699 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_FAST_fast1_en_o; - assign \$1711 = \wp$1707 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_fasto2 : 3'h0; - assign \$1713 = \fus_dest1_o$153 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest2_o$154 ; - assign \$1715 = \fus_dest2_o$156 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest3_o$157 ; - assign \$1717 = \fus_dest3_o$155 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1715 ; - assign \$1719 = \$1713 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1717 ; - assign \$1721 = \addr_en$1646 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1662 ; - assign \$1723 = \addr_en$1694 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1710 ; - assign \$1725 = \addr_en$1678 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1723 ; - assign \$1727 = \$1721 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1725 ; - assign \$1729 = \wp$1643 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1659 ; - assign \$1731 = \wp$1691 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1707 ; - assign \$1733 = \wp$1675 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1731 ; - assign \$1735 = \$1729 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1733 ; - assign \$1737 = fus_nia_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$17 ; - assign \$1739 = \fus_cu_wr__rel_o$148 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[2]; - assign \$1741 = \fus_cu_wr__rel_o$96 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[3]; - assign \$1744 = wrpick_STATE_nia_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_STATE_nia_en_o; - assign \$1747 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1746 ; - assign \$1749 = \wr_pick$1743 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1747 ; - assign \$1752 = \wr_pick$1743 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_STATE_nia_en_o; - assign \$1755 = \wp$1751 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 1'h1 : 1'h0; - assign \$1757 = \fus_nia_ok$158 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$20 ; - assign \$1760 = wrpick_STATE_nia_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_STATE_nia_en_o; - assign \$1763 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1762 ; - assign \$1765 = \wr_pick$1759 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1763 ; - assign \$1768 = \wr_pick$1759 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_STATE_nia_en_o; - assign \$1771 = \wp$1767 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 1'h1 : 1'h0; - assign \$1773 = \fus_dest3_o$159 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest4_o$160 ; - assign \$1776 = \addr_en$1754 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1770 ; - assign \$1775 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \$1776 ; - assign \$1779 = fus_msr_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$20 ; - assign \$1781 = \fus_cu_wr__rel_o$96 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[3]; - assign \$1784 = wrpick_STATE_msr_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_STATE_msr_en_o; - assign \$1787 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1786 ; - assign \$1789 = \wr_pick$1783 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1787 ; - assign \$1792 = \wr_pick$1783 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_STATE_msr_en_o; - assign \$1795 = \wp$1791 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 2'h2 : 2'h0; - assign \$1797 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) \addr_en$1794 ; - assign \$1799 = fus_spr1_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$26 ; - assign \$1801 = \fus_cu_wr__rel_o$102 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[5]; - assign \$1804 = wrpick_SPR_spr1_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_SPR_spr1_en_o; - assign \$1807 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1806 ; - assign \$1809 = \wr_pick$1803 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1807 ; - assign \$1812 = \wr_pick$1803 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_SPR_spr1_en_o; - assign \$1815 = \wp$1811 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_spro : 10'h000; - assign \$182 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) 2'h2; - assign \$181 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) \$182 ; - assign \$186 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) 7'h40; - assign \$185 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) \$186 ; - assign \$190 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) 6'h20; - assign \$189 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) \$190 ; - assign \$194 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) 8'h80; - assign \$193 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) \$194 ; - assign \$198 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) 5'h10; - assign \$197 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) \$198 ; - assign \$202 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) 11'h400; - assign \$201 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) \$202 ; - assign \$206 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) 10'h200; - assign \$205 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) \$206 ; - assign \$210 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) 9'h100; - assign \$209 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) \$210 ; - assign \$214 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) 4'h8; - assign \$213 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) \$214 ; - assign \$218 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) 3'h4; - assign \$217 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) \$218 ; - assign \$221 = counter != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" *) 1'h0; - assign \$224 = counter - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" *) 1'h1; - assign \$226 = counter != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" *) 1'h0; - assign \$229 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok; - assign \$231 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; - assign \$233 = \$231 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; - assign \$235 = \$229 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) \$233 ; - assign \$237 = core_core_rc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) core_core_rc_ok; - assign \$239 = \$235 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) \$237 ; - assign \$241 = core_core_input_carry == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" *) 2'h2; - assign \$243 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4; - assign \$245 = \$243 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4; - assign \$247 = \$241 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) \$245 ; - assign \$228 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) { \$247 , \$239 , core_reg2_ok, core_reg1_ok }; - assign \$250 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) { \core_cr_in2_ok$2 , core_cr_in2_ok, core_cr_in1_ok, core_core_cr_rd_ok, core_reg2_ok, core_reg1_ok }; - assign \$252 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) { core_cr_in1_ok, core_fast2_ok, core_fast1_ok }; - assign \$254 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) { core_fast2_ok, core_fast1_ok, core_reg2_ok, core_reg1_ok }; - assign \$257 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok; - assign \$259 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; - assign \$261 = \$259 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; - assign \$263 = \$257 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) \$261 ; - assign \$265 = core_core_rc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) core_core_rc_ok; - assign \$267 = \$263 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) \$265 ; - assign \$256 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) { \$267 , core_reg2_ok, core_reg1_ok }; - assign \$271 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok; - assign \$273 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; - assign \$275 = \$273 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; - assign \$277 = \$271 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) \$275 ; - assign \$279 = core_core_rc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) core_core_rc_ok; - assign \$281 = \$277 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) \$279 ; - assign \$283 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" *) core_core_oe_ok; - assign \$285 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) 2'h2; - assign \$287 = \$285 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) 2'h2; - assign \$289 = \$283 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) \$287 ; - assign \$291 = core_core_input_carry == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" *) 2'h2; - assign \$293 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4; - assign \$295 = \$293 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4; - assign \$297 = \$291 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) \$295 ; - assign \$270 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) { \$297 , \$289 , \$281 , core_fast1_ok, core_spr1_ok, core_reg1_ok }; - assign \$301 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok; - assign \$303 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; - assign \$305 = \$303 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; - assign \$307 = \$301 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) \$305 ; - assign \$309 = core_core_rc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) core_core_rc_ok; - assign \$311 = \$307 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) \$309 ; - assign \$300 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) { \$311 , core_reg2_ok, core_reg1_ok }; - assign \$315 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok; - assign \$317 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; - assign \$319 = \$317 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; - assign \$321 = \$315 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) \$319 ; - assign \$323 = core_core_rc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) core_core_rc_ok; - assign \$325 = \$321 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) \$323 ; - assign \$314 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) { \$325 , core_reg2_ok, core_reg1_ok }; - assign \$329 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok; - assign \$331 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; - assign \$333 = \$331 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; - assign \$335 = \$329 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) \$333 ; - assign \$337 = core_core_rc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) core_core_rc_ok; - assign \$339 = \$335 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) \$337 ; - assign \$341 = core_core_input_carry == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" *) 2'h2; - assign \$343 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4; - assign \$345 = \$343 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4; - assign \$347 = \$341 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) \$345 ; - assign \$328 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) { \$347 , \$339 , core_reg3_ok, core_reg2_ok, core_reg1_ok }; - assign \$350 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) { core_reg3_ok, core_reg2_ok, core_reg1_ok }; - assign \$352 = fus_cu_rd__rel_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[0]; - assign \$354 = \$352 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_0; - assign \$356 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_alu0_0; - assign \$358 = \$354 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$356 ; - assign \$360 = rdpick_INT_rabc_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; - assign \$362 = rp_INT_rabc_alu0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg2 : 7'h00; - assign \$364 = \fus_cu_rd__rel_o$40 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[1]; - assign \$366 = \$364 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_0; - assign \$368 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_cr0_1; - assign \$370 = \$366 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$368 ; - assign \$372 = rdpick_INT_rabc_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; - assign \$374 = rp_INT_rabc_cr0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg2 : 7'h00; - assign \$376 = \fus_cu_rd__rel_o$43 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[3]; - assign \$378 = \$376 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_0; - assign \$380 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_trap0_2; - assign \$382 = \$378 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$380 ; - assign \$384 = rdpick_INT_rabc_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; - assign \$386 = rp_INT_rabc_trap0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg2 : 7'h00; - assign \$388 = \fus_cu_rd__rel_o$46 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[4]; - assign \$390 = \$388 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_0; - assign \$392 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_logical0_3; - assign \$394 = \$390 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$392 ; - assign \$396 = rdpick_INT_rabc_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; - assign \$398 = rp_INT_rabc_logical0_3 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg2 : 7'h00; - assign \$400 = \fus_cu_rd__rel_o$49 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[6]; - assign \$402 = \$400 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_0; - assign \$404 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_div0_4; - assign \$406 = \$402 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$404 ; - assign \$408 = rdpick_INT_rabc_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; - assign \$410 = rp_INT_rabc_div0_4 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg2 : 7'h00; - assign \$412 = \fus_cu_rd__rel_o$52 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[7]; - assign \$414 = \$412 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_0; - assign \$416 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_mul0_5; - assign \$418 = \$414 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$416 ; - assign \$420 = rdpick_INT_rabc_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; - assign \$422 = rp_INT_rabc_mul0_5 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg2 : 7'h00; - assign \$424 = \fus_cu_rd__rel_o$55 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[8]; - assign \$426 = \$424 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_0; - assign \$428 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_shiftrot0_6; - assign \$430 = \$426 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$428 ; - assign \$432 = rdpick_INT_rabc_o[6] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; - assign \$434 = rp_INT_rabc_shiftrot0_6 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg2 : 7'h00; - assign \$436 = \fus_cu_rd__rel_o$58 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[9]; - assign \$438 = \$436 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_0; - assign \$440 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_ldst0_7; - assign \$442 = \$438 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$440 ; - assign \$444 = rdpick_INT_rabc_o[7] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; - assign \$446 = rp_INT_rabc_ldst0_7 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg2 : 7'h00; - assign \$448 = \fus_cu_rd__rel_o$55 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[8]; - assign \$450 = \$448 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_1; - assign \$452 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_shiftrot0_8; - assign \$454 = \$450 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$452 ; - assign \$456 = rdpick_INT_rabc_o[8] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; - assign \$458 = rp_INT_rabc_shiftrot0_8 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg3 : 7'h00; - assign \$460 = \fus_cu_rd__rel_o$58 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[9]; - assign \$462 = \$460 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_1; - assign \$464 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_ldst0_9; - assign \$466 = \$462 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$464 ; - assign \$468 = rdpick_INT_rabc_o[9] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; - assign \$470 = rp_INT_rabc_ldst0_9 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg3 : 7'h00; - assign \$472 = fus_cu_rd__rel_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[0]; - assign \$474 = \$472 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_2; - assign \$476 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_alu0_10; - assign \$478 = \$474 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$476 ; - assign \$480 = rdpick_INT_rabc_o[10] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; - assign \$482 = rp_INT_rabc_alu0_10 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg1 : 7'h00; - assign \$484 = \fus_cu_rd__rel_o$40 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[1]; - assign \$486 = \$484 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_2; - assign \$488 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_cr0_11; - assign \$490 = \$486 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$488 ; - assign \$492 = rdpick_INT_rabc_o[11] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; - assign \$494 = rp_INT_rabc_cr0_11 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg1 : 7'h00; - assign \$496 = \fus_cu_rd__rel_o$43 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[3]; - assign \$498 = \$496 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_2; - assign \$500 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_trap0_12; - assign \$502 = \$498 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$500 ; - assign \$504 = rdpick_INT_rabc_o[12] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; - assign \$506 = rp_INT_rabc_trap0_12 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg1 : 7'h00; - assign \$508 = \fus_cu_rd__rel_o$46 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[4]; - assign \$510 = \$508 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_2; - assign \$512 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_logical0_13; - assign \$514 = \$510 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$512 ; - assign \$516 = rdpick_INT_rabc_o[13] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; - assign \$518 = rp_INT_rabc_logical0_13 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg1 : 7'h00; - assign \$520 = \fus_cu_rd__rel_o$65 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[5]; - assign \$522 = \$520 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_2; - assign \$524 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_spr0_14; - assign \$526 = \$522 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$524 ; - assign \$528 = rdpick_INT_rabc_o[14] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; - assign \$530 = rp_INT_rabc_spr0_14 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg1 : 7'h00; - assign \$532 = \fus_cu_rd__rel_o$49 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[6]; - assign \$534 = \$532 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_2; - assign \$536 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_div0_15; - assign \$538 = \$534 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$536 ; - assign \$540 = rdpick_INT_rabc_o[15] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; - assign \$542 = rp_INT_rabc_div0_15 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg1 : 7'h00; - assign \$544 = \fus_cu_rd__rel_o$52 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[7]; - assign \$546 = \$544 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_2; - assign \$548 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_mul0_16; - assign \$550 = \$546 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$548 ; - assign \$552 = rdpick_INT_rabc_o[16] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; - assign \$554 = rp_INT_rabc_mul0_16 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg1 : 7'h00; - assign \$556 = \fus_cu_rd__rel_o$55 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[8]; - assign \$558 = \$556 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_2; - assign \$560 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_shiftrot0_17; - assign \$562 = \$558 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$560 ; - assign \$564 = rdpick_INT_rabc_o[17] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; - assign \$566 = rp_INT_rabc_shiftrot0_17 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg1 : 7'h00; - assign \$568 = \fus_cu_rd__rel_o$58 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[9]; - assign \$570 = \$568 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_2; - assign \$572 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_ldst0_18; - assign \$574 = \$570 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$572 ; - assign \$576 = rdpick_INT_rabc_o[18] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o; - assign \$578 = rp_INT_rabc_ldst0_18 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg1 : 7'h00; - assign \$581 = addr_en_INT_rabc_alu0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_cr0_1; - assign \$583 = addr_en_INT_rabc_trap0_2 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_logical0_3; - assign \$585 = \$581 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$583 ; - assign \$587 = addr_en_INT_rabc_div0_4 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_mul0_5; - assign \$589 = addr_en_INT_rabc_ldst0_7 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_shiftrot0_8; - assign \$591 = addr_en_INT_rabc_shiftrot0_6 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$589 ; - assign \$593 = \$587 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$591 ; - assign \$595 = \$585 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$593 ; - assign \$597 = addr_en_INT_rabc_ldst0_9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_alu0_10; - assign \$599 = addr_en_INT_rabc_trap0_12 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_logical0_13; - assign \$601 = addr_en_INT_rabc_cr0_11 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$599 ; - assign \$603 = \$597 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$601 ; - assign \$605 = addr_en_INT_rabc_spr0_14 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_div0_15; - assign \$607 = addr_en_INT_rabc_shiftrot0_17 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_ldst0_18; - assign \$609 = addr_en_INT_rabc_mul0_16 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$607 ; - assign \$611 = \$605 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$609 ; - assign \$613 = \$603 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$611 ; - assign \$615 = \$595 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$613 ; - assign \$617 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:325" *) { rp_INT_rabc_ldst0_18, rp_INT_rabc_shiftrot0_17, rp_INT_rabc_mul0_16, rp_INT_rabc_div0_15, rp_INT_rabc_spr0_14, rp_INT_rabc_logical0_13, rp_INT_rabc_trap0_12, rp_INT_rabc_cr0_11, rp_INT_rabc_alu0_10, rp_INT_rabc_ldst0_9, rp_INT_rabc_shiftrot0_8, rp_INT_rabc_ldst0_7, rp_INT_rabc_shiftrot0_6, rp_INT_rabc_mul0_5, rp_INT_rabc_div0_4, rp_INT_rabc_logical0_3, rp_INT_rabc_trap0_2, rp_INT_rabc_cr0_1, rp_INT_rabc_alu0_0 }; - assign \$619 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok; - assign \$621 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; - assign \$623 = \$621 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1; - assign \$625 = \$619 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) \$623 ; - assign \$627 = core_core_rc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) core_core_rc_ok; - assign \$629 = \$625 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) \$627 ; - assign \$631 = fus_cu_rd__rel_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[0]; - assign \$633 = \$631 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_XER_xer_so_0; - assign \$635 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_XER_xer_so_alu0_0; - assign \$637 = \$633 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$635 ; - assign \$639 = rdpick_XER_xer_so_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_XER_xer_so_en_o; - assign \$641 = rp_XER_xer_so_alu0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) 1'h1 : 1'h0; - assign \$643 = \fus_cu_rd__rel_o$46 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[4]; - assign \$645 = \$643 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_XER_xer_so_0; - assign \$647 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_XER_xer_so_logical0_1; - assign \$649 = \$645 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$647 ; - assign \$651 = rdpick_XER_xer_so_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_XER_xer_so_en_o; - assign \$653 = rp_XER_xer_so_logical0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) 1'h1 : 1'h0; - assign \$655 = \fus_cu_rd__rel_o$65 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[5]; - assign \$657 = \$655 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_XER_xer_so_0; - assign \$659 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_XER_xer_so_spr0_2; - assign \$661 = \$657 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$659 ; - assign \$663 = rdpick_XER_xer_so_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_XER_xer_so_en_o; - assign \$665 = rp_XER_xer_so_spr0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) 1'h1 : 1'h0; - assign \$667 = \fus_cu_rd__rel_o$49 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[6]; - assign \$669 = \$667 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_XER_xer_so_0; - assign \$671 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_XER_xer_so_div0_3; - assign \$673 = \$669 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$671 ; - assign \$675 = rdpick_XER_xer_so_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_XER_xer_so_en_o; - assign \$677 = rp_XER_xer_so_div0_3 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) 1'h1 : 1'h0; - assign \$679 = \fus_cu_rd__rel_o$52 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[7]; - assign \$681 = \$679 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_XER_xer_so_0; - assign \$683 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_XER_xer_so_mul0_4; - assign \$685 = \$681 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$683 ; - assign \$687 = rdpick_XER_xer_so_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_XER_xer_so_en_o; - assign \$689 = rp_XER_xer_so_mul0_4 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) 1'h1 : 1'h0; - assign \$691 = \fus_cu_rd__rel_o$55 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[8]; - assign \$693 = \$691 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_XER_xer_so_0; - assign \$695 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_XER_xer_so_shiftrot0_5; - assign \$697 = \$693 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$695 ; - assign \$699 = rdpick_XER_xer_so_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_XER_xer_so_en_o; - assign \$701 = rp_XER_xer_so_shiftrot0_5 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) 1'h1 : 1'h0; - assign \$704 = addr_en_XER_xer_so_logical0_1 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_XER_xer_so_spr0_2; - assign \$706 = addr_en_XER_xer_so_alu0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$704 ; - assign \$708 = addr_en_XER_xer_so_mul0_4 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_XER_xer_so_shiftrot0_5; - assign \$710 = addr_en_XER_xer_so_div0_3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$708 ; - assign \$712 = \$706 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$710 ; - assign \$703 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$712 ; - assign \$715 = core_core_input_carry == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" *) 2'h2; - assign \$717 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4; - assign \$719 = \$717 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4; - assign \$721 = \$715 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) \$719 ; - assign \$723 = fus_cu_rd__rel_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[0]; - assign \$725 = \$723 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_XER_xer_ca_0; - assign \$727 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_XER_xer_ca_alu0_0; - assign \$729 = \$725 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$727 ; - assign \$731 = rdpick_XER_xer_ca_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_XER_xer_ca_en_o; - assign \$733 = rp_XER_xer_ca_alu0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) 2'h2 : 2'h0; - assign \$735 = \fus_cu_rd__rel_o$65 [5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[5]; - assign \$737 = \$735 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_XER_xer_ca_0; - assign \$739 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_XER_xer_ca_spr0_1; - assign \$741 = \$737 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$739 ; - assign \$743 = rdpick_XER_xer_ca_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_XER_xer_ca_en_o; - assign \$745 = rp_XER_xer_ca_spr0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) 2'h2 : 2'h0; - assign \$747 = \fus_cu_rd__rel_o$55 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[8]; - assign \$749 = \$747 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_XER_xer_ca_0; - assign \$751 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_XER_xer_ca_shiftrot0_2; - assign \$753 = \$749 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$751 ; - assign \$755 = rdpick_XER_xer_ca_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_XER_xer_ca_en_o; - assign \$757 = rp_XER_xer_ca_shiftrot0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) 2'h2 : 2'h0; - assign \$760 = addr_en_XER_xer_ca_spr0_1 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_XER_xer_ca_shiftrot0_2; - assign \$762 = addr_en_XER_xer_ca_alu0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$760 ; - assign \$759 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$762 ; - assign \$765 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" *) core_core_oe_ok; - assign \$767 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) 2'h2; - assign \$769 = \$767 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) 2'h2; - assign \$771 = \$765 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) \$769 ; - assign \$773 = \fus_cu_rd__rel_o$65 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[5]; - assign \$775 = \$773 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_XER_xer_ov_0; - assign \$777 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_XER_xer_ov_spr0_0; - assign \$779 = \$775 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$777 ; - assign \$781 = rdpick_XER_xer_ov_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_XER_xer_ov_en_o; - assign \$783 = rp_XER_xer_ov_spr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) 3'h4 : 3'h0; - assign \$785 = \fus_cu_rd__rel_o$40 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[1]; - assign \$787 = \$785 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_CR_full_cr_0; - assign \$789 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_CR_full_cr_cr0_0; - assign \$791 = \$787 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$789 ; - assign \$793 = rdpick_CR_full_cr_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_CR_full_cr_en_o; - assign \$795 = rp_CR_full_cr_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_core_cr_rd : 8'h00; - assign \$797 = \fus_cu_rd__rel_o$40 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[1]; - assign \$799 = \$797 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_CR_cr_a_0; - assign \$801 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_CR_cr_a_cr0_0; - assign \$803 = \$799 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$801 ; - assign \$805 = rdpick_CR_cr_a_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_CR_cr_a_en_o; - assign \$807 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *) core_cr_in1; - assign \$809 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *) \$807 ; - assign \$811 = rp_CR_cr_a_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) \$809 : 256'h0000000000000000000000000000000000000000000000000000000000000000; - assign \$813 = \fus_cu_rd__rel_o$81 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[2]; - assign \$815 = \$813 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_CR_cr_a_0; - assign \$817 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_CR_cr_a_branch0_1; - assign \$819 = \$815 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$817 ; - assign \$821 = rdpick_CR_cr_a_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_CR_cr_a_en_o; - assign \$823 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *) core_cr_in1; - assign \$825 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *) \$823 ; - assign \$827 = rp_CR_cr_a_branch0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) \$825 : 256'h0000000000000000000000000000000000000000000000000000000000000000; - assign \$830 = addr_en_CR_cr_a_cr0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_CR_cr_a_branch0_1; - assign \$832 = \fus_cu_rd__rel_o$40 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[1]; - assign \$834 = \$832 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_CR_cr_b_0; - assign \$836 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_CR_cr_b_cr0_0; - assign \$838 = \$834 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$836 ; - assign \$840 = rdpick_CR_cr_b_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_CR_cr_b_en_o; - assign \$842 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" *) core_cr_in2; - assign \$844 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" *) \$842 ; - assign \$846 = rp_CR_cr_b_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) \$844 : 256'h0000000000000000000000000000000000000000000000000000000000000000; - assign \$848 = \fus_cu_rd__rel_o$40 [5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[1]; - assign \$850 = \$848 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_CR_cr_c_0; - assign \$852 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_CR_cr_c_cr0_0; - assign \$854 = \$850 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$852 ; - assign \$856 = rdpick_CR_cr_c_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_CR_cr_c_en_o; - assign \$858 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" *) \core_cr_in2$1 ; - assign \$860 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" *) \$858 ; - assign \$862 = rp_CR_cr_c_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) \$860 : 256'h0000000000000000000000000000000000000000000000000000000000000000; - assign \$864 = \fus_cu_rd__rel_o$81 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[2]; - assign \$866 = \$864 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_FAST_fast1_0; - assign \$868 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_FAST_fast1_branch0_0; - assign \$870 = \$866 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$868 ; - assign \$872 = rdpick_FAST_fast1_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_FAST_fast1_en_o; - assign \$874 = rp_FAST_fast1_branch0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_fast1 : 3'h0; - assign \$876 = \fus_cu_rd__rel_o$43 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[3]; - assign \$878 = \$876 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_FAST_fast1_0; - assign \$880 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_FAST_fast1_trap0_1; - assign \$882 = \$878 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$880 ; - assign \$884 = rdpick_FAST_fast1_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_FAST_fast1_en_o; - assign \$886 = rp_FAST_fast1_trap0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_fast1 : 3'h0; - assign \$888 = \fus_cu_rd__rel_o$65 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[5]; - assign \$890 = \$888 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_FAST_fast1_0; - assign \$892 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_FAST_fast1_spr0_2; - assign \$894 = \$890 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$892 ; - assign \$896 = rdpick_FAST_fast1_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_FAST_fast1_en_o; - assign \$898 = rp_FAST_fast1_spr0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_fast1 : 3'h0; - assign \$900 = \fus_cu_rd__rel_o$81 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[2]; - assign \$902 = \$900 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_FAST_fast1_1; - assign \$904 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_FAST_fast1_branch0_3; - assign \$906 = \$902 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$904 ; - assign \$908 = rdpick_FAST_fast1_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_FAST_fast1_en_o; - assign \$910 = rp_FAST_fast1_branch0_3 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_fast2 : 3'h0; - assign \$912 = \fus_cu_rd__rel_o$43 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[3]; - assign \$914 = \$912 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_FAST_fast1_1; - assign \$916 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_FAST_fast1_trap0_4; - assign \$918 = \$914 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$916 ; - assign \$920 = rdpick_FAST_fast1_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_FAST_fast1_en_o; - assign \$922 = rp_FAST_fast1_trap0_4 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_fast2 : 3'h0; - assign \$924 = addr_en_FAST_fast1_branch0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_FAST_fast1_trap0_1; - assign \$926 = addr_en_FAST_fast1_branch0_3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_FAST_fast1_trap0_4; - assign \$928 = addr_en_FAST_fast1_spr0_2 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$926 ; - assign \$930 = \$924 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$928 ; - assign \$932 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:325" *) { rp_FAST_fast1_trap0_4, rp_FAST_fast1_branch0_3, rp_FAST_fast1_spr0_2, rp_FAST_fast1_trap0_1, rp_FAST_fast1_branch0_0 }; - assign \$934 = \fus_cu_rd__rel_o$65 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[5]; - assign \$936 = \$934 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_SPR_spr1_0; - assign \$938 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_SPR_spr1_spr0_0; - assign \$940 = \$936 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$938 ; - assign \$942 = rdpick_SPR_spr1_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_SPR_spr1_en_o; - assign \$944 = rp_SPR_spr1_spr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_spr1 : 10'h000; - assign \$946 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:325" *) rp_SPR_spr1_spr0_0; - assign \$948 = fus_o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) fus_cu_busy_o; - assign \$950 = fus_cu_wr__rel_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[0]; - assign \$952 = \fus_cu_wr__rel_o$93 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[1]; - assign \$954 = \fus_cu_wr__rel_o$96 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[3]; - assign \$956 = \fus_cu_wr__rel_o$99 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[4]; - assign \$958 = \fus_cu_wr__rel_o$102 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[5]; - assign \$960 = \fus_cu_wr__rel_o$105 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[6]; - assign \$962 = \fus_cu_wr__rel_o$108 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[7]; - assign \$964 = \fus_cu_wr__rel_o$111 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[8]; - assign \$966 = \fus_cu_wr__rel_o$113 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[9]; - assign \$968 = \fus_cu_wr__rel_o$113 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[9]; - assign \$970 = wrpick_INT_o_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_INT_o_en_o; - assign \$972 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wr_pick_dly; - assign \$974 = wr_pick & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$972 ; - assign \$980 = wr_pick & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_INT_o_en_o; - assign \$982 = wp ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_rego : 7'h00; - assign \$984 = \fus_o_ok$92 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$14 ; - assign \$987 = wrpick_INT_o_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_INT_o_en_o; - assign \$991 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$989 ; - assign \$993 = \wr_pick$986 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$991 ; - assign \$998 = \wr_pick$986 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_INT_o_en_o; - always @(posedge coresync_clk) - \wr_pick_dly$1806 <= \wr_pick_dly$1806$next ; - always @(posedge coresync_clk) - \wr_pick_dly$1786 <= \wr_pick_dly$1786$next ; - always @(posedge coresync_clk) - \wr_pick_dly$1762 <= \wr_pick_dly$1762$next ; - always @(posedge coresync_clk) - \wr_pick_dly$1746 <= \wr_pick_dly$1746$next ; - always @(posedge coresync_clk) - \wr_pick_dly$1702 <= \wr_pick_dly$1702$next ; - always @(posedge coresync_clk) - \wr_pick_dly$1686 <= \wr_pick_dly$1686$next ; - always @(posedge coresync_clk) - \wr_pick_dly$1670 <= \wr_pick_dly$1670$next ; - always @(posedge coresync_clk) - \wr_pick_dly$1654 <= \wr_pick_dly$1654$next ; - always @(posedge coresync_clk) - \wr_pick_dly$1635 <= \wr_pick_dly$1635$next ; - always @(posedge coresync_clk) - \wr_pick_dly$1593 <= \wr_pick_dly$1593$next ; - always @(posedge coresync_clk) - \wr_pick_dly$1577 <= \wr_pick_dly$1577$next ; - always @(posedge coresync_clk) - \wr_pick_dly$1561 <= \wr_pick_dly$1561$next ; - always @(posedge coresync_clk) - \wr_pick_dly$1545 <= \wr_pick_dly$1545$next ; - always @(posedge coresync_clk) - \wr_pick_dly$1509 <= \wr_pick_dly$1509$next ; - always @(posedge coresync_clk) - \wr_pick_dly$1493 <= \wr_pick_dly$1493$next ; - always @(posedge coresync_clk) - \wr_pick_dly$1477 <= \wr_pick_dly$1477$next ; + assign \$1081 = \wr_pick$1066 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_INT_o_en_o; + assign \$1084 = \wp$1080 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_rego : 7'h00; + assign \$1086 = \fus_o_ok$105 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$29 ; + assign \$1089 = wrpick_INT_o_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_INT_o_en_o; + assign \$1093 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1091 ; + assign \$1095 = \wr_pick$1088 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1093 ; + assign \$1101 = \wr_pick$1088 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_INT_o_en_o; + assign \$1104 = \wp$1100 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_rego : 7'h00; + assign \$1106 = \fus_o_ok$108 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$32 ; + assign \$1109 = wrpick_INT_o_o[6] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_INT_o_en_o; + assign \$1113 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1111 ; + assign \$1115 = \wr_pick$1108 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1113 ; + assign \$1121 = \wr_pick$1108 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_INT_o_en_o; + assign \$1124 = \wp$1120 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_rego : 7'h00; + assign \$1126 = \fus_o_ok$111 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$35 ; + assign \$1129 = wrpick_INT_o_o[7] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_INT_o_en_o; + assign \$1133 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1131 ; + assign \$1135 = \wr_pick$1128 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1133 ; + assign \$1140 = \wr_pick$1128 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_INT_o_en_o; + assign \$1143 = \wp$1139 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_rego : 7'h00; + assign \$1145 = o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$38 ; + assign \$1148 = wrpick_INT_o_o[8] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_INT_o_en_o; + assign \$1152 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1150 ; + assign \$1154 = \wr_pick$1147 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1152 ; + assign \$1158 = \wr_pick$1147 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_INT_o_en_o; + assign \$1161 = \wp$1157 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_rego : 7'h00; + assign \$1163 = ea_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$38 ; + assign \$1166 = wrpick_INT_o_o[9] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_INT_o_en_o; + assign \$1169 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1168 ; + assign \$1171 = \wr_pick$1165 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1169 ; + assign \$1174 = \wr_pick$1165 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_INT_o_en_o; + assign \$1177 = \wp$1173 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_ea : 7'h00; + assign \$1180 = fus_dest1_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest1_o$116 ; + assign \$1182 = \fus_dest1_o$118 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest1_o$119 ; + assign \$1184 = \fus_dest1_o$117 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1182 ; + assign \$1186 = \$1180 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1184 ; + assign \$1188 = \fus_dest1_o$120 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest1_o$121 ; + assign \$1190 = { o_ok, fus_o } | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:258" *) { ea_ok, fus_ea }; + assign \$1192 = \fus_dest1_o$122 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1190 ; + assign \$1194 = \$1188 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1192 ; + assign \$1196 = \$1186 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1194 ; + assign \$1199 = addr_en | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1020 ; + assign \$1201 = \addr_en$1061 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1083 ; + assign \$1203 = \addr_en$1043 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1201 ; + assign \$1205 = \$1199 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1203 ; + assign \$1207 = \addr_en$1103 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1123 ; + assign \$1209 = \addr_en$1160 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1176 ; + assign \$1211 = \addr_en$1142 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1209 ; + assign \$1213 = \$1207 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1211 ; + assign \$1215 = \$1205 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1213 ; + assign \$1217 = wp | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1017 ; + assign \$1219 = \wp$1058 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1080 ; + assign \$1221 = \wp$1040 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1219 ; + assign \$1223 = \$1217 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1221 ; + assign \$1225 = \wp$1100 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1120 ; + assign \$1227 = \wp$1157 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1173 ; + assign \$1229 = \wp$1139 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1227 ; + assign \$1231 = \$1225 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1229 ; + assign \$1233 = \$1223 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1231 ; + assign \$1235 = fus_full_cr_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$14 ; + assign \$1237 = \fus_cu_wr__rel_o$94 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[1]; + assign \$1240 = wrpick_CR_full_cr_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_CR_full_cr_en_o; + assign \$1243 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1242 ; + assign \$1245 = \wr_pick$1239 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1243 ; + assign \$1248 = \wr_pick$1239 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_CR_full_cr_en_o; + assign \$1251 = \wp$1247 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_core_cr_wr : 8'h00; + assign \$1253 = fus_cr_a_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) fus_cu_busy_o; + assign \$1255 = fus_cu_wr__rel_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[0]; + assign \$1257 = \fus_cu_wr__rel_o$94 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[1]; + assign \$1259 = \fus_cu_wr__rel_o$100 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[4]; + assign \$1261 = \fus_cu_wr__rel_o$106 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[6]; + assign \$1263 = \fus_cu_wr__rel_o$109 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[7]; + assign \$1265 = \fus_cu_wr__rel_o$112 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[8]; + assign \$1268 = wrpick_CR_cr_a_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_CR_cr_a_en_o; + assign \$1271 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1270 ; + assign \$1273 = \wr_pick$1267 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1271 ; + assign \$1276 = \wr_pick$1267 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_CR_cr_a_en_o; + assign \$1279 = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) core_cr_out; + assign \$1281 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) \$1279 ; + assign \$1283 = \wp$1275 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) \$1281 : 256'h0000000000000000000000000000000000000000000000000000000000000000; + assign \$1285 = \fus_cr_a_ok$123 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$14 ; + assign \$1288 = wrpick_CR_cr_a_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_CR_cr_a_en_o; + assign \$1291 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1290 ; + assign \$1293 = \wr_pick$1287 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1291 ; + assign \$1296 = \wr_pick$1287 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_CR_cr_a_en_o; + assign \$1299 = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) core_cr_out; + assign \$1301 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) \$1299 ; + assign \$1303 = \wp$1295 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) \$1301 : 256'h0000000000000000000000000000000000000000000000000000000000000000; + assign \$1305 = \fus_cr_a_ok$124 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$23 ; + assign \$1308 = wrpick_CR_cr_a_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_CR_cr_a_en_o; + assign \$1311 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1310 ; + assign \$1313 = \wr_pick$1307 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1311 ; + assign \$1316 = \wr_pick$1307 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_CR_cr_a_en_o; + assign \$1319 = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) core_cr_out; + assign \$1321 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) \$1319 ; + assign \$1323 = \wp$1315 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) \$1321 : 256'h0000000000000000000000000000000000000000000000000000000000000000; + assign \$1325 = \fus_cr_a_ok$125 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$29 ; + assign \$1328 = wrpick_CR_cr_a_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_CR_cr_a_en_o; + assign \$1331 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1330 ; + assign \$1333 = \wr_pick$1327 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1331 ; + assign \$1336 = \wr_pick$1327 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_CR_cr_a_en_o; + assign \$1339 = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) core_cr_out; + assign \$1341 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) \$1339 ; + assign \$1343 = \wp$1335 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) \$1341 : 256'h0000000000000000000000000000000000000000000000000000000000000000; + assign \$1345 = \fus_cr_a_ok$126 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$32 ; + assign \$1348 = wrpick_CR_cr_a_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_CR_cr_a_en_o; + assign \$1351 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1350 ; + assign \$1353 = \wr_pick$1347 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1351 ; + assign \$1356 = \wr_pick$1347 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_CR_cr_a_en_o; + assign \$1359 = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) core_cr_out; + assign \$1361 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) \$1359 ; + assign \$1363 = \wp$1355 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) \$1361 : 256'h0000000000000000000000000000000000000000000000000000000000000000; + assign \$1365 = \fus_cr_a_ok$127 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$35 ; + assign \$1368 = wrpick_CR_cr_a_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_CR_cr_a_en_o; + assign \$1371 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1370 ; + assign \$1373 = \wr_pick$1367 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1371 ; + assign \$1376 = \wr_pick$1367 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_CR_cr_a_en_o; + assign \$1379 = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) core_cr_out; + assign \$1381 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:145" *) \$1379 ; + assign \$1383 = \wp$1375 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) \$1381 : 256'h0000000000000000000000000000000000000000000000000000000000000000; + assign \$1385 = fus_dest3_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest2_o$129 ; + assign \$1387 = \fus_dest2_o$128 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1385 ; + assign \$1389 = \fus_dest2_o$131 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest2_o$132 ; + assign \$1391 = \fus_dest2_o$130 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1389 ; + assign \$1393 = \$1387 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1391 ; + assign \$1396 = \addr_en$1298 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1318 ; + assign \$1398 = \addr_en$1278 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1396 ; + assign \$1400 = \addr_en$1358 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1378 ; + assign \$1402 = \addr_en$1338 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1400 ; + assign \$1404 = \$1398 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1402 ; + assign \$1406 = fus_xer_ca_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) fus_cu_busy_o; + assign \$1408 = fus_cu_wr__rel_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[0]; + assign \$1410 = \fus_cu_wr__rel_o$103 [5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[5]; + assign \$1412 = \fus_cu_wr__rel_o$112 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[8]; + assign \$1415 = wrpick_XER_xer_ca_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_XER_xer_ca_en_o; + assign \$1418 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1417 ; + assign \$1420 = \wr_pick$1414 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1418 ; + assign \$1423 = \wr_pick$1414 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_XER_xer_ca_en_o; + assign \$1426 = \wp$1422 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 2'h2 : 2'h0; + assign \$1428 = \fus_xer_ca_ok$133 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$26 ; + assign \$1431 = wrpick_XER_xer_ca_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_XER_xer_ca_en_o; + assign \$1434 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1433 ; + assign \$1436 = \wr_pick$1430 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1434 ; + assign \$1439 = \wr_pick$1430 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_XER_xer_ca_en_o; + assign \$1442 = \wp$1438 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 2'h2 : 2'h0; + assign \$1444 = \fus_xer_ca_ok$134 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$35 ; + assign \$1447 = wrpick_XER_xer_ca_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_XER_xer_ca_en_o; + assign \$1450 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1449 ; + assign \$1452 = \wr_pick$1446 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1450 ; + assign \$1455 = \wr_pick$1446 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_XER_xer_ca_en_o; + assign \$1458 = \wp$1454 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 2'h2 : 2'h0; + assign \$1460 = fus_dest6_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest3_o$136 ; + assign \$1462 = \fus_dest3_o$135 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1460 ; + assign \$1465 = \addr_en$1441 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1457 ; + assign \$1467 = \addr_en$1425 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1465 ; + assign \$1464 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1467 ; + assign \$1470 = fus_xer_ov_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) fus_cu_busy_o; + assign \$1472 = fus_cu_wr__rel_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[0]; + assign \$1474 = \fus_cu_wr__rel_o$103 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[5]; + assign \$1476 = \fus_cu_wr__rel_o$106 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[6]; + assign \$1478 = \fus_cu_wr__rel_o$109 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[7]; + assign \$1481 = wrpick_XER_xer_ov_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_XER_xer_ov_en_o; + assign \$1484 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1483 ; + assign \$1486 = \wr_pick$1480 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1484 ; + assign \$1489 = \wr_pick$1480 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_XER_xer_ov_en_o; + assign \$1492 = \wp$1488 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 3'h4 : 3'h0; + assign \$1494 = \fus_xer_ov_ok$137 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$26 ; + assign \$1497 = wrpick_XER_xer_ov_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_XER_xer_ov_en_o; + assign \$1500 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1499 ; + assign \$1502 = \wr_pick$1496 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1500 ; + assign \$1505 = \wr_pick$1496 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_XER_xer_ov_en_o; + assign \$1508 = \wp$1504 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 3'h4 : 3'h0; + assign \$1510 = \fus_xer_ov_ok$138 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$29 ; + assign \$1513 = wrpick_XER_xer_ov_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_XER_xer_ov_en_o; + assign \$1516 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1515 ; + assign \$1518 = \wr_pick$1512 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1516 ; + assign \$1521 = \wr_pick$1512 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_XER_xer_ov_en_o; + assign \$1524 = \wp$1520 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 3'h4 : 3'h0; + assign \$1526 = \fus_xer_ov_ok$139 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$32 ; + assign \$1529 = wrpick_XER_xer_ov_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_XER_xer_ov_en_o; + assign \$1532 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1531 ; + assign \$1534 = \wr_pick$1528 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1532 ; + assign \$1537 = \wr_pick$1528 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_XER_xer_ov_en_o; + assign \$1540 = \wp$1536 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 3'h4 : 3'h0; + assign \$1542 = fus_dest4_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) fus_dest5_o; + assign \$1544 = \fus_dest3_o$140 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest3_o$141 ; + assign \$1546 = \$1542 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1544 ; + assign \$1548 = \addr_en$1491 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1507 ; + assign \$1550 = \addr_en$1523 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1539 ; + assign \$1552 = \$1548 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1550 ; + assign \$1554 = fus_xer_so_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) fus_cu_busy_o; + assign \$1556 = fus_cu_wr__rel_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[0]; + assign \$1558 = \fus_cu_wr__rel_o$103 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[5]; + assign \$1560 = \fus_cu_wr__rel_o$106 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[6]; + assign \$1562 = \fus_cu_wr__rel_o$109 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[7]; + assign \$1565 = wrpick_XER_xer_so_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_XER_xer_so_en_o; + assign \$1568 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1567 ; + assign \$1570 = \wr_pick$1564 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1568 ; + assign \$1573 = \wr_pick$1564 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_XER_xer_so_en_o; + assign \$1576 = \wp$1572 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 1'h1 : 1'h0; + assign \$1578 = \fus_xer_so_ok$142 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$26 ; + assign \$1581 = wrpick_XER_xer_so_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_XER_xer_so_en_o; + assign \$1584 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1583 ; + assign \$1586 = \wr_pick$1580 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1584 ; + assign \$1589 = \wr_pick$1580 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_XER_xer_so_en_o; + assign \$1592 = \wp$1588 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 1'h1 : 1'h0; + assign \$1594 = \fus_xer_so_ok$143 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$29 ; + assign \$1597 = wrpick_XER_xer_so_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_XER_xer_so_en_o; + assign \$1600 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1599 ; + assign \$1602 = \wr_pick$1596 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1600 ; + assign \$1605 = \wr_pick$1596 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_XER_xer_so_en_o; + assign \$1608 = \wp$1604 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 1'h1 : 1'h0; + assign \$1610 = \fus_xer_so_ok$144 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$32 ; + assign \$1613 = wrpick_XER_xer_so_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_XER_xer_so_en_o; + assign \$1616 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1615 ; + assign \$1618 = \wr_pick$1612 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1616 ; + assign \$1621 = \wr_pick$1612 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_XER_xer_so_en_o; + assign \$1624 = \wp$1620 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 1'h1 : 1'h0; + assign \$1627 = \fus_dest5_o$145 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest4_o$146 ; + assign \$1629 = \fus_dest4_o$147 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest4_o$148 ; + assign \$1631 = \$1627 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1629 ; + assign \$1626 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1631 ; + assign \$1635 = \addr_en$1575 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1591 ; + assign \$1637 = \addr_en$1607 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1623 ; + assign \$1639 = \$1635 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1637 ; + assign \$1634 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1639 ; + assign \$1642 = fus_fast1_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$17 ; + assign \$1644 = \fus_cu_wr__rel_o$149 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[2]; + assign \$1646 = \fus_cu_wr__rel_o$97 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[3]; + assign \$1648 = \fus_cu_wr__rel_o$103 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[5]; + assign \$1650 = \fus_cu_wr__rel_o$149 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[2]; + assign \$1652 = \fus_cu_wr__rel_o$97 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[3]; + assign \$1654 = \fus_cu_wr__rel_o$97 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[3]; + assign \$1657 = wrpick_FAST_fast1_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_FAST_fast1_en_o; + assign \$1661 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1659 ; + assign \$1663 = \wr_pick$1656 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1661 ; + assign \$1668 = \wr_pick$1656 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_FAST_fast1_en_o; + assign \$1671 = \wp$1667 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_fasto1 : 3'h0; + assign \$1673 = \fus_fast1_ok$151 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$20 ; + assign \$1676 = wrpick_FAST_fast1_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_FAST_fast1_en_o; + assign \$1679 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1678 ; + assign \$1681 = \wr_pick$1675 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1679 ; + assign \$1684 = \wr_pick$1675 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_FAST_fast1_en_o; + assign \$1687 = \wp$1683 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_fasto1 : 3'h0; + assign \$1689 = \fus_fast1_ok$152 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$26 ; + assign \$1692 = wrpick_FAST_fast1_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_FAST_fast1_en_o; + assign \$1695 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1694 ; + assign \$1697 = \wr_pick$1691 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1695 ; + assign \$1700 = \wr_pick$1691 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_FAST_fast1_en_o; + assign \$1703 = \wp$1699 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_fasto1 : 3'h0; + assign \$1705 = fus_fast2_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$17 ; + assign \$1708 = wrpick_FAST_fast1_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_FAST_fast1_en_o; + assign \$1711 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1710 ; + assign \$1713 = \wr_pick$1707 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1711 ; + assign \$1716 = \wr_pick$1707 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_FAST_fast1_en_o; + assign \$1719 = \wp$1715 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_fasto2 : 3'h0; + assign \$1721 = \fus_fast2_ok$153 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$20 ; + assign \$1724 = wrpick_FAST_fast1_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_FAST_fast1_en_o; + assign \$1727 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1726 ; + assign \$1729 = \wr_pick$1723 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1727 ; + assign \$1732 = \wr_pick$1723 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_FAST_fast1_en_o; + assign \$1735 = \wp$1731 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_fasto2 : 3'h0; + assign \$1737 = fus_fast3_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$20 ; + assign \$1740 = wrpick_FAST_fast1_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_FAST_fast1_en_o; + assign \$1743 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1742 ; + assign \$1745 = \wr_pick$1739 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1743 ; + assign \$1748 = \wr_pick$1739 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_FAST_fast1_en_o; + assign \$1751 = \wp$1747 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_fasto3 : 3'h0; + assign \$1753 = \fus_dest2_o$155 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest3_o$156 ; + assign \$1755 = \fus_dest1_o$154 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1753 ; + assign \$1757 = \fus_dest3_o$158 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest4_o$159 ; + assign \$1759 = \fus_dest2_o$157 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1757 ; + assign \$1761 = \$1755 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1759 ; + assign \$1764 = \addr_en$1686 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1702 ; + assign \$1766 = \addr_en$1670 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1764 ; + assign \$1768 = \addr_en$1734 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1750 ; + assign \$1770 = \addr_en$1718 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1768 ; + assign \$1772 = \$1766 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1770 ; + assign \$1763 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1772 ; + assign \$1775 = \wp$1683 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1699 ; + assign \$1777 = \wp$1667 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1775 ; + assign \$1779 = \wp$1731 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1747 ; + assign \$1781 = \wp$1715 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1779 ; + assign \$1783 = \$1777 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1781 ; + assign \$1785 = fus_nia_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$17 ; + assign \$1787 = \fus_cu_wr__rel_o$149 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[2]; + assign \$1789 = \fus_cu_wr__rel_o$97 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[3]; + assign \$1792 = wrpick_STATE_nia_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_STATE_nia_en_o; + assign \$1795 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1794 ; + assign \$1797 = \wr_pick$1791 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1795 ; + assign \$1800 = \wr_pick$1791 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_STATE_nia_en_o; + assign \$1803 = \wp$1799 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 1'h1 : 1'h0; + assign \$1805 = \fus_nia_ok$160 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$20 ; + assign \$1808 = wrpick_STATE_nia_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_STATE_nia_en_o; + assign \$1811 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1810 ; + assign \$1813 = \wr_pick$1807 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1811 ; + assign \$1816 = \wr_pick$1807 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_STATE_nia_en_o; + assign \$1819 = \wp$1815 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 1'h1 : 1'h0; + assign \$1821 = \fus_dest3_o$161 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest5_o$162 ; + assign \$1824 = \addr_en$1802 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1818 ; + assign \$1823 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \$1824 ; + assign \$1827 = fus_msr_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$20 ; + assign \$1829 = \fus_cu_wr__rel_o$97 [5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[3]; + assign \$1832 = wrpick_STATE_msr_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_STATE_msr_en_o; + assign \$1835 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1834 ; + assign \$1837 = \wr_pick$1831 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1835 ; + assign \$1840 = \wr_pick$1831 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_STATE_msr_en_o; + assign \$1843 = \wp$1839 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 2'h2 : 2'h0; + assign \$1845 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:447" *) \addr_en$1842 ; + assign \$1847 = fus_svstate_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$20 ; + assign \$1849 = \fus_cu_wr__rel_o$97 [6] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[3]; + assign \$1852 = wrpick_STATE_svstate_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_STATE_svstate_en_o; + assign \$1855 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1854 ; + assign \$1857 = \wr_pick$1851 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1855 ; + assign \$1860 = \wr_pick$1851 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_STATE_svstate_en_o; + assign \$1863 = \wp$1859 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) 3'h4 : 3'h0; + assign \$1865 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) fus_dest7_o; + assign \$1867 = fus_spr1_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) \fus_cu_busy_o$26 ; + assign \$186 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) 2'h2; + assign \$1869 = \fus_cu_wr__rel_o$103 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[5]; + assign \$1872 = wrpick_SPR_spr1_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_SPR_spr1_en_o; + assign \$1875 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1874 ; + assign \$1877 = \wr_pick$1871 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1875 ; + assign \$185 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) \$186 ; + assign \$1880 = \wr_pick$1871 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:449" *) wrpick_SPR_spr1_en_o; + assign \$1883 = \wp$1879 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:450" *) core_spro : 10'h000; + assign \$190 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) 7'h40; + assign \$189 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) \$190 ; + assign \$194 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) 6'h20; + assign \$193 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) \$194 ; + assign \$198 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) 8'h80; + assign \$197 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) \$198 ; + assign \$202 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) 5'h10; + assign \$201 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) \$202 ; + assign \$206 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) 11'h400; + assign \$205 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) \$206 ; + assign \$210 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) 10'h200; + assign \$209 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) \$210 ; + assign \$214 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) 9'h100; + assign \$213 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) \$214 ; + assign \$218 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) 4'h8; + assign \$217 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) \$218 ; + assign \$222 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) 3'h4; + assign \$221 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211" *) \$222 ; + assign \$225 = counter != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216" *) 1'h0; + assign \$228 = counter - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" *) 1'h1; + assign \$230 = counter != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216" *) 1'h0; + assign \$233 = core_core_oe & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) core_core_oe_ok; + assign \$235 = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$237 = \$235 == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$239 = \$233 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) \$237 ; + assign \$241 = core_core_rc & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) core_core_rc_ok; + assign \$243 = \$239 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) \$241 ; + assign \$245 = core_core_input_carry == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:86" *) 2'h2; + assign \$247 = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) 3'h4; + assign \$249 = \$247 == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) 3'h4; + assign \$251 = \$245 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) \$249 ; + assign \$232 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) { \$251 , \$243 , core_reg2_ok, core_reg1_ok }; + assign \$254 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) { \core_cr_in2_ok$2 , core_cr_in2_ok, core_cr_in1_ok, core_core_cr_rd_ok, core_reg2_ok, core_reg1_ok }; + assign \$256 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) { core_cr_in1_ok, core_fast2_ok, core_fast1_ok }; + assign \$258 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) { core_fast3_ok, core_fast2_ok, core_fast1_ok, core_reg2_ok, core_reg1_ok }; + assign \$261 = core_core_oe & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) core_core_oe_ok; + assign \$263 = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$265 = \$263 == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$267 = \$261 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) \$265 ; + assign \$269 = core_core_rc & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) core_core_rc_ok; + assign \$271 = \$267 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) \$269 ; + assign \$260 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) { \$271 , core_reg2_ok, core_reg1_ok }; + assign \$275 = core_core_oe & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) core_core_oe_ok; + assign \$277 = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$279 = \$277 == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$281 = \$275 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) \$279 ; + assign \$283 = core_core_rc & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) core_core_rc_ok; + assign \$285 = \$281 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) \$283 ; + assign \$287 = core_core_oe & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:83" *) core_core_oe_ok; + assign \$289 = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) 2'h2; + assign \$291 = \$289 == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) 2'h2; + assign \$293 = \$287 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) \$291 ; + assign \$295 = core_core_input_carry == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:86" *) 2'h2; + assign \$297 = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) 3'h4; + assign \$299 = \$297 == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) 3'h4; + assign \$301 = \$295 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) \$299 ; + assign \$274 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) { \$301 , \$293 , \$285 , core_fast1_ok, core_spr1_ok, core_reg1_ok }; + assign \$305 = core_core_oe & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) core_core_oe_ok; + assign \$307 = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$309 = \$307 == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$311 = \$305 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) \$309 ; + assign \$313 = core_core_rc & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) core_core_rc_ok; + assign \$315 = \$311 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) \$313 ; + assign \$304 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) { \$315 , core_reg2_ok, core_reg1_ok }; + assign \$319 = core_core_oe & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) core_core_oe_ok; + assign \$321 = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$323 = \$321 == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$325 = \$319 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) \$323 ; + assign \$327 = core_core_rc & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) core_core_rc_ok; + assign \$329 = \$325 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) \$327 ; + assign \$318 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) { \$329 , core_reg2_ok, core_reg1_ok }; + assign \$333 = core_core_oe & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) core_core_oe_ok; + assign \$335 = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$337 = \$335 == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$339 = \$333 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) \$337 ; + assign \$341 = core_core_rc & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) core_core_rc_ok; + assign \$343 = \$339 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) \$341 ; + assign \$345 = core_core_input_carry == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:86" *) 2'h2; + assign \$347 = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) 3'h4; + assign \$349 = \$347 == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) 3'h4; + assign \$351 = \$345 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) \$349 ; + assign \$332 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) { \$351 , \$343 , core_reg3_ok, core_reg2_ok, core_reg1_ok }; + assign \$354 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" *) { core_reg3_ok, core_reg2_ok, core_reg1_ok }; + assign \$356 = fus_cu_rd__rel_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[0]; + assign \$358 = \$356 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_0; + assign \$360 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_alu0_0; + assign \$362 = \$358 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$360 ; + assign \$364 = rdpick_INT_rabc_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o; + assign \$366 = rp_INT_rabc_alu0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg2 : 7'h00; + assign \$368 = \fus_cu_rd__rel_o$40 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[1]; + assign \$370 = \$368 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_0; + assign \$372 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_cr0_1; + assign \$374 = \$370 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$372 ; + assign \$376 = rdpick_INT_rabc_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o; + assign \$378 = rp_INT_rabc_cr0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg2 : 7'h00; + assign \$380 = \fus_cu_rd__rel_o$43 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[3]; + assign \$382 = \$380 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_0; + assign \$384 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_trap0_2; + assign \$386 = \$382 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$384 ; + assign \$388 = rdpick_INT_rabc_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o; + assign \$390 = rp_INT_rabc_trap0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg2 : 7'h00; + assign \$392 = \fus_cu_rd__rel_o$46 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[4]; + assign \$394 = \$392 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_0; + assign \$396 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_logical0_3; + assign \$398 = \$394 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$396 ; + assign \$400 = rdpick_INT_rabc_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o; + assign \$402 = rp_INT_rabc_logical0_3 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg2 : 7'h00; + assign \$404 = \fus_cu_rd__rel_o$49 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[6]; + assign \$406 = \$404 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_0; + assign \$408 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_div0_4; + assign \$410 = \$406 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$408 ; + assign \$412 = rdpick_INT_rabc_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o; + assign \$414 = rp_INT_rabc_div0_4 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg2 : 7'h00; + assign \$416 = \fus_cu_rd__rel_o$52 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[7]; + assign \$418 = \$416 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_0; + assign \$420 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_mul0_5; + assign \$422 = \$418 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$420 ; + assign \$424 = rdpick_INT_rabc_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o; + assign \$426 = rp_INT_rabc_mul0_5 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg2 : 7'h00; + assign \$428 = \fus_cu_rd__rel_o$55 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[8]; + assign \$430 = \$428 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_0; + assign \$432 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_shiftrot0_6; + assign \$434 = \$430 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$432 ; + assign \$436 = rdpick_INT_rabc_o[6] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o; + assign \$438 = rp_INT_rabc_shiftrot0_6 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg2 : 7'h00; + assign \$440 = \fus_cu_rd__rel_o$58 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[9]; + assign \$442 = \$440 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_0; + assign \$444 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_ldst0_7; + assign \$446 = \$442 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$444 ; + assign \$448 = rdpick_INT_rabc_o[7] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o; + assign \$450 = rp_INT_rabc_ldst0_7 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg2 : 7'h00; + assign \$452 = \fus_cu_rd__rel_o$55 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[8]; + assign \$454 = \$452 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_1; + assign \$456 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_shiftrot0_8; + assign \$458 = \$454 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$456 ; + assign \$460 = rdpick_INT_rabc_o[8] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o; + assign \$462 = rp_INT_rabc_shiftrot0_8 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg3 : 7'h00; + assign \$464 = \fus_cu_rd__rel_o$58 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[9]; + assign \$466 = \$464 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_1; + assign \$468 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_ldst0_9; + assign \$470 = \$466 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$468 ; + assign \$472 = rdpick_INT_rabc_o[9] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o; + assign \$474 = rp_INT_rabc_ldst0_9 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg3 : 7'h00; + assign \$476 = fus_cu_rd__rel_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[0]; + assign \$478 = \$476 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_2; + assign \$480 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_alu0_10; + assign \$482 = \$478 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$480 ; + assign \$484 = rdpick_INT_rabc_o[10] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o; + assign \$486 = rp_INT_rabc_alu0_10 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg1 : 7'h00; + assign \$488 = \fus_cu_rd__rel_o$40 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[1]; + assign \$490 = \$488 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_2; + assign \$492 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_cr0_11; + assign \$494 = \$490 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$492 ; + assign \$496 = rdpick_INT_rabc_o[11] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o; + assign \$498 = rp_INT_rabc_cr0_11 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg1 : 7'h00; + assign \$500 = \fus_cu_rd__rel_o$43 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[3]; + assign \$502 = \$500 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_2; + assign \$504 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_trap0_12; + assign \$506 = \$502 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$504 ; + assign \$508 = rdpick_INT_rabc_o[12] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o; + assign \$510 = rp_INT_rabc_trap0_12 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg1 : 7'h00; + assign \$512 = \fus_cu_rd__rel_o$46 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[4]; + assign \$514 = \$512 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_2; + assign \$516 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_logical0_13; + assign \$518 = \$514 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$516 ; + assign \$520 = rdpick_INT_rabc_o[13] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o; + assign \$522 = rp_INT_rabc_logical0_13 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg1 : 7'h00; + assign \$524 = \fus_cu_rd__rel_o$65 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[5]; + assign \$526 = \$524 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_2; + assign \$528 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_spr0_14; + assign \$530 = \$526 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$528 ; + assign \$532 = rdpick_INT_rabc_o[14] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o; + assign \$534 = rp_INT_rabc_spr0_14 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg1 : 7'h00; + assign \$536 = \fus_cu_rd__rel_o$49 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[6]; + assign \$538 = \$536 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_2; + assign \$540 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_div0_15; + assign \$542 = \$538 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$540 ; + assign \$544 = rdpick_INT_rabc_o[15] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o; + assign \$546 = rp_INT_rabc_div0_15 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg1 : 7'h00; + assign \$548 = \fus_cu_rd__rel_o$52 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[7]; + assign \$550 = \$548 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_2; + assign \$552 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_mul0_16; + assign \$554 = \$550 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$552 ; + assign \$556 = rdpick_INT_rabc_o[16] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o; + assign \$558 = rp_INT_rabc_mul0_16 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg1 : 7'h00; + assign \$560 = \fus_cu_rd__rel_o$55 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[8]; + assign \$562 = \$560 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_2; + assign \$564 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_shiftrot0_17; + assign \$566 = \$562 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$564 ; + assign \$568 = rdpick_INT_rabc_o[17] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o; + assign \$570 = rp_INT_rabc_shiftrot0_17 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg1 : 7'h00; + assign \$572 = \fus_cu_rd__rel_o$58 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[9]; + assign \$574 = \$572 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_INT_rabc_2; + assign \$576 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_INT_rabc_ldst0_18; + assign \$578 = \$574 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$576 ; + assign \$580 = rdpick_INT_rabc_o[18] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_INT_rabc_en_o; + assign \$582 = rp_INT_rabc_ldst0_18 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_reg1 : 7'h00; + assign \$585 = addr_en_INT_rabc_alu0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_cr0_1; + assign \$587 = addr_en_INT_rabc_trap0_2 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_logical0_3; + assign \$589 = \$585 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$587 ; + assign \$591 = addr_en_INT_rabc_div0_4 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_mul0_5; + assign \$593 = addr_en_INT_rabc_ldst0_7 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_shiftrot0_8; + assign \$595 = addr_en_INT_rabc_shiftrot0_6 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$593 ; + assign \$597 = \$591 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$595 ; + assign \$599 = \$589 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$597 ; + assign \$601 = addr_en_INT_rabc_ldst0_9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_alu0_10; + assign \$603 = addr_en_INT_rabc_trap0_12 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_logical0_13; + assign \$605 = addr_en_INT_rabc_cr0_11 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$603 ; + assign \$607 = \$601 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$605 ; + assign \$609 = addr_en_INT_rabc_spr0_14 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_div0_15; + assign \$611 = addr_en_INT_rabc_shiftrot0_17 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_ldst0_18; + assign \$613 = addr_en_INT_rabc_mul0_16 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$611 ; + assign \$615 = \$609 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$613 ; + assign \$617 = \$607 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$615 ; + assign \$619 = \$599 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$617 ; + assign \$621 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:343" *) { rp_INT_rabc_ldst0_18, rp_INT_rabc_shiftrot0_17, rp_INT_rabc_mul0_16, rp_INT_rabc_div0_15, rp_INT_rabc_spr0_14, rp_INT_rabc_logical0_13, rp_INT_rabc_trap0_12, rp_INT_rabc_cr0_11, rp_INT_rabc_alu0_10, rp_INT_rabc_ldst0_9, rp_INT_rabc_shiftrot0_8, rp_INT_rabc_ldst0_7, rp_INT_rabc_shiftrot0_6, rp_INT_rabc_mul0_5, rp_INT_rabc_div0_4, rp_INT_rabc_logical0_3, rp_INT_rabc_trap0_2, rp_INT_rabc_cr0_1, rp_INT_rabc_alu0_0 }; + assign \$623 = core_core_oe & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) core_core_oe_ok; + assign \$625 = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$627 = \$625 == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) 1'h1; + assign \$629 = \$623 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:80" *) \$627 ; + assign \$631 = core_core_rc & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) core_core_rc_ok; + assign \$633 = \$629 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:81" *) \$631 ; + assign \$635 = fus_cu_rd__rel_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[0]; + assign \$637 = \$635 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_XER_xer_so_0; + assign \$639 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_XER_xer_so_alu0_0; + assign \$641 = \$637 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$639 ; + assign \$643 = rdpick_XER_xer_so_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_XER_xer_so_en_o; + assign \$645 = rp_XER_xer_so_alu0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) 1'h1 : 1'h0; + assign \$647 = \fus_cu_rd__rel_o$46 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[4]; + assign \$649 = \$647 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_XER_xer_so_0; + assign \$651 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_XER_xer_so_logical0_1; + assign \$653 = \$649 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$651 ; + assign \$655 = rdpick_XER_xer_so_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_XER_xer_so_en_o; + assign \$657 = rp_XER_xer_so_logical0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) 1'h1 : 1'h0; + assign \$659 = \fus_cu_rd__rel_o$65 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[5]; + assign \$661 = \$659 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_XER_xer_so_0; + assign \$663 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_XER_xer_so_spr0_2; + assign \$665 = \$661 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$663 ; + assign \$667 = rdpick_XER_xer_so_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_XER_xer_so_en_o; + assign \$669 = rp_XER_xer_so_spr0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) 1'h1 : 1'h0; + assign \$671 = \fus_cu_rd__rel_o$49 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[6]; + assign \$673 = \$671 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_XER_xer_so_0; + assign \$675 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_XER_xer_so_div0_3; + assign \$677 = \$673 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$675 ; + assign \$679 = rdpick_XER_xer_so_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_XER_xer_so_en_o; + assign \$681 = rp_XER_xer_so_div0_3 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) 1'h1 : 1'h0; + assign \$683 = \fus_cu_rd__rel_o$52 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[7]; + assign \$685 = \$683 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_XER_xer_so_0; + assign \$687 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_XER_xer_so_mul0_4; + assign \$689 = \$685 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$687 ; + assign \$691 = rdpick_XER_xer_so_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_XER_xer_so_en_o; + assign \$693 = rp_XER_xer_so_mul0_4 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) 1'h1 : 1'h0; + assign \$695 = \fus_cu_rd__rel_o$55 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[8]; + assign \$697 = \$695 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_XER_xer_so_0; + assign \$699 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_XER_xer_so_shiftrot0_5; + assign \$701 = \$697 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$699 ; + assign \$703 = rdpick_XER_xer_so_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_XER_xer_so_en_o; + assign \$705 = rp_XER_xer_so_shiftrot0_5 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) 1'h1 : 1'h0; + assign \$708 = addr_en_XER_xer_so_logical0_1 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_XER_xer_so_spr0_2; + assign \$710 = addr_en_XER_xer_so_alu0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$708 ; + assign \$712 = addr_en_XER_xer_so_mul0_4 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_XER_xer_so_shiftrot0_5; + assign \$714 = addr_en_XER_xer_so_div0_3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$712 ; + assign \$716 = \$710 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$714 ; + assign \$707 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$716 ; + assign \$719 = core_core_input_carry == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:86" *) 2'h2; + assign \$721 = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) 3'h4; + assign \$723 = \$721 == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) 3'h4; + assign \$725 = \$719 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:87" *) \$723 ; + assign \$727 = fus_cu_rd__rel_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[0]; + assign \$729 = \$727 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_XER_xer_ca_0; + assign \$731 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_XER_xer_ca_alu0_0; + assign \$733 = \$729 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$731 ; + assign \$735 = rdpick_XER_xer_ca_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_XER_xer_ca_en_o; + assign \$737 = rp_XER_xer_ca_alu0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) 2'h2 : 2'h0; + assign \$739 = \fus_cu_rd__rel_o$65 [5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[5]; + assign \$741 = \$739 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_XER_xer_ca_0; + assign \$743 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_XER_xer_ca_spr0_1; + assign \$745 = \$741 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$743 ; + assign \$747 = rdpick_XER_xer_ca_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_XER_xer_ca_en_o; + assign \$749 = rp_XER_xer_ca_spr0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) 2'h2 : 2'h0; + assign \$751 = \fus_cu_rd__rel_o$55 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[8]; + assign \$753 = \$751 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_XER_xer_ca_0; + assign \$755 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_XER_xer_ca_shiftrot0_2; + assign \$757 = \$753 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$755 ; + assign \$759 = rdpick_XER_xer_ca_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_XER_xer_ca_en_o; + assign \$761 = rp_XER_xer_ca_shiftrot0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) 2'h2 : 2'h0; + assign \$764 = addr_en_XER_xer_ca_spr0_1 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_XER_xer_ca_shiftrot0_2; + assign \$766 = addr_en_XER_xer_ca_alu0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$764 ; + assign \$763 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$766 ; + assign \$769 = core_core_oe & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:83" *) core_core_oe_ok; + assign \$771 = core_xer_in & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) 2'h2; + assign \$773 = \$771 == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) 2'h2; + assign \$775 = \$769 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:84" *) \$773 ; + assign \$777 = \fus_cu_rd__rel_o$65 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[5]; + assign \$779 = \$777 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_XER_xer_ov_0; + assign \$781 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_XER_xer_ov_spr0_0; + assign \$783 = \$779 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$781 ; + assign \$785 = rdpick_XER_xer_ov_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_XER_xer_ov_en_o; + assign \$787 = rp_XER_xer_ov_spr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) 3'h4 : 3'h0; + assign \$789 = \fus_cu_rd__rel_o$40 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[1]; + assign \$791 = \$789 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_CR_full_cr_0; + assign \$793 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_CR_full_cr_cr0_0; + assign \$795 = \$791 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$793 ; + assign \$797 = rdpick_CR_full_cr_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_CR_full_cr_en_o; + assign \$799 = rp_CR_full_cr_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_core_cr_rd : 8'h00; + assign \$801 = \fus_cu_rd__rel_o$40 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[1]; + assign \$803 = \$801 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_CR_cr_a_0; + assign \$805 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_CR_cr_a_cr0_0; + assign \$807 = \$803 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$805 ; + assign \$809 = rdpick_CR_cr_a_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_CR_cr_a_en_o; + assign \$811 = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:64" *) core_cr_in1; + assign \$813 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:64" *) \$811 ; + assign \$815 = rp_CR_cr_a_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) \$813 : 256'h0000000000000000000000000000000000000000000000000000000000000000; + assign \$817 = \fus_cu_rd__rel_o$81 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[2]; + assign \$819 = \$817 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_CR_cr_a_0; + assign \$821 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_CR_cr_a_branch0_1; + assign \$823 = \$819 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$821 ; + assign \$825 = rdpick_CR_cr_a_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_CR_cr_a_en_o; + assign \$827 = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:64" *) core_cr_in1; + assign \$829 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:64" *) \$827 ; + assign \$831 = rp_CR_cr_a_branch0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) \$829 : 256'h0000000000000000000000000000000000000000000000000000000000000000; + assign \$834 = addr_en_CR_cr_a_cr0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_CR_cr_a_branch0_1; + assign \$836 = \fus_cu_rd__rel_o$40 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[1]; + assign \$838 = \$836 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_CR_cr_b_0; + assign \$840 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_CR_cr_b_cr0_0; + assign \$842 = \$838 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$840 ; + assign \$844 = rdpick_CR_cr_b_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_CR_cr_b_en_o; + assign \$846 = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:66" *) core_cr_in2; + assign \$848 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:66" *) \$846 ; + assign \$850 = rp_CR_cr_b_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) \$848 : 256'h0000000000000000000000000000000000000000000000000000000000000000; + assign \$852 = \fus_cu_rd__rel_o$40 [5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[1]; + assign \$854 = \$852 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_CR_cr_c_0; + assign \$856 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_CR_cr_c_cr0_0; + assign \$858 = \$854 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$856 ; + assign \$860 = rdpick_CR_cr_c_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_CR_cr_c_en_o; + assign \$862 = 3'h7 - (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:68" *) \core_cr_in2$1 ; + assign \$864 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_regspec_map.py:68" *) \$862 ; + assign \$866 = rp_CR_cr_c_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) \$864 : 256'h0000000000000000000000000000000000000000000000000000000000000000; + assign \$868 = \fus_cu_rd__rel_o$81 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[2]; + assign \$870 = \$868 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_FAST_fast1_0; + assign \$872 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_FAST_fast1_branch0_0; + assign \$874 = \$870 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$872 ; + assign \$876 = rdpick_FAST_fast1_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_FAST_fast1_en_o; + assign \$878 = rp_FAST_fast1_branch0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_fast1 : 3'h0; + assign \$880 = \fus_cu_rd__rel_o$43 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[3]; + assign \$882 = \$880 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_FAST_fast1_0; + assign \$884 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_FAST_fast1_trap0_1; + assign \$886 = \$882 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$884 ; + assign \$888 = rdpick_FAST_fast1_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_FAST_fast1_en_o; + assign \$890 = rp_FAST_fast1_trap0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_fast1 : 3'h0; + assign \$892 = \fus_cu_rd__rel_o$65 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[5]; + assign \$894 = \$892 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_FAST_fast1_0; + assign \$896 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_FAST_fast1_spr0_2; + assign \$898 = \$894 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$896 ; + assign \$900 = rdpick_FAST_fast1_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_FAST_fast1_en_o; + assign \$902 = rp_FAST_fast1_spr0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_fast1 : 3'h0; + assign \$904 = \fus_cu_rd__rel_o$81 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[2]; + assign \$906 = \$904 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_FAST_fast1_1; + assign \$908 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_FAST_fast1_branch0_3; + assign \$910 = \$906 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$908 ; + assign \$912 = rdpick_FAST_fast1_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_FAST_fast1_en_o; + assign \$914 = rp_FAST_fast1_branch0_3 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_fast2 : 3'h0; + assign \$916 = \fus_cu_rd__rel_o$43 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[3]; + assign \$918 = \$916 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_FAST_fast1_1; + assign \$920 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_FAST_fast1_trap0_4; + assign \$922 = \$918 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$920 ; + assign \$924 = rdpick_FAST_fast1_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_FAST_fast1_en_o; + assign \$926 = rp_FAST_fast1_trap0_4 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_fast2 : 3'h0; + assign \$928 = \fus_cu_rd__rel_o$43 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[3]; + assign \$930 = \$928 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_FAST_fast1_2; + assign \$932 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_FAST_fast1_trap0_5; + assign \$934 = \$930 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$932 ; + assign \$936 = rdpick_FAST_fast1_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_FAST_fast1_en_o; + assign \$938 = rp_FAST_fast1_trap0_5 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_fast3 : 3'h0; + assign \$941 = addr_en_FAST_fast1_trap0_1 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_FAST_fast1_spr0_2; + assign \$943 = addr_en_FAST_fast1_branch0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$941 ; + assign \$945 = addr_en_FAST_fast1_trap0_4 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_FAST_fast1_trap0_5; + assign \$947 = addr_en_FAST_fast1_branch0_3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$945 ; + assign \$949 = \$943 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$947 ; + assign \$940 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$949 ; + assign \$952 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:343" *) { rp_FAST_fast1_trap0_5, rp_FAST_fast1_trap0_4, rp_FAST_fast1_branch0_3, rp_FAST_fast1_spr0_2, rp_FAST_fast1_trap0_1, rp_FAST_fast1_branch0_0 }; + assign \$954 = \fus_cu_rd__rel_o$65 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) fu_enable[5]; + assign \$956 = \$954 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:308" *) rdflag_SPR_spr1_0; + assign \$958 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) dp_SPR_spr1_spr0_0; + assign \$960 = \$956 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) \$958 ; + assign \$962 = rdpick_SPR_spr1_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:314" *) rdpick_SPR_spr1_en_o; + assign \$964 = rp_SPR_spr1_spr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" *) core_spr1 : 10'h000; + assign \$966 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:343" *) rp_SPR_spr1_spr0_0; + assign \$968 = fus_o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:433" *) fus_cu_busy_o; + assign \$970 = fus_cu_wr__rel_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[0]; + assign \$972 = \fus_cu_wr__rel_o$94 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[1]; + assign \$974 = \fus_cu_wr__rel_o$97 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[3]; + assign \$976 = \fus_cu_wr__rel_o$100 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[4]; + assign \$978 = \fus_cu_wr__rel_o$103 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[5]; + assign \$980 = \fus_cu_wr__rel_o$106 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[6]; + assign \$982 = \fus_cu_wr__rel_o$109 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[7]; + assign \$984 = \fus_cu_wr__rel_o$112 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[8]; + assign \$986 = \fus_cu_wr__rel_o$114 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[9]; + assign \$988 = \fus_cu_wr__rel_o$114 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:437" *) fu_enable[9]; + assign \$990 = wrpick_INT_o_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:441" *) wrpick_INT_o_en_o; + assign \$992 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wr_pick_dly; + assign \$994 = wr_pick & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$992 ; + always @(posedge coresync_clk) + \wr_pick_dly$1874 <= \wr_pick_dly$1874$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1854 <= \wr_pick_dly$1854$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1834 <= \wr_pick_dly$1834$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1810 <= \wr_pick_dly$1810$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1794 <= \wr_pick_dly$1794$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1742 <= \wr_pick_dly$1742$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1726 <= \wr_pick_dly$1726$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1710 <= \wr_pick_dly$1710$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1694 <= \wr_pick_dly$1694$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1678 <= \wr_pick_dly$1678$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1659 <= \wr_pick_dly$1659$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1615 <= \wr_pick_dly$1615$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1599 <= \wr_pick_dly$1599$next ; always @(posedge coresync_clk) - \wr_pick_dly$1461 <= \wr_pick_dly$1461$next ; + \wr_pick_dly$1583 <= \wr_pick_dly$1583$next ; always @(posedge coresync_clk) - \wr_pick_dly$1427 <= \wr_pick_dly$1427$next ; + \wr_pick_dly$1567 <= \wr_pick_dly$1567$next ; always @(posedge coresync_clk) - \wr_pick_dly$1411 <= \wr_pick_dly$1411$next ; + \wr_pick_dly$1531 <= \wr_pick_dly$1531$next ; always @(posedge coresync_clk) - \wr_pick_dly$1395 <= \wr_pick_dly$1395$next ; + \wr_pick_dly$1515 <= \wr_pick_dly$1515$next ; always @(posedge coresync_clk) - \wr_pick_dly$1348 <= \wr_pick_dly$1348$next ; + \wr_pick_dly$1499 <= \wr_pick_dly$1499$next ; always @(posedge coresync_clk) - \wr_pick_dly$1328 <= \wr_pick_dly$1328$next ; + \wr_pick_dly$1483 <= \wr_pick_dly$1483$next ; always @(posedge coresync_clk) - \wr_pick_dly$1308 <= \wr_pick_dly$1308$next ; + \wr_pick_dly$1449 <= \wr_pick_dly$1449$next ; always @(posedge coresync_clk) - \wr_pick_dly$1288 <= \wr_pick_dly$1288$next ; + \wr_pick_dly$1433 <= \wr_pick_dly$1433$next ; always @(posedge coresync_clk) - \wr_pick_dly$1268 <= \wr_pick_dly$1268$next ; + \wr_pick_dly$1417 <= \wr_pick_dly$1417$next ; always @(posedge coresync_clk) - \wr_pick_dly$1248 <= \wr_pick_dly$1248$next ; + \wr_pick_dly$1370 <= \wr_pick_dly$1370$next ; always @(posedge coresync_clk) - \wr_pick_dly$1220 <= \wr_pick_dly$1220$next ; + \wr_pick_dly$1350 <= \wr_pick_dly$1350$next ; always @(posedge coresync_clk) - \wr_pick_dly$1146 <= \wr_pick_dly$1146$next ; + \wr_pick_dly$1330 <= \wr_pick_dly$1330$next ; always @(posedge coresync_clk) - \wr_pick_dly$1128 <= \wr_pick_dly$1128$next ; + \wr_pick_dly$1310 <= \wr_pick_dly$1310$next ; always @(posedge coresync_clk) - \wr_pick_dly$1109 <= \wr_pick_dly$1109$next ; + \wr_pick_dly$1290 <= \wr_pick_dly$1290$next ; always @(posedge coresync_clk) - \wr_pick_dly$1089 <= \wr_pick_dly$1089$next ; + \wr_pick_dly$1270 <= \wr_pick_dly$1270$next ; always @(posedge coresync_clk) - \wr_pick_dly$1069 <= \wr_pick_dly$1069$next ; + \wr_pick_dly$1242 <= \wr_pick_dly$1242$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1168 <= \wr_pick_dly$1168$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1150 <= \wr_pick_dly$1150$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1131 <= \wr_pick_dly$1131$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1111 <= \wr_pick_dly$1111$next ; always @(posedge coresync_clk) - \wr_pick_dly$1047 <= \wr_pick_dly$1047$next ; + \wr_pick_dly$1091 <= \wr_pick_dly$1091$next ; always @(posedge coresync_clk) - \wr_pick_dly$1029 <= \wr_pick_dly$1029$next ; + \wr_pick_dly$1069 <= \wr_pick_dly$1069$next ; + always @(posedge coresync_clk) + \wr_pick_dly$1051 <= \wr_pick_dly$1051$next ; always @(posedge coresync_clk) - \wr_pick_dly$1008 <= \wr_pick_dly$1008$next ; + \wr_pick_dly$1028 <= \wr_pick_dly$1028$next ; always @(posedge coresync_clk) - \wr_pick_dly$989 <= \wr_pick_dly$989$next ; + \wr_pick_dly$1009 <= \wr_pick_dly$1009$next ; always @(posedge coresync_clk) wr_pick_dly <= \wr_pick_dly$next ; always @(posedge coresync_clk) dp_SPR_spr1_spr0_0 <= \dp_SPR_spr1_spr0_0$next ; + always @(posedge coresync_clk) + dp_FAST_fast1_trap0_5 <= \dp_FAST_fast1_trap0_5$next ; always @(posedge coresync_clk) dp_FAST_fast1_trap0_4 <= \dp_FAST_fast1_trap0_4$next ; always @(posedge coresync_clk) @@ -42496,6 +46457,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c .LDST__is_32bit(dec_LDST_LDST__is_32bit), .LDST__is_signed(dec_LDST_LDST__is_signed), .LDST__ldst_mode(dec_LDST_LDST__ldst_mode), + .LDST__msr(dec_LDST_LDST__msr), .LDST__oe__oe(dec_LDST_LDST__oe__oe), .LDST__oe__ok(dec_LDST_LDST__oe__ok), .LDST__rc__ok(dec_LDST_LDST__rc__ok), @@ -42503,6 +46465,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c .LDST__sign_extend(dec_LDST_LDST__sign_extend), .LDST__zero_a(dec_LDST_LDST__zero_a), .bigendian(dec_LDST_bigendian), + .core_msr(core_msr), .raw_opcode_in(dec_LDST_raw_opcode_in), .sv_a_nz(dec_LDST_sv_a_nz) ); @@ -42594,11 +46557,11 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c .coresync_clk(coresync_clk), .coresync_rst(coresync_rst), .cr_a_ok(fus_cr_a_ok), - .\cr_a_ok$110 (\fus_cr_a_ok$122 ), .\cr_a_ok$111 (\fus_cr_a_ok$123 ), .\cr_a_ok$112 (\fus_cr_a_ok$124 ), .\cr_a_ok$113 (\fus_cr_a_ok$125 ), .\cr_a_ok$114 (\fus_cr_a_ok$126 ), + .\cr_a_ok$115 (\fus_cr_a_ok$127 ), .cu_ad__go_i(cu_ad__go_i), .cu_ad__rel_o(cu_ad__rel_o), .cu_busy_o(fus_cu_busy_o), @@ -42654,66 +46617,70 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c .cu_st__go_i(cu_st__go_i), .cu_st__rel_o(cu_st__rel_o), .cu_wr__go_i(fus_cu_wr__go_i), - .\cu_wr__go_i$100 (\fus_cu_wr__go_i$112 ), - .\cu_wr__go_i$102 (\fus_cu_wr__go_i$114 ), - .\cu_wr__go_i$137 (\fus_cu_wr__go_i$149 ), - .\cu_wr__go_i$82 (\fus_cu_wr__go_i$94 ), - .\cu_wr__go_i$85 (\fus_cu_wr__go_i$97 ), - .\cu_wr__go_i$88 (\fus_cu_wr__go_i$100 ), - .\cu_wr__go_i$91 (\fus_cu_wr__go_i$103 ), - .\cu_wr__go_i$94 (\fus_cu_wr__go_i$106 ), - .\cu_wr__go_i$97 (\fus_cu_wr__go_i$109 ), + .\cu_wr__go_i$101 (\fus_cu_wr__go_i$113 ), + .\cu_wr__go_i$103 (\fus_cu_wr__go_i$115 ), + .\cu_wr__go_i$138 (\fus_cu_wr__go_i$150 ), + .\cu_wr__go_i$83 (\fus_cu_wr__go_i$95 ), + .\cu_wr__go_i$86 (\fus_cu_wr__go_i$98 ), + .\cu_wr__go_i$89 (\fus_cu_wr__go_i$101 ), + .\cu_wr__go_i$92 (\fus_cu_wr__go_i$104 ), + .\cu_wr__go_i$95 (\fus_cu_wr__go_i$107 ), + .\cu_wr__go_i$98 (\fus_cu_wr__go_i$110 ), .cu_wr__rel_o(fus_cu_wr__rel_o), - .\cu_wr__rel_o$101 (\fus_cu_wr__rel_o$113 ), - .\cu_wr__rel_o$136 (\fus_cu_wr__rel_o$148 ), - .\cu_wr__rel_o$81 (\fus_cu_wr__rel_o$93 ), - .\cu_wr__rel_o$84 (\fus_cu_wr__rel_o$96 ), - .\cu_wr__rel_o$87 (\fus_cu_wr__rel_o$99 ), - .\cu_wr__rel_o$90 (\fus_cu_wr__rel_o$102 ), - .\cu_wr__rel_o$93 (\fus_cu_wr__rel_o$105 ), - .\cu_wr__rel_o$96 (\fus_cu_wr__rel_o$108 ), - .\cu_wr__rel_o$99 (\fus_cu_wr__rel_o$111 ), + .\cu_wr__rel_o$100 (\fus_cu_wr__rel_o$112 ), + .\cu_wr__rel_o$102 (\fus_cu_wr__rel_o$114 ), + .\cu_wr__rel_o$137 (\fus_cu_wr__rel_o$149 ), + .\cu_wr__rel_o$82 (\fus_cu_wr__rel_o$94 ), + .\cu_wr__rel_o$85 (\fus_cu_wr__rel_o$97 ), + .\cu_wr__rel_o$88 (\fus_cu_wr__rel_o$100 ), + .\cu_wr__rel_o$91 (\fus_cu_wr__rel_o$103 ), + .\cu_wr__rel_o$94 (\fus_cu_wr__rel_o$106 ), + .\cu_wr__rel_o$97 (\fus_cu_wr__rel_o$109 ), .dest1_o(fus_dest1_o), - .\dest1_o$103 (\fus_dest1_o$115 ), .\dest1_o$104 (\fus_dest1_o$116 ), .\dest1_o$105 (\fus_dest1_o$117 ), .\dest1_o$106 (\fus_dest1_o$118 ), .\dest1_o$107 (\fus_dest1_o$119 ), .\dest1_o$108 (\fus_dest1_o$120 ), .\dest1_o$109 (\fus_dest1_o$121 ), - .\dest1_o$141 (\fus_dest1_o$153 ), + .\dest1_o$110 (\fus_dest1_o$122 ), + .\dest1_o$142 (\fus_dest1_o$154 ), .dest2_o(fus_dest2_o), - .\dest2_o$115 (\fus_dest2_o$127 ), .\dest2_o$116 (\fus_dest2_o$128 ), .\dest2_o$117 (\fus_dest2_o$129 ), .\dest2_o$118 (\fus_dest2_o$130 ), .\dest2_o$119 (\fus_dest2_o$131 ), - .\dest2_o$142 (\fus_dest2_o$154 ), - .\dest2_o$144 (\fus_dest2_o$156 ), - .\dest2_o$150 (\fus_dest2_o$162 ), + .\dest2_o$120 (\fus_dest2_o$132 ), + .\dest2_o$143 (\fus_dest2_o$155 ), + .\dest2_o$145 (\fus_dest2_o$157 ), + .\dest2_o$152 (\fus_dest2_o$164 ), .dest3_o(fus_dest3_o), - .\dest3_o$122 (\fus_dest3_o$134 ), .\dest3_o$123 (\fus_dest3_o$135 ), - .\dest3_o$127 (\fus_dest3_o$139 ), + .\dest3_o$124 (\fus_dest3_o$136 ), .\dest3_o$128 (\fus_dest3_o$140 ), - .\dest3_o$143 (\fus_dest3_o$155 ), - .\dest3_o$145 (\fus_dest3_o$157 ), - .\dest3_o$147 (\fus_dest3_o$159 ), + .\dest3_o$129 (\fus_dest3_o$141 ), + .\dest3_o$144 (\fus_dest3_o$156 ), + .\dest3_o$146 (\fus_dest3_o$158 ), + .\dest3_o$149 (\fus_dest3_o$161 ), .dest4_o(fus_dest4_o), - .\dest4_o$133 (\fus_dest4_o$145 ), .\dest4_o$134 (\fus_dest4_o$146 ), .\dest4_o$135 (\fus_dest4_o$147 ), - .\dest4_o$148 (\fus_dest4_o$160 ), + .\dest4_o$136 (\fus_dest4_o$148 ), + .\dest4_o$147 (\fus_dest4_o$159 ), .dest5_o(fus_dest5_o), - .\dest5_o$132 (\fus_dest5_o$144 ), - .\dest5_o$149 (\fus_dest5_o$161 ), + .\dest5_o$133 (\fus_dest5_o$145 ), + .\dest5_o$150 (\fus_dest5_o$162 ), .dest6_o(fus_dest6_o), + .\dest6_o$151 (\fus_dest6_o$163 ), + .dest7_o(fus_dest7_o), .ea(fus_ea), + .\exc_o_$signal (\exc_o_$signal ), .fast1_ok(fus_fast1_ok), - .\fast1_ok$138 (\fus_fast1_ok$150 ), .\fast1_ok$139 (\fus_fast1_ok$151 ), + .\fast1_ok$140 (\fus_fast1_ok$152 ), .fast2_ok(fus_fast2_ok), - .\fast2_ok$140 (\fus_fast2_ok$152 ), + .\fast2_ok$141 (\fus_fast2_ok$153 ), + .fast3_ok(fus_fast3_ok), .full_cr_ok(fus_full_cr_ok), .ldst_port0_addr_i(fus_ldst_port0_addr_i), .ldst_port0_addr_i_ok(fus_ldst_port0_addr_i_ok), @@ -42721,31 +46688,33 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c .ldst_port0_busy_o(fus_ldst_port0_busy_o), .ldst_port0_data_len(fus_ldst_port0_data_len), .\ldst_port0_exc_$signal (\fus_ldst_port0_exc_$signal ), - .\ldst_port0_exc_$signal$151 (\fus_ldst_port0_exc_$signal$163 ), - .\ldst_port0_exc_$signal$152 (\fus_ldst_port0_exc_$signal$164 ), .\ldst_port0_exc_$signal$153 (\fus_ldst_port0_exc_$signal$165 ), .\ldst_port0_exc_$signal$154 (\fus_ldst_port0_exc_$signal$166 ), .\ldst_port0_exc_$signal$155 (\fus_ldst_port0_exc_$signal$167 ), .\ldst_port0_exc_$signal$156 (\fus_ldst_port0_exc_$signal$168 ), .\ldst_port0_exc_$signal$157 (\fus_ldst_port0_exc_$signal$169 ), + .\ldst_port0_exc_$signal$158 (\fus_ldst_port0_exc_$signal$170 ), + .\ldst_port0_exc_$signal$159 (\fus_ldst_port0_exc_$signal$171 ), .ldst_port0_is_ld_i(fus_ldst_port0_is_ld_i), .ldst_port0_is_st_i(fus_ldst_port0_is_st_i), .ldst_port0_ld_data_o(fus_ldst_port0_ld_data_o), .ldst_port0_ld_data_o_ok(fus_ldst_port0_ld_data_o_ok), + .ldst_port0_msr_pr(fus_ldst_port0_msr_pr), .ldst_port0_st_data_i(fus_ldst_port0_st_data_i), .ldst_port0_st_data_i_ok(fus_ldst_port0_st_data_i_ok), .msr_ok(fus_msr_ok), .nia_ok(fus_nia_ok), - .\nia_ok$146 (\fus_nia_ok$158 ), + .\nia_ok$148 (\fus_nia_ok$160 ), .o(fus_o), .o_ok(fus_o_ok), - .\o_ok$80 (\fus_o_ok$92 ), - .\o_ok$83 (\fus_o_ok$95 ), - .\o_ok$86 (\fus_o_ok$98 ), - .\o_ok$89 (\fus_o_ok$101 ), - .\o_ok$92 (\fus_o_ok$104 ), - .\o_ok$95 (\fus_o_ok$107 ), - .\o_ok$98 (\fus_o_ok$110 ), + .\o_ok$81 (\fus_o_ok$93 ), + .\o_ok$84 (\fus_o_ok$96 ), + .\o_ok$87 (\fus_o_ok$99 ), + .\o_ok$90 (\fus_o_ok$102 ), + .\o_ok$93 (\fus_o_ok$105 ), + .\o_ok$96 (\fus_o_ok$108 ), + .\o_ok$99 (\fus_o_ok$111 ), + .oper_i_alu_alu0__SV_Ptype(fus_oper_i_alu_alu0__SV_Ptype), .oper_i_alu_alu0__data_len(fus_oper_i_alu_alu0__data_len), .oper_i_alu_alu0__fn_unit(fus_oper_i_alu_alu0__fn_unit), .oper_i_alu_alu0__imm_data__data(fus_oper_i_alu_alu0__imm_data__data), @@ -42762,8 +46731,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c .oper_i_alu_alu0__output_carry(fus_oper_i_alu_alu0__output_carry), .oper_i_alu_alu0__rc__ok(fus_oper_i_alu_alu0__rc__ok), .oper_i_alu_alu0__rc__rc(fus_oper_i_alu_alu0__rc__rc), + .oper_i_alu_alu0__sv_pred_dz(fus_oper_i_alu_alu0__sv_pred_dz), + .oper_i_alu_alu0__sv_pred_sz(fus_oper_i_alu_alu0__sv_pred_sz), + .oper_i_alu_alu0__sv_saturate(fus_oper_i_alu_alu0__sv_saturate), .oper_i_alu_alu0__write_cr0(fus_oper_i_alu_alu0__write_cr0), .oper_i_alu_alu0__zero_a(fus_oper_i_alu_alu0__zero_a), + .oper_i_alu_branch0__SV_Ptype(fus_oper_i_alu_branch0__SV_Ptype), .oper_i_alu_branch0__cia(fus_oper_i_alu_branch0__cia), .oper_i_alu_branch0__fn_unit(fus_oper_i_alu_branch0__fn_unit), .oper_i_alu_branch0__imm_data__data(fus_oper_i_alu_branch0__imm_data__data), @@ -42772,9 +46745,17 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c .oper_i_alu_branch0__insn_type(fus_oper_i_alu_branch0__insn_type), .oper_i_alu_branch0__is_32bit(fus_oper_i_alu_branch0__is_32bit), .oper_i_alu_branch0__lk(fus_oper_i_alu_branch0__lk), + .oper_i_alu_branch0__sv_pred_dz(fus_oper_i_alu_branch0__sv_pred_dz), + .oper_i_alu_branch0__sv_pred_sz(fus_oper_i_alu_branch0__sv_pred_sz), + .oper_i_alu_branch0__sv_saturate(fus_oper_i_alu_branch0__sv_saturate), + .oper_i_alu_cr0__SV_Ptype(fus_oper_i_alu_cr0__SV_Ptype), .oper_i_alu_cr0__fn_unit(fus_oper_i_alu_cr0__fn_unit), .oper_i_alu_cr0__insn(fus_oper_i_alu_cr0__insn), .oper_i_alu_cr0__insn_type(fus_oper_i_alu_cr0__insn_type), + .oper_i_alu_cr0__sv_pred_dz(fus_oper_i_alu_cr0__sv_pred_dz), + .oper_i_alu_cr0__sv_pred_sz(fus_oper_i_alu_cr0__sv_pred_sz), + .oper_i_alu_cr0__sv_saturate(fus_oper_i_alu_cr0__sv_saturate), + .oper_i_alu_div0__SV_Ptype(fus_oper_i_alu_div0__SV_Ptype), .oper_i_alu_div0__data_len(fus_oper_i_alu_div0__data_len), .oper_i_alu_div0__fn_unit(fus_oper_i_alu_div0__fn_unit), .oper_i_alu_div0__imm_data__data(fus_oper_i_alu_div0__imm_data__data), @@ -42791,8 +46772,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c .oper_i_alu_div0__output_carry(fus_oper_i_alu_div0__output_carry), .oper_i_alu_div0__rc__ok(fus_oper_i_alu_div0__rc__ok), .oper_i_alu_div0__rc__rc(fus_oper_i_alu_div0__rc__rc), + .oper_i_alu_div0__sv_pred_dz(fus_oper_i_alu_div0__sv_pred_dz), + .oper_i_alu_div0__sv_pred_sz(fus_oper_i_alu_div0__sv_pred_sz), + .oper_i_alu_div0__sv_saturate(fus_oper_i_alu_div0__sv_saturate), .oper_i_alu_div0__write_cr0(fus_oper_i_alu_div0__write_cr0), .oper_i_alu_div0__zero_a(fus_oper_i_alu_div0__zero_a), + .oper_i_alu_logical0__SV_Ptype(fus_oper_i_alu_logical0__SV_Ptype), .oper_i_alu_logical0__data_len(fus_oper_i_alu_logical0__data_len), .oper_i_alu_logical0__fn_unit(fus_oper_i_alu_logical0__fn_unit), .oper_i_alu_logical0__imm_data__data(fus_oper_i_alu_logical0__imm_data__data), @@ -42809,8 +46794,12 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c .oper_i_alu_logical0__output_carry(fus_oper_i_alu_logical0__output_carry), .oper_i_alu_logical0__rc__ok(fus_oper_i_alu_logical0__rc__ok), .oper_i_alu_logical0__rc__rc(fus_oper_i_alu_logical0__rc__rc), + .oper_i_alu_logical0__sv_pred_dz(fus_oper_i_alu_logical0__sv_pred_dz), + .oper_i_alu_logical0__sv_pred_sz(fus_oper_i_alu_logical0__sv_pred_sz), + .oper_i_alu_logical0__sv_saturate(fus_oper_i_alu_logical0__sv_saturate), .oper_i_alu_logical0__write_cr0(fus_oper_i_alu_logical0__write_cr0), .oper_i_alu_logical0__zero_a(fus_oper_i_alu_logical0__zero_a), + .oper_i_alu_mul0__SV_Ptype(fus_oper_i_alu_mul0__SV_Ptype), .oper_i_alu_mul0__fn_unit(fus_oper_i_alu_mul0__fn_unit), .oper_i_alu_mul0__imm_data__data(fus_oper_i_alu_mul0__imm_data__data), .oper_i_alu_mul0__imm_data__ok(fus_oper_i_alu_mul0__imm_data__ok), @@ -42822,7 +46811,11 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c .oper_i_alu_mul0__oe__ok(fus_oper_i_alu_mul0__oe__ok), .oper_i_alu_mul0__rc__ok(fus_oper_i_alu_mul0__rc__ok), .oper_i_alu_mul0__rc__rc(fus_oper_i_alu_mul0__rc__rc), + .oper_i_alu_mul0__sv_pred_dz(fus_oper_i_alu_mul0__sv_pred_dz), + .oper_i_alu_mul0__sv_pred_sz(fus_oper_i_alu_mul0__sv_pred_sz), + .oper_i_alu_mul0__sv_saturate(fus_oper_i_alu_mul0__sv_saturate), .oper_i_alu_mul0__write_cr0(fus_oper_i_alu_mul0__write_cr0), + .oper_i_alu_shift_rot0__SV_Ptype(fus_oper_i_alu_shift_rot0__SV_Ptype), .oper_i_alu_shift_rot0__fn_unit(fus_oper_i_alu_shift_rot0__fn_unit), .oper_i_alu_shift_rot0__imm_data__data(fus_oper_i_alu_shift_rot0__imm_data__data), .oper_i_alu_shift_rot0__imm_data__ok(fus_oper_i_alu_shift_rot0__imm_data__ok), @@ -42839,11 +46832,19 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c .oper_i_alu_shift_rot0__output_cr(fus_oper_i_alu_shift_rot0__output_cr), .oper_i_alu_shift_rot0__rc__ok(fus_oper_i_alu_shift_rot0__rc__ok), .oper_i_alu_shift_rot0__rc__rc(fus_oper_i_alu_shift_rot0__rc__rc), + .oper_i_alu_shift_rot0__sv_pred_dz(fus_oper_i_alu_shift_rot0__sv_pred_dz), + .oper_i_alu_shift_rot0__sv_pred_sz(fus_oper_i_alu_shift_rot0__sv_pred_sz), + .oper_i_alu_shift_rot0__sv_saturate(fus_oper_i_alu_shift_rot0__sv_saturate), .oper_i_alu_shift_rot0__write_cr0(fus_oper_i_alu_shift_rot0__write_cr0), + .oper_i_alu_spr0__SV_Ptype(fus_oper_i_alu_spr0__SV_Ptype), .oper_i_alu_spr0__fn_unit(fus_oper_i_alu_spr0__fn_unit), .oper_i_alu_spr0__insn(fus_oper_i_alu_spr0__insn), .oper_i_alu_spr0__insn_type(fus_oper_i_alu_spr0__insn_type), .oper_i_alu_spr0__is_32bit(fus_oper_i_alu_spr0__is_32bit), + .oper_i_alu_spr0__sv_pred_dz(fus_oper_i_alu_spr0__sv_pred_dz), + .oper_i_alu_spr0__sv_pred_sz(fus_oper_i_alu_spr0__sv_pred_sz), + .oper_i_alu_spr0__sv_saturate(fus_oper_i_alu_spr0__sv_saturate), + .oper_i_alu_trap0__SV_Ptype(fus_oper_i_alu_trap0__SV_Ptype), .oper_i_alu_trap0__cia(fus_oper_i_alu_trap0__cia), .oper_i_alu_trap0__fn_unit(fus_oper_i_alu_trap0__fn_unit), .oper_i_alu_trap0__insn(fus_oper_i_alu_trap0__insn), @@ -42851,8 +46852,13 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c .oper_i_alu_trap0__is_32bit(fus_oper_i_alu_trap0__is_32bit), .oper_i_alu_trap0__ldst_exc(fus_oper_i_alu_trap0__ldst_exc), .oper_i_alu_trap0__msr(fus_oper_i_alu_trap0__msr), + .oper_i_alu_trap0__sv_pred_dz(fus_oper_i_alu_trap0__sv_pred_dz), + .oper_i_alu_trap0__sv_pred_sz(fus_oper_i_alu_trap0__sv_pred_sz), + .oper_i_alu_trap0__sv_saturate(fus_oper_i_alu_trap0__sv_saturate), + .oper_i_alu_trap0__svstate(fus_oper_i_alu_trap0__svstate), .oper_i_alu_trap0__trapaddr(fus_oper_i_alu_trap0__trapaddr), .oper_i_alu_trap0__traptype(fus_oper_i_alu_trap0__traptype), + .oper_i_ldst_ldst0__SV_Ptype(fus_oper_i_ldst_ldst0__SV_Ptype), .oper_i_ldst_ldst0__byte_reverse(fus_oper_i_ldst_ldst0__byte_reverse), .oper_i_ldst_ldst0__data_len(fus_oper_i_ldst_ldst0__data_len), .oper_i_ldst_ldst0__fn_unit(fus_oper_i_ldst_ldst0__fn_unit), @@ -42863,11 +46869,15 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c .oper_i_ldst_ldst0__is_32bit(fus_oper_i_ldst_ldst0__is_32bit), .oper_i_ldst_ldst0__is_signed(fus_oper_i_ldst_ldst0__is_signed), .oper_i_ldst_ldst0__ldst_mode(fus_oper_i_ldst_ldst0__ldst_mode), + .oper_i_ldst_ldst0__msr(fus_oper_i_ldst_ldst0__msr), .oper_i_ldst_ldst0__oe__oe(fus_oper_i_ldst_ldst0__oe__oe), .oper_i_ldst_ldst0__oe__ok(fus_oper_i_ldst_ldst0__oe__ok), .oper_i_ldst_ldst0__rc__ok(fus_oper_i_ldst_ldst0__rc__ok), .oper_i_ldst_ldst0__rc__rc(fus_oper_i_ldst_ldst0__rc__rc), .oper_i_ldst_ldst0__sign_extend(fus_oper_i_ldst_ldst0__sign_extend), + .oper_i_ldst_ldst0__sv_pred_dz(fus_oper_i_ldst_ldst0__sv_pred_dz), + .oper_i_ldst_ldst0__sv_pred_sz(fus_oper_i_ldst_ldst0__sv_pred_sz), + .oper_i_ldst_ldst0__sv_saturate(fus_oper_i_ldst_ldst0__sv_saturate), .oper_i_ldst_ldst0__zero_a(fus_oper_i_ldst_ldst0__zero_a), .spr1_ok(fus_spr1_ok), .src1_i(fus_src1_i), @@ -42889,7 +46899,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c .\src2_i$45 (\fus_src2_i$57 ), .\src2_i$48 (\fus_src2_i$60 ), .\src2_i$77 (\fus_src2_i$89 ), - .\src2_i$79 (\fus_src2_i$91 ), + .\src2_i$80 (\fus_src2_i$92 ), .src3_i(fus_src3_i), .\src3_i$49 (\fus_src3_i$61 ), .\src3_i$60 (\fus_src3_i$72 ), @@ -42908,19 +46918,21 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c .src5_i(fus_src5_i), .\src5_i$66 (\fus_src5_i$78 ), .\src5_i$72 (\fus_src5_i$84 ), + .\src5_i$79 (\fus_src5_i$91 ), .src6_i(fus_src6_i), .\src6_i$73 (\fus_src6_i$85 ), + .svstate_ok(fus_svstate_ok), .xer_ca_ok(fus_xer_ca_ok), - .\xer_ca_ok$120 (\fus_xer_ca_ok$132 ), .\xer_ca_ok$121 (\fus_xer_ca_ok$133 ), + .\xer_ca_ok$122 (\fus_xer_ca_ok$134 ), .xer_ov_ok(fus_xer_ov_ok), - .\xer_ov_ok$124 (\fus_xer_ov_ok$136 ), .\xer_ov_ok$125 (\fus_xer_ov_ok$137 ), .\xer_ov_ok$126 (\fus_xer_ov_ok$138 ), + .\xer_ov_ok$127 (\fus_xer_ov_ok$139 ), .xer_so_ok(fus_xer_so_ok), - .\xer_so_ok$129 (\fus_xer_so_ok$141 ), .\xer_so_ok$130 (\fus_xer_so_ok$142 ), - .\xer_so_ok$131 (\fus_xer_so_ok$143 ) + .\xer_so_ok$131 (\fus_xer_so_ok$143 ), + .\xer_so_ok$132 (\fus_xer_so_ok$144 ) ); \int \int ( .coresync_clk(coresync_clk), @@ -42953,17 +46965,18 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c .ldst_port0_busy_o(fus_ldst_port0_busy_o), .ldst_port0_data_len(fus_ldst_port0_data_len), .\ldst_port0_exc_$signal (\fus_ldst_port0_exc_$signal ), - .\ldst_port0_exc_$signal$1 (\fus_ldst_port0_exc_$signal$163 ), - .\ldst_port0_exc_$signal$2 (\fus_ldst_port0_exc_$signal$164 ), - .\ldst_port0_exc_$signal$3 (\fus_ldst_port0_exc_$signal$165 ), - .\ldst_port0_exc_$signal$4 (\fus_ldst_port0_exc_$signal$166 ), - .\ldst_port0_exc_$signal$5 (\fus_ldst_port0_exc_$signal$167 ), - .\ldst_port0_exc_$signal$6 (\fus_ldst_port0_exc_$signal$168 ), - .\ldst_port0_exc_$signal$7 (\fus_ldst_port0_exc_$signal$169 ), + .\ldst_port0_exc_$signal$1 (\fus_ldst_port0_exc_$signal$165 ), + .\ldst_port0_exc_$signal$2 (\fus_ldst_port0_exc_$signal$166 ), + .\ldst_port0_exc_$signal$3 (\fus_ldst_port0_exc_$signal$167 ), + .\ldst_port0_exc_$signal$4 (\fus_ldst_port0_exc_$signal$168 ), + .\ldst_port0_exc_$signal$5 (\fus_ldst_port0_exc_$signal$169 ), + .\ldst_port0_exc_$signal$6 (\fus_ldst_port0_exc_$signal$170 ), + .\ldst_port0_exc_$signal$7 (\fus_ldst_port0_exc_$signal$171 ), .ldst_port0_is_ld_i(fus_ldst_port0_is_ld_i), .ldst_port0_is_st_i(fus_ldst_port0_is_st_i), .ldst_port0_ld_data_o(fus_ldst_port0_ld_data_o), .ldst_port0_ld_data_o_ok(fus_ldst_port0_ld_data_o_ok), + .ldst_port0_msr_pr(fus_ldst_port0_msr_pr), .ldst_port0_st_data_i(fus_ldst_port0_st_data_i), .ldst_port0_st_data_i_ok(fus_ldst_port0_st_data_i_ok), .wb_dcache_en(wb_dcache_en) @@ -43022,7 +47035,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c .coresync_clk(coresync_clk), .coresync_rst(coresync_rst), .spr1__addr(spr_spr1__addr), - .\spr1__addr$1 (\spr_spr1__addr$175 ), + .\spr1__addr$1 (\spr_spr1__addr$179 ), .spr1__data_i(spr_spr1__data_i), .spr1__data_o(spr_spr1__data_o), .spr1__ren(spr_spr1__ren), @@ -43036,7 +47049,8 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c .data_i(data_i), .\data_i$2 (\data_i$11 ), .\data_i$3 (state_data_i), - .\data_i$4 (\state_data_i$174 ), + .\data_i$4 (\state_data_i$176 ), + .\data_i$6 (\state_data_i$177 ), .msr__data_o(msr__data_o), .msr__ren(msr__ren), .state_nia_wen(state_nia_wen), @@ -43044,7 +47058,8 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c .sv__ren(sv__ren), .wen(wen), .\wen$1 (\wen$10 ), - .\wen$5 (state_wen) + .\wen$5 (state_wen), + .\wen$7 (\state_wen$178 ) ); wrpick_CR_cr_a wrpick_CR_cr_a ( .en_o(wrpick_CR_cr_a_en_o), @@ -43081,6 +47096,11 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c .i(wrpick_STATE_nia_i), .o(wrpick_STATE_nia_o) ); + wrpick_STATE_svstate wrpick_STATE_svstate ( + .en_o(wrpick_STATE_svstate_en_o), + .i(wrpick_STATE_svstate_i), + .o(wrpick_STATE_svstate_o) + ); wrpick_XER_xer_ca wrpick_XER_xer_ca ( .en_o(wrpick_XER_xer_ca_en_o), .i(wrpick_XER_xer_ca_i), @@ -43100,8 +47120,8 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c .coresync_clk(coresync_clk), .coresync_rst(coresync_rst), .data_i(xer_data_i), - .\data_i$1 (\xer_data_i$170 ), - .\data_i$3 (\xer_data_i$172 ), + .\data_i$1 (\xer_data_i$172 ), + .\data_i$3 (\xer_data_i$174 ), .full_rd__data_o(full_rd__data_o), .full_rd__ren(full_rd__ren), .src1__data_o(xer_src1__data_o), @@ -43111,33 +47131,456 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c .src3__data_o(xer_src3__data_o), .src3__ren(xer_src3__ren), .wen(xer_wen), - .\wen$2 (\xer_wen$171 ), - .\wen$4 (\xer_wen$173 ) + .\wen$2 (\xer_wen$173 ), + .\wen$4 (\xer_wen$175 ) ); + always @* begin + if (\initial ) begin end + fus_oper_i_alu_trap0__sv_saturate = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[3]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_alu_trap0__sv_saturate = core_core__sv_saturate; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_trap0__SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[3]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_alu_trap0__SV_Ptype = core_core__SV_Ptype; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \fus_cu_issue_i$19 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[3]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + \fus_cu_issue_i$19 = issue_i; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \fus_cu_rdmaskn_i$21 = 5'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[3]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + \fus_cu_rdmaskn_i$21 = \$258 ; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_logical0__insn_type = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_alu_logical0__insn_type = dec_LOGICAL_LOGICAL__insn_type; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_logical0__fn_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_alu_logical0__fn_unit = dec_LOGICAL_LOGICAL__fn_unit; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_logical0__imm_data__data = 64'h0000000000000000; + fus_oper_i_alu_logical0__imm_data__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + { fus_oper_i_alu_logical0__imm_data__ok, fus_oper_i_alu_logical0__imm_data__data } = { dec_LOGICAL_LOGICAL__imm_data__ok, dec_LOGICAL_LOGICAL__imm_data__data }; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_logical0__rc__rc = 1'h0; + fus_oper_i_alu_logical0__rc__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + { fus_oper_i_alu_logical0__rc__ok, fus_oper_i_alu_logical0__rc__rc } = { dec_LOGICAL_LOGICAL__rc__ok, dec_LOGICAL_LOGICAL__rc__rc }; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_logical0__oe__oe = 1'h0; + fus_oper_i_alu_logical0__oe__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + { fus_oper_i_alu_logical0__oe__ok, fus_oper_i_alu_logical0__oe__oe } = { dec_LOGICAL_LOGICAL__oe__ok, dec_LOGICAL_LOGICAL__oe__oe }; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_logical0__invert_in = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_alu_logical0__invert_in = dec_LOGICAL_LOGICAL__invert_in; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_logical0__zero_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_alu_logical0__zero_a = dec_LOGICAL_LOGICAL__zero_a; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_logical0__input_carry = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_alu_logical0__input_carry = dec_LOGICAL_LOGICAL__input_carry; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_logical0__invert_out = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_alu_logical0__invert_out = dec_LOGICAL_LOGICAL__invert_out; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_logical0__write_cr0 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_alu_logical0__write_cr0 = dec_LOGICAL_LOGICAL__write_cr0; + endcase + endcase + endcase + end always @* begin if (\initial ) begin end fus_oper_i_alu_logical0__output_carry = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_logical0__output_carry = dec_LOGICAL_LOGICAL__output_carry; endcase @@ -43147,27 +47590,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_logical0__is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_logical0__is_32bit = dec_LOGICAL_LOGICAL__is_32bit; endcase @@ -43177,27 +47620,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_logical0__is_signed = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_logical0__is_signed = dec_LOGICAL_LOGICAL__is_signed; endcase @@ -43207,27 +47650,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_logical0__data_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_logical0__data_len = dec_LOGICAL_LOGICAL__data_len; endcase @@ -43237,57 +47680,177 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_logical0__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_logical0__insn = dec_LOGICAL_LOGICAL__insn; endcase endcase endcase end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_logical0__sv_pred_sz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_alu_logical0__sv_pred_sz = LOGICAL__sv_pred_sz; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_logical0__sv_pred_dz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_alu_logical0__sv_pred_dz = LOGICAL__sv_pred_dz; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_logical0__sv_saturate = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_alu_logical0__sv_saturate = LOGICAL__sv_saturate; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_logical0__SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_alu_logical0__SV_Ptype = LOGICAL__SV_Ptype; + endcase + endcase + endcase + end always @* begin if (\initial ) begin end \fus_cu_issue_i$22 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: \fus_cu_issue_i$22 = issue_i; endcase @@ -43297,29 +47860,29 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_cu_rdmaskn_i$24 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - \fus_cu_rdmaskn_i$24 = \$256 ; + \fus_cu_rdmaskn_i$24 = \$260 ; endcase endcase endcase @@ -43327,27 +47890,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_spr0__insn_type = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[5]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_spr0__insn_type = dec_SPR_SPR__insn_type; endcase @@ -43356,28 +47919,28 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c end always @* begin if (\initial ) begin end - fus_oper_i_alu_spr0__fn_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_spr0__fn_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[5]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_spr0__fn_unit = dec_SPR_SPR__fn_unit; endcase @@ -43387,27 +47950,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_spr0__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[5]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_spr0__insn = dec_SPR_SPR__insn; endcase @@ -43417,57 +47980,177 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_spr0__is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[5]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_spr0__is_32bit = dec_SPR_SPR__is_32bit; endcase endcase endcase end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_spr0__sv_pred_sz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[5]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_alu_spr0__sv_pred_sz = SPR__sv_pred_sz; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_spr0__sv_pred_dz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[5]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_alu_spr0__sv_pred_dz = SPR__sv_pred_dz; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_spr0__sv_saturate = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[5]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_alu_spr0__sv_saturate = SPR__sv_saturate; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_spr0__SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[5]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_alu_spr0__SV_Ptype = SPR__SV_Ptype; + endcase + endcase + endcase + end always @* begin if (\initial ) begin end \fus_cu_issue_i$25 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[5]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: \fus_cu_issue_i$25 = issue_i; endcase @@ -43477,29 +48160,29 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_cu_rdmaskn_i$27 = 6'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[5]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - \fus_cu_rdmaskn_i$27 = \$270 ; + \fus_cu_rdmaskn_i$27 = \$274 ; endcase endcase endcase @@ -43507,27 +48190,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_div0__insn_type = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_div0__insn_type = dec_DIV_DIV__insn_type; endcase @@ -43536,28 +48219,28 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c end always @* begin if (\initial ) begin end - fus_oper_i_alu_div0__fn_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_div0__fn_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_div0__fn_unit = dec_DIV_DIV__fn_unit; endcase @@ -43568,27 +48251,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c if (\initial ) begin end fus_oper_i_alu_div0__imm_data__data = 64'h0000000000000000; fus_oper_i_alu_div0__imm_data__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: { fus_oper_i_alu_div0__imm_data__ok, fus_oper_i_alu_div0__imm_data__data } = { dec_DIV_DIV__imm_data__ok, dec_DIV_DIV__imm_data__data }; endcase @@ -43599,27 +48282,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c if (\initial ) begin end fus_oper_i_alu_div0__rc__rc = 1'h0; fus_oper_i_alu_div0__rc__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: { fus_oper_i_alu_div0__rc__ok, fus_oper_i_alu_div0__rc__rc } = { dec_DIV_DIV__rc__ok, dec_DIV_DIV__rc__rc }; endcase @@ -43630,27 +48313,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c if (\initial ) begin end fus_oper_i_alu_div0__oe__oe = 1'h0; fus_oper_i_alu_div0__oe__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: { fus_oper_i_alu_div0__oe__ok, fus_oper_i_alu_div0__oe__oe } = { dec_DIV_DIV__oe__ok, dec_DIV_DIV__oe__oe }; endcase @@ -43660,27 +48343,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_div0__invert_in = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_div0__invert_in = dec_DIV_DIV__invert_in; endcase @@ -43690,27 +48373,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_div0__zero_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_div0__zero_a = dec_DIV_DIV__zero_a; endcase @@ -43720,27 +48403,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_div0__input_carry = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_div0__input_carry = dec_DIV_DIV__input_carry; endcase @@ -43750,27 +48433,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_div0__invert_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_div0__invert_out = dec_DIV_DIV__invert_out; endcase @@ -43780,27 +48463,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_div0__write_cr0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_div0__write_cr0 = dec_DIV_DIV__write_cr0; endcase @@ -43810,27 +48493,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_div0__output_carry = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_div0__output_carry = dec_DIV_DIV__output_carry; endcase @@ -43840,27 +48523,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_div0__is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_div0__is_32bit = dec_DIV_DIV__is_32bit; endcase @@ -43870,27 +48553,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_div0__is_signed = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_div0__is_signed = dec_DIV_DIV__is_signed; endcase @@ -43900,27 +48583,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_div0__data_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_div0__data_len = dec_DIV_DIV__data_len; endcase @@ -43930,57 +48613,177 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_div0__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_div0__insn = dec_DIV_DIV__insn; endcase endcase endcase end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_div0__sv_pred_sz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[6]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_alu_div0__sv_pred_sz = DIV__sv_pred_sz; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_div0__sv_pred_dz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[6]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_alu_div0__sv_pred_dz = DIV__sv_pred_dz; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_div0__sv_saturate = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[6]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_alu_div0__sv_saturate = DIV__sv_saturate; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_div0__SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[6]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_alu_div0__SV_Ptype = DIV__SV_Ptype; + endcase + endcase + endcase + end always @* begin if (\initial ) begin end \fus_cu_issue_i$28 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: \fus_cu_issue_i$28 = issue_i; endcase @@ -43990,29 +48793,29 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_cu_rdmaskn_i$30 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - \fus_cu_rdmaskn_i$30 = \$300 ; + \fus_cu_rdmaskn_i$30 = \$304 ; endcase endcase endcase @@ -44020,27 +48823,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_mul0__insn_type = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[7]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_mul0__insn_type = dec_MUL_MUL__insn_type; endcase @@ -44049,28 +48852,28 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c end always @* begin if (\initial ) begin end - fus_oper_i_alu_mul0__fn_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_mul0__fn_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[7]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_mul0__fn_unit = dec_MUL_MUL__fn_unit; endcase @@ -44081,27 +48884,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c if (\initial ) begin end fus_oper_i_alu_mul0__imm_data__data = 64'h0000000000000000; fus_oper_i_alu_mul0__imm_data__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[7]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: { fus_oper_i_alu_mul0__imm_data__ok, fus_oper_i_alu_mul0__imm_data__data } = { dec_MUL_MUL__imm_data__ok, dec_MUL_MUL__imm_data__data }; endcase @@ -44112,27 +48915,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c if (\initial ) begin end fus_oper_i_alu_mul0__rc__rc = 1'h0; fus_oper_i_alu_mul0__rc__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[7]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: { fus_oper_i_alu_mul0__rc__ok, fus_oper_i_alu_mul0__rc__rc } = { dec_MUL_MUL__rc__ok, dec_MUL_MUL__rc__rc }; endcase @@ -44143,27 +48946,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c if (\initial ) begin end fus_oper_i_alu_mul0__oe__oe = 1'h0; fus_oper_i_alu_mul0__oe__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[7]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: { fus_oper_i_alu_mul0__oe__ok, fus_oper_i_alu_mul0__oe__oe } = { dec_MUL_MUL__oe__ok, dec_MUL_MUL__oe__oe }; endcase @@ -44173,27 +48976,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_mul0__write_cr0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[7]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_mul0__write_cr0 = dec_MUL_MUL__write_cr0; endcase @@ -44203,27 +49006,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_mul0__is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[7]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_mul0__is_32bit = dec_MUL_MUL__is_32bit; endcase @@ -44233,27 +49036,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_mul0__is_signed = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[7]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_mul0__is_signed = dec_MUL_MUL__is_signed; endcase @@ -44263,57 +49066,177 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_mul0__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[7]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_mul0__insn = dec_MUL_MUL__insn; endcase endcase endcase end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_mul0__sv_pred_sz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[7]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_alu_mul0__sv_pred_sz = MUL__sv_pred_sz; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_mul0__sv_pred_dz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[7]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_alu_mul0__sv_pred_dz = MUL__sv_pred_dz; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_mul0__sv_saturate = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[7]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_alu_mul0__sv_saturate = MUL__sv_saturate; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_mul0__SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[7]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_alu_mul0__SV_Ptype = MUL__SV_Ptype; + endcase + endcase + endcase + end always @* begin if (\initial ) begin end \fus_cu_issue_i$31 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[7]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: \fus_cu_issue_i$31 = issue_i; endcase @@ -44323,29 +49246,29 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_cu_rdmaskn_i$33 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[7]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - \fus_cu_rdmaskn_i$33 = \$314 ; + \fus_cu_rdmaskn_i$33 = \$318 ; endcase endcase endcase @@ -44353,27 +49276,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_shift_rot0__insn_type = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_shift_rot0__insn_type = dec_SHIFT_ROT_SHIFT_ROT__insn_type; endcase @@ -44382,28 +49305,28 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c end always @* begin if (\initial ) begin end - fus_oper_i_alu_shift_rot0__fn_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_shift_rot0__fn_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_shift_rot0__fn_unit = dec_SHIFT_ROT_SHIFT_ROT__fn_unit; endcase @@ -44414,27 +49337,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c if (\initial ) begin end fus_oper_i_alu_shift_rot0__imm_data__data = 64'h0000000000000000; fus_oper_i_alu_shift_rot0__imm_data__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: { fus_oper_i_alu_shift_rot0__imm_data__ok, fus_oper_i_alu_shift_rot0__imm_data__data } = { dec_SHIFT_ROT_SHIFT_ROT__imm_data__ok, dec_SHIFT_ROT_SHIFT_ROT__imm_data__data }; endcase @@ -44445,27 +49368,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c if (\initial ) begin end fus_oper_i_alu_shift_rot0__rc__rc = 1'h0; fus_oper_i_alu_shift_rot0__rc__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: { fus_oper_i_alu_shift_rot0__rc__ok, fus_oper_i_alu_shift_rot0__rc__rc } = { dec_SHIFT_ROT_SHIFT_ROT__rc__ok, dec_SHIFT_ROT_SHIFT_ROT__rc__rc }; endcase @@ -44476,27 +49399,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c if (\initial ) begin end fus_oper_i_alu_shift_rot0__oe__oe = 1'h0; fus_oper_i_alu_shift_rot0__oe__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: { fus_oper_i_alu_shift_rot0__oe__ok, fus_oper_i_alu_shift_rot0__oe__oe } = { dec_SHIFT_ROT_SHIFT_ROT__oe__ok, dec_SHIFT_ROT_SHIFT_ROT__oe__oe }; endcase @@ -44506,27 +49429,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_shift_rot0__write_cr0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_shift_rot0__write_cr0 = dec_SHIFT_ROT_SHIFT_ROT__write_cr0; endcase @@ -44536,27 +49459,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_shift_rot0__invert_in = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_shift_rot0__invert_in = dec_SHIFT_ROT_SHIFT_ROT__invert_in; endcase @@ -44566,27 +49489,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_shift_rot0__input_carry = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_shift_rot0__input_carry = dec_SHIFT_ROT_SHIFT_ROT__input_carry; endcase @@ -44596,27 +49519,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_shift_rot0__output_carry = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_shift_rot0__output_carry = dec_SHIFT_ROT_SHIFT_ROT__output_carry; endcase @@ -44626,27 +49549,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_shift_rot0__input_cr = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_shift_rot0__input_cr = dec_SHIFT_ROT_SHIFT_ROT__input_cr; endcase @@ -44656,27 +49579,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_shift_rot0__output_cr = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_shift_rot0__output_cr = dec_SHIFT_ROT_SHIFT_ROT__output_cr; endcase @@ -44686,27 +49609,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_shift_rot0__is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_shift_rot0__is_32bit = dec_SHIFT_ROT_SHIFT_ROT__is_32bit; endcase @@ -44716,27 +49639,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_shift_rot0__is_signed = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_shift_rot0__is_signed = dec_SHIFT_ROT_SHIFT_ROT__is_signed; endcase @@ -44746,57 +49669,177 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_alu_shift_rot0__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_shift_rot0__insn = dec_SHIFT_ROT_SHIFT_ROT__insn; endcase endcase endcase end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_shift_rot0__sv_pred_sz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[8]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_alu_shift_rot0__sv_pred_sz = SHIFT_ROT__sv_pred_sz; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_shift_rot0__sv_pred_dz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[8]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_alu_shift_rot0__sv_pred_dz = SHIFT_ROT__sv_pred_dz; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_shift_rot0__sv_saturate = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[8]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_alu_shift_rot0__sv_saturate = SHIFT_ROT__sv_saturate; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_shift_rot0__SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[8]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_alu_shift_rot0__SV_Ptype = SHIFT_ROT__SV_Ptype; + endcase + endcase + endcase + end always @* begin if (\initial ) begin end \fus_cu_issue_i$34 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: \fus_cu_issue_i$34 = issue_i; endcase @@ -44806,29 +49849,29 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_cu_rdmaskn_i$36 = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - \fus_cu_rdmaskn_i$36 = \$328 ; + \fus_cu_rdmaskn_i$36 = \$332 ; endcase endcase endcase @@ -44836,27 +49879,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_ldst_ldst0__insn_type = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[9]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_ldst_ldst0__insn_type = dec_LDST_LDST__insn_type; endcase @@ -44865,28 +49908,28 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c end always @* begin if (\initial ) begin end - fus_oper_i_ldst_ldst0__fn_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_ldst_ldst0__fn_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[9]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_ldst_ldst0__fn_unit = dec_LDST_LDST__fn_unit; endcase @@ -44897,27 +49940,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c if (\initial ) begin end fus_oper_i_ldst_ldst0__imm_data__data = 64'h0000000000000000; fus_oper_i_ldst_ldst0__imm_data__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[9]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: { fus_oper_i_ldst_ldst0__imm_data__ok, fus_oper_i_ldst_ldst0__imm_data__data } = { dec_LDST_LDST__imm_data__ok, dec_LDST_LDST__imm_data__data }; endcase @@ -44927,27 +49970,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_ldst_ldst0__zero_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[9]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_ldst_ldst0__zero_a = dec_LDST_LDST__zero_a; endcase @@ -44958,27 +50001,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c if (\initial ) begin end fus_oper_i_ldst_ldst0__rc__rc = 1'h0; fus_oper_i_ldst_ldst0__rc__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[9]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: { fus_oper_i_ldst_ldst0__rc__ok, fus_oper_i_ldst_ldst0__rc__rc } = { dec_LDST_LDST__rc__ok, dec_LDST_LDST__rc__rc }; endcase @@ -44989,57 +50032,87 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c if (\initial ) begin end fus_oper_i_ldst_ldst0__oe__oe = 1'h0; fus_oper_i_ldst_ldst0__oe__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[9]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: { fus_oper_i_ldst_ldst0__oe__ok, fus_oper_i_ldst_ldst0__oe__oe } = { dec_LDST_LDST__oe__ok, dec_LDST_LDST__oe__oe }; endcase endcase endcase end + always @* begin + if (\initial ) begin end + fus_oper_i_ldst_ldst0__msr = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[9]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_ldst_ldst0__msr = dec_LDST_LDST__msr; + endcase + endcase + endcase + end always @* begin if (\initial ) begin end fus_oper_i_ldst_ldst0__is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[9]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_ldst_ldst0__is_32bit = dec_LDST_LDST__is_32bit; endcase @@ -45049,27 +50122,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_ldst_ldst0__is_signed = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[9]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_ldst_ldst0__is_signed = dec_LDST_LDST__is_signed; endcase @@ -45079,27 +50152,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_ldst_ldst0__data_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[9]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_ldst_ldst0__data_len = dec_LDST_LDST__data_len; endcase @@ -45109,27 +50182,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_ldst_ldst0__byte_reverse = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[9]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_ldst_ldst0__byte_reverse = dec_LDST_LDST__byte_reverse; endcase @@ -45139,27 +50212,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_ldst_ldst0__sign_extend = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[9]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_ldst_ldst0__sign_extend = dec_LDST_LDST__sign_extend; endcase @@ -45169,27 +50242,27 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_ldst_ldst0__ldst_mode = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[9]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_ldst_ldst0__ldst_mode = dec_LDST_LDST__ldst_mode; endcase @@ -45199,57 +50272,177 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_oper_i_ldst_ldst0__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[9]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_ldst_ldst0__insn = dec_LDST_LDST__insn; endcase endcase endcase end + always @* begin + if (\initial ) begin end + fus_oper_i_ldst_ldst0__sv_pred_sz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[9]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_ldst_ldst0__sv_pred_sz = LDST__sv_pred_sz; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_ldst_ldst0__sv_pred_dz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[9]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_ldst_ldst0__sv_pred_dz = LDST__sv_pred_dz; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_ldst_ldst0__sv_saturate = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[9]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_ldst_ldst0__sv_saturate = LDST__sv_saturate; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_ldst_ldst0__SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[9]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_ldst_ldst0__SV_Ptype = LDST__SV_Ptype; + endcase + endcase + endcase + end always @* begin if (\initial ) begin end \fus_cu_issue_i$37 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[9]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: \fus_cu_issue_i$37 = issue_i; endcase @@ -45259,29 +50452,29 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_cu_rdmaskn_i$39 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[9]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - \fus_cu_rdmaskn_i$39 = \$350 ; + \fus_cu_rdmaskn_i$39 = \$354 ; endcase endcase endcase @@ -45289,7 +50482,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_alu0_0$next = rp_INT_rabc_alu0_0; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_alu0_0$next = 1'h0; @@ -45298,9 +50491,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_src2_i = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_INT_rabc_alu0_0) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: fus_src2_i = int_src1__data_o; endcase @@ -45308,7 +50501,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_cr0_1$next = rp_INT_rabc_cr0_1; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_cr0_1$next = 1'h0; @@ -45317,9 +50510,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src2_i$42 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_INT_rabc_cr0_1) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: \fus_src2_i$42 = int_src1__data_o; endcase @@ -45327,7 +50520,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_trap0_2$next = rp_INT_rabc_trap0_2; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_trap0_2$next = 1'h0; @@ -45336,9 +50529,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src2_i$45 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_INT_rabc_trap0_2) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: \fus_src2_i$45 = int_src1__data_o; endcase @@ -45346,7 +50539,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_logical0_3$next = rp_INT_rabc_logical0_3; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_logical0_3$next = 1'h0; @@ -45355,9 +50548,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src2_i$48 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_INT_rabc_logical0_3) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: \fus_src2_i$48 = int_src1__data_o; endcase @@ -45365,7 +50558,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_div0_4$next = rp_INT_rabc_div0_4; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_div0_4$next = 1'h0; @@ -45374,9 +50567,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src2_i$51 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_INT_rabc_div0_4) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: \fus_src2_i$51 = int_src1__data_o; endcase @@ -45384,7 +50577,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_mul0_5$next = rp_INT_rabc_mul0_5; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_mul0_5$next = 1'h0; @@ -45393,9 +50586,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src2_i$54 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_INT_rabc_mul0_5) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: \fus_src2_i$54 = int_src1__data_o; endcase @@ -45403,7 +50596,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_shiftrot0_6$next = rp_INT_rabc_shiftrot0_6; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_shiftrot0_6$next = 1'h0; @@ -45412,9 +50605,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src2_i$57 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_INT_rabc_shiftrot0_6) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: \fus_src2_i$57 = int_src1__data_o; endcase @@ -45422,7 +50615,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_ldst0_7$next = rp_INT_rabc_ldst0_7; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_ldst0_7$next = 1'h0; @@ -45431,9 +50624,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src2_i$60 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_INT_rabc_ldst0_7) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: \fus_src2_i$60 = int_src1__data_o; endcase @@ -45441,7 +50634,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_shiftrot0_8$next = rp_INT_rabc_shiftrot0_8; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_shiftrot0_8$next = 1'h0; @@ -45450,9 +50643,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_src3_i = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_INT_rabc_shiftrot0_8) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: fus_src3_i = int_src1__data_o; endcase @@ -45460,7 +50653,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_ldst0_9$next = rp_INT_rabc_ldst0_9; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_ldst0_9$next = 1'h0; @@ -45469,9 +50662,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src3_i$61 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_INT_rabc_ldst0_9) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: \fus_src3_i$61 = int_src1__data_o; endcase @@ -45479,7 +50672,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_alu0_10$next = rp_INT_rabc_alu0_10; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_alu0_10$next = 1'h0; @@ -45488,9 +50681,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_src1_i = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_INT_rabc_alu0_10) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: fus_src1_i = int_src1__data_o; endcase @@ -45498,7 +50691,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_cr0_11$next = rp_INT_rabc_cr0_11; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_cr0_11$next = 1'h0; @@ -45507,9 +50700,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src1_i$62 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_INT_rabc_cr0_11) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: \fus_src1_i$62 = int_src1__data_o; endcase @@ -45517,7 +50710,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_trap0_12$next = rp_INT_rabc_trap0_12; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_trap0_12$next = 1'h0; @@ -45526,9 +50719,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src1_i$63 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_INT_rabc_trap0_12) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: \fus_src1_i$63 = int_src1__data_o; endcase @@ -45536,7 +50729,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_logical0_13$next = rp_INT_rabc_logical0_13; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_logical0_13$next = 1'h0; @@ -45545,9 +50738,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src1_i$64 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_INT_rabc_logical0_13) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: \fus_src1_i$64 = int_src1__data_o; endcase @@ -45555,7 +50748,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_spr0_14$next = rp_INT_rabc_spr0_14; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_spr0_14$next = 1'h0; @@ -45564,9 +50757,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src1_i$67 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_INT_rabc_spr0_14) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: \fus_src1_i$67 = int_src1__data_o; endcase @@ -45574,7 +50767,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_div0_15$next = rp_INT_rabc_div0_15; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_div0_15$next = 1'h0; @@ -45583,9 +50776,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src1_i$68 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_INT_rabc_div0_15) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: \fus_src1_i$68 = int_src1__data_o; endcase @@ -45593,7 +50786,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_mul0_16$next = rp_INT_rabc_mul0_16; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_mul0_16$next = 1'h0; @@ -45602,9 +50795,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src1_i$69 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_INT_rabc_mul0_16) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: \fus_src1_i$69 = int_src1__data_o; endcase @@ -45612,7 +50805,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_shiftrot0_17$next = rp_INT_rabc_shiftrot0_17; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_shiftrot0_17$next = 1'h0; @@ -45621,9 +50814,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src1_i$70 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_INT_rabc_shiftrot0_17) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: \fus_src1_i$70 = int_src1__data_o; endcase @@ -45631,7 +50824,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_ldst0_18$next = rp_INT_rabc_ldst0_18; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_ldst0_18$next = 1'h0; @@ -45640,9 +50833,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src1_i$71 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_INT_rabc_ldst0_18) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: \fus_src1_i$71 = int_src1__data_o; endcase @@ -45650,7 +50843,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_XER_xer_so_alu0_0$next = rp_XER_xer_so_alu0_0; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_XER_xer_so_alu0_0$next = 1'h0; @@ -45659,9 +50852,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src3_i$72 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_XER_xer_so_alu0_0) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: \fus_src3_i$72 = xer_src1__data_o[0]; endcase @@ -45669,7 +50862,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_XER_xer_so_logical0_1$next = rp_XER_xer_so_logical0_1; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_XER_xer_so_logical0_1$next = 1'h0; @@ -45678,9 +50871,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src3_i$73 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_XER_xer_so_logical0_1) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: \fus_src3_i$73 = xer_src1__data_o[0]; endcase @@ -45688,7 +50881,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_XER_xer_so_spr0_2$next = rp_XER_xer_so_spr0_2; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_XER_xer_so_spr0_2$next = 1'h0; @@ -45697,9 +50890,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_src4_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_XER_xer_so_spr0_2) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: fus_src4_i = xer_src1__data_o[0]; endcase @@ -45707,7 +50900,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_XER_xer_so_div0_3$next = rp_XER_xer_so_div0_3; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_XER_xer_so_div0_3$next = 1'h0; @@ -45716,9 +50909,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src3_i$74 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_XER_xer_so_div0_3) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: \fus_src3_i$74 = xer_src1__data_o[0]; endcase @@ -45726,7 +50919,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_XER_xer_so_mul0_4$next = rp_XER_xer_so_mul0_4; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_XER_xer_so_mul0_4$next = 1'h0; @@ -45735,9 +50928,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src3_i$75 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_XER_xer_so_mul0_4) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: \fus_src3_i$75 = xer_src1__data_o[0]; endcase @@ -45745,7 +50938,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_XER_xer_so_shiftrot0_5$next = rp_XER_xer_so_shiftrot0_5; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_XER_xer_so_shiftrot0_5$next = 1'h0; @@ -45754,9 +50947,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src4_i$76 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_XER_xer_so_shiftrot0_5) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: \fus_src4_i$76 = xer_src1__data_o[0]; endcase @@ -45764,7 +50957,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_XER_xer_ca_alu0_0$next = rp_XER_xer_ca_alu0_0; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_XER_xer_ca_alu0_0$next = 1'h0; @@ -45773,9 +50966,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src4_i$77 = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_XER_xer_ca_alu0_0) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: \fus_src4_i$77 = xer_src2__data_o; endcase @@ -45783,18 +50976,49 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_XER_xer_ca_spr0_1$next = rp_XER_xer_ca_spr0_1; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_XER_xer_ca_spr0_1$next = 1'h0; endcase end + always @* begin + if (\initial ) begin end + \counter$next = counter; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216" *) + casez (\$225 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216" */ + 1'h1: + \counter$next = \$227 [1:0]; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + \counter$next = 2'h2; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + casez (coresync_rst) + 1'h1: + \counter$next = 2'h0; + endcase + end always @* begin if (\initial ) begin end fus_src6_i = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_XER_xer_ca_spr0_1) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: fus_src6_i = xer_src2__data_o; endcase @@ -45802,7 +51026,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_XER_xer_ca_shiftrot0_2$next = rp_XER_xer_ca_shiftrot0_2; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_XER_xer_ca_shiftrot0_2$next = 1'h0; @@ -45811,17 +51035,109 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end fus_src5_i = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_XER_xer_ca_shiftrot0_2) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: fus_src5_i = xer_src2__data_o; endcase end + always @* begin + if (\initial ) begin end + corebusy_o = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216" *) + casez (\$230 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216" */ + 1'h1: + corebusy_o = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + corebusy_o = 1'h1; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + begin + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[0]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + corebusy_o = fus_cu_busy_o; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[1]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + corebusy_o = \fus_cu_busy_o$14 ; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[2]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + corebusy_o = \fus_cu_busy_o$17 ; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[3]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + corebusy_o = \fus_cu_busy_o$20 ; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[4]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + corebusy_o = \fus_cu_busy_o$23 ; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[5]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + corebusy_o = \fus_cu_busy_o$26 ; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[6]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + corebusy_o = \fus_cu_busy_o$29 ; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[7]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + corebusy_o = \fus_cu_busy_o$32 ; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[8]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + corebusy_o = \fus_cu_busy_o$35 ; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[9]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + corebusy_o = \fus_cu_busy_o$38 ; + endcase + end + endcase + endcase + end always @* begin if (\initial ) begin end \dp_XER_xer_ov_spr0_0$next = rp_XER_xer_ov_spr0_0; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_XER_xer_ov_spr0_0$next = 1'h0; @@ -45830,9 +51146,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src5_i$78 = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_XER_xer_ov_spr0_0) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: \fus_src5_i$78 = xer_src3__data_o; endcase @@ -45840,18 +51156,39 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_CR_full_cr_cr0_0$next = rp_CR_full_cr_cr0_0; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_CR_full_cr_cr0_0$next = 1'h0; endcase end + always @* begin + if (\initial ) begin end + \core_terminate_o$next = core_terminate_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + \core_terminate_o$next = 1'h1; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + casez (coresync_rst) + 1'h1: + \core_terminate_o$next = 1'h0; + endcase + end always @* begin if (\initial ) begin end \fus_src3_i$79 = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_CR_full_cr_cr0_0) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: \fus_src3_i$79 = cr_full_rd__data_o; endcase @@ -45859,7 +51196,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_CR_cr_a_cr0_0$next = rp_CR_cr_a_cr0_0; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_CR_cr_a_cr0_0$next = 1'h0; @@ -45868,17 +51205,47 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src4_i$80 = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_CR_cr_a_cr0_0) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: \fus_src4_i$80 = cr_src1__data_o; endcase end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_alu0__insn_type = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[0]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_alu_alu0__insn_type = dec_ALU_ALU__insn_type; + endcase + endcase + endcase + end always @* begin if (\initial ) begin end \dp_CR_cr_a_branch0_1$next = rp_CR_cr_a_branch0_1; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_CR_cr_a_branch0_1$next = 1'h0; @@ -45887,59 +51254,58 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src3_i$83 = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_CR_cr_a_branch0_1) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: \fus_src3_i$83 = cr_src1__data_o; endcase end always @* begin if (\initial ) begin end - \dp_CR_cr_b_cr0_0$next = rp_CR_cr_b_cr0_0; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) - casez (coresync_rst) - 1'h1: - \dp_CR_cr_b_cr0_0$next = 1'h0; - endcase - end - always @* begin - if (\initial ) begin end - \counter$next = counter; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" *) - casez (\$221 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" */ - 1'h1: - \counter$next = \$223 [1:0]; - endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_alu0__fn_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: - \counter$next = 2'h2; + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[0]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_oper_i_alu_alu0__fn_unit = dec_ALU_ALU__fn_unit; + endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + end + always @* begin + if (\initial ) begin end + \dp_CR_cr_b_cr0_0$next = rp_CR_cr_b_cr0_0; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \counter$next = 2'h0; + \dp_CR_cr_b_cr0_0$next = 1'h0; endcase end always @* begin if (\initial ) begin end \fus_src5_i$84 = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_CR_cr_b_cr0_0) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: \fus_src5_i$84 = cr_src2__data_o; endcase @@ -45947,7 +51313,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_CR_cr_c_cr0_0$next = rp_CR_cr_c_cr0_0; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_CR_cr_c_cr0_0$next = 1'h0; @@ -45955,110 +51321,49 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c end always @* begin if (\initial ) begin end - \fus_src6_i$85 = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) - casez (dp_CR_cr_c_cr0_0) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ - 1'h1: - \fus_src6_i$85 = cr_src3__data_o; - endcase - end - always @* begin - if (\initial ) begin end - corebusy_o = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" *) - casez (\$226 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" */ - 1'h1: - corebusy_o = 1'h1; - endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_alu0__imm_data__data = 64'h0000000000000000; + fus_oper_i_alu_alu0__imm_data__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: - corebusy_o = 1'h1; + /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - begin - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - corebusy_o = fus_cu_busy_o; - endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[1]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ - 1'h1: - corebusy_o = \fus_cu_busy_o$14 ; - endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[2]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ - 1'h1: - corebusy_o = \fus_cu_busy_o$17 ; - endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[3]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ - 1'h1: - corebusy_o = \fus_cu_busy_o$20 ; - endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ - 1'h1: - corebusy_o = \fus_cu_busy_o$23 ; - endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[5]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ - 1'h1: - corebusy_o = \fus_cu_busy_o$26 ; - endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[6]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ - 1'h1: - corebusy_o = \fus_cu_busy_o$29 ; - endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[7]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ - 1'h1: - corebusy_o = \fus_cu_busy_o$32 ; - endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[8]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ - 1'h1: - corebusy_o = \fus_cu_busy_o$35 ; - endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[9]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ - 1'h1: - corebusy_o = \fus_cu_busy_o$38 ; + { fus_oper_i_alu_alu0__imm_data__ok, fus_oper_i_alu_alu0__imm_data__data } = { dec_ALU_ALU__imm_data__ok, dec_ALU_ALU__imm_data__data }; endcase - end endcase endcase end + always @* begin + if (\initial ) begin end + \fus_src6_i$85 = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) + casez (dp_CR_cr_c_cr0_0) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ + 1'h1: + \fus_src6_i$85 = cr_src3__data_o; + endcase + end always @* begin if (\initial ) begin end \dp_FAST_fast1_branch0_0$next = rp_FAST_fast1_branch0_0; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_FAST_fast1_branch0_0$next = 1'h0; @@ -46067,38 +51372,17 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src1_i$86 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_FAST_fast1_branch0_0) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: \fus_src1_i$86 = fast_src1__data_o; endcase end - always @* begin - if (\initial ) begin end - \core_terminate_o$next = core_terminate_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) - casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ - 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) - casez (core_core_insn_type) - /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ - 7'h05: - \core_terminate_o$next = 1'h1; - endcase - endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) - casez (coresync_rst) - 1'h1: - \core_terminate_o$next = 1'h0; - endcase - end always @* begin if (\initial ) begin end \dp_FAST_fast1_trap0_1$next = rp_FAST_fast1_trap0_1; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_FAST_fast1_trap0_1$next = 1'h0; @@ -46107,9 +51391,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src3_i$87 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_FAST_fast1_trap0_1) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: \fus_src3_i$87 = fast_src1__data_o; endcase @@ -46117,7 +51401,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_FAST_fast1_spr0_2$next = rp_FAST_fast1_spr0_2; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_FAST_fast1_spr0_2$next = 1'h0; @@ -46125,48 +51409,49 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c end always @* begin if (\initial ) begin end - \fus_src3_i$88 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) - casez (dp_FAST_fast1_spr0_2) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ - 1'h1: - \fus_src3_i$88 = fast_src1__data_o; - endcase - end - always @* begin - if (\initial ) begin end - fus_oper_i_alu_alu0__insn_type = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_alu0__rc__rc = 1'h0; + fus_oper_i_alu_alu0__rc__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - fus_oper_i_alu_alu0__insn_type = dec_ALU_ALU__insn_type; + { fus_oper_i_alu_alu0__rc__ok, fus_oper_i_alu_alu0__rc__rc } = { dec_ALU_ALU__rc__ok, dec_ALU_ALU__rc__rc }; endcase endcase endcase end + always @* begin + if (\initial ) begin end + \fus_src3_i$88 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) + casez (dp_FAST_fast1_spr0_2) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ + 1'h1: + \fus_src3_i$88 = fast_src1__data_o; + endcase + end always @* begin if (\initial ) begin end \dp_FAST_fast1_branch0_3$next = rp_FAST_fast1_branch0_3; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_FAST_fast1_branch0_3$next = 1'h0; @@ -46175,9 +51460,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src2_i$89 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_FAST_fast1_branch0_3) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: \fus_src2_i$89 = fast_src1__data_o; endcase @@ -46185,7 +51470,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_FAST_fast1_trap0_4$next = rp_FAST_fast1_trap0_4; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dp_FAST_fast1_trap0_4$next = 1'h0; @@ -46194,338 +51479,211 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \fus_src4_i$90 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) casez (dp_FAST_fast1_trap0_4) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: \fus_src4_i$90 = fast_src1__data_o; endcase end always @* begin if (\initial ) begin end - fus_oper_i_alu_alu0__fn_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) - casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ - 1'h1: - (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) - casez (core_core_insn_type) - /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ - 7'h05: - /* empty */; - /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ - 7'h01: - /* empty */; - /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ - default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ - 1'h1: - fus_oper_i_alu_alu0__fn_unit = dec_ALU_ALU__fn_unit; - endcase - endcase - endcase - end - always @* begin - if (\initial ) begin end - \dp_SPR_spr1_spr0_0$next = rp_SPR_spr1_spr0_0; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \dp_FAST_fast1_trap0_5$next = rp_FAST_fast1_trap0_5; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \dp_SPR_spr1_spr0_0$next = 1'h0; + \dp_FAST_fast1_trap0_5$next = 1'h0; endcase end always @* begin if (\initial ) begin end - \fus_src2_i$91 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *) - casez (dp_SPR_spr1_spr0_0) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */ + \fus_src5_i$91 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) + casez (dp_FAST_fast1_trap0_5) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: - \fus_src2_i$91 = spr_spr1__data_o; + \fus_src5_i$91 = fast_src1__data_o; endcase end always @* begin if (\initial ) begin end - fus_oper_i_alu_alu0__imm_data__data = 64'h0000000000000000; - fus_oper_i_alu_alu0__imm_data__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_alu0__oe__oe = 1'h0; + fus_oper_i_alu_alu0__oe__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - { fus_oper_i_alu_alu0__imm_data__ok, fus_oper_i_alu_alu0__imm_data__data } = { dec_ALU_ALU__imm_data__ok, dec_ALU_ALU__imm_data__data }; + { fus_oper_i_alu_alu0__oe__ok, fus_oper_i_alu_alu0__oe__oe } = { dec_ALU_ALU__oe__ok, dec_ALU_ALU__oe__oe }; endcase endcase endcase end always @* begin if (\initial ) begin end - \wr_pick_dly$next = wr_pick; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) - casez (coresync_rst) - 1'h1: - \wr_pick_dly$next = 1'h0; - endcase - end - always @* begin - if (\initial ) begin end - \wr_pick_dly$989$next = \wr_pick$986 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) - casez (coresync_rst) - 1'h1: - \wr_pick_dly$989$next = 1'h0; - endcase - end - always @* begin - if (\initial ) begin end - \wr_pick_dly$1008$next = \wr_pick$1005 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \dp_SPR_spr1_spr0_0$next = rp_SPR_spr1_spr0_0; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \wr_pick_dly$1008$next = 1'h0; - endcase - end - always @* begin - if (\initial ) begin end - fus_oper_i_alu_alu0__rc__rc = 1'h0; - fus_oper_i_alu_alu0__rc__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) - casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ - 1'h1: - (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) - casez (core_core_insn_type) - /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ - 7'h05: - /* empty */; - /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ - 7'h01: - /* empty */; - /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ - default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ - 1'h1: - { fus_oper_i_alu_alu0__rc__ok, fus_oper_i_alu_alu0__rc__rc } = { dec_ALU_ALU__rc__ok, dec_ALU_ALU__rc__rc }; - endcase - endcase + \dp_SPR_spr1_spr0_0$next = 1'h0; endcase end always @* begin if (\initial ) begin end - \wr_pick_dly$1029$next = \wr_pick$1026 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) - casez (coresync_rst) + \fus_src2_i$92 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" *) + casez (dp_SPR_spr1_spr0_0) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327" */ 1'h1: - \wr_pick_dly$1029$next = 1'h0; + \fus_src2_i$92 = spr_spr1__data_o; endcase end always @* begin if (\initial ) begin end - \wr_pick_dly$1047$next = \wr_pick$1044 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \wr_pick_dly$next = wr_pick; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \wr_pick_dly$1047$next = 1'h0; + \wr_pick_dly$next = 1'h0; endcase end always @* begin if (\initial ) begin end - \wr_pick_dly$1069$next = \wr_pick$1066 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \wr_pick_dly$1009$next = \wr_pick$1006 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \wr_pick_dly$1069$next = 1'h0; + \wr_pick_dly$1009$next = 1'h0; endcase end always @* begin if (\initial ) begin end - fus_oper_i_alu_alu0__oe__oe = 1'h0; - fus_oper_i_alu_alu0__oe__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_alu0__invert_in = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - { fus_oper_i_alu_alu0__oe__ok, fus_oper_i_alu_alu0__oe__oe } = { dec_ALU_ALU__oe__ok, dec_ALU_ALU__oe__oe }; + fus_oper_i_alu_alu0__invert_in = dec_ALU_ALU__invert_in; endcase endcase endcase end always @* begin if (\initial ) begin end - \wr_pick_dly$1089$next = \wr_pick$1086 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) - casez (coresync_rst) - 1'h1: - \wr_pick_dly$1089$next = 1'h0; - endcase - end - always @* begin - if (\initial ) begin end - \wr_pick_dly$1109$next = \wr_pick$1106 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) - casez (coresync_rst) - 1'h1: - \wr_pick_dly$1109$next = 1'h0; - endcase - end - always @* begin - if (\initial ) begin end - \wr_pick_dly$1128$next = \wr_pick$1125 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \wr_pick_dly$1028$next = \wr_pick$1025 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \wr_pick_dly$1128$next = 1'h0; + \wr_pick_dly$1028$next = 1'h0; endcase end always @* begin if (\initial ) begin end - fus_oper_i_alu_alu0__invert_in = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_alu0__zero_a = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - fus_oper_i_alu_alu0__invert_in = dec_ALU_ALU__invert_in; + fus_oper_i_alu_alu0__zero_a = dec_ALU_ALU__zero_a; endcase endcase endcase end always @* begin if (\initial ) begin end - \wr_pick_dly$1146$next = \wr_pick$1143 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \wr_pick_dly$1051$next = \wr_pick$1048 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \wr_pick_dly$1146$next = 1'h0; - endcase - end - always @* begin - if (\initial ) begin end - fus_oper_i_alu_alu0__zero_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) - casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ - 1'h1: - (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) - casez (core_core_insn_type) - /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ - 7'h05: - /* empty */; - /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ - 7'h01: - /* empty */; - /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ - default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ - 1'h1: - fus_oper_i_alu_alu0__zero_a = dec_ALU_ALU__zero_a; - endcase - endcase + \wr_pick_dly$1051$next = 1'h0; endcase end always @* begin if (\initial ) begin end - \wr_pick_dly$1220$next = \wr_pick$1217 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \wr_pick_dly$1069$next = \wr_pick$1066 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \wr_pick_dly$1220$next = 1'h0; + \wr_pick_dly$1069$next = 1'h0; endcase end always @* begin if (\initial ) begin end fus_oper_i_alu_alu0__invert_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_alu0__invert_out = dec_ALU_ALU__invert_out; endcase @@ -46534,37 +51692,37 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c end always @* begin if (\initial ) begin end - \wr_pick_dly$1248$next = \wr_pick$1245 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \wr_pick_dly$1091$next = \wr_pick$1088 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \wr_pick_dly$1248$next = 1'h0; + \wr_pick_dly$1091$next = 1'h0; endcase end always @* begin if (\initial ) begin end fus_oper_i_alu_alu0__write_cr0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_alu0__write_cr0 = dec_ALU_ALU__write_cr0; endcase @@ -46573,46 +51731,37 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c end always @* begin if (\initial ) begin end - \wr_pick_dly$1268$next = \wr_pick$1265 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) - casez (coresync_rst) - 1'h1: - \wr_pick_dly$1268$next = 1'h0; - endcase - end - always @* begin - if (\initial ) begin end - \wr_pick_dly$1288$next = \wr_pick$1285 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \wr_pick_dly$1111$next = \wr_pick$1108 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \wr_pick_dly$1288$next = 1'h0; + \wr_pick_dly$1111$next = 1'h0; endcase end always @* begin if (\initial ) begin end fus_oper_i_alu_alu0__input_carry = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_alu0__input_carry = dec_ALU_ALU__input_carry; endcase @@ -46621,46 +51770,46 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c end always @* begin if (\initial ) begin end - \wr_pick_dly$1308$next = \wr_pick$1305 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \wr_pick_dly$1131$next = \wr_pick$1128 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \wr_pick_dly$1308$next = 1'h0; + \wr_pick_dly$1131$next = 1'h0; endcase end always @* begin if (\initial ) begin end - \wr_pick_dly$1328$next = \wr_pick$1325 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \wr_pick_dly$1150$next = \wr_pick$1147 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \wr_pick_dly$1328$next = 1'h0; + \wr_pick_dly$1150$next = 1'h0; endcase end always @* begin if (\initial ) begin end fus_oper_i_alu_alu0__output_carry = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_alu0__output_carry = dec_ALU_ALU__output_carry; endcase @@ -46669,37 +51818,37 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c end always @* begin if (\initial ) begin end - \wr_pick_dly$1348$next = \wr_pick$1345 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \wr_pick_dly$1168$next = \wr_pick$1165 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \wr_pick_dly$1348$next = 1'h0; + \wr_pick_dly$1168$next = 1'h0; endcase end always @* begin if (\initial ) begin end fus_oper_i_alu_alu0__is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_alu0__is_32bit = dec_ALU_ALU__is_32bit; endcase @@ -46708,37 +51857,37 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c end always @* begin if (\initial ) begin end - \wr_pick_dly$1395$next = \wr_pick$1392 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \wr_pick_dly$1242$next = \wr_pick$1239 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \wr_pick_dly$1395$next = 1'h0; + \wr_pick_dly$1242$next = 1'h0; endcase end always @* begin if (\initial ) begin end fus_oper_i_alu_alu0__is_signed = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_alu0__is_signed = dec_ALU_ALU__is_signed; endcase @@ -46747,46 +51896,46 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c end always @* begin if (\initial ) begin end - \wr_pick_dly$1411$next = \wr_pick$1408 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \wr_pick_dly$1270$next = \wr_pick$1267 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \wr_pick_dly$1411$next = 1'h0; + \wr_pick_dly$1270$next = 1'h0; endcase end always @* begin if (\initial ) begin end - \wr_pick_dly$1427$next = \wr_pick$1424 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \wr_pick_dly$1290$next = \wr_pick$1287 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \wr_pick_dly$1427$next = 1'h0; + \wr_pick_dly$1290$next = 1'h0; endcase end always @* begin if (\initial ) begin end fus_oper_i_alu_alu0__data_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_alu0__data_len = dec_ALU_ALU__data_len; endcase @@ -46795,37 +51944,37 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c end always @* begin if (\initial ) begin end - \wr_pick_dly$1461$next = \wr_pick$1458 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \wr_pick_dly$1310$next = \wr_pick$1307 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \wr_pick_dly$1461$next = 1'h0; + \wr_pick_dly$1310$next = 1'h0; endcase end always @* begin if (\initial ) begin end fus_oper_i_alu_alu0__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: fus_oper_i_alu_alu0__insn = dec_ALU_ALU__insn; endcase @@ -46834,1751 +51983,1978 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c end always @* begin if (\initial ) begin end - \wr_pick_dly$1477$next = \wr_pick$1474 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \wr_pick_dly$1330$next = \wr_pick$1327 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \wr_pick_dly$1477$next = 1'h0; + \wr_pick_dly$1330$next = 1'h0; endcase end always @* begin if (\initial ) begin end - \wr_pick_dly$1493$next = \wr_pick$1490 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \wr_pick_dly$1350$next = \wr_pick$1347 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \wr_pick_dly$1493$next = 1'h0; + \wr_pick_dly$1350$next = 1'h0; endcase end always @* begin if (\initial ) begin end - fus_cu_issue_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_alu0__sv_pred_sz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - fus_cu_issue_i = issue_i; + fus_oper_i_alu_alu0__sv_pred_sz = ALU__sv_pred_sz; endcase endcase endcase end always @* begin if (\initial ) begin end - \wr_pick_dly$1509$next = \wr_pick$1506 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \wr_pick_dly$1370$next = \wr_pick$1367 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \wr_pick_dly$1509$next = 1'h0; + \wr_pick_dly$1370$next = 1'h0; endcase end always @* begin if (\initial ) begin end - fus_cu_rdmaskn_i = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_alu0__sv_pred_dz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - fus_cu_rdmaskn_i = \$228 ; + fus_oper_i_alu_alu0__sv_pred_dz = ALU__sv_pred_dz; endcase endcase endcase end always @* begin if (\initial ) begin end - \wr_pick_dly$1545$next = \wr_pick$1542 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \wr_pick_dly$1417$next = \wr_pick$1414 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \wr_pick_dly$1545$next = 1'h0; + \wr_pick_dly$1417$next = 1'h0; endcase end always @* begin if (\initial ) begin end - \wr_pick_dly$1561$next = \wr_pick$1558 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \wr_pick_dly$1433$next = \wr_pick$1430 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \wr_pick_dly$1561$next = 1'h0; + \wr_pick_dly$1433$next = 1'h0; endcase end always @* begin if (\initial ) begin end - fus_oper_i_alu_cr0__insn_type = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_alu0__sv_saturate = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[1]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[0]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - fus_oper_i_alu_cr0__insn_type = dec_CR_CR__insn_type; + fus_oper_i_alu_alu0__sv_saturate = ALU__sv_saturate; endcase endcase endcase end always @* begin if (\initial ) begin end - \wr_pick_dly$1577$next = \wr_pick$1574 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \wr_pick_dly$1449$next = \wr_pick$1446 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \wr_pick_dly$1577$next = 1'h0; + \wr_pick_dly$1449$next = 1'h0; endcase end always @* begin if (\initial ) begin end - fus_oper_i_alu_cr0__fn_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_alu0__SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[1]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[0]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - fus_oper_i_alu_cr0__fn_unit = dec_CR_CR__fn_unit; + fus_oper_i_alu_alu0__SV_Ptype = ALU__SV_Ptype; endcase endcase endcase end always @* begin if (\initial ) begin end - \wr_pick_dly$1593$next = \wr_pick$1590 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \wr_pick_dly$1483$next = \wr_pick$1480 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \wr_pick_dly$1593$next = 1'h0; + \wr_pick_dly$1483$next = 1'h0; endcase end always @* begin if (\initial ) begin end - \wr_pick_dly$1635$next = \wr_pick$1632 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \wr_pick_dly$1499$next = \wr_pick$1496 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \wr_pick_dly$1635$next = 1'h0; + \wr_pick_dly$1499$next = 1'h0; endcase end always @* begin if (\initial ) begin end - fus_oper_i_alu_cr0__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_cu_issue_i = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[0]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_cu_issue_i = issue_i; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1515$next = \wr_pick$1512 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1515$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_cu_rdmaskn_i = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[0]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + fus_cu_rdmaskn_i = \$232 ; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1531$next = \wr_pick$1528 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1531$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_cr0__insn_type = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[1]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - fus_oper_i_alu_cr0__insn = dec_CR_CR__insn; + fus_oper_i_alu_cr0__insn_type = dec_CR_CR__insn_type; endcase endcase endcase end always @* begin if (\initial ) begin end - \wr_pick_dly$1654$next = \wr_pick$1651 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \wr_pick_dly$1567$next = \wr_pick$1564 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \wr_pick_dly$1654$next = 1'h0; + \wr_pick_dly$1567$next = 1'h0; endcase end always @* begin if (\initial ) begin end - \fus_cu_issue_i$13 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + \wr_pick_dly$1583$next = \wr_pick$1580 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1583$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_cr0__fn_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[1]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - \fus_cu_issue_i$13 = issue_i; + fus_oper_i_alu_cr0__fn_unit = dec_CR_CR__fn_unit; endcase endcase endcase end always @* begin if (\initial ) begin end - \wr_pick_dly$1670$next = \wr_pick$1667 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \wr_pick_dly$1599$next = \wr_pick$1596 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \wr_pick_dly$1670$next = 1'h0; + \wr_pick_dly$1599$next = 1'h0; endcase end always @* begin if (\initial ) begin end - \wr_pick_dly$1686$next = \wr_pick$1683 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \wr_pick_dly$1615$next = \wr_pick$1612 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \wr_pick_dly$1686$next = 1'h0; + \wr_pick_dly$1615$next = 1'h0; endcase end always @* begin if (\initial ) begin end - \fus_cu_rdmaskn_i$15 = 6'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_cr0__insn = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[1]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - \fus_cu_rdmaskn_i$15 = \$250 ; + fus_oper_i_alu_cr0__insn = dec_CR_CR__insn; endcase endcase endcase end always @* begin if (\initial ) begin end - \wr_pick_dly$1702$next = \wr_pick$1699 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \wr_pick_dly$1659$next = \wr_pick$1656 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \wr_pick_dly$1702$next = 1'h0; + \wr_pick_dly$1659$next = 1'h0; endcase end always @* begin if (\initial ) begin end - fus_oper_i_alu_branch0__cia = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_cr0__sv_pred_sz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[2]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[1]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - fus_oper_i_alu_branch0__cia = dec_BRANCH_BRANCH__cia; + fus_oper_i_alu_cr0__sv_pred_sz = CR__sv_pred_sz; endcase endcase endcase end always @* begin if (\initial ) begin end - \wr_pick_dly$1746$next = \wr_pick$1743 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \wr_pick_dly$1678$next = \wr_pick$1675 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \wr_pick_dly$1746$next = 1'h0; + \wr_pick_dly$1678$next = 1'h0; endcase end always @* begin if (\initial ) begin end - fus_oper_i_alu_branch0__insn_type = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_cr0__sv_pred_dz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[2]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[1]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - fus_oper_i_alu_branch0__insn_type = dec_BRANCH_BRANCH__insn_type; + fus_oper_i_alu_cr0__sv_pred_dz = CR__sv_pred_dz; endcase endcase endcase end always @* begin if (\initial ) begin end - \wr_pick_dly$1762$next = \wr_pick$1759 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \wr_pick_dly$1694$next = \wr_pick$1691 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \wr_pick_dly$1762$next = 1'h0; + \wr_pick_dly$1694$next = 1'h0; endcase end always @* begin if (\initial ) begin end - \wr_pick_dly$1786$next = \wr_pick$1783 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \wr_pick_dly$1710$next = \wr_pick$1707 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \wr_pick_dly$1786$next = 1'h0; + \wr_pick_dly$1710$next = 1'h0; endcase end always @* begin if (\initial ) begin end - fus_oper_i_alu_branch0__fn_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_cr0__sv_saturate = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[2]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[1]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - fus_oper_i_alu_branch0__fn_unit = dec_BRANCH_BRANCH__fn_unit; + fus_oper_i_alu_cr0__sv_saturate = CR__sv_saturate; endcase endcase endcase end always @* begin if (\initial ) begin end - \wr_pick_dly$1806$next = \wr_pick$1803 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \wr_pick_dly$1726$next = \wr_pick$1723 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \wr_pick_dly$1806$next = 1'h0; + \wr_pick_dly$1726$next = 1'h0; endcase end always @* begin if (\initial ) begin end - fus_oper_i_alu_branch0__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + \wr_pick_dly$1742$next = \wr_pick$1739 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1742$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_cr0__SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[2]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[1]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - fus_oper_i_alu_branch0__insn = dec_BRANCH_BRANCH__insn; + fus_oper_i_alu_cr0__SV_Ptype = CR__SV_Ptype; endcase endcase endcase end always @* begin if (\initial ) begin end - fus_oper_i_alu_branch0__imm_data__data = 64'h0000000000000000; - fus_oper_i_alu_branch0__imm_data__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + \wr_pick_dly$1794$next = \wr_pick$1791 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1794$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_cu_issue_i$13 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[2]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[1]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - { fus_oper_i_alu_branch0__imm_data__ok, fus_oper_i_alu_branch0__imm_data__data } = { dec_BRANCH_BRANCH__imm_data__ok, dec_BRANCH_BRANCH__imm_data__data }; + \fus_cu_issue_i$13 = issue_i; endcase endcase endcase end always @* begin if (\initial ) begin end - fus_oper_i_alu_branch0__lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + \wr_pick_dly$1810$next = \wr_pick$1807 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1810$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fus_cu_rdmaskn_i$15 = 6'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + casez (ivalid_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) + casez (core_core_insn_type) + /* \nmigen.decoding = "OP_ATTN/5" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ + 7'h05: + /* empty */; + /* \nmigen.decoding = "OP_NOP/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ + 7'h01: + /* empty */; + /* \nmigen.decoding = {0{1'b0}} */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ + default: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[1]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ + 1'h1: + \fus_cu_rdmaskn_i$15 = \$254 ; + endcase + endcase + endcase + end + always @* begin + if (\initial ) begin end + \wr_pick_dly$1834$next = \wr_pick$1831 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1834$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_branch0__cia = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[2]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - fus_oper_i_alu_branch0__lk = dec_BRANCH_BRANCH__lk; + fus_oper_i_alu_branch0__cia = dec_BRANCH_BRANCH__cia; endcase endcase endcase end always @* begin if (\initial ) begin end - fus_oper_i_alu_branch0__is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + \wr_pick_dly$1854$next = \wr_pick$1851 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1854$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_branch0__insn_type = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[2]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - fus_oper_i_alu_branch0__is_32bit = dec_BRANCH_BRANCH__is_32bit; + fus_oper_i_alu_branch0__insn_type = dec_BRANCH_BRANCH__insn_type; endcase endcase endcase end always @* begin if (\initial ) begin end - \fus_cu_issue_i$16 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + \wr_pick_dly$1874$next = \wr_pick$1871 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + casez (coresync_rst) + 1'h1: + \wr_pick_dly$1874$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + fus_oper_i_alu_branch0__fn_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[2]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - \fus_cu_issue_i$16 = issue_i; + fus_oper_i_alu_branch0__fn_unit = dec_BRANCH_BRANCH__fn_unit; endcase endcase endcase end always @* begin if (\initial ) begin end - \fus_cu_rdmaskn_i$18 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_branch0__insn = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[2]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - \fus_cu_rdmaskn_i$18 = \$252 ; + fus_oper_i_alu_branch0__insn = dec_BRANCH_BRANCH__insn; endcase endcase endcase end always @* begin if (\initial ) begin end - fus_oper_i_alu_trap0__insn_type = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_branch0__imm_data__data = 64'h0000000000000000; + fus_oper_i_alu_branch0__imm_data__ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[3]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[2]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - fus_oper_i_alu_trap0__insn_type = core_core_insn_type; + { fus_oper_i_alu_branch0__imm_data__ok, fus_oper_i_alu_branch0__imm_data__data } = { dec_BRANCH_BRANCH__imm_data__ok, dec_BRANCH_BRANCH__imm_data__data }; endcase endcase endcase end always @* begin if (\initial ) begin end - fus_oper_i_alu_trap0__fn_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_branch0__lk = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[3]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[2]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - fus_oper_i_alu_trap0__fn_unit = core_core_fn_unit; + fus_oper_i_alu_branch0__lk = dec_BRANCH_BRANCH__lk; endcase endcase endcase end always @* begin if (\initial ) begin end - fus_oper_i_alu_trap0__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_branch0__is_32bit = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[3]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[2]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - fus_oper_i_alu_trap0__insn = core_core_insn; + fus_oper_i_alu_branch0__is_32bit = dec_BRANCH_BRANCH__is_32bit; endcase endcase endcase end always @* begin if (\initial ) begin end - fus_oper_i_alu_trap0__msr = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_branch0__sv_pred_sz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[3]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[2]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - fus_oper_i_alu_trap0__msr = core_core_msr; + fus_oper_i_alu_branch0__sv_pred_sz = BRANCH__sv_pred_sz; endcase endcase endcase end always @* begin if (\initial ) begin end - fus_oper_i_alu_trap0__cia = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_branch0__sv_pred_dz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[3]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[2]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - fus_oper_i_alu_trap0__cia = core_core_cia; + fus_oper_i_alu_branch0__sv_pred_dz = BRANCH__sv_pred_dz; endcase endcase endcase end always @* begin if (\initial ) begin end - fus_oper_i_alu_trap0__is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_branch0__sv_saturate = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[3]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[2]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - fus_oper_i_alu_trap0__is_32bit = core_core_is_32bit; + fus_oper_i_alu_branch0__sv_saturate = BRANCH__sv_saturate; endcase endcase endcase end always @* begin if (\initial ) begin end - fus_oper_i_alu_trap0__traptype = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_branch0__SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[3]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[2]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - fus_oper_i_alu_trap0__traptype = core_core_traptype; + fus_oper_i_alu_branch0__SV_Ptype = BRANCH__SV_Ptype; endcase endcase endcase end always @* begin if (\initial ) begin end - fus_oper_i_alu_trap0__trapaddr = 13'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + \fus_cu_issue_i$16 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[3]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[2]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - fus_oper_i_alu_trap0__trapaddr = core_core_trapaddr; + \fus_cu_issue_i$16 = issue_i; endcase endcase endcase end always @* begin if (\initial ) begin end - fus_oper_i_alu_trap0__ldst_exc = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + \fus_cu_rdmaskn_i$18 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[3]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[2]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - fus_oper_i_alu_trap0__ldst_exc = { \core_core_exc_$signal$9 , \core_core_exc_$signal$8 , \core_core_exc_$signal$7 , \core_core_exc_$signal$6 , \core_core_exc_$signal$5 , \core_core_exc_$signal$4 , \core_core_exc_$signal$3 , \core_core_exc_$signal }; + \fus_cu_rdmaskn_i$18 = \$256 ; endcase endcase endcase end always @* begin if (\initial ) begin end - \fus_cu_issue_i$19 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_trap0__insn_type = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[3]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - \fus_cu_issue_i$19 = issue_i; + fus_oper_i_alu_trap0__insn_type = core_core_insn_type; endcase endcase endcase end always @* begin if (\initial ) begin end - \fus_cu_rdmaskn_i$21 = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_trap0__fn_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) casez (fu_enable[3]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - \fus_cu_rdmaskn_i$21 = \$254 ; + fus_oper_i_alu_trap0__fn_unit = core_core_fn_unit; endcase endcase endcase end always @* begin if (\initial ) begin end - fus_oper_i_alu_logical0__insn_type = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_trap0__insn = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[3]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - fus_oper_i_alu_logical0__insn_type = dec_LOGICAL_LOGICAL__insn_type; + fus_oper_i_alu_trap0__insn = core_core_insn; endcase endcase endcase end always @* begin if (\initial ) begin end - fus_oper_i_alu_logical0__fn_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_trap0__msr = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[3]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - fus_oper_i_alu_logical0__fn_unit = dec_LOGICAL_LOGICAL__fn_unit; + fus_oper_i_alu_trap0__msr = core_core_msr; endcase endcase endcase end always @* begin if (\initial ) begin end - fus_oper_i_alu_logical0__imm_data__data = 64'h0000000000000000; - fus_oper_i_alu_logical0__imm_data__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_trap0__cia = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[3]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - { fus_oper_i_alu_logical0__imm_data__ok, fus_oper_i_alu_logical0__imm_data__data } = { dec_LOGICAL_LOGICAL__imm_data__ok, dec_LOGICAL_LOGICAL__imm_data__data }; + fus_oper_i_alu_trap0__cia = core_core_cia; endcase endcase endcase end always @* begin if (\initial ) begin end - fus_oper_i_alu_logical0__rc__rc = 1'h0; - fus_oper_i_alu_logical0__rc__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_trap0__svstate = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[3]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - { fus_oper_i_alu_logical0__rc__ok, fus_oper_i_alu_logical0__rc__rc } = { dec_LOGICAL_LOGICAL__rc__ok, dec_LOGICAL_LOGICAL__rc__rc }; + fus_oper_i_alu_trap0__svstate = core_core_svstate; endcase endcase endcase end always @* begin if (\initial ) begin end - fus_oper_i_alu_logical0__oe__oe = 1'h0; - fus_oper_i_alu_logical0__oe__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_trap0__is_32bit = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[3]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - { fus_oper_i_alu_logical0__oe__ok, fus_oper_i_alu_logical0__oe__oe } = { dec_LOGICAL_LOGICAL__oe__ok, dec_LOGICAL_LOGICAL__oe__oe }; + fus_oper_i_alu_trap0__is_32bit = core_core_is_32bit; endcase endcase endcase end always @* begin if (\initial ) begin end - fus_oper_i_alu_logical0__invert_in = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_trap0__traptype = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[3]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - fus_oper_i_alu_logical0__invert_in = dec_LOGICAL_LOGICAL__invert_in; + fus_oper_i_alu_trap0__traptype = core_core_traptype; endcase endcase endcase end always @* begin if (\initial ) begin end - fus_oper_i_alu_logical0__zero_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_trap0__trapaddr = 13'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[3]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - fus_oper_i_alu_logical0__zero_a = dec_LOGICAL_LOGICAL__zero_a; + fus_oper_i_alu_trap0__trapaddr = core_core_trapaddr; endcase endcase endcase end always @* begin if (\initial ) begin end - fus_oper_i_alu_logical0__input_carry = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_trap0__ldst_exc = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[3]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - fus_oper_i_alu_logical0__input_carry = dec_LOGICAL_LOGICAL__input_carry; + fus_oper_i_alu_trap0__ldst_exc = { \core_core_exc_$signal$9 , \core_core_exc_$signal$8 , \core_core_exc_$signal$7 , \core_core_exc_$signal$6 , \core_core_exc_$signal$5 , \core_core_exc_$signal$4 , \core_core_exc_$signal$3 , \core_core_exc_$signal }; endcase endcase endcase end always @* begin if (\initial ) begin end - fus_oper_i_alu_logical0__invert_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_trap0__sv_pred_sz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[3]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - fus_oper_i_alu_logical0__invert_out = dec_LOGICAL_LOGICAL__invert_out; + fus_oper_i_alu_trap0__sv_pred_sz = core_core__sv_pred_sz; endcase endcase endcase end always @* begin if (\initial ) begin end - fus_oper_i_alu_logical0__write_cr0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *) + fus_oper_i_alu_trap0__sv_pred_dz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) casez (ivalid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" */ 7'h05: /* empty */; /* \nmigen.decoding = "OP_NOP/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" */ 7'h01: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *) - casez (fu_enable[4]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" *) + casez (fu_enable[3]) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" */ 1'h1: - fus_oper_i_alu_logical0__write_cr0 = dec_LOGICAL_LOGICAL__write_cr0; + fus_oper_i_alu_trap0__sv_pred_dz = core_core__sv_pred_dz; endcase endcase endcase end - assign \$223 = \$224 ; - assign \$580 = \$615 ; - assign \$829 = \$830 ; - assign \$1157 = \$1174 ; - assign \$1176 = \$1193 ; - assign \$1373 = \$1382 ; + assign \$227 = \$228 ; + assign \$584 = \$619 ; + assign \$833 = \$834 ; + assign \$1179 = \$1196 ; + assign \$1198 = \$1215 ; + assign \$1395 = \$1404 ; + assign sv_a_nz = 1'h0; + assign ALU__sv_pred_sz = 1'h0; + assign ALU__sv_pred_dz = 1'h0; + assign ALU__sv_saturate = 2'h0; + assign ALU__SV_Ptype = 2'h0; + assign CR__sv_pred_sz = 1'h0; + assign CR__sv_pred_dz = 1'h0; + assign CR__sv_saturate = 2'h0; + assign CR__SV_Ptype = 2'h0; + assign BRANCH__sv_pred_sz = 1'h0; + assign BRANCH__sv_pred_dz = 1'h0; + assign BRANCH__sv_saturate = 2'h0; + assign BRANCH__SV_Ptype = 2'h0; + assign LOGICAL__sv_pred_sz = 1'h0; + assign LOGICAL__sv_pred_dz = 1'h0; + assign LOGICAL__sv_saturate = 2'h0; + assign LOGICAL__SV_Ptype = 2'h0; + assign SPR__sv_pred_sz = 1'h0; + assign SPR__sv_pred_dz = 1'h0; + assign SPR__sv_saturate = 2'h0; + assign SPR__SV_Ptype = 2'h0; + assign DIV__sv_pred_sz = 1'h0; + assign DIV__sv_pred_dz = 1'h0; + assign DIV__sv_saturate = 2'h0; + assign DIV__SV_Ptype = 2'h0; + assign MUL__sv_pred_sz = 1'h0; + assign MUL__sv_pred_dz = 1'h0; + assign MUL__sv_saturate = 2'h0; + assign MUL__SV_Ptype = 2'h0; + assign SHIFT_ROT__sv_pred_sz = 1'h0; + assign SHIFT_ROT__sv_pred_dz = 1'h0; + assign SHIFT_ROT__sv_saturate = 2'h0; + assign SHIFT_ROT__SV_Ptype = 2'h0; + assign LDST__sv_pred_sz = 1'h0; + assign LDST__sv_pred_dz = 1'h0; + assign LDST__sv_saturate = 2'h0; + assign LDST__SV_Ptype = 2'h0; assign o_ok = 1'h0; assign ea_ok = 1'h0; - assign spr_spr1__wen = \wp$1811 ; - assign \spr_spr1__addr$175 = \addr_en$1814 [3:0]; - assign spr_spr1__data_i = \fus_dest2_o$162 ; - assign \addr_en$1814 = \$1815 ; - assign \wp$1811 = \$1812 ; - assign \wr_pick_rise$1057 = \$1809 ; - assign \wr_pick$1803 = \$1804 ; - assign wrpick_SPR_spr1_i = \$1801 ; - assign wrflag_spr0_spr1_1 = \$1799 ; - assign state_wen = \$1797 ; - assign \state_data_i$174 = \fus_dest5_o$161 ; - assign \addr_en$1794 = \$1795 ; - assign \wp$1791 = \$1792 ; - assign \wr_pick_rise$1017 = \$1789 ; - assign \wr_pick$1783 = \$1784 ; - assign wrpick_STATE_msr_i = \$1781 ; - assign wrflag_trap0_msr_4 = \$1779 ; - assign state_nia_wen = \$1775 ; - assign state_data_i = \$1773 ; - assign \addr_en$1770 = \$1771 ; - assign \wp$1767 = \$1768 ; - assign \wr_pick_rise$1016 = \$1765 ; - assign \wr_pick$1759 = \$1760 ; - assign wrflag_trap0_nia_3 = \$1757 ; - assign \addr_en$1754 = \$1755 ; - assign \wp$1751 = \$1752 ; - assign \wr_pick_rise$1642 = \$1749 ; - assign \wr_pick$1743 = \$1744 ; - assign wrpick_STATE_nia_i[1] = \$1741 ; - assign wrpick_STATE_nia_i[0] = \$1739 ; - assign wrflag_branch0_nia_2 = \$1737 ; - assign fast_dest1__wen = \$1735 ; - assign fast_dest1__addr = \$1727 ; - assign fast_dest1__data_i = \$1719 ; - assign \addr_en$1710 = \$1711 ; - assign \wp$1707 = \$1708 ; - assign \wr_pick_rise$1015 = \$1705 ; - assign \wr_pick$1699 = \$1700 ; - assign wrflag_trap0_fast1_2 = \$1697 ; - assign \addr_en$1694 = \$1695 ; - assign \wp$1691 = \$1692 ; - assign \wr_pick_rise$1641 = \$1689 ; - assign \wr_pick$1683 = \$1684 ; - assign wrflag_branch0_fast1_1 = \$1681 ; - assign \addr_en$1678 = \$1679 ; - assign \wp$1675 = \$1676 ; - assign \wr_pick_rise$1056 = \$1673 ; - assign \wr_pick$1667 = \$1668 ; - assign wrflag_spr0_fast1_2 = \$1665 ; - assign \addr_en$1662 = \$1663 ; - assign \wp$1659 = \$1660 ; - assign \wr_pick_rise$1014 = \$1657 ; - assign \wr_pick$1651 = \$1652 ; - assign wrflag_trap0_fast1_1 = \$1649 ; - assign \addr_en$1646 = \$1647 ; - assign \wp$1643 = \$1644 ; - assign \fus_cu_wr__go_i$149 [2] = \wr_pick_rise$1642 ; - assign \fus_cu_wr__go_i$149 [1] = \wr_pick_rise$1641 ; - assign \fus_cu_wr__go_i$149 [0] = \wr_pick_rise$1636 ; - assign \wr_pick_rise$1636 = \$1639 ; - assign \wr_pick$1632 = \$1633 ; - assign wrpick_FAST_fast1_i[4] = \$1630 ; - assign wrpick_FAST_fast1_i[3] = \$1628 ; - assign wrpick_FAST_fast1_i[2] = \$1626 ; - assign wrpick_FAST_fast1_i[1] = \$1624 ; - assign wrpick_FAST_fast1_i[0] = \$1622 ; - assign wrflag_branch0_fast1_0 = \$1620 ; - assign \xer_wen$173 = \$1612 ; - assign \xer_data_i$172 = \$1604 ; - assign \addr_en$1601 = \$1602 ; - assign \wp$1598 = \$1599 ; - assign \wr_pick_rise$1097 = \$1596 ; - assign \wr_pick$1590 = \$1591 ; - assign wrflag_mul0_xer_so_3 = \$1588 ; - assign \addr_en$1585 = \$1586 ; - assign \wp$1582 = \$1583 ; - assign \wr_pick_rise$1077 = \$1580 ; - assign \wr_pick$1574 = \$1575 ; - assign wrflag_div0_xer_so_3 = \$1572 ; - assign \addr_en$1569 = \$1570 ; - assign \wp$1566 = \$1567 ; - assign \wr_pick_rise$1055 = \$1564 ; - assign \wr_pick$1558 = \$1559 ; - assign wrflag_spr0_xer_so_3 = \$1556 ; - assign \addr_en$1553 = \$1554 ; - assign \wp$1550 = \$1551 ; - assign \wr_pick_rise$979 = \$1548 ; - assign \wr_pick$1542 = \$1543 ; - assign wrpick_XER_xer_so_i[3] = \$1540 ; - assign wrpick_XER_xer_so_i[2] = \$1538 ; - assign wrpick_XER_xer_so_i[1] = \$1536 ; - assign wrpick_XER_xer_so_i[0] = \$1534 ; - assign wrflag_alu0_xer_so_4 = \$1532 ; - assign \xer_wen$171 = \$1530 ; - assign \xer_data_i$170 = \$1524 ; - assign \addr_en$1517 = \$1518 ; - assign \wp$1514 = \$1515 ; - assign \wr_pick_rise$1096 = \$1512 ; - assign \wr_pick$1506 = \$1507 ; - assign wrflag_mul0_xer_ov_2 = \$1504 ; - assign \addr_en$1501 = \$1502 ; - assign \wp$1498 = \$1499 ; - assign \wr_pick_rise$1076 = \$1496 ; - assign \wr_pick$1490 = \$1491 ; - assign wrflag_div0_xer_ov_2 = \$1488 ; - assign \addr_en$1485 = \$1486 ; - assign \wp$1482 = \$1483 ; - assign \wr_pick_rise$1054 = \$1480 ; - assign \wr_pick$1474 = \$1475 ; - assign wrflag_spr0_xer_ov_4 = \$1472 ; - assign \addr_en$1469 = \$1470 ; - assign \wp$1466 = \$1467 ; - assign \wr_pick_rise$978 = \$1464 ; - assign \wr_pick$1458 = \$1459 ; - assign wrpick_XER_xer_ov_i[3] = \$1456 ; - assign wrpick_XER_xer_ov_i[2] = \$1454 ; - assign wrpick_XER_xer_ov_i[1] = \$1452 ; - assign wrpick_XER_xer_ov_i[0] = \$1450 ; - assign wrflag_alu0_xer_ov_3 = \$1448 ; - assign xer_wen = \$1442 ; - assign xer_data_i = \$1440 ; - assign \addr_en$1435 = \$1436 ; - assign \wp$1432 = \$1433 ; - assign \wr_pick_rise$1116 = \$1430 ; - assign \wr_pick$1424 = \$1425 ; - assign wrflag_shiftrot0_xer_ca_2 = \$1422 ; - assign \addr_en$1419 = \$1420 ; - assign \wp$1416 = \$1417 ; - assign \wr_pick_rise$1053 = \$1414 ; - assign \wr_pick$1408 = \$1409 ; - assign wrflag_spr0_xer_ca_5 = \$1406 ; - assign \addr_en$1403 = \$1404 ; - assign \wp$1400 = \$1401 ; - assign \wr_pick_rise$977 = \$1398 ; - assign \wr_pick$1392 = \$1393 ; - assign wrpick_XER_xer_ca_i[2] = \$1390 ; - assign wrpick_XER_xer_ca_i[1] = \$1388 ; - assign wrpick_XER_xer_ca_i[0] = \$1386 ; - assign wrflag_alu0_xer_ca_2 = \$1384 ; - assign cr_wen = \$1382 [7:0]; - assign cr_data_i = \$1371 ; - assign \addr_en$1356 = \$1361 ; - assign \wp$1353 = \$1354 ; - assign \wr_pick_rise$1115 = \$1351 ; - assign \wr_pick$1345 = \$1346 ; - assign wrflag_shiftrot0_cr_a_1 = \$1343 ; - assign \addr_en$1336 = \$1341 ; - assign \wp$1333 = \$1334 ; - assign \wr_pick_rise$1095 = \$1331 ; - assign \wr_pick$1325 = \$1326 ; - assign wrflag_mul0_cr_a_1 = \$1323 ; - assign \addr_en$1316 = \$1321 ; - assign \wp$1313 = \$1314 ; - assign \wr_pick_rise$1075 = \$1311 ; - assign \wr_pick$1305 = \$1306 ; - assign wrflag_div0_cr_a_1 = \$1303 ; - assign \addr_en$1296 = \$1301 ; - assign \wp$1293 = \$1294 ; - assign \wr_pick_rise$1035 = \$1291 ; - assign \wr_pick$1285 = \$1286 ; - assign wrflag_logical0_cr_a_1 = \$1283 ; - assign \addr_en$1276 = \$1281 ; - assign \wp$1273 = \$1274 ; - assign \wr_pick_rise$996 = \$1271 ; - assign \wr_pick$1265 = \$1266 ; - assign wrflag_cr0_cr_a_2 = \$1263 ; - assign \addr_en$1256 = \$1261 ; - assign \wp$1253 = \$1254 ; - assign \wr_pick_rise$976 = \$1251 ; - assign \wr_pick$1245 = \$1246 ; - assign wrpick_CR_cr_a_i[5] = \$1243 ; - assign wrpick_CR_cr_a_i[4] = \$1241 ; - assign wrpick_CR_cr_a_i[3] = \$1239 ; - assign wrpick_CR_cr_a_i[2] = \$1237 ; - assign wrpick_CR_cr_a_i[1] = \$1235 ; - assign wrpick_CR_cr_a_i[0] = \$1233 ; - assign wrflag_alu0_cr_a_1 = \$1231 ; - assign cr_full_wr__wen = \addr_en$1228 ; + assign spr_spr1__wen = \wp$1879 ; + assign \spr_spr1__addr$179 = \addr_en$1882 [3:0]; + assign spr_spr1__data_i = \fus_dest2_o$164 ; + assign \addr_en$1882 = \$1883 ; + assign \wp$1879 = \$1880 ; + assign \wr_pick_rise$1079 = \$1877 ; + assign \wr_pick$1871 = \$1872 ; + assign wrpick_SPR_spr1_i = \$1869 ; + assign wrflag_spr0_spr1_1 = \$1867 ; + assign \state_wen$178 = \addr_en$1862 ; + assign \state_data_i$177 = \$1865 ; + assign \addr_en$1862 = \$1863 ; + assign \wp$1859 = \$1860 ; + assign \wr_pick_rise$1039 = \$1857 ; + assign \wr_pick$1851 = \$1852 ; + assign wrpick_STATE_svstate_i = \$1849 ; + assign wrflag_trap0_svstate_6 = \$1847 ; + assign state_wen = \$1845 ; + assign \state_data_i$176 = \fus_dest6_o$163 ; + assign \addr_en$1842 = \$1843 ; + assign \wp$1839 = \$1840 ; + assign \wr_pick_rise$1038 = \$1837 ; + assign \wr_pick$1831 = \$1832 ; + assign wrpick_STATE_msr_i = \$1829 ; + assign wrflag_trap0_msr_5 = \$1827 ; + assign state_nia_wen = \$1823 ; + assign state_data_i = \$1821 ; + assign \addr_en$1818 = \$1819 ; + assign \wp$1815 = \$1816 ; + assign \wr_pick_rise$1037 = \$1813 ; + assign \wr_pick$1807 = \$1808 ; + assign wrflag_trap0_nia_4 = \$1805 ; + assign \addr_en$1802 = \$1803 ; + assign \wp$1799 = \$1800 ; + assign \wr_pick_rise$1666 = \$1797 ; + assign \wr_pick$1791 = \$1792 ; + assign wrpick_STATE_nia_i[1] = \$1789 ; + assign wrpick_STATE_nia_i[0] = \$1787 ; + assign wrflag_branch0_nia_2 = \$1785 ; + assign fast_dest1__wen = \$1783 ; + assign fast_dest1__addr = \$1763 ; + assign fast_dest1__data_i = \$1761 ; + assign \addr_en$1750 = \$1751 ; + assign \wp$1747 = \$1748 ; + assign \wr_pick_rise$1036 = \$1745 ; + assign \wr_pick$1739 = \$1740 ; + assign wrflag_trap0_fast1_3 = \$1737 ; + assign \addr_en$1734 = \$1735 ; + assign \wp$1731 = \$1732 ; + assign \wr_pick_rise$1035 = \$1729 ; + assign \wr_pick$1723 = \$1724 ; + assign wrflag_trap0_fast1_2 = \$1721 ; + assign \addr_en$1718 = \$1719 ; + assign \wp$1715 = \$1716 ; + assign \wr_pick_rise$1665 = \$1713 ; + assign \wr_pick$1707 = \$1708 ; + assign wrflag_branch0_fast1_1 = \$1705 ; + assign \addr_en$1702 = \$1703 ; + assign \wp$1699 = \$1700 ; + assign \wr_pick_rise$1078 = \$1697 ; + assign \wr_pick$1691 = \$1692 ; + assign wrflag_spr0_fast1_2 = \$1689 ; + assign \addr_en$1686 = \$1687 ; + assign \wp$1683 = \$1684 ; + assign \wr_pick_rise$1034 = \$1681 ; + assign \wr_pick$1675 = \$1676 ; + assign wrflag_trap0_fast1_1 = \$1673 ; + assign \addr_en$1670 = \$1671 ; + assign \wp$1667 = \$1668 ; + assign \fus_cu_wr__go_i$150 [2] = \wr_pick_rise$1666 ; + assign \fus_cu_wr__go_i$150 [1] = \wr_pick_rise$1665 ; + assign \fus_cu_wr__go_i$150 [0] = \wr_pick_rise$1660 ; + assign \wr_pick_rise$1660 = \$1663 ; + assign \wr_pick$1656 = \$1657 ; + assign wrpick_FAST_fast1_i[5] = \$1654 ; + assign wrpick_FAST_fast1_i[4] = \$1652 ; + assign wrpick_FAST_fast1_i[3] = \$1650 ; + assign wrpick_FAST_fast1_i[2] = \$1648 ; + assign wrpick_FAST_fast1_i[1] = \$1646 ; + assign wrpick_FAST_fast1_i[0] = \$1644 ; + assign wrflag_branch0_fast1_0 = \$1642 ; + assign \xer_wen$175 = \$1634 ; + assign \xer_data_i$174 = \$1626 ; + assign \addr_en$1623 = \$1624 ; + assign \wp$1620 = \$1621 ; + assign \wr_pick_rise$1119 = \$1618 ; + assign \wr_pick$1612 = \$1613 ; + assign wrflag_mul0_xer_so_3 = \$1610 ; + assign \addr_en$1607 = \$1608 ; + assign \wp$1604 = \$1605 ; + assign \wr_pick_rise$1099 = \$1602 ; + assign \wr_pick$1596 = \$1597 ; + assign wrflag_div0_xer_so_3 = \$1594 ; + assign \addr_en$1591 = \$1592 ; + assign \wp$1588 = \$1589 ; + assign \wr_pick_rise$1077 = \$1586 ; + assign \wr_pick$1580 = \$1581 ; + assign wrflag_spr0_xer_so_3 = \$1578 ; + assign \addr_en$1575 = \$1576 ; + assign \wp$1572 = \$1573 ; + assign \wr_pick_rise$999 = \$1570 ; + assign \wr_pick$1564 = \$1565 ; + assign wrpick_XER_xer_so_i[3] = \$1562 ; + assign wrpick_XER_xer_so_i[2] = \$1560 ; + assign wrpick_XER_xer_so_i[1] = \$1558 ; + assign wrpick_XER_xer_so_i[0] = \$1556 ; + assign wrflag_alu0_xer_so_4 = \$1554 ; + assign \xer_wen$173 = \$1552 ; + assign \xer_data_i$172 = \$1546 ; + assign \addr_en$1539 = \$1540 ; + assign \wp$1536 = \$1537 ; + assign \wr_pick_rise$1118 = \$1534 ; + assign \wr_pick$1528 = \$1529 ; + assign wrflag_mul0_xer_ov_2 = \$1526 ; + assign \addr_en$1523 = \$1524 ; + assign \wp$1520 = \$1521 ; + assign \wr_pick_rise$1098 = \$1518 ; + assign \wr_pick$1512 = \$1513 ; + assign wrflag_div0_xer_ov_2 = \$1510 ; + assign \addr_en$1507 = \$1508 ; + assign \wp$1504 = \$1505 ; + assign \wr_pick_rise$1076 = \$1502 ; + assign \wr_pick$1496 = \$1497 ; + assign wrflag_spr0_xer_ov_4 = \$1494 ; + assign \addr_en$1491 = \$1492 ; + assign \wp$1488 = \$1489 ; + assign \wr_pick_rise$998 = \$1486 ; + assign \wr_pick$1480 = \$1481 ; + assign wrpick_XER_xer_ov_i[3] = \$1478 ; + assign wrpick_XER_xer_ov_i[2] = \$1476 ; + assign wrpick_XER_xer_ov_i[1] = \$1474 ; + assign wrpick_XER_xer_ov_i[0] = \$1472 ; + assign wrflag_alu0_xer_ov_3 = \$1470 ; + assign xer_wen = \$1464 ; + assign xer_data_i = \$1462 ; + assign \addr_en$1457 = \$1458 ; + assign \wp$1454 = \$1455 ; + assign \wr_pick_rise$1138 = \$1452 ; + assign \wr_pick$1446 = \$1447 ; + assign wrflag_shiftrot0_xer_ca_2 = \$1444 ; + assign \addr_en$1441 = \$1442 ; + assign \wp$1438 = \$1439 ; + assign \wr_pick_rise$1075 = \$1436 ; + assign \wr_pick$1430 = \$1431 ; + assign wrflag_spr0_xer_ca_5 = \$1428 ; + assign \addr_en$1425 = \$1426 ; + assign \wp$1422 = \$1423 ; + assign \wr_pick_rise$997 = \$1420 ; + assign \wr_pick$1414 = \$1415 ; + assign wrpick_XER_xer_ca_i[2] = \$1412 ; + assign wrpick_XER_xer_ca_i[1] = \$1410 ; + assign wrpick_XER_xer_ca_i[0] = \$1408 ; + assign wrflag_alu0_xer_ca_2 = \$1406 ; + assign cr_wen = \$1404 [7:0]; + assign cr_data_i = \$1393 ; + assign \addr_en$1378 = \$1383 ; + assign \wp$1375 = \$1376 ; + assign \wr_pick_rise$1137 = \$1373 ; + assign \wr_pick$1367 = \$1368 ; + assign wrflag_shiftrot0_cr_a_1 = \$1365 ; + assign \addr_en$1358 = \$1363 ; + assign \wp$1355 = \$1356 ; + assign \wr_pick_rise$1117 = \$1353 ; + assign \wr_pick$1347 = \$1348 ; + assign wrflag_mul0_cr_a_1 = \$1345 ; + assign \addr_en$1338 = \$1343 ; + assign \wp$1335 = \$1336 ; + assign \wr_pick_rise$1097 = \$1333 ; + assign \wr_pick$1327 = \$1328 ; + assign wrflag_div0_cr_a_1 = \$1325 ; + assign \addr_en$1318 = \$1323 ; + assign \wp$1315 = \$1316 ; + assign \wr_pick_rise$1057 = \$1313 ; + assign \wr_pick$1307 = \$1308 ; + assign wrflag_logical0_cr_a_1 = \$1305 ; + assign \addr_en$1298 = \$1303 ; + assign \wp$1295 = \$1296 ; + assign \wr_pick_rise$1016 = \$1293 ; + assign \wr_pick$1287 = \$1288 ; + assign wrflag_cr0_cr_a_2 = \$1285 ; + assign \addr_en$1278 = \$1283 ; + assign \wp$1275 = \$1276 ; + assign \wr_pick_rise$996 = \$1273 ; + assign \wr_pick$1267 = \$1268 ; + assign wrpick_CR_cr_a_i[5] = \$1265 ; + assign wrpick_CR_cr_a_i[4] = \$1263 ; + assign wrpick_CR_cr_a_i[3] = \$1261 ; + assign wrpick_CR_cr_a_i[2] = \$1259 ; + assign wrpick_CR_cr_a_i[1] = \$1257 ; + assign wrpick_CR_cr_a_i[0] = \$1255 ; + assign wrflag_alu0_cr_a_1 = \$1253 ; + assign cr_full_wr__wen = \addr_en$1250 ; assign cr_full_wr__data_i = fus_dest2_o; - assign \addr_en$1228 = \$1229 ; - assign \wp$1225 = \$1226 ; - assign \wr_pick_rise$995 = \$1223 ; - assign \wr_pick$1217 = \$1218 ; - assign wrpick_CR_full_cr_i = \$1215 ; - assign wrflag_cr0_full_cr_1 = \$1213 ; - assign int_dest1__wen = \$1211 ; - assign int_dest1__addr = \$1193 [4:0]; - assign int_dest1__data_i = \$1174 [63:0]; - assign \addr_en$1154 = \$1155 ; - assign \wp$1151 = \$1152 ; - assign \wr_pick_rise$1134 = \$1149 ; - assign \wr_pick$1143 = \$1144 ; - assign wrflag_ldst0_o_1 = \$1141 ; - assign \addr_en$1138 = \$1139 ; - assign \wp$1135 = \$1136 ; - assign \fus_cu_wr__go_i$114 [1] = \wr_pick_rise$1134 ; - assign \fus_cu_wr__go_i$114 [0] = \wr_pick_rise$1129 ; - assign \wr_pick_rise$1129 = \$1132 ; - assign \wr_pick$1125 = \$1126 ; - assign wrflag_ldst0_o_0 = \$1123 ; - assign \addr_en$1120 = \$1121 ; - assign \wp$1117 = \$1118 ; - assign \fus_cu_wr__go_i$112 [2] = \wr_pick_rise$1116 ; - assign \fus_cu_wr__go_i$112 [1] = \wr_pick_rise$1115 ; - assign \fus_cu_wr__go_i$112 [0] = \wr_pick_rise$1110 ; - assign \wr_pick_rise$1110 = \$1113 ; - assign \wr_pick$1106 = \$1107 ; - assign wrflag_shiftrot0_o_0 = \$1104 ; - assign \addr_en$1101 = \$1102 ; - assign \wp$1098 = \$1099 ; - assign \fus_cu_wr__go_i$109 [3] = \wr_pick_rise$1097 ; - assign \fus_cu_wr__go_i$109 [2] = \wr_pick_rise$1096 ; - assign \fus_cu_wr__go_i$109 [1] = \wr_pick_rise$1095 ; - assign \fus_cu_wr__go_i$109 [0] = \wr_pick_rise$1090 ; - assign \wr_pick_rise$1090 = \$1093 ; - assign \wr_pick$1086 = \$1087 ; - assign wrflag_mul0_o_0 = \$1084 ; - assign \addr_en$1081 = \$1082 ; - assign \wp$1078 = \$1079 ; - assign \fus_cu_wr__go_i$106 [3] = \wr_pick_rise$1077 ; - assign \fus_cu_wr__go_i$106 [2] = \wr_pick_rise$1076 ; - assign \fus_cu_wr__go_i$106 [1] = \wr_pick_rise$1075 ; - assign \fus_cu_wr__go_i$106 [0] = \wr_pick_rise$1070 ; + assign \addr_en$1250 = \$1251 ; + assign \wp$1247 = \$1248 ; + assign \wr_pick_rise$1015 = \$1245 ; + assign \wr_pick$1239 = \$1240 ; + assign wrpick_CR_full_cr_i = \$1237 ; + assign wrflag_cr0_full_cr_1 = \$1235 ; + assign int_dest1__wen = \$1233 ; + assign int_dest1__addr = \$1215 [4:0]; + assign int_dest1__data_i = \$1196 [63:0]; + assign \addr_en$1176 = \$1177 ; + assign \wp$1173 = \$1174 ; + assign \wr_pick_rise$1156 = \$1171 ; + assign \wr_pick$1165 = \$1166 ; + assign wrflag_ldst0_o_1 = \$1163 ; + assign \addr_en$1160 = \$1161 ; + assign \wp$1157 = \$1158 ; + assign \fus_cu_wr__go_i$115 [1] = \wr_pick_rise$1156 ; + assign \fus_cu_wr__go_i$115 [0] = \wr_pick_rise$1151 ; + assign \wr_pick_rise$1151 = \$1154 ; + assign \wr_pick$1147 = \$1148 ; + assign wrflag_ldst0_o_0 = \$1145 ; + assign \addr_en$1142 = \$1143 ; + assign \wp$1139 = \$1140 ; + assign \fus_cu_wr__go_i$113 [2] = \wr_pick_rise$1138 ; + assign \fus_cu_wr__go_i$113 [1] = \wr_pick_rise$1137 ; + assign \fus_cu_wr__go_i$113 [0] = \wr_pick_rise$1132 ; + assign \wr_pick_rise$1132 = \$1135 ; + assign \wr_pick$1128 = \$1129 ; + assign wrflag_shiftrot0_o_0 = \$1126 ; + assign \addr_en$1123 = \$1124 ; + assign \wp$1120 = \$1121 ; + assign \fus_cu_wr__go_i$110 [3] = \wr_pick_rise$1119 ; + assign \fus_cu_wr__go_i$110 [2] = \wr_pick_rise$1118 ; + assign \fus_cu_wr__go_i$110 [1] = \wr_pick_rise$1117 ; + assign \fus_cu_wr__go_i$110 [0] = \wr_pick_rise$1112 ; + assign \wr_pick_rise$1112 = \$1115 ; + assign \wr_pick$1108 = \$1109 ; + assign wrflag_mul0_o_0 = \$1106 ; + assign \addr_en$1103 = \$1104 ; + assign \wp$1100 = \$1101 ; + assign \fus_cu_wr__go_i$107 [3] = \wr_pick_rise$1099 ; + assign \fus_cu_wr__go_i$107 [2] = \wr_pick_rise$1098 ; + assign \fus_cu_wr__go_i$107 [1] = \wr_pick_rise$1097 ; + assign \fus_cu_wr__go_i$107 [0] = \wr_pick_rise$1092 ; + assign \wr_pick_rise$1092 = \$1095 ; + assign \wr_pick$1088 = \$1089 ; + assign wrflag_div0_o_0 = \$1086 ; + assign \addr_en$1083 = \$1084 ; + assign \wp$1080 = \$1081 ; + assign \fus_cu_wr__go_i$104 [1] = \wr_pick_rise$1079 ; + assign \fus_cu_wr__go_i$104 [2] = \wr_pick_rise$1078 ; + assign \fus_cu_wr__go_i$104 [3] = \wr_pick_rise$1077 ; + assign \fus_cu_wr__go_i$104 [4] = \wr_pick_rise$1076 ; + assign \fus_cu_wr__go_i$104 [5] = \wr_pick_rise$1075 ; + assign \fus_cu_wr__go_i$104 [0] = \wr_pick_rise$1070 ; assign \wr_pick_rise$1070 = \$1073 ; assign \wr_pick$1066 = \$1067 ; - assign wrflag_div0_o_0 = \$1064 ; + assign wrflag_spr0_o_0 = \$1064 ; assign \addr_en$1061 = \$1062 ; assign \wp$1058 = \$1059 ; - assign \fus_cu_wr__go_i$103 [1] = \wr_pick_rise$1057 ; - assign \fus_cu_wr__go_i$103 [2] = \wr_pick_rise$1056 ; - assign \fus_cu_wr__go_i$103 [3] = \wr_pick_rise$1055 ; - assign \fus_cu_wr__go_i$103 [4] = \wr_pick_rise$1054 ; - assign \fus_cu_wr__go_i$103 [5] = \wr_pick_rise$1053 ; - assign \fus_cu_wr__go_i$103 [0] = \wr_pick_rise$1048 ; - assign \wr_pick_rise$1048 = \$1051 ; - assign \wr_pick$1044 = \$1045 ; - assign wrflag_spr0_o_0 = \$1042 ; - assign \addr_en$1039 = \$1040 ; - assign \wp$1036 = \$1037 ; - assign \fus_cu_wr__go_i$100 [1] = \wr_pick_rise$1035 ; - assign \fus_cu_wr__go_i$100 [0] = \wr_pick_rise$1030 ; - assign \wr_pick_rise$1030 = \$1033 ; - assign \wr_pick$1026 = \$1027 ; - assign wrflag_logical0_o_0 = \$1024 ; - assign \addr_en$1021 = \$1022 ; - assign \wp$1018 = \$1019 ; - assign \fus_cu_wr__go_i$97 [4] = \wr_pick_rise$1017 ; - assign \fus_cu_wr__go_i$97 [3] = \wr_pick_rise$1016 ; - assign \fus_cu_wr__go_i$97 [2] = \wr_pick_rise$1015 ; - assign \fus_cu_wr__go_i$97 [1] = \wr_pick_rise$1014 ; - assign \fus_cu_wr__go_i$97 [0] = \wr_pick_rise$1009 ; - assign \wr_pick_rise$1009 = \$1012 ; - assign \wr_pick$1005 = \$1006 ; - assign wrflag_trap0_o_0 = \$1003 ; - assign \addr_en$1000 = \$1001 ; - assign \wp$997 = \$998 ; - assign \fus_cu_wr__go_i$94 [2] = \wr_pick_rise$996 ; - assign \fus_cu_wr__go_i$94 [1] = \wr_pick_rise$995 ; - assign \fus_cu_wr__go_i$94 [0] = \wr_pick_rise$990 ; - assign \wr_pick_rise$990 = \$993 ; - assign \wr_pick$986 = \$987 ; - assign wrflag_cr0_o_0 = \$984 ; - assign addr_en = \$982 ; - assign wp = \$980 ; - assign fus_cu_wr__go_i[4] = \wr_pick_rise$979 ; - assign fus_cu_wr__go_i[3] = \wr_pick_rise$978 ; - assign fus_cu_wr__go_i[2] = \wr_pick_rise$977 ; - assign fus_cu_wr__go_i[1] = \wr_pick_rise$976 ; + assign \fus_cu_wr__go_i$101 [1] = \wr_pick_rise$1057 ; + assign \fus_cu_wr__go_i$101 [0] = \wr_pick_rise$1052 ; + assign \wr_pick_rise$1052 = \$1055 ; + assign \wr_pick$1048 = \$1049 ; + assign wrflag_logical0_o_0 = \$1046 ; + assign \addr_en$1043 = \$1044 ; + assign \wp$1040 = \$1041 ; + assign \fus_cu_wr__go_i$98 [6] = \wr_pick_rise$1039 ; + assign \fus_cu_wr__go_i$98 [5] = \wr_pick_rise$1038 ; + assign \fus_cu_wr__go_i$98 [4] = \wr_pick_rise$1037 ; + assign \fus_cu_wr__go_i$98 [3] = \wr_pick_rise$1036 ; + assign \fus_cu_wr__go_i$98 [2] = \wr_pick_rise$1035 ; + assign \fus_cu_wr__go_i$98 [1] = \wr_pick_rise$1034 ; + assign \fus_cu_wr__go_i$98 [0] = \wr_pick_rise$1029 ; + assign \wr_pick_rise$1029 = \$1032 ; + assign \wr_pick$1025 = \$1026 ; + assign wrflag_trap0_o_0 = \$1023 ; + assign \addr_en$1020 = \$1021 ; + assign \wp$1017 = \$1018 ; + assign \fus_cu_wr__go_i$95 [2] = \wr_pick_rise$1016 ; + assign \fus_cu_wr__go_i$95 [1] = \wr_pick_rise$1015 ; + assign \fus_cu_wr__go_i$95 [0] = \wr_pick_rise$1010 ; + assign \wr_pick_rise$1010 = \$1013 ; + assign \wr_pick$1006 = \$1007 ; + assign wrflag_cr0_o_0 = \$1004 ; + assign addr_en = \$1002 ; + assign wp = \$1000 ; + assign fus_cu_wr__go_i[4] = \wr_pick_rise$999 ; + assign fus_cu_wr__go_i[3] = \wr_pick_rise$998 ; + assign fus_cu_wr__go_i[2] = \wr_pick_rise$997 ; + assign fus_cu_wr__go_i[1] = \wr_pick_rise$996 ; assign fus_cu_wr__go_i[0] = wr_pick_rise; - assign wr_pick_rise = \$974 ; - assign wr_pick = \$970 ; - assign wrpick_INT_o_i[9] = \$968 ; - assign wrpick_INT_o_i[8] = \$966 ; - assign wrpick_INT_o_i[7] = \$964 ; - assign wrpick_INT_o_i[6] = \$962 ; - assign wrpick_INT_o_i[5] = \$960 ; - assign wrpick_INT_o_i[4] = \$958 ; - assign wrpick_INT_o_i[3] = \$956 ; - assign wrpick_INT_o_i[2] = \$954 ; - assign wrpick_INT_o_i[1] = \$952 ; - assign wrpick_INT_o_i[0] = \$950 ; - assign wrflag_alu0_o_0 = \$948 ; - assign spr_spr1__ren = \$946 ; + assign wr_pick_rise = \$994 ; + assign wr_pick = \$990 ; + assign wrpick_INT_o_i[9] = \$988 ; + assign wrpick_INT_o_i[8] = \$986 ; + assign wrpick_INT_o_i[7] = \$984 ; + assign wrpick_INT_o_i[6] = \$982 ; + assign wrpick_INT_o_i[5] = \$980 ; + assign wrpick_INT_o_i[4] = \$978 ; + assign wrpick_INT_o_i[3] = \$976 ; + assign wrpick_INT_o_i[2] = \$974 ; + assign wrpick_INT_o_i[1] = \$972 ; + assign wrpick_INT_o_i[0] = \$970 ; + assign wrflag_alu0_o_0 = \$968 ; + assign spr_spr1__ren = \$966 ; assign spr_spr1__addr = addr_en_SPR_spr1_spr0_0[3:0]; - assign addr_en_SPR_spr1_spr0_0 = \$944 ; - assign rp_SPR_spr1_spr0_0 = \$942 ; + assign addr_en_SPR_spr1_spr0_0 = \$964 ; + assign rp_SPR_spr1_spr0_0 = \$962 ; assign rdpick_SPR_spr1_i = pick_SPR_spr1_spr0_0; - assign pick_SPR_spr1_spr0_0 = \$940 ; + assign pick_SPR_spr1_spr0_0 = \$960 ; assign rdflag_SPR_spr1_0 = core_spr1_ok; - assign fast_src1__ren = \$932 ; - assign fast_src1__addr = \$930 ; - assign addr_en_FAST_fast1_trap0_4 = \$922 ; - assign rp_FAST_fast1_trap0_4 = \$920 ; - assign pick_FAST_fast1_trap0_4 = \$918 ; - assign addr_en_FAST_fast1_branch0_3 = \$910 ; - assign rp_FAST_fast1_branch0_3 = \$908 ; - assign pick_FAST_fast1_branch0_3 = \$906 ; - assign addr_en_FAST_fast1_spr0_2 = \$898 ; - assign rp_FAST_fast1_spr0_2 = \$896 ; - assign pick_FAST_fast1_spr0_2 = \$894 ; - assign addr_en_FAST_fast1_trap0_1 = \$886 ; - assign rp_FAST_fast1_trap0_1 = \$884 ; - assign pick_FAST_fast1_trap0_1 = \$882 ; - assign addr_en_FAST_fast1_branch0_0 = \$874 ; - assign rp_FAST_fast1_branch0_0 = \$872 ; + assign fast_src1__ren = \$952 ; + assign fast_src1__addr = \$940 ; + assign addr_en_FAST_fast1_trap0_5 = \$938 ; + assign rp_FAST_fast1_trap0_5 = \$936 ; + assign pick_FAST_fast1_trap0_5 = \$934 ; + assign addr_en_FAST_fast1_trap0_4 = \$926 ; + assign rp_FAST_fast1_trap0_4 = \$924 ; + assign pick_FAST_fast1_trap0_4 = \$922 ; + assign addr_en_FAST_fast1_branch0_3 = \$914 ; + assign rp_FAST_fast1_branch0_3 = \$912 ; + assign pick_FAST_fast1_branch0_3 = \$910 ; + assign addr_en_FAST_fast1_spr0_2 = \$902 ; + assign rp_FAST_fast1_spr0_2 = \$900 ; + assign pick_FAST_fast1_spr0_2 = \$898 ; + assign addr_en_FAST_fast1_trap0_1 = \$890 ; + assign rp_FAST_fast1_trap0_1 = \$888 ; + assign pick_FAST_fast1_trap0_1 = \$886 ; + assign addr_en_FAST_fast1_branch0_0 = \$878 ; + assign rp_FAST_fast1_branch0_0 = \$876 ; + assign rdpick_FAST_fast1_i[5] = pick_FAST_fast1_trap0_5; assign rdpick_FAST_fast1_i[4] = pick_FAST_fast1_trap0_4; assign rdpick_FAST_fast1_i[3] = pick_FAST_fast1_branch0_3; assign rdpick_FAST_fast1_i[2] = pick_FAST_fast1_spr0_2; assign rdpick_FAST_fast1_i[1] = pick_FAST_fast1_trap0_1; assign rdpick_FAST_fast1_i[0] = pick_FAST_fast1_branch0_0; - assign pick_FAST_fast1_branch0_0 = \$870 ; + assign pick_FAST_fast1_branch0_0 = \$874 ; + assign rdflag_FAST_fast1_2 = core_fast3_ok; assign rdflag_FAST_fast1_1 = core_fast2_ok; assign rdflag_FAST_fast1_0 = core_fast1_ok; assign cr_src3__ren = addr_en_CR_cr_c_cr0_0[7:0]; - assign addr_en_CR_cr_c_cr0_0 = \$862 ; - assign rp_CR_cr_c_cr0_0 = \$856 ; + assign addr_en_CR_cr_c_cr0_0 = \$866 ; + assign rp_CR_cr_c_cr0_0 = \$860 ; assign rdpick_CR_cr_c_i = pick_CR_cr_c_cr0_0; - assign pick_CR_cr_c_cr0_0 = \$854 ; + assign pick_CR_cr_c_cr0_0 = \$858 ; assign rdflag_CR_cr_c_0 = \core_cr_in2_ok$2 ; assign cr_src2__ren = addr_en_CR_cr_b_cr0_0[7:0]; - assign addr_en_CR_cr_b_cr0_0 = \$846 ; - assign rp_CR_cr_b_cr0_0 = \$840 ; + assign addr_en_CR_cr_b_cr0_0 = \$850 ; + assign rp_CR_cr_b_cr0_0 = \$844 ; assign rdpick_CR_cr_b_i = pick_CR_cr_b_cr0_0; - assign pick_CR_cr_b_cr0_0 = \$838 ; + assign pick_CR_cr_b_cr0_0 = \$842 ; assign rdflag_CR_cr_b_0 = core_cr_in2_ok; - assign cr_src1__ren = \$830 [7:0]; - assign addr_en_CR_cr_a_branch0_1 = \$827 ; - assign rp_CR_cr_a_branch0_1 = \$821 ; + assign cr_src1__ren = \$834 [7:0]; + assign addr_en_CR_cr_a_branch0_1 = \$831 ; + assign rp_CR_cr_a_branch0_1 = \$825 ; assign \fus_cu_rd__go_i$82 [1] = dp_FAST_fast1_branch0_3; assign \fus_cu_rd__go_i$82 [0] = dp_FAST_fast1_branch0_0; assign \fus_cu_rd__go_i$82 [2] = dp_CR_cr_a_branch0_1; - assign pick_CR_cr_a_branch0_1 = \$819 ; - assign addr_en_CR_cr_a_cr0_0 = \$811 ; - assign rp_CR_cr_a_cr0_0 = \$805 ; + assign pick_CR_cr_a_branch0_1 = \$823 ; + assign addr_en_CR_cr_a_cr0_0 = \$815 ; + assign rp_CR_cr_a_cr0_0 = \$809 ; assign rdpick_CR_cr_a_i[1] = pick_CR_cr_a_branch0_1; assign rdpick_CR_cr_a_i[0] = pick_CR_cr_a_cr0_0; - assign pick_CR_cr_a_cr0_0 = \$803 ; + assign pick_CR_cr_a_cr0_0 = \$807 ; assign rdflag_CR_cr_a_0 = core_cr_in1_ok; assign cr_full_rd__ren = addr_en_CR_full_cr_cr0_0; - assign addr_en_CR_full_cr_cr0_0 = \$795 ; - assign rp_CR_full_cr_cr0_0 = \$793 ; + assign addr_en_CR_full_cr_cr0_0 = \$799 ; + assign rp_CR_full_cr_cr0_0 = \$797 ; assign rdpick_CR_full_cr_i = pick_CR_full_cr_cr0_0; - assign pick_CR_full_cr_cr0_0 = \$791 ; + assign pick_CR_full_cr_cr0_0 = \$795 ; assign rdflag_CR_full_cr_0 = core_core_cr_rd_ok; assign xer_src3__ren = addr_en_XER_xer_ov_spr0_0; - assign addr_en_XER_xer_ov_spr0_0 = \$783 ; - assign rp_XER_xer_ov_spr0_0 = \$781 ; + assign addr_en_XER_xer_ov_spr0_0 = \$787 ; + assign rp_XER_xer_ov_spr0_0 = \$785 ; assign rdpick_XER_xer_ov_i = pick_XER_xer_ov_spr0_0; - assign pick_XER_xer_ov_spr0_0 = \$779 ; - assign rdflag_XER_xer_ov_0 = \$771 ; - assign xer_src2__ren = \$759 ; - assign addr_en_XER_xer_ca_shiftrot0_2 = \$757 ; - assign rp_XER_xer_ca_shiftrot0_2 = \$755 ; - assign pick_XER_xer_ca_shiftrot0_2 = \$753 ; - assign addr_en_XER_xer_ca_spr0_1 = \$745 ; - assign rp_XER_xer_ca_spr0_1 = \$743 ; - assign pick_XER_xer_ca_spr0_1 = \$741 ; - assign addr_en_XER_xer_ca_alu0_0 = \$733 ; - assign rp_XER_xer_ca_alu0_0 = \$731 ; + assign pick_XER_xer_ov_spr0_0 = \$783 ; + assign rdflag_XER_xer_ov_0 = \$775 ; + assign xer_src2__ren = \$763 ; + assign addr_en_XER_xer_ca_shiftrot0_2 = \$761 ; + assign rp_XER_xer_ca_shiftrot0_2 = \$759 ; + assign pick_XER_xer_ca_shiftrot0_2 = \$757 ; + assign addr_en_XER_xer_ca_spr0_1 = \$749 ; + assign rp_XER_xer_ca_spr0_1 = \$747 ; + assign pick_XER_xer_ca_spr0_1 = \$745 ; + assign addr_en_XER_xer_ca_alu0_0 = \$737 ; + assign rp_XER_xer_ca_alu0_0 = \$735 ; assign rdpick_XER_xer_ca_i[2] = pick_XER_xer_ca_shiftrot0_2; assign rdpick_XER_xer_ca_i[1] = pick_XER_xer_ca_spr0_1; assign rdpick_XER_xer_ca_i[0] = pick_XER_xer_ca_alu0_0; - assign pick_XER_xer_ca_alu0_0 = \$729 ; - assign rdflag_XER_xer_ca_0 = \$721 ; - assign xer_src1__ren = \$703 ; - assign addr_en_XER_xer_so_shiftrot0_5 = \$701 ; - assign rp_XER_xer_so_shiftrot0_5 = \$699 ; - assign pick_XER_xer_so_shiftrot0_5 = \$697 ; - assign addr_en_XER_xer_so_mul0_4 = \$689 ; - assign rp_XER_xer_so_mul0_4 = \$687 ; - assign pick_XER_xer_so_mul0_4 = \$685 ; - assign addr_en_XER_xer_so_div0_3 = \$677 ; - assign rp_XER_xer_so_div0_3 = \$675 ; - assign pick_XER_xer_so_div0_3 = \$673 ; - assign addr_en_XER_xer_so_spr0_2 = \$665 ; - assign rp_XER_xer_so_spr0_2 = \$663 ; - assign pick_XER_xer_so_spr0_2 = \$661 ; - assign addr_en_XER_xer_so_logical0_1 = \$653 ; - assign rp_XER_xer_so_logical0_1 = \$651 ; - assign pick_XER_xer_so_logical0_1 = \$649 ; - assign addr_en_XER_xer_so_alu0_0 = \$641 ; - assign rp_XER_xer_so_alu0_0 = \$639 ; + assign pick_XER_xer_ca_alu0_0 = \$733 ; + assign rdflag_XER_xer_ca_0 = \$725 ; + assign xer_src1__ren = \$707 ; + assign addr_en_XER_xer_so_shiftrot0_5 = \$705 ; + assign rp_XER_xer_so_shiftrot0_5 = \$703 ; + assign pick_XER_xer_so_shiftrot0_5 = \$701 ; + assign addr_en_XER_xer_so_mul0_4 = \$693 ; + assign rp_XER_xer_so_mul0_4 = \$691 ; + assign pick_XER_xer_so_mul0_4 = \$689 ; + assign addr_en_XER_xer_so_div0_3 = \$681 ; + assign rp_XER_xer_so_div0_3 = \$679 ; + assign pick_XER_xer_so_div0_3 = \$677 ; + assign addr_en_XER_xer_so_spr0_2 = \$669 ; + assign rp_XER_xer_so_spr0_2 = \$667 ; + assign pick_XER_xer_so_spr0_2 = \$665 ; + assign addr_en_XER_xer_so_logical0_1 = \$657 ; + assign rp_XER_xer_so_logical0_1 = \$655 ; + assign pick_XER_xer_so_logical0_1 = \$653 ; + assign addr_en_XER_xer_so_alu0_0 = \$645 ; + assign rp_XER_xer_so_alu0_0 = \$643 ; assign rdpick_XER_xer_so_i[5] = pick_XER_xer_so_shiftrot0_5; assign rdpick_XER_xer_so_i[4] = pick_XER_xer_so_mul0_4; assign rdpick_XER_xer_so_i[3] = pick_XER_xer_so_div0_3; assign rdpick_XER_xer_so_i[2] = pick_XER_xer_so_spr0_2; assign rdpick_XER_xer_so_i[1] = pick_XER_xer_so_logical0_1; assign rdpick_XER_xer_so_i[0] = pick_XER_xer_so_alu0_0; - assign pick_XER_xer_so_alu0_0 = \$637 ; - assign rdflag_XER_xer_so_0 = \$629 ; - assign int_src1__ren = \$617 ; - assign int_src1__addr = \$615 [4:0]; - assign addr_en_INT_rabc_ldst0_18 = \$578 ; - assign rp_INT_rabc_ldst0_18 = \$576 ; - assign pick_INT_rabc_ldst0_18 = \$574 ; - assign addr_en_INT_rabc_shiftrot0_17 = \$566 ; - assign rp_INT_rabc_shiftrot0_17 = \$564 ; - assign pick_INT_rabc_shiftrot0_17 = \$562 ; - assign addr_en_INT_rabc_mul0_16 = \$554 ; - assign rp_INT_rabc_mul0_16 = \$552 ; - assign pick_INT_rabc_mul0_16 = \$550 ; - assign addr_en_INT_rabc_div0_15 = \$542 ; - assign rp_INT_rabc_div0_15 = \$540 ; - assign pick_INT_rabc_div0_15 = \$538 ; - assign addr_en_INT_rabc_spr0_14 = \$530 ; - assign rp_INT_rabc_spr0_14 = \$528 ; + assign pick_XER_xer_so_alu0_0 = \$641 ; + assign rdflag_XER_xer_so_0 = \$633 ; + assign int_src1__ren = \$621 ; + assign int_src1__addr = \$619 [4:0]; + assign addr_en_INT_rabc_ldst0_18 = \$582 ; + assign rp_INT_rabc_ldst0_18 = \$580 ; + assign pick_INT_rabc_ldst0_18 = \$578 ; + assign addr_en_INT_rabc_shiftrot0_17 = \$570 ; + assign rp_INT_rabc_shiftrot0_17 = \$568 ; + assign pick_INT_rabc_shiftrot0_17 = \$566 ; + assign addr_en_INT_rabc_mul0_16 = \$558 ; + assign rp_INT_rabc_mul0_16 = \$556 ; + assign pick_INT_rabc_mul0_16 = \$554 ; + assign addr_en_INT_rabc_div0_15 = \$546 ; + assign rp_INT_rabc_div0_15 = \$544 ; + assign pick_INT_rabc_div0_15 = \$542 ; + assign addr_en_INT_rabc_spr0_14 = \$534 ; + assign rp_INT_rabc_spr0_14 = \$532 ; assign \fus_cu_rd__go_i$66 [1] = dp_SPR_spr1_spr0_0; assign \fus_cu_rd__go_i$66 [2] = dp_FAST_fast1_spr0_2; assign \fus_cu_rd__go_i$66 [4] = dp_XER_xer_ov_spr0_0; assign \fus_cu_rd__go_i$66 [5] = dp_XER_xer_ca_spr0_1; assign \fus_cu_rd__go_i$66 [3] = dp_XER_xer_so_spr0_2; assign \fus_cu_rd__go_i$66 [0] = dp_INT_rabc_spr0_14; - assign pick_INT_rabc_spr0_14 = \$526 ; - assign addr_en_INT_rabc_logical0_13 = \$518 ; - assign rp_INT_rabc_logical0_13 = \$516 ; - assign pick_INT_rabc_logical0_13 = \$514 ; - assign addr_en_INT_rabc_trap0_12 = \$506 ; - assign rp_INT_rabc_trap0_12 = \$504 ; - assign pick_INT_rabc_trap0_12 = \$502 ; - assign addr_en_INT_rabc_cr0_11 = \$494 ; - assign rp_INT_rabc_cr0_11 = \$492 ; - assign pick_INT_rabc_cr0_11 = \$490 ; - assign addr_en_INT_rabc_alu0_10 = \$482 ; - assign rp_INT_rabc_alu0_10 = \$480 ; - assign pick_INT_rabc_alu0_10 = \$478 ; - assign addr_en_INT_rabc_ldst0_9 = \$470 ; - assign rp_INT_rabc_ldst0_9 = \$468 ; - assign pick_INT_rabc_ldst0_9 = \$466 ; - assign addr_en_INT_rabc_shiftrot0_8 = \$458 ; - assign rp_INT_rabc_shiftrot0_8 = \$456 ; - assign pick_INT_rabc_shiftrot0_8 = \$454 ; - assign addr_en_INT_rabc_ldst0_7 = \$446 ; - assign rp_INT_rabc_ldst0_7 = \$444 ; + assign pick_INT_rabc_spr0_14 = \$530 ; + assign addr_en_INT_rabc_logical0_13 = \$522 ; + assign rp_INT_rabc_logical0_13 = \$520 ; + assign pick_INT_rabc_logical0_13 = \$518 ; + assign addr_en_INT_rabc_trap0_12 = \$510 ; + assign rp_INT_rabc_trap0_12 = \$508 ; + assign pick_INT_rabc_trap0_12 = \$506 ; + assign addr_en_INT_rabc_cr0_11 = \$498 ; + assign rp_INT_rabc_cr0_11 = \$496 ; + assign pick_INT_rabc_cr0_11 = \$494 ; + assign addr_en_INT_rabc_alu0_10 = \$486 ; + assign rp_INT_rabc_alu0_10 = \$484 ; + assign pick_INT_rabc_alu0_10 = \$482 ; + assign addr_en_INT_rabc_ldst0_9 = \$474 ; + assign rp_INT_rabc_ldst0_9 = \$472 ; + assign pick_INT_rabc_ldst0_9 = \$470 ; + assign addr_en_INT_rabc_shiftrot0_8 = \$462 ; + assign rp_INT_rabc_shiftrot0_8 = \$460 ; + assign pick_INT_rabc_shiftrot0_8 = \$458 ; + assign addr_en_INT_rabc_ldst0_7 = \$450 ; + assign rp_INT_rabc_ldst0_7 = \$448 ; assign \fus_cu_rd__go_i$59 [0] = dp_INT_rabc_ldst0_18; assign \fus_cu_rd__go_i$59 [2] = dp_INT_rabc_ldst0_9; assign \fus_cu_rd__go_i$59 [1] = dp_INT_rabc_ldst0_7; - assign pick_INT_rabc_ldst0_7 = \$442 ; - assign addr_en_INT_rabc_shiftrot0_6 = \$434 ; - assign rp_INT_rabc_shiftrot0_6 = \$432 ; + assign pick_INT_rabc_ldst0_7 = \$446 ; + assign addr_en_INT_rabc_shiftrot0_6 = \$438 ; + assign rp_INT_rabc_shiftrot0_6 = \$436 ; assign \fus_cu_rd__go_i$56 [4] = dp_XER_xer_ca_shiftrot0_2; assign \fus_cu_rd__go_i$56 [3] = dp_XER_xer_so_shiftrot0_5; assign \fus_cu_rd__go_i$56 [0] = dp_INT_rabc_shiftrot0_17; assign \fus_cu_rd__go_i$56 [2] = dp_INT_rabc_shiftrot0_8; assign \fus_cu_rd__go_i$56 [1] = dp_INT_rabc_shiftrot0_6; - assign pick_INT_rabc_shiftrot0_6 = \$430 ; - assign addr_en_INT_rabc_mul0_5 = \$422 ; - assign rp_INT_rabc_mul0_5 = \$420 ; + assign pick_INT_rabc_shiftrot0_6 = \$434 ; + assign addr_en_INT_rabc_mul0_5 = \$426 ; + assign rp_INT_rabc_mul0_5 = \$424 ; assign \fus_cu_rd__go_i$53 [2] = dp_XER_xer_so_mul0_4; assign \fus_cu_rd__go_i$53 [0] = dp_INT_rabc_mul0_16; assign \fus_cu_rd__go_i$53 [1] = dp_INT_rabc_mul0_5; - assign pick_INT_rabc_mul0_5 = \$418 ; - assign addr_en_INT_rabc_div0_4 = \$410 ; - assign rp_INT_rabc_div0_4 = \$408 ; + assign pick_INT_rabc_mul0_5 = \$422 ; + assign addr_en_INT_rabc_div0_4 = \$414 ; + assign rp_INT_rabc_div0_4 = \$412 ; assign \fus_cu_rd__go_i$50 [2] = dp_XER_xer_so_div0_3; assign \fus_cu_rd__go_i$50 [0] = dp_INT_rabc_div0_15; assign \fus_cu_rd__go_i$50 [1] = dp_INT_rabc_div0_4; - assign pick_INT_rabc_div0_4 = \$406 ; - assign addr_en_INT_rabc_logical0_3 = \$398 ; - assign rp_INT_rabc_logical0_3 = \$396 ; + assign pick_INT_rabc_div0_4 = \$410 ; + assign addr_en_INT_rabc_logical0_3 = \$402 ; + assign rp_INT_rabc_logical0_3 = \$400 ; assign \fus_cu_rd__go_i$47 [2] = dp_XER_xer_so_logical0_1; assign \fus_cu_rd__go_i$47 [0] = dp_INT_rabc_logical0_13; assign \fus_cu_rd__go_i$47 [1] = dp_INT_rabc_logical0_3; - assign pick_INT_rabc_logical0_3 = \$394 ; - assign addr_en_INT_rabc_trap0_2 = \$386 ; - assign rp_INT_rabc_trap0_2 = \$384 ; + assign pick_INT_rabc_logical0_3 = \$398 ; + assign addr_en_INT_rabc_trap0_2 = \$390 ; + assign rp_INT_rabc_trap0_2 = \$388 ; + assign \fus_cu_rd__go_i$44 [4] = dp_FAST_fast1_trap0_5; assign \fus_cu_rd__go_i$44 [3] = dp_FAST_fast1_trap0_4; assign \fus_cu_rd__go_i$44 [2] = dp_FAST_fast1_trap0_1; assign \fus_cu_rd__go_i$44 [0] = dp_INT_rabc_trap0_12; assign \fus_cu_rd__go_i$44 [1] = dp_INT_rabc_trap0_2; - assign pick_INT_rabc_trap0_2 = \$382 ; - assign addr_en_INT_rabc_cr0_1 = \$374 ; - assign rp_INT_rabc_cr0_1 = \$372 ; + assign pick_INT_rabc_trap0_2 = \$386 ; + assign addr_en_INT_rabc_cr0_1 = \$378 ; + assign rp_INT_rabc_cr0_1 = \$376 ; assign \fus_cu_rd__go_i$41 [5] = dp_CR_cr_c_cr0_0; assign \fus_cu_rd__go_i$41 [4] = dp_CR_cr_b_cr0_0; assign \fus_cu_rd__go_i$41 [3] = dp_CR_cr_a_cr0_0; assign \fus_cu_rd__go_i$41 [2] = dp_CR_full_cr_cr0_0; assign \fus_cu_rd__go_i$41 [0] = dp_INT_rabc_cr0_11; assign \fus_cu_rd__go_i$41 [1] = dp_INT_rabc_cr0_1; - assign pick_INT_rabc_cr0_1 = \$370 ; - assign addr_en_INT_rabc_alu0_0 = \$362 ; - assign rp_INT_rabc_alu0_0 = \$360 ; + assign pick_INT_rabc_cr0_1 = \$374 ; + assign addr_en_INT_rabc_alu0_0 = \$366 ; + assign rp_INT_rabc_alu0_0 = \$364 ; assign fus_cu_rd__go_i[3] = dp_XER_xer_ca_alu0_0; assign fus_cu_rd__go_i[2] = dp_XER_xer_so_alu0_0; assign fus_cu_rd__go_i[0] = dp_INT_rabc_alu0_10; @@ -48602,19 +53978,19 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c assign rdpick_INT_rabc_i[2] = pick_INT_rabc_trap0_2; assign rdpick_INT_rabc_i[1] = pick_INT_rabc_cr0_1; assign rdpick_INT_rabc_i[0] = pick_INT_rabc_alu0_0; - assign pick_INT_rabc_alu0_0 = \$358 ; + assign pick_INT_rabc_alu0_0 = \$362 ; assign rdflag_INT_rabc_2 = core_reg1_ok; assign rdflag_INT_rabc_1 = core_reg3_ok; assign rdflag_INT_rabc_0 = core_reg2_ok; - assign en_ldst0 = \$217 ; - assign en_shiftrot0 = \$213 ; - assign en_mul0 = \$209 ; - assign en_div0 = \$205 ; - assign en_spr0 = \$201 ; - assign en_logical0 = \$197 ; - assign en_trap0 = \$193 ; - assign en_branch0 = \$189 ; - assign en_cr0 = \$185 ; + assign en_ldst0 = \$221 ; + assign en_shiftrot0 = \$217 ; + assign en_mul0 = \$213 ; + assign en_div0 = \$209 ; + assign en_spr0 = \$205 ; + assign en_logical0 = \$201 ; + assign en_trap0 = \$197 ; + assign en_branch0 = \$193 ; + assign en_cr0 = \$189 ; assign fu_enable[9] = en_ldst0; assign fu_enable[8] = en_shiftrot0; assign fu_enable[7] = en_mul0; @@ -48625,32 +54001,32 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c assign fu_enable[2] = en_branch0; assign fu_enable[1] = en_cr0; assign fu_enable[0] = en_alu0; - assign en_alu0 = \$181 ; - assign dec_LDST_sv_a_nz = sv_a_nz; + assign en_alu0 = \$185 ; + assign dec_LDST_sv_a_nz = 1'h0; assign dec_LDST_bigendian = bigendian_i; assign dec_LDST_raw_opcode_in = raw_insn_i; - assign \sv_a_nz$180 = sv_a_nz; + assign \sv_a_nz$184 = 1'h0; assign dec_SHIFT_ROT_bigendian = bigendian_i; assign dec_SHIFT_ROT_raw_opcode_in = raw_insn_i; - assign \sv_a_nz$179 = sv_a_nz; + assign \sv_a_nz$183 = 1'h0; assign dec_MUL_bigendian = bigendian_i; assign dec_MUL_raw_opcode_in = raw_insn_i; - assign dec_DIV_sv_a_nz = sv_a_nz; + assign dec_DIV_sv_a_nz = 1'h0; assign dec_DIV_bigendian = bigendian_i; assign dec_DIV_raw_opcode_in = raw_insn_i; - assign \sv_a_nz$178 = sv_a_nz; + assign \sv_a_nz$182 = 1'h0; assign dec_SPR_bigendian = bigendian_i; assign dec_SPR_raw_opcode_in = raw_insn_i; - assign dec_LOGICAL_sv_a_nz = sv_a_nz; + assign dec_LOGICAL_sv_a_nz = 1'h0; assign dec_LOGICAL_bigendian = bigendian_i; assign dec_LOGICAL_raw_opcode_in = raw_insn_i; - assign \sv_a_nz$177 = sv_a_nz; + assign \sv_a_nz$181 = 1'h0; assign dec_BRANCH_bigendian = bigendian_i; assign dec_BRANCH_raw_opcode_in = raw_insn_i; - assign \sv_a_nz$176 = sv_a_nz; + assign \sv_a_nz$180 = 1'h0; assign dec_CR_bigendian = bigendian_i; assign dec_CR_raw_opcode_in = raw_insn_i; - assign dec_ALU_sv_a_nz = sv_a_nz; + assign dec_ALU_sv_a_nz = 1'h0; assign dec_ALU_bigendian = bigendian_i; assign dec_ALU_raw_opcode_in = raw_insn_i; endmodule @@ -48707,9 +54083,9 @@ module cr(coresync_rst, full_rd2__ren, full_rd2__data_o, full_rd__data_o, full_r wire [3:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) wire [3:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] data_i; @@ -48983,17 +54359,17 @@ module cr(coresync_rst, full_rd2__ren, full_rd2__data_o, full_rd__data_o, full_r wire [3:0] reg_7_w7__data_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire reg_7_w7__wen; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) reg [7:0] ren_delay = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) reg [7:0] \ren_delay$17 = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) reg [7:0] \ren_delay$17$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) reg [7:0] \ren_delay$34 = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) reg [7:0] \ren_delay$34$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) reg [7:0] \ren_delay$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) output [3:0] src1__data_o; @@ -49207,7 +54583,7 @@ module cr(coresync_rst, full_rd2__ren, full_rd2__data_o, full_rd__data_o, full_r always @* begin if (\initial ) begin end \ren_delay$17$next = src2__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \ren_delay$17$next = 8'h00; @@ -49216,9 +54592,9 @@ module cr(coresync_rst, full_rd2__ren, full_rd2__data_o, full_rd__data_o, full_r always @* begin if (\initial ) begin end src2__data_o = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" *) casez (\$18 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" */ 1'h1: src2__data_o = \$32 ; endcase @@ -49226,7 +54602,7 @@ module cr(coresync_rst, full_rd2__ren, full_rd2__data_o, full_rd__data_o, full_r always @* begin if (\initial ) begin end \ren_delay$34$next = src3__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \ren_delay$34$next = 8'h00; @@ -49235,9 +54611,9 @@ module cr(coresync_rst, full_rd2__ren, full_rd2__data_o, full_rd__data_o, full_r always @* begin if (\initial ) begin end src3__data_o = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" *) casez (\$35 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" */ 1'h1: src3__data_o = \$49 ; endcase @@ -49245,7 +54621,7 @@ module cr(coresync_rst, full_rd2__ren, full_rd2__data_o, full_rd__data_o, full_r always @* begin if (\initial ) begin end \ren_delay$next = src1__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \ren_delay$next = 8'h00; @@ -49254,9 +54630,9 @@ module cr(coresync_rst, full_rd2__ren, full_rd2__data_o, full_rd__data_o, full_r always @* begin if (\initial ) begin end src1__data_o = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" *) casez (\$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" */ 1'h1: src1__data_o = \$15 ; endcase @@ -49294,7 +54670,7 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.cr0" *) (* generator = "nMigen" *) -module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, oper_i_alu_cr0__insn, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, src4_i, src5_i, src6_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, full_cr_ok, dest2_o, cr_a_ok, dest3_o, coresync_clk); +module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, oper_i_alu_cr0__insn, oper_i_alu_cr0__sv_pred_sz, oper_i_alu_cr0__sv_pred_dz, oper_i_alu_cr0__sv_saturate, oper_i_alu_cr0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, src4_i, src5_i, src6_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, full_cr_ok, dest2_o, cr_a_ok, dest3_o, coresync_clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) wire \$101 ; @@ -49420,36 +54796,45 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope wire all_rd_pulse; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) wire all_rd_rise; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [3:0] alu_cr0_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [3:0] \alu_cr0_cr_a$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [3:0] alu_cr0_cr_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [3:0] alu_cr0_cr_c; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] alu_cr0_cr_op__SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \alu_cr0_cr_op__SV_Ptype$next ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] alu_cr0_cr_op__fn_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] \alu_cr0_cr_op__fn_unit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] alu_cr0_cr_op__fn_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] \alu_cr0_cr_op__fn_unit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] alu_cr0_cr_op__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] \alu_cr0_cr_op__insn$next ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -49526,27 +54911,45 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] alu_cr0_cr_op__insn_type = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] \alu_cr0_cr_op__insn_type$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg alu_cr0_cr_op__sv_pred_dz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \alu_cr0_cr_op__sv_pred_dz$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg alu_cr0_cr_op__sv_pred_sz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \alu_cr0_cr_op__sv_pred_sz$next ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] alu_cr0_cr_op__sv_saturate = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \alu_cr0_cr_op__sv_saturate$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [31:0] alu_cr0_full_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [31:0] \alu_cr0_full_cr$1 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) wire alu_cr0_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire alu_cr0_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] alu_cr0_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire alu_cr0_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) wire alu_cr0_p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] alu_cr0_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] alu_cr0_rb; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" *) wire alu_done; @@ -49576,11 +54979,11 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_a_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) output cu_busy_o; @@ -49637,9 +55040,9 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) output [3:0] dest3_o; reg [3:0] dest3_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output full_cr_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire opc_l_q_opc; @@ -49651,24 +55054,31 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope reg opc_l_s_opc = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) reg \opc_l_s_opc$next ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_cr0__SV_Ptype; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] oper_i_alu_cr0__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] oper_i_alu_cr0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] oper_i_alu_cr0__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -49745,8 +55155,20 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] oper_i_alu_cr0__insn_type; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_cr0__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_cr0__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_cr0__sv_saturate; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *) reg [2:0] prev_wr_go = 3'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *) @@ -49928,6 +55350,14 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope alu_cr0_cr_op__fn_unit <= \alu_cr0_cr_op__fn_unit$next ; always @(posedge coresync_clk) alu_cr0_cr_op__insn <= \alu_cr0_cr_op__insn$next ; + always @(posedge coresync_clk) + alu_cr0_cr_op__sv_pred_sz <= \alu_cr0_cr_op__sv_pred_sz$next ; + always @(posedge coresync_clk) + alu_cr0_cr_op__sv_pred_dz <= \alu_cr0_cr_op__sv_pred_dz$next ; + always @(posedge coresync_clk) + alu_cr0_cr_op__sv_saturate <= \alu_cr0_cr_op__sv_saturate$next ; + always @(posedge coresync_clk) + alu_cr0_cr_op__SV_Ptype <= \alu_cr0_cr_op__SV_Ptype$next ; always @(posedge coresync_clk) req_l_r_req <= \req_l_r_req$next ; always @(posedge coresync_clk) @@ -49962,9 +55392,13 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope .cr_a_ok(cr_a_ok), .cr_b(alu_cr0_cr_b), .cr_c(alu_cr0_cr_c), + .cr_op__SV_Ptype(alu_cr0_cr_op__SV_Ptype), .cr_op__fn_unit(alu_cr0_cr_op__fn_unit), .cr_op__insn(alu_cr0_cr_op__insn), .cr_op__insn_type(alu_cr0_cr_op__insn_type), + .cr_op__sv_pred_dz(alu_cr0_cr_op__sv_pred_dz), + .cr_op__sv_pred_sz(alu_cr0_cr_op__sv_pred_sz), + .cr_op__sv_saturate(alu_cr0_cr_op__sv_saturate), .full_cr(alu_cr0_full_cr), .\full_cr$1 (\alu_cr0_full_cr$1 ), .full_cr_ok(full_cr_ok), @@ -50038,7 +55472,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \rok_l_s_rdok$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_s_rdok$next = 1'h0; @@ -50047,7 +55481,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \rok_l_r_rdok$next = \$65 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_r_rdok$next = 1'h1; @@ -50056,7 +55490,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \rst_l_s_rst$next = all_rd; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_s_rst$next = 1'h0; @@ -50065,7 +55499,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \rst_l_r_rst$next = rst_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_r_rst$next = 1'h1; @@ -50074,7 +55508,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \opc_l_s_opc$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_s_opc$next = 1'h0; @@ -50083,7 +55517,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \opc_l_r_opc$next = req_done; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_r_opc$next = 1'h1; @@ -50092,7 +55526,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_s_src$next = 6'h00; @@ -50101,7 +55535,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \src_l_r_src$next = reset_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_r_src$next = 6'h3f; @@ -50110,7 +55544,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \req_l_s_req$next = \$67 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_s_req$next = 3'h0; @@ -50119,7 +55553,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \req_l_r_req$next = \$69 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_r_req$next = 3'h7; @@ -50130,11 +55564,15 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope \alu_cr0_cr_op__insn_type$next = alu_cr0_cr_op__insn_type; \alu_cr0_cr_op__fn_unit$next = alu_cr0_cr_op__fn_unit; \alu_cr0_cr_op__insn$next = alu_cr0_cr_op__insn; + \alu_cr0_cr_op__sv_pred_sz$next = alu_cr0_cr_op__sv_pred_sz; + \alu_cr0_cr_op__sv_pred_dz$next = alu_cr0_cr_op__sv_pred_dz; + \alu_cr0_cr_op__sv_saturate$next = alu_cr0_cr_op__sv_saturate; + \alu_cr0_cr_op__SV_Ptype$next = alu_cr0_cr_op__SV_Ptype; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *) casez (cu_issue_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" */ 1'h1: - { \alu_cr0_cr_op__insn$next , \alu_cr0_cr_op__fn_unit$next , \alu_cr0_cr_op__insn_type$next } = { oper_i_alu_cr0__insn, oper_i_alu_cr0__fn_unit, oper_i_alu_cr0__insn_type }; + { \alu_cr0_cr_op__SV_Ptype$next , \alu_cr0_cr_op__sv_saturate$next , \alu_cr0_cr_op__sv_pred_dz$next , \alu_cr0_cr_op__sv_pred_sz$next , \alu_cr0_cr_op__insn$next , \alu_cr0_cr_op__fn_unit$next , \alu_cr0_cr_op__insn_type$next } = { oper_i_alu_cr0__SV_Ptype, oper_i_alu_cr0__sv_saturate, oper_i_alu_cr0__sv_pred_dz, oper_i_alu_cr0__sv_pred_sz, oper_i_alu_cr0__insn, oper_i_alu_cr0__fn_unit, oper_i_alu_cr0__insn_type }; endcase end always @* begin @@ -50153,7 +55591,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope 1'h1: { \data_r0__o_ok$next , \data_r0__o$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r0__o_ok$next = 1'h0; @@ -50175,7 +55613,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope 1'h1: { \data_r1__full_cr_ok$next , \data_r1__full_cr$next } = 33'h000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r1__full_cr_ok$next = 1'h0; @@ -50197,7 +55635,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope 1'h1: { \data_r2__cr_a_ok$next , \data_r2__cr_a$next } = 5'h00; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r2__cr_a_ok$next = 1'h0; @@ -50266,7 +55704,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \alui_l_r_alui$next = \$89 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alui_l_r_alui$next = 1'h1; @@ -50275,7 +55713,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \alu_l_r_alu$next = \$91 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alu_l_r_alu$next = 1'h1; @@ -50314,7 +55752,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \prev_wr_go$next = \$21 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \prev_wr_go$next = 3'h0; @@ -50367,9 +55805,9 @@ module cyc_l(coresync_rst, s_cyc, r_cyc, q_cyc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_cyc; @@ -50395,7 +55833,7 @@ module cyc_l(coresync_rst, s_cyc, r_cyc, q_cyc, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -50538,23 +55976,23 @@ module dbg(rst, dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, c wire \$97 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *) wire \$99 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) input clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:28" *) input [6:0] core_dbg_core_dbg_dststep; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:31" *) input [6:0] core_dbg_core_dbg_maxvl; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:29" *) input [6:0] core_dbg_core_dbg_srcstep; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:27" *) input [1:0] core_dbg_core_dbg_subvl; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:26" *) input [1:0] core_dbg_core_dbg_svstep; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:30" *) input [6:0] core_dbg_core_dbg_vl; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:17" *) input [63:0] core_dbg_msr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:16" *) input [63:0] core_dbg_pc; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:99" *) output core_rst_o; @@ -50641,7 +56079,7 @@ module dbg(rst, dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, c wire [63:0] log_dmi_data; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:120" *) wire [31:0] log_write_addr_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) input rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:135" *) wire [63:0] stat_reg; @@ -50774,7 +56212,7 @@ module dbg(rst, dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, c always @* begin if (\initial ) begin end \dmi_req_i_1$next = dmi_req_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \dmi_req_i_1$next = 1'h0; @@ -50824,7 +56262,7 @@ module dbg(rst, dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, c 1'h1: \terminated$next = 1'h1; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \terminated$next = 1'h0; @@ -50868,7 +56306,7 @@ module dbg(rst, dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, c 1'h1: \stopping$next = 1'h1; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \stopping$next = 1'h0; @@ -50896,7 +56334,7 @@ module dbg(rst, dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, c endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \gspr_index$next = 7'h00; @@ -50930,7 +56368,7 @@ module dbg(rst, dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, c 2'b1?: \log_dmi_addr$next [1:0] = \$117 [1:0]; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \log_dmi_addr$next = 32'd0; @@ -50939,7 +56377,7 @@ module dbg(rst, dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, c always @* begin if (\initial ) begin end \dmi_read_log_data_1$next = dmi_read_log_data; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \dmi_read_log_data_1$next = 1'h0; @@ -50948,7 +56386,7 @@ module dbg(rst, dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, c always @* begin if (\initial ) begin end \dmi_read_log_data$next = \$122 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \dmi_read_log_data$next = 1'h0; @@ -51041,7 +56479,7 @@ module dbg(rst, dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, c endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \do_step$next = 1'h0; @@ -51071,7 +56509,7 @@ module dbg(rst, dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, c endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \do_reset$next = 1'h0; @@ -51101,7 +56539,7 @@ module dbg(rst, dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, c endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \do_icreset$next = 1'h0; @@ -51135,7 +56573,7 @@ module dbg(rst, dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, c 2'b1?: \do_dmi_log_rd$next = 1'h1; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \do_dmi_log_rd$next = 1'h0; @@ -51156,75 +56594,91 @@ endmodule (* generator = "nMigen" *) module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_function_unit, ALU_in1_sel, ALU_in2_sel, ALU_cr_out, ALU_ldst_len, ALU_inv_a, ALU_inv_out, ALU_cry_in, ALU_cry_out, ALU_is_32b, ALU_sgn, ALU_RA, ALU_SI, ALU_UI, ALU_SH32, ALU_sh, ALU_LI, ALU_Rc, ALU_OE, ALU_BD, ALU_DS, raw_opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:519" *) wire [31:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire ALU_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] ALU_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] ALU_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] ALU_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [13:0] ALU_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] ALU_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] ALU_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] ALU_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] ALU_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] ALU_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] ALU_CR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] ALU_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [13:0] ALU_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] ALU_FRA; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] ALU_FRB; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] ALU_FRC; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] ALU_FRS; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] ALU_FRT; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] ALU_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire ALU_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [23:0] ALU_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire ALU_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] ALU_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] ALU_MB32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] ALU_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] ALU_ME32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output ALU_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] ALU_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [4:0] ALU_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] ALU_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] ALU_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] ALU_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output ALU_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] ALU_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [4:0] ALU_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [15:0] ALU_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [9:0] ALU_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + reg [1:0] ALU_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] ALU_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [15:0] ALU_UI; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -51235,7 +56689,7 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [2:0] ALU_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -51244,19 +56698,25 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_cr_out; reg [2:0] ALU_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] ALU_cry_in; reg [1:0] ALU_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_cry_out; reg ALU_cry_out; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] ALU_dec19_ALU_dec19_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -51266,7 +56726,7 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec19_ALU_dec19_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -51275,40 +56735,43 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec19_ALU_dec19_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] ALU_dec19_ALU_dec19_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec19_ALU_dec19_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] ALU_dec19_ALU_dec19_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] ALU_dec19_ALU_dec19_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec19_ALU_dec19_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -51325,7 +56788,8 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] ALU_dec19_ALU_dec19_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -51402,13 +56866,15 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] ALU_dec19_ALU_dec19_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec19_ALU_dec19_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec19_ALU_dec19_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec19_ALU_dec19_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -51416,18 +56882,24 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] ALU_dec19_ALU_dec19_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] ALU_dec19_ALU_dec19_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec19_ALU_dec19_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] ALU_dec19_opcode_in; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] ALU_dec31_ALU_dec31_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -51437,7 +56909,7 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_ALU_dec31_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -51446,40 +56918,43 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_ALU_dec31_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] ALU_dec31_ALU_dec31_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_ALU_dec31_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] ALU_dec31_ALU_dec31_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] ALU_dec31_ALU_dec31_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] ALU_dec31_ALU_dec31_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -51496,7 +56971,8 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] ALU_dec31_ALU_dec31_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -51573,13 +57049,15 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] ALU_dec31_ALU_dec31_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_ALU_dec31_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_ALU_dec31_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_ALU_dec31_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -51587,43 +57065,46 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] ALU_dec31_ALU_dec31_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] ALU_dec31_ALU_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire ALU_dec31_ALU_dec31_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] ALU_dec31_opcode_in; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] ALU_function_unit; - reg [13:0] ALU_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] ALU_function_unit; + reg [14:0] ALU_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] ALU_in1_sel; reg [2:0] ALU_in1_sel; (* enum_base_type = "In2Sel" *) @@ -51641,7 +57122,8 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] ALU_in2_sel; reg [3:0] ALU_in2_sel; (* enum_base_type = "MicrOp" *) @@ -51719,16 +57201,18 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] ALU_internal_op; reg [6:0] ALU_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_inv_a; reg ALU_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_inv_out; reg ALU_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_is_32b; reg ALU_is_32b; (* enum_base_type = "LdstLen" *) @@ -51737,627 +57221,628 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] ALU_ldst_len; reg [3:0] ALU_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] ALU_rc_sel; reg [1:0] ALU_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output ALU_sgn; reg ALU_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [5:0] ALU_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire A_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire B_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [13:0] B_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] B_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] B_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire B_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQE_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQE_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] DQE_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [11:0] DQ_DQ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] DQ_PT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire DQ_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] DQ_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire DQ_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] DQ_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] DQ_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [13:0] DS_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] DS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] DX_d0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] DX_d0_d1_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DX_d1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire DX_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] D_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] D_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire D_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] D_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] D_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] EVS_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire I_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [23:0] I_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire I_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_IB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_IS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire MDS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] MDS_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] MDS_XBI_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] MDS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MDS_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MDS_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MD_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MD_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire MD_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] MD_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MD_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MD_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MD_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire M_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] SC_LEV; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] SC_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] SVL_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] SVL_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SVL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] SVL_SVi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] SVL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SVL_ms; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SVL_vs; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] TX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] TX_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] TX_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] TX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] VA_SHB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] VA_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire VC_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VC_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VC_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VC_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] VC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire VX_PS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_SIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] VX_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] VX_UIM_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] VX_UIM_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] VX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [10:0] VX_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] XFL_FLM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFL_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XFL_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XFL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XFL_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_BHRBE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFX_DUI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_DUIS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] XFX_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFX_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XL_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XL_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XL_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XL_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [14:0] XL_OC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XL_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XO_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XO_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XO_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XO_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XO_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XO_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XS_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XX2_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX2_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] XX2_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX2_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] XX2_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX2_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] XX2_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XX2_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_dc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] XX2_dc_dm_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_dm; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX3_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX3_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX3_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XX3_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX3_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX3_DM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX3_SHW; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX3_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX3_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] XX3_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] XX3_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XX3_XO_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_CX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_CX_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX4_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_CT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] X_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_DRM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_E; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_EO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_EX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_E_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_IH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] X_IMM8; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_L1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_L2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_L3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_MO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_NB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_PRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_RIC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_RM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_RO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_R_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_SP; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_SR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] X_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] X_TBR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_TH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] X_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_U; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_WC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] X_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] X_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] Z22_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] Z22_DCM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] Z22_DGM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire Z22_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] Z22_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] Z22_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire Z23_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] Z23_RMC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire Z23_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_TE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] Z23_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] all_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:479" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) output [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [5:0] opcode_switch; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:478" *) input [31:0] raw_opcode_in; - assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; + assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:519" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; ALU_dec19 ALU_dec19 ( + .ALU_dec19_SV_Ptype(ALU_dec19_ALU_dec19_SV_Ptype), .ALU_dec19_cr_in(ALU_dec19_ALU_dec19_cr_in), .ALU_dec19_cr_out(ALU_dec19_ALU_dec19_cr_out), .ALU_dec19_cry_in(ALU_dec19_ALU_dec19_cry_in), @@ -52375,6 +57860,7 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct .opcode_in(ALU_dec19_opcode_in) ); ALU_dec31 ALU_dec31 ( + .ALU_dec31_SV_Ptype(ALU_dec31_ALU_dec31_SV_Ptype), .ALU_dec31_cr_in(ALU_dec31_ALU_dec31_cr_in), .ALU_dec31_cr_out(ALU_dec31_ALU_dec31_cr_out), .ALU_dec31_cry_in(ALU_dec31_ALU_dec31_cry_in), @@ -52391,36 +57877,70 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct .ALU_dec31_sgn(ALU_dec31_ALU_dec31_sgn), .opcode_in(ALU_dec31_opcode_in) ); + always @* begin + if (\initial ) begin end + ALU_ldst_len = 4'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h13: + ALU_ldst_len = ALU_dec19_ALU_dec19_ldst_len; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h1f: + ALU_ldst_len = ALU_dec31_ALU_dec31_ldst_len; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h0c: + ALU_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h0d: + ALU_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h0e: + ALU_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h0f: + ALU_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h0b: + ALU_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h0a: + ALU_ldst_len = 4'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h08: + ALU_ldst_len = 4'h0; + endcase + end always @* begin if (\initial ) begin end ALU_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: ALU_rc_sel = ALU_dec19_ALU_dec19_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: ALU_rc_sel = ALU_dec31_ALU_dec31_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: ALU_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: ALU_rc_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: ALU_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: ALU_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: ALU_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: ALU_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: ALU_rc_sel = 2'h0; endcase @@ -52428,33 +57948,33 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct always @* begin if (\initial ) begin end ALU_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: ALU_cry_in = ALU_dec19_ALU_dec19_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: ALU_cry_in = ALU_dec31_ALU_dec31_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: ALU_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: ALU_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: ALU_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: ALU_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: ALU_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: ALU_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: ALU_cry_in = 2'h1; endcase @@ -52462,33 +57982,33 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct always @* begin if (\initial ) begin end ALU_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: ALU_inv_a = ALU_dec19_ALU_dec19_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: ALU_inv_a = ALU_dec31_ALU_dec31_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: ALU_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: ALU_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: ALU_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: ALU_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: ALU_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: ALU_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: ALU_inv_a = 1'h1; endcase @@ -52496,33 +58016,33 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct always @* begin if (\initial ) begin end ALU_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: ALU_inv_out = ALU_dec19_ALU_dec19_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: ALU_inv_out = ALU_dec31_ALU_dec31_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: ALU_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: ALU_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: ALU_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: ALU_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: ALU_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: ALU_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: ALU_inv_out = 1'h0; endcase @@ -52530,33 +58050,33 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct always @* begin if (\initial ) begin end ALU_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: ALU_cry_out = ALU_dec19_ALU_dec19_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: ALU_cry_out = ALU_dec31_ALU_dec31_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: ALU_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: ALU_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: ALU_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: ALU_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: ALU_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: ALU_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: ALU_cry_out = 1'h1; endcase @@ -52564,33 +58084,33 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct always @* begin if (\initial ) begin end ALU_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: ALU_is_32b = ALU_dec19_ALU_dec19_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: ALU_is_32b = ALU_dec31_ALU_dec31_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: ALU_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: ALU_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: ALU_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: ALU_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: ALU_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: ALU_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: ALU_is_32b = 1'h0; endcase @@ -52598,135 +58118,169 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct always @* begin if (\initial ) begin end ALU_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: ALU_sgn = ALU_dec19_ALU_dec19_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: ALU_sgn = ALU_dec31_ALU_dec31_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: ALU_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: ALU_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: ALU_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: ALU_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: ALU_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: ALU_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: ALU_sgn = 1'h0; endcase end always @* begin if (\initial ) begin end - ALU_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + ALU_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: ALU_function_unit = ALU_dec19_ALU_dec19_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: ALU_function_unit = ALU_dec31_ALU_dec31_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: - ALU_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: - ALU_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: - ALU_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: - ALU_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: - ALU_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: - ALU_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + ALU_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: - ALU_function_unit = 14'h0002; + ALU_function_unit = 15'h0002; endcase end always @* begin if (\initial ) begin end ALU_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: ALU_internal_op = ALU_dec19_ALU_dec19_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: ALU_internal_op = ALU_dec31_ALU_dec31_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: ALU_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: ALU_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: ALU_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: ALU_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: ALU_internal_op = 7'h0a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: ALU_internal_op = 7'h0a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: ALU_internal_op = 7'h02; endcase end + always @* begin + if (\initial ) begin end + ALU_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h13: + ALU_SV_Ptype = ALU_dec19_ALU_dec19_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h1f: + ALU_SV_Ptype = ALU_dec31_ALU_dec31_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h0c: + ALU_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h0d: + ALU_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h0e: + ALU_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h0f: + ALU_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h0b: + ALU_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h0a: + ALU_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h08: + ALU_SV_Ptype = 2'h2; + endcase + end always @* begin if (\initial ) begin end ALU_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: ALU_in1_sel = ALU_dec19_ALU_dec19_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: ALU_in1_sel = ALU_dec31_ALU_dec31_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: ALU_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: ALU_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: ALU_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: ALU_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: ALU_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: ALU_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: ALU_in1_sel = 3'h1; endcase @@ -52734,33 +58288,33 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct always @* begin if (\initial ) begin end ALU_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: ALU_in2_sel = ALU_dec19_ALU_dec19_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: ALU_in2_sel = ALU_dec31_ALU_dec31_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: ALU_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: ALU_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: ALU_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: ALU_in2_sel = 4'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: ALU_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: ALU_in2_sel = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: ALU_in2_sel = 4'h3; endcase @@ -52768,33 +58322,33 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct always @* begin if (\initial ) begin end ALU_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: ALU_cr_in = ALU_dec19_ALU_dec19_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: ALU_cr_in = ALU_dec31_ALU_dec31_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: ALU_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: ALU_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: ALU_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: ALU_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: ALU_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: ALU_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: ALU_cr_in = 3'h0; endcase @@ -52802,71 +58356,37 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct always @* begin if (\initial ) begin end ALU_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: ALU_cr_out = ALU_dec19_ALU_dec19_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: ALU_cr_out = ALU_dec31_ALU_dec31_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: ALU_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: ALU_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: ALU_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: ALU_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: ALU_cr_out = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: ALU_cr_out = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: ALU_cr_out = 3'h0; endcase end - always @* begin - if (\initial ) begin end - ALU_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) - casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h13: - ALU_ldst_len = ALU_dec19_ALU_dec19_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h1f: - ALU_ldst_len = ALU_dec31_ALU_dec31_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h0c: - ALU_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h0d: - ALU_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h0e: - ALU_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h0f: - ALU_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h0b: - ALU_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h0a: - ALU_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h08: - ALU_ldst_len = 4'h0; - endcase - end assign VC_XO = opcode_in[9:0]; assign VC_VRT = opcode_in[25:21]; assign VC_VRB = opcode_in[15:11]; @@ -53199,6 +58719,11 @@ module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_funct assign ALU_RA = opcode_in[20:16]; assign ALU_RT = opcode_in[25:21]; assign ALU_RS = opcode_in[25:21]; + assign ALU_FRC = opcode_in[10:6]; + assign ALU_FRB = opcode_in[15:11]; + assign ALU_FRA = opcode_in[20:16]; + assign ALU_FRT = opcode_in[25:21]; + assign ALU_FRS = opcode_in[25:21]; assign ALU_PO = opcode_in[31:26]; assign opcode_in = \$1 ; assign ALU_dec31_opcode_in = opcode_in; @@ -53210,105 +58735,121 @@ endmodule (* generator = "nMigen" *) module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_function_unit, CR_cr_out, CR_Rc, CR_OE, raw_opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:519" *) wire [31:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire A_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire B_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [13:0] B_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] B_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] B_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire B_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire CR_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] CR_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] CR_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] CR_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] CR_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] CR_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] CR_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] CR_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] CR_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] CR_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] CR_CR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] CR_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] CR_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] CR_FRA; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] CR_FRB; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] CR_FRC; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] CR_FRS; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] CR_FRT; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] CR_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire CR_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [23:0] CR_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire CR_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] CR_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] CR_MB32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] CR_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] CR_ME32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output CR_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] CR_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] CR_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] CR_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] CR_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] CR_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output CR_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] CR_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] CR_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] CR_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [9:0] CR_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + reg [1:0] CR_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] CR_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] CR_UI; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -53319,7 +58860,7 @@ module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_fun (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [2:0] CR_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -53328,9 +58869,15 @@ module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_fun (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] CR_cr_out; reg [2:0] CR_cr_out; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] CR_dec19_CR_dec19_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -53340,7 +58887,7 @@ module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_fun (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] CR_dec19_CR_dec19_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -53349,25 +58896,26 @@ module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_fun (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] CR_dec19_CR_dec19_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] CR_dec19_CR_dec19_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] CR_dec19_CR_dec19_function_unit; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -53443,16 +58991,24 @@ module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_fun (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] CR_dec19_CR_dec19_internal_op; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] CR_dec19_CR_dec19_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] CR_dec19_opcode_in; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] CR_dec31_CR_dec31_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -53462,7 +59018,7 @@ module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_fun (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] CR_dec31_CR_dec31_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -53471,25 +59027,26 @@ module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_fun (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] CR_dec31_CR_dec31_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] CR_dec31_CR_dec31_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] CR_dec31_CR_dec31_function_unit; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -53565,34 +59122,37 @@ module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_fun (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] CR_dec31_CR_dec31_internal_op; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] CR_dec31_CR_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] CR_dec31_opcode_in; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] CR_function_unit; - reg [13:0] CR_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] CR_function_unit; + reg [14:0] CR_function_unit; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -53668,594 +59228,597 @@ module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_fun (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] CR_internal_op; reg [6:0] CR_internal_op; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] CR_rc_sel; reg [1:0] CR_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] CR_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQE_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQE_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] DQE_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [11:0] DQ_DQ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] DQ_PT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire DQ_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] DQ_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire DQ_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] DQ_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] DQ_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [13:0] DS_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] DS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] DX_d0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] DX_d0_d1_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DX_d1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire DX_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] D_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] D_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire D_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] D_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] D_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] EVS_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire I_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [23:0] I_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire I_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_IB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_IS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire MDS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] MDS_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] MDS_XBI_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] MDS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MDS_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MDS_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MD_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MD_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire MD_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] MD_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MD_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MD_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MD_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire M_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] SC_LEV; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] SC_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] SVL_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] SVL_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SVL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] SVL_SVi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] SVL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SVL_ms; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SVL_vs; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] TX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] TX_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] TX_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] TX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] VA_SHB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] VA_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire VC_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VC_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VC_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VC_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] VC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire VX_PS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_SIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] VX_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] VX_UIM_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] VX_UIM_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] VX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [10:0] VX_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] XFL_FLM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFL_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XFL_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XFL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XFL_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_BHRBE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFX_DUI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_DUIS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] XFX_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFX_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XL_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XL_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XL_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XL_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [14:0] XL_OC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XL_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XO_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XO_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XO_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XO_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XO_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XO_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XS_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XX2_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX2_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] XX2_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX2_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] XX2_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX2_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] XX2_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XX2_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_dc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] XX2_dc_dm_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_dm; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX3_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX3_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX3_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XX3_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX3_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX3_DM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX3_SHW; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX3_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX3_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] XX3_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] XX3_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XX3_XO_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_CX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_CX_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX4_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_CT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] X_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_DRM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_E; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_EO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_EX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_E_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_IH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] X_IMM8; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_L1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_L2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_L3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_MO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_NB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_PRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_RIC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_RM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_RO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_R_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_SP; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_SR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] X_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] X_TBR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_TH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] X_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_U; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_WC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] X_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] X_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] Z22_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] Z22_DCM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] Z22_DGM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire Z22_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] Z22_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] Z22_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire Z23_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] Z23_RMC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire Z23_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_TE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] Z23_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] all_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:479" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) output [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [5:0] opcode_switch; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:478" *) input [31:0] raw_opcode_in; - assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; + assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:519" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; CR_dec19 CR_dec19 ( + .CR_dec19_SV_Ptype(CR_dec19_CR_dec19_SV_Ptype), .CR_dec19_cr_in(CR_dec19_CR_dec19_cr_in), .CR_dec19_cr_out(CR_dec19_CR_dec19_cr_out), .CR_dec19_function_unit(CR_dec19_CR_dec19_function_unit), @@ -54264,6 +59827,7 @@ module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_fun .opcode_in(CR_dec19_opcode_in) ); CR_dec31 CR_dec31 ( + .CR_dec31_SV_Ptype(CR_dec31_CR_dec31_SV_Ptype), .CR_dec31_cr_in(CR_dec31_CR_dec31_cr_in), .CR_dec31_cr_out(CR_dec31_CR_dec31_cr_out), .CR_dec31_function_unit(CR_dec31_CR_dec31_function_unit), @@ -54273,13 +59837,13 @@ module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_fun ); always @* begin if (\initial ) begin end - CR_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + CR_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: CR_function_unit = CR_dec19_CR_dec19_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: CR_function_unit = CR_dec31_CR_dec31_function_unit; endcase @@ -54287,25 +59851,38 @@ module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_fun always @* begin if (\initial ) begin end CR_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: CR_internal_op = CR_dec19_CR_dec19_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: CR_internal_op = CR_dec31_CR_dec31_internal_op; endcase end + always @* begin + if (\initial ) begin end + CR_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h13: + CR_SV_Ptype = CR_dec19_CR_dec19_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h1f: + CR_SV_Ptype = CR_dec31_CR_dec31_SV_Ptype; + endcase + end always @* begin if (\initial ) begin end CR_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: CR_cr_in = CR_dec19_CR_dec19_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: CR_cr_in = CR_dec31_CR_dec31_cr_in; endcase @@ -54313,12 +59890,12 @@ module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_fun always @* begin if (\initial ) begin end CR_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: CR_cr_out = CR_dec19_CR_dec19_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: CR_cr_out = CR_dec31_CR_dec31_cr_out; endcase @@ -54326,12 +59903,12 @@ module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_fun always @* begin if (\initial ) begin end CR_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: CR_rc_sel = CR_dec19_CR_dec19_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: CR_rc_sel = CR_dec31_CR_dec31_rc_sel; endcase @@ -54668,6 +60245,11 @@ module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_fun assign CR_RA = opcode_in[20:16]; assign CR_RT = opcode_in[25:21]; assign CR_RS = opcode_in[25:21]; + assign CR_FRC = opcode_in[10:6]; + assign CR_FRB = opcode_in[15:11]; + assign CR_FRA = opcode_in[20:16]; + assign CR_FRT = opcode_in[25:21]; + assign CR_FRS = opcode_in[25:21]; assign CR_PO = opcode_in[31:26]; assign opcode_in = \$1 ; assign CR_dec31_opcode_in = opcode_in; @@ -54679,95 +60261,111 @@ endmodule (* generator = "nMigen" *) module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH_SPR, BRANCH_function_unit, BRANCH_in2_sel, BRANCH_cr_out, BRANCH_is_32b, BRANCH_lk, BRANCH_LK, BRANCH_SI, BRANCH_UI, BRANCH_SH32, BRANCH_sh, BRANCH_LI, BRANCH_Rc, BRANCH_OE, BRANCH_BD, BRANCH_DS, raw_opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:519" *) wire [31:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire A_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire BRANCH_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] BRANCH_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] BRANCH_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] BRANCH_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [13:0] BRANCH_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] BRANCH_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] BRANCH_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] BRANCH_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] BRANCH_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] BRANCH_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] BRANCH_CR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] BRANCH_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [13:0] BRANCH_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] BRANCH_FRA; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] BRANCH_FRB; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] BRANCH_FRC; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] BRANCH_FRS; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] BRANCH_FRT; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] BRANCH_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire BRANCH_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [23:0] BRANCH_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output BRANCH_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] BRANCH_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] BRANCH_MB32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] BRANCH_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] BRANCH_ME32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output BRANCH_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] BRANCH_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] BRANCH_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] BRANCH_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] BRANCH_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] BRANCH_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output BRANCH_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] BRANCH_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [4:0] BRANCH_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [15:0] BRANCH_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [9:0] BRANCH_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + reg [1:0] BRANCH_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] BRANCH_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [15:0] BRANCH_UI; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -54778,7 +60376,7 @@ module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [2:0] BRANCH_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -54787,9 +60385,15 @@ module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] BRANCH_cr_out; reg [2:0] BRANCH_cr_out; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] BRANCH_dec19_BRANCH_dec19_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -54799,7 +60403,7 @@ module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] BRANCH_dec19_BRANCH_dec19_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -54808,25 +60412,26 @@ module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] BRANCH_dec19_BRANCH_dec19_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] BRANCH_dec19_BRANCH_dec19_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] BRANCH_dec19_BRANCH_dec19_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -54842,7 +60447,8 @@ module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] BRANCH_dec19_BRANCH_dec19_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -54919,38 +60525,41 @@ module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] BRANCH_dec19_BRANCH_dec19_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire BRANCH_dec19_BRANCH_dec19_is_32b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire BRANCH_dec19_BRANCH_dec19_lk; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] BRANCH_dec19_BRANCH_dec19_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] BRANCH_dec19_opcode_in; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] BRANCH_function_unit; - reg [13:0] BRANCH_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] BRANCH_function_unit; + reg [14:0] BRANCH_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -54966,7 +60575,8 @@ module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] BRANCH_in2_sel; reg [3:0] BRANCH_in2_sel; (* enum_base_type = "MicrOp" *) @@ -55044,610 +60654,613 @@ module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] BRANCH_internal_op; reg [6:0] BRANCH_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output BRANCH_is_32b; reg BRANCH_is_32b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output BRANCH_lk; reg BRANCH_lk; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] BRANCH_rc_sel; reg [1:0] BRANCH_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [5:0] BRANCH_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire B_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [13:0] B_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] B_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] B_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire B_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQE_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQE_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] DQE_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [11:0] DQ_DQ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] DQ_PT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire DQ_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] DQ_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire DQ_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] DQ_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] DQ_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [13:0] DS_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] DS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] DX_d0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] DX_d0_d1_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DX_d1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire DX_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] D_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] D_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire D_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] D_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] D_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] EVS_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire I_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [23:0] I_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire I_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_IB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_IS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire MDS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] MDS_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] MDS_XBI_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] MDS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MDS_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MDS_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MD_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MD_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire MD_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] MD_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MD_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MD_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MD_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire M_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] SC_LEV; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] SC_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] SVL_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] SVL_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SVL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] SVL_SVi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] SVL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SVL_ms; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SVL_vs; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] TX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] TX_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] TX_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] TX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] VA_SHB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] VA_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire VC_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VC_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VC_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VC_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] VC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire VX_PS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_SIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] VX_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] VX_UIM_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] VX_UIM_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] VX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [10:0] VX_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] XFL_FLM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFL_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XFL_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XFL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XFL_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_BHRBE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFX_DUI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_DUIS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] XFX_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFX_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XL_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XL_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XL_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XL_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [14:0] XL_OC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XL_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XO_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XO_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XO_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XO_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XO_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XO_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XS_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XX2_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX2_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] XX2_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX2_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] XX2_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX2_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] XX2_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XX2_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_dc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] XX2_dc_dm_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_dm; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX3_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX3_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX3_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XX3_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX3_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX3_DM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX3_SHW; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX3_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX3_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] XX3_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] XX3_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XX3_XO_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_CX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_CX_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX4_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_CT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] X_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_DRM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_E; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_EO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_EX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_E_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_IH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] X_IMM8; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_L1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_L2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_L3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_MO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_NB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_PRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_RIC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_RM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_RO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_R_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_SP; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_SR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] X_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] X_TBR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_TH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] X_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_U; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_WC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] X_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] X_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] Z22_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] Z22_DCM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] Z22_DGM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire Z22_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] Z22_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] Z22_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire Z23_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] Z23_RMC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire Z23_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_TE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] Z23_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] all_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:479" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) output [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [5:0] opcode_switch; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:478" *) input [31:0] raw_opcode_in; - assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; + assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:519" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; BRANCH_dec19 BRANCH_dec19 ( + .BRANCH_dec19_SV_Ptype(BRANCH_dec19_BRANCH_dec19_SV_Ptype), .BRANCH_dec19_cr_in(BRANCH_dec19_BRANCH_dec19_cr_in), .BRANCH_dec19_cr_out(BRANCH_dec19_BRANCH_dec19_cr_out), .BRANCH_dec19_function_unit(BRANCH_dec19_BRANCH_dec19_function_unit), @@ -55660,48 +61273,80 @@ module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH ); always @* begin if (\initial ) begin end - BRANCH_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + BRANCH_lk = 1'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h13: + BRANCH_lk = BRANCH_dec19_BRANCH_dec19_lk; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h12: + BRANCH_lk = 1'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h10: + BRANCH_lk = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + BRANCH_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: BRANCH_function_unit = BRANCH_dec19_BRANCH_dec19_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: - BRANCH_function_unit = 14'h0020; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + BRANCH_function_unit = 15'h0020; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: - BRANCH_function_unit = 14'h0020; + BRANCH_function_unit = 15'h0020; endcase end always @* begin if (\initial ) begin end BRANCH_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: BRANCH_internal_op = BRANCH_dec19_BRANCH_dec19_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: BRANCH_internal_op = 7'h06; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: BRANCH_internal_op = 7'h07; endcase end + always @* begin + if (\initial ) begin end + BRANCH_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h13: + BRANCH_SV_Ptype = BRANCH_dec19_BRANCH_dec19_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h12: + BRANCH_SV_Ptype = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h10: + BRANCH_SV_Ptype = 2'h0; + endcase + end always @* begin if (\initial ) begin end BRANCH_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: BRANCH_in2_sel = BRANCH_dec19_BRANCH_dec19_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: BRANCH_in2_sel = 4'h6; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: BRANCH_in2_sel = 4'h7; endcase @@ -55709,15 +61354,15 @@ module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH always @* begin if (\initial ) begin end BRANCH_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: BRANCH_cr_in = BRANCH_dec19_BRANCH_dec19_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: BRANCH_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: BRANCH_cr_in = 3'h2; endcase @@ -55725,15 +61370,15 @@ module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH always @* begin if (\initial ) begin end BRANCH_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: BRANCH_cr_out = BRANCH_dec19_BRANCH_dec19_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: BRANCH_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: BRANCH_cr_out = 3'h0; endcase @@ -55741,15 +61386,15 @@ module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH always @* begin if (\initial ) begin end BRANCH_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: BRANCH_rc_sel = BRANCH_dec19_BRANCH_dec19_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: BRANCH_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: BRANCH_rc_sel = 2'h0; endcase @@ -55757,35 +61402,19 @@ module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH always @* begin if (\initial ) begin end BRANCH_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: BRANCH_is_32b = BRANCH_dec19_BRANCH_dec19_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: BRANCH_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: BRANCH_is_32b = 1'h0; endcase end - always @* begin - if (\initial ) begin end - BRANCH_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) - casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h13: - BRANCH_lk = BRANCH_dec19_BRANCH_dec19_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h12: - BRANCH_lk = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h10: - BRANCH_lk = 1'h1; - endcase - end assign VC_XO = opcode_in[9:0]; assign VC_VRT = opcode_in[25:21]; assign VC_VRB = opcode_in[15:11]; @@ -56118,6 +61747,11 @@ module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH assign BRANCH_RA = opcode_in[20:16]; assign BRANCH_RT = opcode_in[25:21]; assign BRANCH_RS = opcode_in[25:21]; + assign BRANCH_FRC = opcode_in[10:6]; + assign BRANCH_FRB = opcode_in[15:11]; + assign BRANCH_FRA = opcode_in[20:16]; + assign BRANCH_FRT = opcode_in[25:21]; + assign BRANCH_FRS = opcode_in[25:21]; assign BRANCH_PO = opcode_in[31:26]; assign opcode_in = \$1 ; assign BRANCH_dec19_opcode_in = opcode_in; @@ -56128,195 +61762,211 @@ endmodule (* generator = "nMigen" *) module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGICAL_SPR, LOGICAL_function_unit, LOGICAL_in1_sel, LOGICAL_in2_sel, LOGICAL_cr_out, LOGICAL_ldst_len, LOGICAL_inv_a, LOGICAL_inv_out, LOGICAL_cry_in, LOGICAL_cry_out, LOGICAL_is_32b, LOGICAL_sgn, LOGICAL_RA, LOGICAL_SI, LOGICAL_UI, LOGICAL_SH32, LOGICAL_sh, LOGICAL_LI, LOGICAL_Rc, LOGICAL_OE, LOGICAL_BD, LOGICAL_DS, raw_opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:519" *) wire [31:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire A_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire B_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [13:0] B_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] B_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] B_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire B_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQE_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQE_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] DQE_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [11:0] DQ_DQ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] DQ_PT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire DQ_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] DQ_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire DQ_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] DQ_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] DQ_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [13:0] DS_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] DS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] DX_d0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] DX_d0_d1_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DX_d1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire DX_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] D_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] D_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire D_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] D_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] D_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] EVS_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire I_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [23:0] I_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire I_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire LOGICAL_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] LOGICAL_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] LOGICAL_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] LOGICAL_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [13:0] LOGICAL_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] LOGICAL_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] LOGICAL_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] LOGICAL_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] LOGICAL_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] LOGICAL_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] LOGICAL_CR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] LOGICAL_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [13:0] LOGICAL_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] LOGICAL_FRA; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] LOGICAL_FRB; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] LOGICAL_FRC; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] LOGICAL_FRS; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] LOGICAL_FRT; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] LOGICAL_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire LOGICAL_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [23:0] LOGICAL_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire LOGICAL_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] LOGICAL_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] LOGICAL_MB32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] LOGICAL_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] LOGICAL_ME32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output LOGICAL_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] LOGICAL_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [4:0] LOGICAL_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] LOGICAL_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] LOGICAL_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] LOGICAL_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output LOGICAL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] LOGICAL_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [4:0] LOGICAL_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [15:0] LOGICAL_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [9:0] LOGICAL_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + reg [1:0] LOGICAL_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] LOGICAL_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [15:0] LOGICAL_UI; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -56327,7 +61977,7 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [2:0] LOGICAL_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -56336,19 +61986,25 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LOGICAL_cr_out; reg [2:0] LOGICAL_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LOGICAL_cry_in; reg [1:0] LOGICAL_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_cry_out; reg LOGICAL_cry_out; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] LOGICAL_dec31_LOGICAL_dec31_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -56358,7 +62014,7 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LOGICAL_dec31_LOGICAL_dec31_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -56367,40 +62023,43 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LOGICAL_dec31_LOGICAL_dec31_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LOGICAL_dec31_LOGICAL_dec31_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LOGICAL_dec31_LOGICAL_dec31_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] LOGICAL_dec31_LOGICAL_dec31_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] LOGICAL_dec31_LOGICAL_dec31_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LOGICAL_dec31_LOGICAL_dec31_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -56417,7 +62076,8 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LOGICAL_dec31_LOGICAL_dec31_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -56494,13 +62154,15 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] LOGICAL_dec31_LOGICAL_dec31_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LOGICAL_dec31_LOGICAL_dec31_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LOGICAL_dec31_LOGICAL_dec31_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LOGICAL_dec31_LOGICAL_dec31_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -56508,43 +62170,46 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LOGICAL_dec31_LOGICAL_dec31_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LOGICAL_dec31_LOGICAL_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LOGICAL_dec31_LOGICAL_dec31_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] LOGICAL_dec31_opcode_in; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] LOGICAL_function_unit; - reg [13:0] LOGICAL_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] LOGICAL_function_unit; + reg [14:0] LOGICAL_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LOGICAL_in1_sel; reg [2:0] LOGICAL_in1_sel; (* enum_base_type = "In2Sel" *) @@ -56562,7 +62227,8 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LOGICAL_in2_sel; reg [3:0] LOGICAL_in2_sel; (* enum_base_type = "MicrOp" *) @@ -56640,16 +62306,18 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] LOGICAL_internal_op; reg [6:0] LOGICAL_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_inv_a; reg LOGICAL_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_inv_out; reg LOGICAL_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_is_32b; reg LOGICAL_is_32b; (* enum_base_type = "LdstLen" *) @@ -56658,507 +62326,508 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LOGICAL_ldst_len; reg [3:0] LOGICAL_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LOGICAL_rc_sel; reg [1:0] LOGICAL_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LOGICAL_sgn; reg LOGICAL_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [5:0] LOGICAL_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_IB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_IS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire MDS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] MDS_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] MDS_XBI_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] MDS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MDS_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MDS_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MD_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MD_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire MD_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] MD_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MD_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MD_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MD_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire M_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] SC_LEV; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] SC_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] SVL_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] SVL_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SVL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] SVL_SVi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] SVL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SVL_ms; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SVL_vs; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] TX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] TX_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] TX_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] TX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] VA_SHB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] VA_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire VC_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VC_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VC_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VC_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] VC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire VX_PS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_SIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] VX_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] VX_UIM_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] VX_UIM_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] VX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [10:0] VX_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] XFL_FLM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFL_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XFL_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XFL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XFL_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_BHRBE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFX_DUI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_DUIS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] XFX_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFX_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XL_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XL_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XL_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XL_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [14:0] XL_OC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XL_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XO_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XO_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XO_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XO_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XO_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XO_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XS_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XX2_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX2_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] XX2_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX2_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] XX2_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX2_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] XX2_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XX2_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_dc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] XX2_dc_dm_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_dm; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX3_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX3_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX3_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XX3_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX3_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX3_DM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX3_SHW; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX3_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX3_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] XX3_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] XX3_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XX3_XO_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_CX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_CX_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX4_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_CT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] X_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_DRM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_E; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_EO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_EX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_E_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_IH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] X_IMM8; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_L1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_L2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_L3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_MO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_NB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_PRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_RIC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_RM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_RO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_R_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_SP; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_SR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] X_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] X_TBR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_TH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] X_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_U; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_WC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] X_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] X_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] Z22_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] Z22_DCM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] Z22_DGM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire Z22_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] Z22_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] Z22_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire Z23_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] Z23_RMC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire Z23_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_TE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] Z23_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] all_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:479" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) output [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [5:0] opcode_switch; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:478" *) input [31:0] raw_opcode_in; - assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; + assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:519" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; LOGICAL_dec31 LOGICAL_dec31 ( + .LOGICAL_dec31_SV_Ptype(LOGICAL_dec31_LOGICAL_dec31_SV_Ptype), .LOGICAL_dec31_cr_in(LOGICAL_dec31_LOGICAL_dec31_cr_in), .LOGICAL_dec31_cr_out(LOGICAL_dec31_LOGICAL_dec31_cr_out), .LOGICAL_dec31_cry_in(LOGICAL_dec31_LOGICAL_dec31_cry_in), @@ -57175,30 +62844,58 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI .LOGICAL_dec31_sgn(LOGICAL_dec31_LOGICAL_dec31_sgn), .opcode_in(LOGICAL_dec31_opcode_in) ); + always @* begin + if (\initial ) begin end + LOGICAL_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h1f: + LOGICAL_rc_sel = LOGICAL_dec31_LOGICAL_dec31_rc_sel; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h1c: + LOGICAL_rc_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h1d: + LOGICAL_rc_sel = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h18: + LOGICAL_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h19: + LOGICAL_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h1a: + LOGICAL_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h1b: + LOGICAL_rc_sel = 2'h0; + endcase + end always @* begin if (\initial ) begin end LOGICAL_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: LOGICAL_cry_in = LOGICAL_dec31_LOGICAL_dec31_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: LOGICAL_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: LOGICAL_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: LOGICAL_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: LOGICAL_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: LOGICAL_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: LOGICAL_cry_in = 2'h0; endcase @@ -57206,27 +62903,27 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI always @* begin if (\initial ) begin end LOGICAL_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: LOGICAL_inv_a = LOGICAL_dec31_LOGICAL_dec31_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: LOGICAL_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: LOGICAL_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: LOGICAL_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: LOGICAL_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: LOGICAL_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: LOGICAL_inv_a = 1'h0; endcase @@ -57234,27 +62931,27 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI always @* begin if (\initial ) begin end LOGICAL_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: LOGICAL_inv_out = LOGICAL_dec31_LOGICAL_dec31_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: LOGICAL_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: LOGICAL_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: LOGICAL_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: LOGICAL_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: LOGICAL_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: LOGICAL_inv_out = 1'h0; endcase @@ -57262,27 +62959,27 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI always @* begin if (\initial ) begin end LOGICAL_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: LOGICAL_cry_out = LOGICAL_dec31_LOGICAL_dec31_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: LOGICAL_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: LOGICAL_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: LOGICAL_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: LOGICAL_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: LOGICAL_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: LOGICAL_cry_out = 1'h0; endcase @@ -57290,27 +62987,27 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI always @* begin if (\initial ) begin end LOGICAL_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: LOGICAL_is_32b = LOGICAL_dec31_LOGICAL_dec31_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: LOGICAL_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: LOGICAL_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: LOGICAL_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: LOGICAL_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: LOGICAL_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: LOGICAL_is_32b = 1'h0; endcase @@ -57318,111 +63015,139 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI always @* begin if (\initial ) begin end LOGICAL_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: LOGICAL_sgn = LOGICAL_dec31_LOGICAL_dec31_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: LOGICAL_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: LOGICAL_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: LOGICAL_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: LOGICAL_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: LOGICAL_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: LOGICAL_sgn = 1'h0; endcase end always @* begin if (\initial ) begin end - LOGICAL_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + LOGICAL_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: LOGICAL_function_unit = LOGICAL_dec31_LOGICAL_dec31_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: - LOGICAL_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LOGICAL_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: - LOGICAL_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LOGICAL_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: - LOGICAL_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LOGICAL_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: - LOGICAL_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LOGICAL_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: - LOGICAL_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LOGICAL_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: - LOGICAL_function_unit = 14'h0010; + LOGICAL_function_unit = 15'h0010; endcase end always @* begin if (\initial ) begin end LOGICAL_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: LOGICAL_internal_op = LOGICAL_dec31_LOGICAL_dec31_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: LOGICAL_internal_op = 7'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: LOGICAL_internal_op = 7'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: LOGICAL_internal_op = 7'h35; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: LOGICAL_internal_op = 7'h35; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: LOGICAL_internal_op = 7'h43; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: LOGICAL_internal_op = 7'h43; endcase end + always @* begin + if (\initial ) begin end + LOGICAL_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h1f: + LOGICAL_SV_Ptype = LOGICAL_dec31_LOGICAL_dec31_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h1c: + LOGICAL_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h1d: + LOGICAL_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h18: + LOGICAL_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h19: + LOGICAL_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h1a: + LOGICAL_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h1b: + LOGICAL_SV_Ptype = 2'h2; + endcase + end always @* begin if (\initial ) begin end LOGICAL_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: LOGICAL_in1_sel = LOGICAL_dec31_LOGICAL_dec31_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: LOGICAL_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: LOGICAL_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: LOGICAL_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: LOGICAL_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: LOGICAL_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: LOGICAL_in1_sel = 3'h4; endcase @@ -57430,27 +63155,27 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI always @* begin if (\initial ) begin end LOGICAL_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: LOGICAL_in2_sel = LOGICAL_dec31_LOGICAL_dec31_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: LOGICAL_in2_sel = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: LOGICAL_in2_sel = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: LOGICAL_in2_sel = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: LOGICAL_in2_sel = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: LOGICAL_in2_sel = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: LOGICAL_in2_sel = 4'h4; endcase @@ -57458,27 +63183,27 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI always @* begin if (\initial ) begin end LOGICAL_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: LOGICAL_cr_in = LOGICAL_dec31_LOGICAL_dec31_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: LOGICAL_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: LOGICAL_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: LOGICAL_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: LOGICAL_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: LOGICAL_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: LOGICAL_cr_in = 3'h0; endcase @@ -57486,27 +63211,27 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI always @* begin if (\initial ) begin end LOGICAL_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: LOGICAL_cr_out = LOGICAL_dec31_LOGICAL_dec31_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: LOGICAL_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: LOGICAL_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: LOGICAL_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: LOGICAL_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: LOGICAL_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: LOGICAL_cr_out = 3'h0; endcase @@ -57514,59 +63239,31 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI always @* begin if (\initial ) begin end LOGICAL_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: LOGICAL_ldst_len = LOGICAL_dec31_LOGICAL_dec31_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: LOGICAL_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: LOGICAL_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: LOGICAL_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: LOGICAL_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: LOGICAL_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: LOGICAL_ldst_len = 4'h0; endcase end - always @* begin - if (\initial ) begin end - LOGICAL_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) - casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h1f: - LOGICAL_rc_sel = LOGICAL_dec31_LOGICAL_dec31_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h1c: - LOGICAL_rc_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h1d: - LOGICAL_rc_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h18: - LOGICAL_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h19: - LOGICAL_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h1a: - LOGICAL_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h1b: - LOGICAL_rc_sel = 2'h0; - endcase - end assign VC_XO = opcode_in[9:0]; assign VC_VRT = opcode_in[25:21]; assign VC_VRB = opcode_in[15:11]; @@ -57899,6 +63596,11 @@ module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGI assign LOGICAL_RA = opcode_in[20:16]; assign LOGICAL_RT = opcode_in[25:21]; assign LOGICAL_RS = opcode_in[25:21]; + assign LOGICAL_FRC = opcode_in[10:6]; + assign LOGICAL_FRB = opcode_in[15:11]; + assign LOGICAL_FRA = opcode_in[20:16]; + assign LOGICAL_FRT = opcode_in[25:21]; + assign LOGICAL_FRS = opcode_in[25:21]; assign LOGICAL_PO = opcode_in[31:26]; assign opcode_in = \$1 ; assign LOGICAL_dec31_opcode_in = opcode_in; @@ -57909,251 +63611,267 @@ endmodule (* generator = "nMigen" *) module \dec$150 (bigendian, opcode_in, SPR_rc_sel, SPR_internal_op, SPR_SPR, SPR_function_unit, SPR_cr_out, SPR_is_32b, SPR_Rc, SPR_OE, raw_opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:519" *) wire [31:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire A_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire B_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [13:0] B_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] B_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] B_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire B_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQE_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQE_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] DQE_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [11:0] DQ_DQ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] DQ_PT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire DQ_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] DQ_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire DQ_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] DQ_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] DQ_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [13:0] DS_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] DS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] DX_d0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] DX_d0_d1_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DX_d1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire DX_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] D_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] D_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire D_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] D_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] D_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] EVS_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire I_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [23:0] I_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire I_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_IB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_IS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire MDS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] MDS_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] MDS_XBI_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] MDS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MDS_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MDS_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MD_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MD_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire MD_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] MD_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MD_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MD_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MD_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire M_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] SC_LEV; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] SC_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SPR_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SPR_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SPR_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SPR_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] SPR_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] SPR_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] SPR_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SPR_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SPR_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SPR_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] SPR_CR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] SPR_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] SPR_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] SPR_FRA; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] SPR_FRB; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] SPR_FRC; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] SPR_FRS; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] SPR_FRT; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] SPR_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SPR_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [23:0] SPR_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SPR_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SPR_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SPR_MB32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SPR_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SPR_ME32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output SPR_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] SPR_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SPR_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SPR_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SPR_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SPR_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output SPR_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SPR_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SPR_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] SPR_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [9:0] SPR_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + reg [1:0] SPR_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SPR_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] SPR_UI; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -58164,7 +63882,7 @@ module \dec$150 (bigendian, opcode_in, SPR_rc_sel, SPR_internal_op, SPR_SPR, SPR (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [2:0] SPR_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -58173,9 +63891,15 @@ module \dec$150 (bigendian, opcode_in, SPR_rc_sel, SPR_internal_op, SPR_SPR, SPR (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SPR_cr_out; reg [2:0] SPR_cr_out; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] SPR_dec31_SPR_dec31_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -58185,7 +63909,7 @@ module \dec$150 (bigendian, opcode_in, SPR_rc_sel, SPR_internal_op, SPR_SPR, SPR (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] SPR_dec31_SPR_dec31_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -58194,25 +63918,26 @@ module \dec$150 (bigendian, opcode_in, SPR_rc_sel, SPR_internal_op, SPR_SPR, SPR (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] SPR_dec31_SPR_dec31_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] SPR_dec31_SPR_dec31_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] SPR_dec31_SPR_dec31_function_unit; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -58288,36 +64013,39 @@ module \dec$150 (bigendian, opcode_in, SPR_rc_sel, SPR_internal_op, SPR_SPR, SPR (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] SPR_dec31_SPR_dec31_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SPR_dec31_SPR_dec31_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] SPR_dec31_SPR_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] SPR_dec31_opcode_in; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] SPR_function_unit; - reg [13:0] SPR_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] SPR_function_unit; + reg [14:0] SPR_function_unit; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -58393,451 +64121,454 @@ module \dec$150 (bigendian, opcode_in, SPR_rc_sel, SPR_internal_op, SPR_SPR, SPR (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] SPR_internal_op; reg [6:0] SPR_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SPR_is_32b; reg SPR_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] SPR_rc_sel; reg [1:0] SPR_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] SPR_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] SVL_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] SVL_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SVL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] SVL_SVi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] SVL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SVL_ms; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SVL_vs; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] TX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] TX_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] TX_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] TX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] VA_SHB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] VA_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire VC_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VC_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VC_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VC_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] VC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire VX_PS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_SIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] VX_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] VX_UIM_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] VX_UIM_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] VX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [10:0] VX_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] XFL_FLM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFL_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XFL_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XFL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XFL_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_BHRBE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFX_DUI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_DUIS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] XFX_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFX_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XL_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XL_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XL_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XL_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [14:0] XL_OC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XL_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XO_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XO_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XO_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XO_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XO_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XO_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XS_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XX2_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX2_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] XX2_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX2_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] XX2_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX2_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] XX2_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XX2_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_dc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] XX2_dc_dm_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_dm; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX3_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX3_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX3_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XX3_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX3_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX3_DM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX3_SHW; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX3_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX3_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] XX3_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] XX3_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XX3_XO_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_CX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_CX_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX4_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_CT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] X_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_DRM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_E; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_EO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_EX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_E_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_IH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] X_IMM8; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_L1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_L2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_L3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_MO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_NB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_PRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_RIC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_RM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_RO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_R_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_SP; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_SR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] X_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] X_TBR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_TH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] X_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_U; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_WC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] X_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] X_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] Z22_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] Z22_DCM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] Z22_DGM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire Z22_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] Z22_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] Z22_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire Z23_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] Z23_RMC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire Z23_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_TE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] Z23_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] all_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:479" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) output [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [5:0] opcode_switch; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:478" *) input [31:0] raw_opcode_in; - assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; + assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:519" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; SPR_dec31 SPR_dec31 ( + .SPR_dec31_SV_Ptype(SPR_dec31_SPR_dec31_SV_Ptype), .SPR_dec31_cr_in(SPR_dec31_SPR_dec31_cr_in), .SPR_dec31_cr_out(SPR_dec31_SPR_dec31_cr_out), .SPR_dec31_function_unit(SPR_dec31_SPR_dec31_function_unit), @@ -58848,10 +64579,10 @@ module \dec$150 (bigendian, opcode_in, SPR_rc_sel, SPR_internal_op, SPR_SPR, SPR ); always @* begin if (\initial ) begin end - SPR_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + SPR_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: SPR_function_unit = SPR_dec31_SPR_dec31_function_unit; endcase @@ -58859,19 +64590,29 @@ module \dec$150 (bigendian, opcode_in, SPR_rc_sel, SPR_internal_op, SPR_SPR, SPR always @* begin if (\initial ) begin end SPR_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: SPR_internal_op = SPR_dec31_SPR_dec31_internal_op; endcase end + always @* begin + if (\initial ) begin end + SPR_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h1f: + SPR_SV_Ptype = SPR_dec31_SPR_dec31_SV_Ptype; + endcase + end always @* begin if (\initial ) begin end SPR_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: SPR_cr_in = SPR_dec31_SPR_dec31_cr_in; endcase @@ -58879,9 +64620,9 @@ module \dec$150 (bigendian, opcode_in, SPR_rc_sel, SPR_internal_op, SPR_SPR, SPR always @* begin if (\initial ) begin end SPR_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: SPR_cr_out = SPR_dec31_SPR_dec31_cr_out; endcase @@ -58889,9 +64630,9 @@ module \dec$150 (bigendian, opcode_in, SPR_rc_sel, SPR_internal_op, SPR_SPR, SPR always @* begin if (\initial ) begin end SPR_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: SPR_rc_sel = SPR_dec31_SPR_dec31_rc_sel; endcase @@ -58899,9 +64640,9 @@ module \dec$150 (bigendian, opcode_in, SPR_rc_sel, SPR_internal_op, SPR_SPR, SPR always @* begin if (\initial ) begin end SPR_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: SPR_is_32b = SPR_dec31_SPR_dec31_is_32b; endcase @@ -59238,6 +64979,11 @@ module \dec$150 (bigendian, opcode_in, SPR_rc_sel, SPR_internal_op, SPR_SPR, SPR assign SPR_RA = opcode_in[20:16]; assign SPR_RT = opcode_in[25:21]; assign SPR_RS = opcode_in[25:21]; + assign SPR_FRC = opcode_in[10:6]; + assign SPR_FRB = opcode_in[15:11]; + assign SPR_FRA = opcode_in[20:16]; + assign SPR_FRT = opcode_in[25:21]; + assign SPR_FRS = opcode_in[25:21]; assign SPR_PO = opcode_in[31:26]; assign opcode_in = \$1 ; assign SPR_dec31_opcode_in = opcode_in; @@ -59248,105 +64994,121 @@ endmodule (* generator = "nMigen" *) module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV_function_unit, DIV_in1_sel, DIV_in2_sel, DIV_cr_out, DIV_ldst_len, DIV_inv_a, DIV_inv_out, DIV_cry_in, DIV_cry_out, DIV_is_32b, DIV_sgn, DIV_RA, DIV_SI, DIV_UI, DIV_SH32, DIV_sh, DIV_LI, DIV_Rc, DIV_OE, DIV_BD, DIV_DS, raw_opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:519" *) wire [31:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire A_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire B_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [13:0] B_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] B_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] B_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire B_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire DIV_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DIV_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DIV_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DIV_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [13:0] DIV_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] DIV_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] DIV_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DIV_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DIV_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DIV_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] DIV_CR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] DIV_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [13:0] DIV_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] DIV_FRA; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] DIV_FRB; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] DIV_FRC; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] DIV_FRS; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] DIV_FRT; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] DIV_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire DIV_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [23:0] DIV_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire DIV_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DIV_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DIV_MB32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DIV_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DIV_ME32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output DIV_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] DIV_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [4:0] DIV_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DIV_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DIV_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DIV_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output DIV_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DIV_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [4:0] DIV_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [15:0] DIV_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [9:0] DIV_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + reg [1:0] DIV_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] DIV_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [15:0] DIV_UI; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -59357,7 +65119,7 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [2:0] DIV_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -59366,19 +65128,25 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] DIV_cr_out; reg [2:0] DIV_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] DIV_cry_in; reg [1:0] DIV_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_cry_out; reg DIV_cry_out; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] DIV_dec31_DIV_dec31_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -59388,7 +65156,7 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] DIV_dec31_DIV_dec31_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -59397,40 +65165,43 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] DIV_dec31_DIV_dec31_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] DIV_dec31_DIV_dec31_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire DIV_dec31_DIV_dec31_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] DIV_dec31_DIV_dec31_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] DIV_dec31_DIV_dec31_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] DIV_dec31_DIV_dec31_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -59447,7 +65218,8 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] DIV_dec31_DIV_dec31_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -59524,13 +65296,15 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] DIV_dec31_DIV_dec31_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire DIV_dec31_DIV_dec31_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire DIV_dec31_DIV_dec31_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire DIV_dec31_DIV_dec31_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -59538,43 +65312,46 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] DIV_dec31_DIV_dec31_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] DIV_dec31_DIV_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire DIV_dec31_DIV_dec31_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] DIV_dec31_opcode_in; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] DIV_function_unit; - reg [13:0] DIV_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] DIV_function_unit; + reg [14:0] DIV_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] DIV_in1_sel; reg [2:0] DIV_in1_sel; (* enum_base_type = "In2Sel" *) @@ -59592,7 +65369,8 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] DIV_in2_sel; reg [3:0] DIV_in2_sel; (* enum_base_type = "MicrOp" *) @@ -59670,16 +65448,18 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] DIV_internal_op; reg [6:0] DIV_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_inv_a; reg DIV_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_inv_out; reg DIV_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_is_32b; reg DIV_is_32b; (* enum_base_type = "LdstLen" *) @@ -59688,597 +65468,598 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] DIV_ldst_len; reg [3:0] DIV_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] DIV_rc_sel; reg [1:0] DIV_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output DIV_sgn; reg DIV_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [5:0] DIV_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQE_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQE_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] DQE_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [11:0] DQ_DQ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] DQ_PT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire DQ_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] DQ_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire DQ_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] DQ_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] DQ_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [13:0] DS_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] DS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] DX_d0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] DX_d0_d1_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DX_d1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire DX_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] D_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] D_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire D_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] D_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] D_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] EVS_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire I_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [23:0] I_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire I_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_IB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_IS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire MDS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] MDS_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] MDS_XBI_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] MDS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MDS_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MDS_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MD_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MD_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire MD_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] MD_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MD_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MD_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MD_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire M_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] SC_LEV; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] SC_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] SVL_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] SVL_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SVL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] SVL_SVi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] SVL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SVL_ms; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SVL_vs; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] TX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] TX_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] TX_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] TX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] VA_SHB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] VA_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire VC_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VC_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VC_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VC_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] VC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire VX_PS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_SIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] VX_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] VX_UIM_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] VX_UIM_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] VX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [10:0] VX_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] XFL_FLM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFL_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XFL_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XFL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XFL_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_BHRBE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFX_DUI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_DUIS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] XFX_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFX_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XL_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XL_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XL_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XL_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [14:0] XL_OC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XL_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XO_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XO_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XO_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XO_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XO_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XO_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XS_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XX2_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX2_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] XX2_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX2_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] XX2_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX2_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] XX2_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XX2_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_dc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] XX2_dc_dm_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_dm; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX3_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX3_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX3_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XX3_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX3_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX3_DM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX3_SHW; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX3_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX3_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] XX3_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] XX3_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XX3_XO_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_CX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_CX_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX4_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_CT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] X_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_DRM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_E; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_EO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_EX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_E_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_IH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] X_IMM8; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_L1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_L2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_L3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_MO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_NB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_PRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_RIC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_RM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_RO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_R_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_SP; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_SR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] X_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] X_TBR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_TH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] X_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_U; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_WC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] X_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] X_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] Z22_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] Z22_DCM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] Z22_DGM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire Z22_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] Z22_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] Z22_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire Z23_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] Z23_RMC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire Z23_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_TE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] Z23_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] all_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:479" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) output [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [5:0] opcode_switch; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:478" *) input [31:0] raw_opcode_in; - assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; + assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:519" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; DIV_dec31 DIV_dec31 ( + .DIV_dec31_SV_Ptype(DIV_dec31_DIV_dec31_SV_Ptype), .DIV_dec31_cr_in(DIV_dec31_DIV_dec31_cr_in), .DIV_dec31_cr_out(DIV_dec31_DIV_dec31_cr_out), .DIV_dec31_cry_in(DIV_dec31_DIV_dec31_cry_in), @@ -60295,12 +66076,22 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV .DIV_dec31_sgn(DIV_dec31_DIV_dec31_sgn), .opcode_in(DIV_dec31_opcode_in) ); + always @* begin + if (\initial ) begin end + DIV_rc_sel = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h1f: + DIV_rc_sel = DIV_dec31_DIV_dec31_rc_sel; + endcase + end always @* begin if (\initial ) begin end DIV_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: DIV_cry_in = DIV_dec31_DIV_dec31_cry_in; endcase @@ -60308,9 +66099,9 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV always @* begin if (\initial ) begin end DIV_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: DIV_inv_a = DIV_dec31_DIV_dec31_inv_a; endcase @@ -60318,9 +66109,9 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV always @* begin if (\initial ) begin end DIV_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: DIV_inv_out = DIV_dec31_DIV_dec31_inv_out; endcase @@ -60328,9 +66119,9 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV always @* begin if (\initial ) begin end DIV_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: DIV_cry_out = DIV_dec31_DIV_dec31_cry_out; endcase @@ -60338,9 +66129,9 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV always @* begin if (\initial ) begin end DIV_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: DIV_is_32b = DIV_dec31_DIV_dec31_is_32b; endcase @@ -60348,19 +66139,19 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV always @* begin if (\initial ) begin end DIV_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: DIV_sgn = DIV_dec31_DIV_dec31_sgn; endcase end always @* begin if (\initial ) begin end - DIV_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + DIV_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: DIV_function_unit = DIV_dec31_DIV_dec31_function_unit; endcase @@ -60368,19 +66159,29 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV always @* begin if (\initial ) begin end DIV_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: DIV_internal_op = DIV_dec31_DIV_dec31_internal_op; endcase end + always @* begin + if (\initial ) begin end + DIV_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h1f: + DIV_SV_Ptype = DIV_dec31_DIV_dec31_SV_Ptype; + endcase + end always @* begin if (\initial ) begin end DIV_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: DIV_in1_sel = DIV_dec31_DIV_dec31_in1_sel; endcase @@ -60388,9 +66189,9 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV always @* begin if (\initial ) begin end DIV_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: DIV_in2_sel = DIV_dec31_DIV_dec31_in2_sel; endcase @@ -60398,9 +66199,9 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV always @* begin if (\initial ) begin end DIV_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: DIV_cr_in = DIV_dec31_DIV_dec31_cr_in; endcase @@ -60408,9 +66209,9 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV always @* begin if (\initial ) begin end DIV_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: DIV_cr_out = DIV_dec31_DIV_dec31_cr_out; endcase @@ -60418,23 +66219,13 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV always @* begin if (\initial ) begin end DIV_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: DIV_ldst_len = DIV_dec31_DIV_dec31_ldst_len; endcase end - always @* begin - if (\initial ) begin end - DIV_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) - casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h1f: - DIV_rc_sel = DIV_dec31_DIV_dec31_rc_sel; - endcase - end assign VC_XO = opcode_in[9:0]; assign VC_VRT = opcode_in[25:21]; assign VC_VRB = opcode_in[15:11]; @@ -60767,6 +66558,11 @@ module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV assign DIV_RA = opcode_in[20:16]; assign DIV_RT = opcode_in[25:21]; assign DIV_RS = opcode_in[25:21]; + assign DIV_FRC = opcode_in[10:6]; + assign DIV_FRB = opcode_in[15:11]; + assign DIV_FRA = opcode_in[20:16]; + assign DIV_FRT = opcode_in[25:21]; + assign DIV_FRS = opcode_in[25:21]; assign DIV_PO = opcode_in[31:26]; assign opcode_in = \$1 ; assign DIV_dec31_opcode_in = opcode_in; @@ -60777,231 +66573,247 @@ endmodule (* generator = "nMigen" *) module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL_function_unit, MUL_in2_sel, MUL_cr_out, MUL_is_32b, MUL_sgn, MUL_SI, MUL_UI, MUL_SH32, MUL_sh, MUL_LI, MUL_Rc, MUL_OE, MUL_BD, MUL_DS, raw_opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:519" *) wire [31:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire A_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire B_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [13:0] B_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] B_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] B_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire B_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQE_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQE_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] DQE_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [11:0] DQ_DQ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] DQ_PT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire DQ_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] DQ_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire DQ_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] DQ_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] DQ_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [13:0] DS_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] DS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] DX_d0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] DX_d0_d1_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DX_d1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire DX_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] D_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] D_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire D_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] D_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] D_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] EVS_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire I_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [23:0] I_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire I_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_IB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_IS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire MDS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] MDS_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] MDS_XBI_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] MDS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MDS_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MDS_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MD_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MD_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire MD_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] MD_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MD_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MD_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MD_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire MUL_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MUL_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MUL_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MUL_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [13:0] MUL_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] MUL_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] MUL_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MUL_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MUL_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MUL_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] MUL_CR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] MUL_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [13:0] MUL_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] MUL_FRA; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] MUL_FRB; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] MUL_FRC; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] MUL_FRS; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] MUL_FRT; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] MUL_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire MUL_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [23:0] MUL_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire MUL_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MUL_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MUL_MB32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MUL_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MUL_ME32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output MUL_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] MUL_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MUL_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MUL_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MUL_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MUL_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output MUL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MUL_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [4:0] MUL_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [15:0] MUL_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [9:0] MUL_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + reg [1:0] MUL_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MUL_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [15:0] MUL_UI; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -61012,7 +66824,7 @@ module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [2:0] MUL_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -61021,9 +66833,15 @@ module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] MUL_cr_out; reg [2:0] MUL_cr_out; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] MUL_dec31_MUL_dec31_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -61033,7 +66851,7 @@ module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] MUL_dec31_MUL_dec31_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -61042,25 +66860,26 @@ module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] MUL_dec31_MUL_dec31_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] MUL_dec31_MUL_dec31_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] MUL_dec31_MUL_dec31_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -61076,7 +66895,8 @@ module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] MUL_dec31_MUL_dec31_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -61153,38 +66973,41 @@ module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] MUL_dec31_MUL_dec31_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire MUL_dec31_MUL_dec31_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] MUL_dec31_MUL_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire MUL_dec31_MUL_dec31_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] MUL_dec31_opcode_in; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] MUL_function_unit; - reg [13:0] MUL_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] MUL_function_unit; + reg [14:0] MUL_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -61200,7 +67023,8 @@ module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] MUL_in2_sel; reg [3:0] MUL_in2_sel; (* enum_base_type = "MicrOp" *) @@ -61278,474 +67102,477 @@ module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] MUL_internal_op; reg [6:0] MUL_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output MUL_is_32b; reg MUL_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] MUL_rc_sel; reg [1:0] MUL_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output MUL_sgn; reg MUL_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [5:0] MUL_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire M_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] SC_LEV; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] SC_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] SVL_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] SVL_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SVL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] SVL_SVi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] SVL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SVL_ms; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SVL_vs; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] TX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] TX_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] TX_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] TX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] VA_SHB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] VA_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire VC_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VC_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VC_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VC_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] VC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire VX_PS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_SIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] VX_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] VX_UIM_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] VX_UIM_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] VX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [10:0] VX_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] XFL_FLM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFL_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XFL_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XFL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XFL_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_BHRBE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFX_DUI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_DUIS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] XFX_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFX_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XL_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XL_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XL_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XL_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [14:0] XL_OC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XL_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XO_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XO_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XO_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XO_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XO_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XO_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XS_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XX2_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX2_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] XX2_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX2_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] XX2_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX2_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] XX2_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XX2_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_dc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] XX2_dc_dm_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_dm; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX3_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX3_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX3_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XX3_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX3_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX3_DM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX3_SHW; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX3_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX3_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] XX3_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] XX3_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XX3_XO_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_CX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_CX_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX4_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_CT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] X_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_DRM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_E; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_EO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_EX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_E_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_IH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] X_IMM8; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_L1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_L2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_L3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_MO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_NB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_PRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_RIC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_RM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_RO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_R_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_SP; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_SR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] X_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] X_TBR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_TH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] X_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_U; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_WC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] X_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] X_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] Z22_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] Z22_DCM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] Z22_DGM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire Z22_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] Z22_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] Z22_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire Z23_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] Z23_RMC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire Z23_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_TE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] Z23_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] all_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:479" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) output [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [5:0] opcode_switch; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:478" *) input [31:0] raw_opcode_in; - assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; + assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:519" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; MUL_dec31 MUL_dec31 ( + .MUL_dec31_SV_Ptype(MUL_dec31_MUL_dec31_SV_Ptype), .MUL_dec31_cr_in(MUL_dec31_MUL_dec31_cr_in), .MUL_dec31_cr_out(MUL_dec31_MUL_dec31_cr_out), .MUL_dec31_function_unit(MUL_dec31_MUL_dec31_function_unit), @@ -61758,39 +67585,65 @@ module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL ); always @* begin if (\initial ) begin end - MUL_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + MUL_sgn = 1'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h1f: + MUL_sgn = MUL_dec31_MUL_dec31_sgn; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h07: + MUL_sgn = 1'h1; + endcase + end + always @* begin + if (\initial ) begin end + MUL_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: MUL_function_unit = MUL_dec31_MUL_dec31_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: - MUL_function_unit = 14'h0100; + MUL_function_unit = 15'h0100; endcase end always @* begin if (\initial ) begin end MUL_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: MUL_internal_op = MUL_dec31_MUL_dec31_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: MUL_internal_op = 7'h32; endcase end + always @* begin + if (\initial ) begin end + MUL_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h1f: + MUL_SV_Ptype = MUL_dec31_MUL_dec31_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h07: + MUL_SV_Ptype = 2'h2; + endcase + end always @* begin if (\initial ) begin end MUL_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: MUL_in2_sel = MUL_dec31_MUL_dec31_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: MUL_in2_sel = 4'h3; endcase @@ -61798,12 +67651,12 @@ module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL always @* begin if (\initial ) begin end MUL_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: MUL_cr_in = MUL_dec31_MUL_dec31_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: MUL_cr_in = 3'h0; endcase @@ -61811,12 +67664,12 @@ module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL always @* begin if (\initial ) begin end MUL_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: MUL_cr_out = MUL_dec31_MUL_dec31_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: MUL_cr_out = 3'h1; endcase @@ -61824,12 +67677,12 @@ module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL always @* begin if (\initial ) begin end MUL_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: MUL_rc_sel = MUL_dec31_MUL_dec31_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: MUL_rc_sel = 2'h0; endcase @@ -61837,29 +67690,16 @@ module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL always @* begin if (\initial ) begin end MUL_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: MUL_is_32b = MUL_dec31_MUL_dec31_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: MUL_is_32b = 1'h0; endcase end - always @* begin - if (\initial ) begin end - MUL_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) - casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h1f: - MUL_sgn = MUL_dec31_MUL_dec31_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h07: - MUL_sgn = 1'h1; - endcase - end assign VC_XO = opcode_in[9:0]; assign VC_VRT = opcode_in[25:21]; assign VC_VRB = opcode_in[15:11]; @@ -62192,6 +68032,11 @@ module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL assign MUL_RA = opcode_in[20:16]; assign MUL_RT = opcode_in[25:21]; assign MUL_RS = opcode_in[25:21]; + assign MUL_FRC = opcode_in[10:6]; + assign MUL_FRB = opcode_in[15:11]; + assign MUL_FRA = opcode_in[20:16]; + assign MUL_FRT = opcode_in[25:21]; + assign MUL_FRS = opcode_in[25:21]; assign MUL_PO = opcode_in[31:26]; assign opcode_in = \$1 ; assign MUL_dec31_opcode_in = opcode_in; @@ -62202,251 +68047,267 @@ endmodule (* generator = "nMigen" *) module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, SHIFT_ROT_SPR, SHIFT_ROT_function_unit, SHIFT_ROT_in2_sel, SHIFT_ROT_cr_out, SHIFT_ROT_cr_in, SHIFT_ROT_inv_a, SHIFT_ROT_cry_in, SHIFT_ROT_cry_out, SHIFT_ROT_is_32b, SHIFT_ROT_sgn, SHIFT_ROT_SI, SHIFT_ROT_UI, SHIFT_ROT_SH32, SHIFT_ROT_sh, SHIFT_ROT_LI, SHIFT_ROT_Rc, SHIFT_ROT_OE, SHIFT_ROT_BD, SHIFT_ROT_DS, raw_opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:519" *) wire [31:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire A_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire B_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [13:0] B_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] B_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] B_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire B_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQE_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQE_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] DQE_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [11:0] DQ_DQ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] DQ_PT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire DQ_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] DQ_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire DQ_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] DQ_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] DQ_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [13:0] DS_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] DS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] DX_d0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] DX_d0_d1_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DX_d1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire DX_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] D_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] D_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire D_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] D_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] D_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] EVS_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire I_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [23:0] I_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire I_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_IB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_IS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire MDS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] MDS_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] MDS_XBI_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] MDS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MDS_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MDS_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MD_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MD_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire MD_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] MD_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MD_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MD_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MD_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire M_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] SC_LEV; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] SC_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SHIFT_ROT_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SHIFT_ROT_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SHIFT_ROT_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SHIFT_ROT_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [13:0] SHIFT_ROT_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] SHIFT_ROT_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] SHIFT_ROT_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SHIFT_ROT_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SHIFT_ROT_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SHIFT_ROT_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] SHIFT_ROT_CR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] SHIFT_ROT_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [13:0] SHIFT_ROT_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] SHIFT_ROT_FRA; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] SHIFT_ROT_FRB; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] SHIFT_ROT_FRC; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] SHIFT_ROT_FRS; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] SHIFT_ROT_FRT; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] SHIFT_ROT_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SHIFT_ROT_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [23:0] SHIFT_ROT_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire SHIFT_ROT_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SHIFT_ROT_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SHIFT_ROT_MB32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SHIFT_ROT_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SHIFT_ROT_ME32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output SHIFT_ROT_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] SHIFT_ROT_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SHIFT_ROT_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SHIFT_ROT_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SHIFT_ROT_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SHIFT_ROT_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output SHIFT_ROT_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SHIFT_ROT_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [4:0] SHIFT_ROT_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [15:0] SHIFT_ROT_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [9:0] SHIFT_ROT_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + reg [1:0] SHIFT_ROT_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SHIFT_ROT_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [15:0] SHIFT_ROT_UI; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -62457,7 +68318,7 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SHIFT_ROT_cr_in; reg [2:0] SHIFT_ROT_cr_in; (* enum_base_type = "CROutSel" *) @@ -62467,19 +68328,25 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] SHIFT_ROT_cr_out; reg [2:0] SHIFT_ROT_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] SHIFT_ROT_cry_in; reg [1:0] SHIFT_ROT_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_cry_out; reg SHIFT_ROT_cry_out; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] SHIFT_ROT_dec30_SHIFT_ROT_dec30_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -62489,7 +68356,7 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -62498,33 +68365,34 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -62540,7 +68408,8 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -62617,22 +68486,30 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec30_SHIFT_ROT_dec30_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] SHIFT_ROT_dec30_opcode_in; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] SHIFT_ROT_dec31_SHIFT_ROT_dec31_SV_Ptype; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -62642,7 +68519,7 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -62651,33 +68528,34 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -62693,7 +68571,8 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -62770,40 +68649,43 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec31_SHIFT_ROT_dec31_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] SHIFT_ROT_dec31_opcode_in; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] SHIFT_ROT_function_unit; - reg [13:0] SHIFT_ROT_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] SHIFT_ROT_function_unit; + reg [14:0] SHIFT_ROT_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -62819,7 +68701,8 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] SHIFT_ROT_in2_sel; reg [3:0] SHIFT_ROT_in2_sel; (* enum_base_type = "MicrOp" *) @@ -62897,457 +68780,460 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] SHIFT_ROT_internal_op; reg [6:0] SHIFT_ROT_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_inv_a; reg SHIFT_ROT_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_is_32b; reg SHIFT_ROT_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] SHIFT_ROT_rc_sel; reg [1:0] SHIFT_ROT_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output SHIFT_ROT_sgn; reg SHIFT_ROT_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [5:0] SHIFT_ROT_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] SVL_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] SVL_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SVL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] SVL_SVi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] SVL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SVL_ms; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SVL_vs; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] TX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] TX_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] TX_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] TX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] VA_SHB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] VA_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire VC_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VC_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VC_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VC_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] VC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire VX_PS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_SIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] VX_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] VX_UIM_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] VX_UIM_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] VX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [10:0] VX_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] XFL_FLM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFL_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XFL_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XFL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XFL_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_BHRBE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFX_DUI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_DUIS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] XFX_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFX_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XL_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XL_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XL_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XL_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [14:0] XL_OC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XL_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XO_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XO_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XO_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XO_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XO_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XO_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XS_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XX2_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX2_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] XX2_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX2_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] XX2_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX2_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] XX2_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XX2_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_dc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] XX2_dc_dm_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_dm; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX3_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX3_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX3_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XX3_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX3_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX3_DM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX3_SHW; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX3_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX3_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] XX3_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] XX3_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XX3_XO_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_CX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_CX_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX4_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_CT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] X_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_DRM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_E; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_EO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_EX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_E_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_IH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] X_IMM8; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_L1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_L2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_L3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_MO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_NB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_PRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_RIC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_RM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_RO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_R_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_SP; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_SR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] X_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] X_TBR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_TH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] X_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_U; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_WC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] X_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] X_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] Z22_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] Z22_DCM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] Z22_DGM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire Z22_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] Z22_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] Z22_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire Z23_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] Z23_RMC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire Z23_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_TE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] Z23_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] all_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:479" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) output [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [5:0] opcode_switch; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:478" *) input [31:0] raw_opcode_in; - assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; + assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:519" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; SHIFT_ROT_dec30 SHIFT_ROT_dec30 ( + .SHIFT_ROT_dec30_SV_Ptype(SHIFT_ROT_dec30_SHIFT_ROT_dec30_SV_Ptype), .SHIFT_ROT_dec30_cr_in(SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in), .SHIFT_ROT_dec30_cr_out(SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out), .SHIFT_ROT_dec30_cry_in(SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in), @@ -63362,6 +69248,7 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, .opcode_in(SHIFT_ROT_dec30_opcode_in) ); SHIFT_ROT_dec31 SHIFT_ROT_dec31 ( + .SHIFT_ROT_dec31_SV_Ptype(SHIFT_ROT_dec31_SHIFT_ROT_dec31_SV_Ptype), .SHIFT_ROT_dec31_cr_in(SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in), .SHIFT_ROT_dec31_cr_out(SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out), .SHIFT_ROT_dec31_cry_in(SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in), @@ -63375,24 +69262,46 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, .SHIFT_ROT_dec31_sgn(SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn), .opcode_in(SHIFT_ROT_dec31_opcode_in) ); + always @* begin + if (\initial ) begin end + SHIFT_ROT_cry_in = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h1e: + SHIFT_ROT_cry_in = SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h1f: + SHIFT_ROT_cry_in = SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h14: + SHIFT_ROT_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h15: + SHIFT_ROT_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h17: + SHIFT_ROT_cry_in = 2'h0; + endcase + end always @* begin if (\initial ) begin end SHIFT_ROT_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: SHIFT_ROT_inv_a = SHIFT_ROT_dec30_SHIFT_ROT_dec30_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: SHIFT_ROT_inv_a = SHIFT_ROT_dec31_SHIFT_ROT_dec31_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: SHIFT_ROT_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: SHIFT_ROT_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: SHIFT_ROT_inv_a = 1'h0; endcase @@ -63400,21 +69309,21 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, always @* begin if (\initial ) begin end SHIFT_ROT_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: SHIFT_ROT_cry_out = SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: SHIFT_ROT_cry_out = SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: SHIFT_ROT_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: SHIFT_ROT_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: SHIFT_ROT_cry_out = 1'h0; endcase @@ -63422,21 +69331,21 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, always @* begin if (\initial ) begin end SHIFT_ROT_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: SHIFT_ROT_is_32b = SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: SHIFT_ROT_is_32b = SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: SHIFT_ROT_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: SHIFT_ROT_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: SHIFT_ROT_is_32b = 1'h1; endcase @@ -63444,87 +69353,109 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, always @* begin if (\initial ) begin end SHIFT_ROT_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: SHIFT_ROT_sgn = SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: SHIFT_ROT_sgn = SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: SHIFT_ROT_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: SHIFT_ROT_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: SHIFT_ROT_sgn = 1'h0; endcase end always @* begin if (\initial ) begin end - SHIFT_ROT_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + SHIFT_ROT_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: SHIFT_ROT_function_unit = SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: SHIFT_ROT_function_unit = SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: - SHIFT_ROT_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + SHIFT_ROT_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: - SHIFT_ROT_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + SHIFT_ROT_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: - SHIFT_ROT_function_unit = 14'h0008; + SHIFT_ROT_function_unit = 15'h0008; endcase end always @* begin if (\initial ) begin end SHIFT_ROT_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: SHIFT_ROT_internal_op = SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: SHIFT_ROT_internal_op = SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: SHIFT_ROT_internal_op = 7'h38; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: SHIFT_ROT_internal_op = 7'h38; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: SHIFT_ROT_internal_op = 7'h38; endcase end + always @* begin + if (\initial ) begin end + SHIFT_ROT_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h1e: + SHIFT_ROT_SV_Ptype = SHIFT_ROT_dec30_SHIFT_ROT_dec30_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h1f: + SHIFT_ROT_SV_Ptype = SHIFT_ROT_dec31_SHIFT_ROT_dec31_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h14: + SHIFT_ROT_SV_Ptype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h15: + SHIFT_ROT_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h17: + SHIFT_ROT_SV_Ptype = 2'h1; + endcase + end always @* begin if (\initial ) begin end SHIFT_ROT_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: SHIFT_ROT_in2_sel = SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: SHIFT_ROT_in2_sel = SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: SHIFT_ROT_in2_sel = 4'hb; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: SHIFT_ROT_in2_sel = 4'hb; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: SHIFT_ROT_in2_sel = 4'h1; endcase @@ -63532,21 +69463,21 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, always @* begin if (\initial ) begin end SHIFT_ROT_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: SHIFT_ROT_cr_in = SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: SHIFT_ROT_cr_in = SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: SHIFT_ROT_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: SHIFT_ROT_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: SHIFT_ROT_cr_in = 3'h0; endcase @@ -63554,21 +69485,21 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, always @* begin if (\initial ) begin end SHIFT_ROT_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: SHIFT_ROT_cr_out = SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: SHIFT_ROT_cr_out = SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: SHIFT_ROT_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: SHIFT_ROT_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: SHIFT_ROT_cr_out = 3'h1; endcase @@ -63576,47 +69507,25 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, always @* begin if (\initial ) begin end SHIFT_ROT_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: SHIFT_ROT_rc_sel = SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: SHIFT_ROT_rc_sel = SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: SHIFT_ROT_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: SHIFT_ROT_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: SHIFT_ROT_rc_sel = 2'h2; endcase end - always @* begin - if (\initial ) begin end - SHIFT_ROT_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) - casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h1e: - SHIFT_ROT_cry_in = SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h1f: - SHIFT_ROT_cry_in = SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h14: - SHIFT_ROT_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h15: - SHIFT_ROT_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h17: - SHIFT_ROT_cry_in = 2'h0; - endcase - end assign VC_XO = opcode_in[9:0]; assign VC_VRT = opcode_in[25:21]; assign VC_VRB = opcode_in[15:11]; @@ -63949,6 +69858,11 @@ module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, assign SHIFT_ROT_RA = opcode_in[20:16]; assign SHIFT_ROT_RT = opcode_in[25:21]; assign SHIFT_ROT_RS = opcode_in[25:21]; + assign SHIFT_ROT_FRC = opcode_in[10:6]; + assign SHIFT_ROT_FRB = opcode_in[15:11]; + assign SHIFT_ROT_FRA = opcode_in[20:16]; + assign SHIFT_ROT_FRT = opcode_in[25:21]; + assign SHIFT_ROT_FRS = opcode_in[25:21]; assign SHIFT_ROT_PO = opcode_in[31:26]; assign opcode_in = \$1 ; assign SHIFT_ROT_dec31_opcode_in = opcode_in; @@ -63960,197 +69874,213 @@ endmodule (* generator = "nMigen" *) module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, LDST_function_unit, LDST_in1_sel, LDST_in2_sel, LDST_cr_out, LDST_ldst_len, LDST_is_32b, LDST_sgn, LDST_br, LDST_sgn_ext, LDST_upd, LDST_RA, LDST_SI, LDST_UI, LDST_SH32, LDST_sh, LDST_LI, LDST_Rc, LDST_OE, LDST_BD, LDST_DS, raw_opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:519" *) wire [31:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire A_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire B_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [13:0] B_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] B_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] B_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire B_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQE_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQE_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] DQE_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [11:0] DQ_DQ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] DQ_PT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire DQ_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] DQ_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire DQ_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] DQ_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] DQ_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [13:0] DS_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] DS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] DX_d0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] DX_d0_d1_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DX_d1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire DX_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] D_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] D_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire D_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] D_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] D_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] EVS_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire I_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [23:0] I_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire I_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire LDST_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] LDST_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] LDST_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] LDST_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [13:0] LDST_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] LDST_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] LDST_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] LDST_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] LDST_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] LDST_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] LDST_CR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] LDST_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [13:0] LDST_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] LDST_FRA; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] LDST_FRB; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] LDST_FRC; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] LDST_FRS; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] LDST_FRT; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] LDST_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire LDST_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [23:0] LDST_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire LDST_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] LDST_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] LDST_MB32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] LDST_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] LDST_ME32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output LDST_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] LDST_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [4:0] LDST_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] LDST_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] LDST_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] LDST_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output LDST_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] LDST_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [4:0] LDST_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [15:0] LDST_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [9:0] LDST_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + reg [1:0] LDST_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] LDST_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [15:0] LDST_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_br; reg LDST_br; (* enum_base_type = "CRInSel" *) @@ -64162,7 +70092,7 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [2:0] LDST_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -64171,10 +70101,16 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_cr_out; reg [2:0] LDST_cr_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] LDST_dec31_LDST_dec31_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_LDST_dec31_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -64185,7 +70121,7 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec31_LDST_dec31_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -64194,32 +70130,35 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec31_LDST_dec31_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] LDST_dec31_LDST_dec31_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] LDST_dec31_LDST_dec31_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec31_LDST_dec31_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -64236,7 +70175,8 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LDST_dec31_LDST_dec31_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -64313,9 +70253,11 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] LDST_dec31_LDST_dec31_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_LDST_dec31_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -64323,28 +70265,34 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LDST_dec31_LDST_dec31_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LDST_dec31_LDST_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_LDST_dec31_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec31_LDST_dec31_sgn_ext; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LDST_dec31_LDST_dec31_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] LDST_dec31_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] LDST_dec58_LDST_dec58_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec58_LDST_dec58_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -64355,7 +70303,7 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec58_LDST_dec58_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -64364,32 +70312,35 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec58_LDST_dec58_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] LDST_dec58_LDST_dec58_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] LDST_dec58_LDST_dec58_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec58_LDST_dec58_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -64406,7 +70357,8 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LDST_dec58_LDST_dec58_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -64483,9 +70435,11 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] LDST_dec58_LDST_dec58_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec58_LDST_dec58_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -64493,28 +70447,34 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LDST_dec58_LDST_dec58_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LDST_dec58_LDST_dec58_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec58_LDST_dec58_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec58_LDST_dec58_sgn_ext; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LDST_dec58_LDST_dec58_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] LDST_dec58_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] LDST_dec62_LDST_dec62_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec62_LDST_dec62_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -64525,7 +70485,7 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec62_LDST_dec62_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -64534,32 +70494,35 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec62_LDST_dec62_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] LDST_dec62_LDST_dec62_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] LDST_dec62_LDST_dec62_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] LDST_dec62_LDST_dec62_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -64576,7 +70539,8 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LDST_dec62_LDST_dec62_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -64653,9 +70617,11 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] LDST_dec62_LDST_dec62_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec62_LDST_dec62_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -64663,52 +70629,55 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] LDST_dec62_LDST_dec62_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LDST_dec62_LDST_dec62_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec62_LDST_dec62_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire LDST_dec62_LDST_dec62_sgn_ext; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] LDST_dec62_LDST_dec62_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] LDST_dec62_opcode_in; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] LDST_function_unit; - reg [13:0] LDST_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] LDST_function_unit; + reg [14:0] LDST_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] LDST_in1_sel; reg [2:0] LDST_in1_sel; (* enum_base_type = "In2Sel" *) @@ -64726,7 +70695,8 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LDST_in2_sel; reg [3:0] LDST_in2_sel; (* enum_base_type = "MicrOp" *) @@ -64804,10 +70774,12 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] LDST_internal_op; reg [6:0] LDST_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_is_32b; reg LDST_is_32b; (* enum_base_type = "LdstLen" *) @@ -64816,518 +70788,519 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] LDST_ldst_len; reg [3:0] LDST_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LDST_rc_sel; reg [1:0] LDST_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_sgn; reg LDST_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output LDST_sgn_ext; reg LDST_sgn_ext; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [5:0] LDST_sh; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] LDST_upd; reg [1:0] LDST_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_IB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_IS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire MDS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] MDS_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] MDS_XBI_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] MDS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MDS_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MDS_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MD_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MD_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire MD_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] MD_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MD_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MD_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MD_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire M_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] SC_LEV; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] SC_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] SVL_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] SVL_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SVL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] SVL_SVi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] SVL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SVL_ms; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SVL_vs; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] TX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] TX_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] TX_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] TX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] VA_SHB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] VA_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire VC_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VC_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VC_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VC_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] VC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire VX_PS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_SIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] VX_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] VX_UIM_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] VX_UIM_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] VX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [10:0] VX_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] XFL_FLM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFL_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XFL_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XFL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XFL_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_BHRBE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFX_DUI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_DUIS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] XFX_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFX_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XL_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XL_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XL_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XL_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [14:0] XL_OC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XL_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XO_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XO_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XO_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XO_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XO_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XO_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XS_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XX2_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX2_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] XX2_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX2_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] XX2_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX2_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] XX2_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XX2_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_dc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] XX2_dc_dm_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_dm; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX3_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX3_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX3_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XX3_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX3_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX3_DM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX3_SHW; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX3_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX3_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] XX3_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] XX3_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XX3_XO_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_CX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_CX_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX4_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_CT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] X_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_DRM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_E; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_EO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_EX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_E_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_IH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] X_IMM8; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_L1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_L2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_L3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_MO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_NB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_PRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_RIC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_RM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_RO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_R_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_SP; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_SR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] X_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] X_TBR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_TH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] X_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_U; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_WC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] X_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] X_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] Z22_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] Z22_DCM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] Z22_DGM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire Z22_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] Z22_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] Z22_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire Z23_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] Z23_RMC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire Z23_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_TE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] Z23_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] all_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:479" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) output [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [5:0] opcode_switch; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:478" *) input [31:0] raw_opcode_in; - assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; + assign \$1 = bigendian ? (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:519" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; LDST_dec31 LDST_dec31 ( + .LDST_dec31_SV_Ptype(LDST_dec31_LDST_dec31_SV_Ptype), .LDST_dec31_br(LDST_dec31_LDST_dec31_br), .LDST_dec31_cr_in(LDST_dec31_LDST_dec31_cr_in), .LDST_dec31_cr_out(LDST_dec31_LDST_dec31_cr_out), @@ -65344,6 +71317,7 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, .opcode_in(LDST_dec31_opcode_in) ); LDST_dec58 LDST_dec58 ( + .LDST_dec58_SV_Ptype(LDST_dec58_LDST_dec58_SV_Ptype), .LDST_dec58_br(LDST_dec58_LDST_dec58_br), .LDST_dec58_cr_in(LDST_dec58_LDST_dec58_cr_in), .LDST_dec58_cr_out(LDST_dec58_LDST_dec58_cr_out), @@ -65360,6 +71334,7 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, .opcode_in(LDST_dec58_opcode_in) ); LDST_dec62 LDST_dec62 ( + .LDST_dec62_SV_Ptype(LDST_dec62_LDST_dec62_SV_Ptype), .LDST_dec62_br(LDST_dec62_LDST_dec62_br), .LDST_dec62_cr_in(LDST_dec62_LDST_dec62_cr_in), .LDST_dec62_cr_out(LDST_dec62_LDST_dec62_cr_out), @@ -65375,60 +71350,166 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, .LDST_dec62_upd(LDST_dec62_LDST_dec62_upd), .opcode_in(LDST_dec62_opcode_in) ); + always @* begin + if (\initial ) begin end + LDST_cr_out = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h1f: + LDST_cr_out = LDST_dec31_LDST_dec31_cr_out; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h3a: + LDST_cr_out = LDST_dec58_LDST_dec58_cr_out; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h3e: + LDST_cr_out = LDST_dec62_LDST_dec62_cr_out; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h22: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h23: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h2a: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h2b: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h28: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h29: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h20: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h21: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h26: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h27: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h2c: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h2d: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h24: + LDST_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h25: + LDST_cr_out = 3'h0; + endcase + end always @* begin if (\initial ) begin end LDST_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: LDST_ldst_len = LDST_dec31_LDST_dec31_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: LDST_ldst_len = LDST_dec58_LDST_dec58_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: LDST_ldst_len = LDST_dec62_LDST_dec62_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: LDST_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: LDST_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + LDST_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + LDST_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + LDST_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + LDST_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: LDST_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: LDST_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: LDST_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: LDST_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: LDST_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: LDST_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: LDST_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: LDST_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + LDST_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + LDST_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + LDST_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + LDST_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: LDST_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: LDST_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: LDST_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: LDST_ldst_len = 4'h4; endcase @@ -65436,57 +71517,81 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, always @* begin if (\initial ) begin end LDST_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: LDST_upd = LDST_dec31_LDST_dec31_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: LDST_upd = LDST_dec58_LDST_dec58_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: LDST_upd = LDST_dec62_LDST_dec62_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: LDST_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: LDST_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + LDST_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + LDST_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + LDST_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + LDST_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: LDST_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: LDST_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: LDST_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: LDST_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: LDST_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: LDST_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: LDST_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: LDST_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + LDST_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + LDST_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + LDST_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + LDST_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: LDST_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: LDST_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: LDST_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: LDST_upd = 2'h1; endcase @@ -65494,57 +71599,81 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, always @* begin if (\initial ) begin end LDST_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: LDST_rc_sel = LDST_dec31_LDST_dec31_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: LDST_rc_sel = LDST_dec58_LDST_dec58_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: LDST_rc_sel = LDST_dec62_LDST_dec62_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: LDST_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: LDST_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + LDST_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + LDST_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + LDST_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + LDST_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: LDST_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: LDST_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: LDST_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: LDST_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: LDST_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: LDST_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: LDST_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: LDST_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + LDST_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + LDST_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + LDST_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + LDST_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: LDST_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: LDST_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: LDST_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: LDST_rc_sel = 2'h0; endcase @@ -65552,57 +71681,81 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, always @* begin if (\initial ) begin end LDST_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: LDST_br = LDST_dec31_LDST_dec31_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: LDST_br = LDST_dec58_LDST_dec58_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: LDST_br = LDST_dec62_LDST_dec62_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: LDST_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: LDST_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + LDST_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + LDST_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + LDST_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + LDST_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: LDST_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: LDST_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: LDST_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: LDST_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: LDST_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: LDST_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: LDST_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: LDST_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + LDST_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + LDST_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + LDST_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + LDST_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: LDST_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: LDST_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: LDST_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: LDST_br = 1'h0; endcase @@ -65610,57 +71763,81 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, always @* begin if (\initial ) begin end LDST_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: LDST_sgn_ext = LDST_dec31_LDST_dec31_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: LDST_sgn_ext = LDST_dec58_LDST_dec58_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: LDST_sgn_ext = LDST_dec62_LDST_dec62_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: LDST_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: LDST_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + LDST_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + LDST_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + LDST_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + LDST_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: LDST_sgn_ext = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: LDST_sgn_ext = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: LDST_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: LDST_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: LDST_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: LDST_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: LDST_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: LDST_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + LDST_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + LDST_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + LDST_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + LDST_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: LDST_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: LDST_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: LDST_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: LDST_sgn_ext = 1'h0; endcase @@ -65668,57 +71845,81 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, always @* begin if (\initial ) begin end LDST_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: LDST_is_32b = LDST_dec31_LDST_dec31_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: LDST_is_32b = LDST_dec58_LDST_dec58_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: LDST_is_32b = LDST_dec62_LDST_dec62_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: LDST_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: LDST_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + LDST_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + LDST_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + LDST_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + LDST_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: LDST_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: LDST_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: LDST_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: LDST_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: LDST_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: LDST_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: LDST_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: LDST_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + LDST_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + LDST_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + LDST_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + LDST_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: LDST_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: LDST_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: LDST_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: LDST_is_32b = 1'h0; endcase @@ -65726,231 +71927,409 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, always @* begin if (\initial ) begin end LDST_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: LDST_sgn = LDST_dec31_LDST_dec31_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: LDST_sgn = LDST_dec58_LDST_dec58_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: LDST_sgn = LDST_dec62_LDST_dec62_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: LDST_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: LDST_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + LDST_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + LDST_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + LDST_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + LDST_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: LDST_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: LDST_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: LDST_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: LDST_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: LDST_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: LDST_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: LDST_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: LDST_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + LDST_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + LDST_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + LDST_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + LDST_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: LDST_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: LDST_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: LDST_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: LDST_sgn = 1'h0; endcase end always @* begin if (\initial ) begin end - LDST_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + LDST_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: LDST_function_unit = LDST_dec31_LDST_dec31_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: LDST_function_unit = LDST_dec58_LDST_dec58_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: LDST_function_unit = LDST_dec62_LDST_dec62_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: - LDST_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: - LDST_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + LDST_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + LDST_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + LDST_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + LDST_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: - LDST_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: - LDST_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: - LDST_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: - LDST_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: - LDST_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: - LDST_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: - LDST_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: - LDST_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + LDST_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + LDST_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + LDST_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + LDST_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: - LDST_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: - LDST_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: - LDST_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: - LDST_function_unit = 14'h0004; + LDST_function_unit = 15'h0004; endcase end always @* begin if (\initial ) begin end LDST_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: LDST_internal_op = LDST_dec31_LDST_dec31_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: LDST_internal_op = LDST_dec58_LDST_dec58_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: LDST_internal_op = LDST_dec62_LDST_dec62_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: LDST_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: LDST_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + LDST_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + LDST_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + LDST_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + LDST_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: LDST_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: LDST_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: LDST_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: LDST_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: LDST_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: LDST_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: LDST_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: LDST_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + LDST_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + LDST_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + LDST_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + LDST_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: LDST_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: LDST_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: LDST_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: LDST_internal_op = 7'h26; endcase end + always @* begin + if (\initial ) begin end + LDST_SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) + casez (opcode_switch) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h1f: + LDST_SV_Ptype = LDST_dec31_LDST_dec31_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h3a: + LDST_SV_Ptype = LDST_dec58_LDST_dec58_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h3e: + LDST_SV_Ptype = LDST_dec62_LDST_dec62_SV_Ptype; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h22: + LDST_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h23: + LDST_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + LDST_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + LDST_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + LDST_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + LDST_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h2a: + LDST_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h2b: + LDST_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h28: + LDST_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h29: + LDST_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h20: + LDST_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h21: + LDST_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h26: + LDST_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h27: + LDST_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + LDST_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + LDST_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + LDST_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + LDST_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h2c: + LDST_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h2d: + LDST_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h24: + LDST_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h25: + LDST_SV_Ptype = 2'h2; + endcase + end always @* begin if (\initial ) begin end LDST_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: LDST_in1_sel = LDST_dec31_LDST_dec31_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: LDST_in1_sel = LDST_dec58_LDST_dec58_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: LDST_in1_sel = LDST_dec62_LDST_dec62_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: LDST_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: LDST_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + LDST_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + LDST_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + LDST_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + LDST_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: LDST_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: LDST_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: LDST_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: LDST_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: LDST_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: LDST_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: LDST_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: LDST_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + LDST_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + LDST_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + LDST_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + LDST_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: LDST_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: LDST_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: LDST_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: LDST_in1_sel = 3'h2; endcase @@ -65958,57 +72337,81 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, always @* begin if (\initial ) begin end LDST_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: LDST_in2_sel = LDST_dec31_LDST_dec31_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: LDST_in2_sel = LDST_dec58_LDST_dec58_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: LDST_in2_sel = LDST_dec62_LDST_dec62_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: LDST_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: LDST_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + LDST_in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + LDST_in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + LDST_in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + LDST_in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: LDST_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: LDST_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: LDST_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: LDST_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: LDST_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: LDST_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: LDST_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: LDST_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + LDST_in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + LDST_in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + LDST_in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + LDST_in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: LDST_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: LDST_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: LDST_in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: LDST_in2_sel = 4'h3; endcase @@ -66016,117 +72419,83 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, always @* begin if (\initial ) begin end LDST_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: LDST_cr_in = LDST_dec31_LDST_dec31_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: LDST_cr_in = LDST_dec58_LDST_dec58_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: LDST_cr_in = LDST_dec62_LDST_dec62_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: LDST_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: LDST_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + LDST_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + LDST_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + LDST_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + LDST_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: LDST_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: LDST_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: LDST_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: LDST_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: LDST_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: LDST_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: LDST_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: LDST_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h2c: + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: LDST_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h2d: + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: LDST_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h24: + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: LDST_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h25: + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: LDST_cr_in = 3'h0; - endcase - end - always @* begin - if (\initial ) begin end - LDST_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) - casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h1f: - LDST_cr_out = LDST_dec31_LDST_dec31_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h3a: - LDST_cr_out = LDST_dec58_LDST_dec58_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h3e: - LDST_cr_out = LDST_dec62_LDST_dec62_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h22: - LDST_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h23: - LDST_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h2a: - LDST_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h2b: - LDST_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h28: - LDST_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h29: - LDST_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h20: - LDST_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h21: - LDST_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h26: - LDST_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 6'h27: - LDST_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: - LDST_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: - LDST_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: - LDST_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + LDST_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: - LDST_cr_out = 3'h0; + LDST_cr_in = 3'h0; endcase end assign VC_XO = opcode_in[9:0]; @@ -66461,6 +72830,11 @@ module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, assign LDST_RA = opcode_in[20:16]; assign LDST_RT = opcode_in[25:21]; assign LDST_RS = opcode_in[25:21]; + assign LDST_FRC = opcode_in[10:6]; + assign LDST_FRB = opcode_in[15:11]; + assign LDST_FRA = opcode_in[20:16]; + assign LDST_FRT = opcode_in[25:21]; + assign LDST_FRS = opcode_in[25:21]; assign LDST_PO = opcode_in[31:26]; assign opcode_in = \$1 ; assign LDST_dec62_opcode_in = opcode_in; @@ -66471,692 +72845,702 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.dec2.dec" *) (* generator = "nMigen" *) -module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_unit, cr_out, cry_in, is_32b, lk, LK, cr_in, in1_sel, in2_sel, in3_sel, out_sel, asmcode, upd, RS, RT, RA, RB, Rc, OE, BB, BA, BT, FXM, BO, BI, BC, X_BF, X_BFA, XL_BT, XL_XO, bigendian); +module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_unit, cr_out, cry_in, is_32b, lk, LK, cr_in, in1_sel, in2_sel, in3_sel, out_sel, asmcode, upd, FRS, FRT, FRA, FRB, FRC, RS, RT, RA, RB, Rc, OE, BB, BA, BT, FXM, BO, BI, BC, X_BF, X_BFA, XL_BT, XL_XO, bigendian); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:519" *) wire [31:0] \$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire A_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] A_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [4:0] BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [4:0] BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [4:0] BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [2:0] BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [1:0] BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [4:0] BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [4:0] BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [4:0] BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire B_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [13:0] B_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] B_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] B_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire B_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] CR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQE_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQE_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] DQE_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [11:0] DQ_DQ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] DQ_PT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire DQ_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] DQ_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DQ_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire DQ_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] DQ_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] DQ_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [13:0] DS_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DS_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] DS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] DX_d0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] DX_d0_d1_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] DX_d1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire DX_d2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] D_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] D_D; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire D_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] D_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] D_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [15:0] D_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] EVS_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + output [4:0] FRA; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + output [4:0] FRB; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + output [4:0] FRC; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + output [4:0] FRS; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + output [4:0] FRT; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [7:0] FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire I_AA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [23:0] I_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire I_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [23:0] LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] MB32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_IB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_IS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MDS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire MDS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] MDS_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] MDS_XBI_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] MDS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MDS_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MDS_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MD_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] MD_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire MD_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] MD_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MD_mb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MD_me; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] MD_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] ME32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_MB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_ME; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire M_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] M_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [4:0] RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [4:0] RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [4:0] RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [4:0] RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] SC_LEV; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] SC_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) output [9:0] SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] SVL_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] SVL_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SVL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] SVL_SVi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] SVL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SVL_ms; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire SVL_vs; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [1:0] SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [1:0] SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] TX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] TX_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] TX_XBI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] TX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] VA_SHB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VA_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] VA_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire VC_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VC_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VC_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VC_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] VC_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire VX_PS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_SIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] VX_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] VX_UIM_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] VX_UIM_3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_VRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_VRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] VX_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] VX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [10:0] VX_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] XFL_FLM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFL_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XFL_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XFL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XFL_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_BHRBE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFX_DUI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_DUIS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] XFX_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFX_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XFX_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] XFX_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XL_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XL_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XL_BH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XL_BO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) output [4:0] XL_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XL_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [14:0] XL_OC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XL_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) output [9:0] XL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XO_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XO_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XO_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XO_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XO_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XO_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XS_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XS_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XS_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XS_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XS_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XX2_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX2_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] XX2_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX2_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] XX2_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX2_UIM_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] XX2_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XX2_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_dc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] XX2_dc_dm_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX2_dm; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX2_dx; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX3_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX3_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX3_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] XX3_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX3_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX3_DM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX3_SHW; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX3_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX3_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX3_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] XX3_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] XX3_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] XX3_XO_2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_AX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_AX_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_BX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_BX_B; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_CX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_CX_C; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] XX4_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire XX4_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] XX4_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] XX4_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_A; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) output [2:0] X_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) output [2:0] X_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_CT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [6:0] X_DCMX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_DRM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_E; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_EO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_EO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_EX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_E_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] X_IH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] X_IMM8; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_L; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_L1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_L2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_L3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_MO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_NB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_PRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_RIC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_RM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_RO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RSp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_RTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_R_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_SP; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_SR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_SX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] X_SX_S; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] X_TBR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_TH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_TO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_TX; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] X_TX_T; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [3:0] X_U; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_UIM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_VRS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] X_VRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire X_W; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] X_WC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] X_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] X_XO_1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] Z22_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] Z22_DCM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] Z22_DGM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z22_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire Z22_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] Z22_SH; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [8:0] Z22_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRAp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRBp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_FRTp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire Z23_R; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [1:0] Z23_RMC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire Z23_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] Z23_TE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [7:0] Z23_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [5:0] all_PO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] asmcode; reg [7:0] asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:479" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) reg br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -67167,7 +73551,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] cr_in; reg [2:0] cr_in; (* enum_base_type = "CROutSel" *) @@ -67177,33 +73561,33 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] cr_out; reg [2:0] cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] cry_in; reg [1:0] cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) reg cry_out; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec19_dec19_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec19_dec19_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [7:0] dec19_dec19_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec19_dec19_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -67214,7 +73598,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec19_dec19_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -67223,15 +73607,15 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec19_dec19_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec19_dec19_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec19_dec19_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -67264,32 +73648,35 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [4:0] dec19_dec19_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec19_dec19_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec19_dec19_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec19_dec19_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -67306,14 +73693,17 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec19_dec19_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec19_dec19_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec19_dec19_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -67389,13 +73779,15 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec19_dec19_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec19_dec19_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec19_dec19_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec19_dec19_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -67403,9 +73795,9 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec19_dec19_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec19_dec19_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -67413,21 +73805,22 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec19_dec19_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec19_dec19_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec19_dec19_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec19_dec19_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec19_dec19_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec19_dec19_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -67436,7 +73829,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec19_dec19_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -67445,7 +73838,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec19_dec19_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -67454,7 +73847,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec19_dec19_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -67463,7 +73856,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec19_dec19_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -67472,7 +73865,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec19_dec19_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -67481,7 +73874,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec19_dec19_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -67490,32 +73883,32 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec19_dec19_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec19_dec19_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] dec19_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec22_dec22_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec22_dec22_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [7:0] dec22_dec22_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec22_dec22_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -67526,7 +73919,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec22_dec22_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -67535,15 +73928,15 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec22_dec22_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec22_dec22_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec22_dec22_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -67576,32 +73969,35 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [4:0] dec22_dec22_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec22_dec22_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec22_dec22_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec22_dec22_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -67618,14 +74014,17 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec22_dec22_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec22_dec22_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec22_dec22_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -67701,13 +74100,15 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec22_dec22_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec22_dec22_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec22_dec22_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec22_dec22_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -67715,9 +74116,9 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec22_dec22_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec22_dec22_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -67725,21 +74126,22 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec22_dec22_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec22_dec22_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec22_dec22_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec22_dec22_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec22_dec22_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec22_dec22_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -67748,7 +74150,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec22_dec22_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -67757,7 +74159,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec22_dec22_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -67766,7 +74168,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec22_dec22_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -67775,7 +74177,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec22_dec22_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -67784,7 +74186,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec22_dec22_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -67793,7 +74195,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec22_dec22_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -67802,32 +74204,32 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec22_dec22_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec22_dec22_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] dec22_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec30_dec30_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec30_dec30_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [7:0] dec30_dec30_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec30_dec30_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -67838,7 +74240,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec30_dec30_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -67847,15 +74249,15 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec30_dec30_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec30_dec30_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec30_dec30_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -67888,32 +74290,35 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [4:0] dec30_dec30_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec30_dec30_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec30_dec30_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec30_dec30_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -67930,14 +74335,17 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec30_dec30_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec30_dec30_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec30_dec30_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -68013,13 +74421,15 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec30_dec30_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec30_dec30_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec30_dec30_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec30_dec30_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -68027,9 +74437,9 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec30_dec30_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec30_dec30_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -68037,21 +74447,22 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec30_dec30_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec30_dec30_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec30_dec30_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec30_dec30_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec30_dec30_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec30_dec30_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68060,7 +74471,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec30_dec30_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68069,7 +74480,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec30_dec30_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68078,7 +74489,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec30_dec30_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68087,7 +74498,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec30_dec30_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68096,7 +74507,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec30_dec30_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68105,7 +74516,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec30_dec30_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68114,32 +74525,32 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec30_dec30_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec30_dec30_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] dec30_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec31_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec31_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [7:0] dec31_dec31_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec31_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -68150,7 +74561,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec31_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -68159,15 +74570,15 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec31_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec31_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec31_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -68200,32 +74611,35 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [4:0] dec31_dec31_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec31_dec31_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec31_dec31_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec31_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -68242,14 +74656,17 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec31_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec31_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec31_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -68325,13 +74742,15 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec31_dec31_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec31_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec31_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec31_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -68339,9 +74758,9 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec31_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec31_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -68349,21 +74768,22 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec31_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec31_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec31_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec31_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec31_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68372,7 +74792,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec31_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68381,7 +74801,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec31_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68390,7 +74810,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec31_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68399,7 +74819,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec31_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68408,7 +74828,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec31_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68417,7 +74837,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec31_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68426,32 +74846,32 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec31_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec31_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] dec31_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec58_dec58_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec58_dec58_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [7:0] dec58_dec58_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec58_dec58_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -68462,7 +74882,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec58_dec58_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -68471,15 +74891,15 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec58_dec58_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec58_dec58_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec58_dec58_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -68512,32 +74932,35 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [4:0] dec58_dec58_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec58_dec58_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec58_dec58_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec58_dec58_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -68554,14 +74977,17 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec58_dec58_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec58_dec58_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec58_dec58_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -68637,13 +75063,15 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec58_dec58_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec58_dec58_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec58_dec58_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec58_dec58_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -68651,9 +75079,9 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec58_dec58_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec58_dec58_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -68661,21 +75089,22 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec58_dec58_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec58_dec58_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec58_dec58_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec58_dec58_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec58_dec58_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec58_dec58_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68684,7 +75113,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec58_dec58_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68693,7 +75122,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec58_dec58_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68702,7 +75131,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec58_dec58_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68711,7 +75140,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec58_dec58_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68720,7 +75149,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec58_dec58_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68729,7 +75158,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec58_dec58_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68738,32 +75167,32 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec58_dec58_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec58_dec58_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] dec58_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec62_dec62_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec62_dec62_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [7:0] dec62_dec62_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec62_dec62_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -68774,7 +75203,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec62_dec62_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -68783,15 +75212,15 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec62_dec62_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec62_dec62_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec62_dec62_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -68824,32 +75253,35 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [4:0] dec62_dec62_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec62_dec62_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec62_dec62_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec62_dec62_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -68866,14 +75298,17 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec62_dec62_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec62_dec62_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec62_dec62_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -68949,13 +75384,15 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec62_dec62_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec62_dec62_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec62_dec62_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec62_dec62_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -68963,9 +75400,9 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec62_dec62_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec62_dec62_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -68973,21 +75410,22 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec62_dec62_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec62_dec62_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec62_dec62_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec62_dec62_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec62_dec62_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec62_dec62_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -68996,7 +75434,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec62_dec62_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -69005,7 +75443,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec62_dec62_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -69014,7 +75452,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec62_dec62_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -69023,7 +75461,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec62_dec62_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -69032,7 +75470,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec62_dec62_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -69041,7 +75479,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec62_dec62_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -69050,16 +75488,16 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec62_dec62_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec62_dec62_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] dec62_opcode_in; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -69092,33 +75530,36 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [4:0] form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] function_unit; - reg [13:0] function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] function_unit; + reg [14:0] function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] in1_sel; reg [2:0] in1_sel; (* enum_base_type = "In2Sel" *) @@ -69136,16 +75577,19 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] in2_sel; reg [3:0] in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [1:0] in3_sel; - reg [1:0] in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [2:0] in3_sel; + reg [2:0] in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -69221,14 +75665,16 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] internal_op; reg [6:0] internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) reg inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) reg inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output is_32b; reg is_32b; (* enum_base_type = "LdstLen" *) @@ -69237,16 +75683,16 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [3:0] ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output lk; reg lk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) output [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [5:0] opcode_switch; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [31:0] \opcode_switch$1 ; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -69254,27 +75700,28 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] out_sel; reg [2:0] out_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:478" *) input [31:0] raw_opcode_in; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] rc_sel; reg [1:0] rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) reg rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) reg sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) reg sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) reg sgn_ext; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] sh; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -69283,7 +75730,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [2:0] sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -69292,7 +75739,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [2:0] sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -69301,7 +75748,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [2:0] sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -69310,7 +75757,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [2:0] sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -69319,7 +75766,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [2:0] sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -69328,7 +75775,7 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [2:0] sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -69337,17 +75784,17 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) reg [2:0] sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] upd; reg [1:0] upd; - assign \$2 = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; + assign \$2 = bigendian ? (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:519" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in; dec19 dec19 ( .dec19_SV_Etype(dec19_dec19_SV_Etype), .dec19_SV_Ptype(dec19_dec19_SV_Ptype), @@ -69567,144 +76014,168 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: form = dec19_dec19_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: form = dec30_dec30_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: form = dec31_dec31_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: form = dec58_dec58_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: form = dec62_dec62_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h16: form = dec22_dec22_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h11: form = 5'h03; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: form = 5'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: form = 5'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: form = 5'h01; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: form = 5'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: form = 5'h13; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: form = 5'h13; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: form = 5'h13; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + form = 5'h04; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h02: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h03: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: form = 5'h04; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000000???????????????0100000000?: form = 5'h00; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'd1610612736: form = 5'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000001???????????????0000000011?: form = 5'h00; endcase @@ -69712,289 +76183,337 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: asmcode = dec19_dec19_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: asmcode = dec30_dec30_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: asmcode = dec31_dec31_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: asmcode = dec58_dec58_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: asmcode = dec62_dec62_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h16: asmcode = dec22_dec22_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: asmcode = 8'h07; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: asmcode = 8'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: asmcode = 8'h06; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: asmcode = 8'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h11: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: asmcode = 8'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: asmcode = 8'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: asmcode = 8'h14; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: asmcode = 8'h15; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: asmcode = 8'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: asmcode = 8'h1f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: - asmcode = 8'h4e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + asmcode = 8'h64; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: - asmcode = 8'h4f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + asmcode = 8'h65; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + asmcode = 8'h72; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + asmcode = 8'h74; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + asmcode = 8'h6e; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + asmcode = 8'h70; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: - asmcode = 8'h58; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + asmcode = 8'h78; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: - asmcode = 8'h5a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + asmcode = 8'h7a; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: - asmcode = 8'h5e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + asmcode = 8'h7e; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: - asmcode = 8'h5f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + asmcode = 8'h7f; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: - asmcode = 8'h67; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + asmcode = 8'h87; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: - asmcode = 8'h69; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + asmcode = 8'h89; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: - asmcode = 8'h80; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + asmcode = 8'ha0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: - asmcode = 8'h8a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + asmcode = 8'haa; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: - asmcode = 8'h8b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + asmcode = 8'hab; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: - asmcode = 8'h98; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + asmcode = 8'hb8; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: - asmcode = 8'h99; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + asmcode = 8'hb9; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: - asmcode = 8'h9a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + asmcode = 8'hba; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: - asmcode = 8'ha7; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + asmcode = 8'hc7; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: - asmcode = 8'haa; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + asmcode = 8'hca; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + asmcode = 8'hd7; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + asmcode = 8'hd9; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + asmcode = 8'hd3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + asmcode = 8'hd5; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: - asmcode = 8'hb3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + asmcode = 8'hdc; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: - asmcode = 8'hb6; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + asmcode = 8'hdf; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: - asmcode = 8'hb9; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + asmcode = 8'he2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: - asmcode = 8'hbc; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + asmcode = 8'he5; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: - asmcode = 8'hc4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + asmcode = 8'hed; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h02: - asmcode = 8'hcc; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + asmcode = 8'hf5; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h03: - asmcode = 8'hd0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + asmcode = 8'hf9; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: - asmcode = 8'hd2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + asmcode = 8'hfb; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: - asmcode = 8'hd3; + asmcode = 8'hfc; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000000???????????????0100000000?: asmcode = 8'h13; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'd1610612736: - asmcode = 8'h86; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + asmcode = 8'ha6; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000001???????????????0000000011?: - asmcode = 8'h9d; + asmcode = 8'hbd; endcase end always @* begin if (\initial ) begin end SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: SV_Etype = dec19_dec19_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: SV_Etype = dec30_dec30_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: SV_Etype = dec31_dec31_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: SV_Etype = dec58_dec58_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: SV_Etype = dec62_dec62_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h16: SV_Etype = dec22_dec22_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h11: SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + SV_Etype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h02: SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h03: SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: SV_Etype = 2'h2; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000000???????????????0100000000?: SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'd1610612736: SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000001???????????????0000000011?: SV_Etype = 2'h0; endcase @@ -70002,144 +76521,168 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: SV_Ptype = dec19_dec19_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: SV_Ptype = dec30_dec30_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: SV_Ptype = dec31_dec31_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: SV_Ptype = dec58_dec58_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: SV_Ptype = dec62_dec62_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h16: SV_Ptype = dec22_dec22_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h11: SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h02: SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h03: SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: SV_Ptype = 2'h2; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000000???????????????0100000000?: SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'd1610612736: SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000001???????????????0000000011?: SV_Ptype = 2'h0; endcase @@ -70147,144 +76690,168 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: in1_sel = dec19_dec19_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: in1_sel = dec30_dec30_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: in1_sel = dec31_dec31_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: in1_sel = dec58_dec58_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: in1_sel = dec62_dec62_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h16: in1_sel = dec22_dec22_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h11: in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: in1_sel = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h02: in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h03: in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: in1_sel = 3'h4; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000000???????????????0100000000?: in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'd1610612736: in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000001???????????????0000000011?: in1_sel = 3'h0; endcase @@ -70292,434 +76859,506 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: in2_sel = dec19_dec19_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: in2_sel = dec30_dec30_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: in2_sel = dec31_dec31_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: in2_sel = dec58_dec58_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: in2_sel = dec62_dec62_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h16: in2_sel = dec22_dec22_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: in2_sel = 4'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h11: in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: in2_sel = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: in2_sel = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: in2_sel = 4'h6; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: in2_sel = 4'h7; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: in2_sel = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: in2_sel = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: in2_sel = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: in2_sel = 4'hb; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: in2_sel = 4'hb; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + in2_sel = 4'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h02: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h03: in2_sel = 4'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: in2_sel = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: in2_sel = 4'h4; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000000???????????????0100000000?: in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'd1610612736: in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000001???????????????0000000011?: in2_sel = 4'h0; endcase end always @* begin if (\initial ) begin end - in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + in3_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: in3_sel = dec19_dec19_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: in3_sel = dec30_dec30_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: in3_sel = dec31_dec31_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: in3_sel = dec58_dec58_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: in3_sel = dec62_dec62_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h16: in3_sel = dec22_dec22_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: - in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: - in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: - in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: - in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h11: - in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: - in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: - in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: - in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: - in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: - in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: - in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: - in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: - in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: - in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: - in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: - in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: - in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: - in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: - in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: - in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: - in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: - in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: - in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: - in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: - in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: - in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: - in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + in3_sel = 3'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + in3_sel = 3'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + in3_sel = 3'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + in3_sel = 3'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: - in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: - in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: - in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: - in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: - in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h02: - in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h03: - in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: - in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: - in3_sel = 2'h0; + in3_sel = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000000???????????????0100000000?: - in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'd1610612736: - in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000001???????????????0000000011?: - in3_sel = 2'h0; + in3_sel = 3'h0; endcase end always @* begin if (\initial ) begin end out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: out_sel = dec19_dec19_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: out_sel = dec30_dec30_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: out_sel = dec31_dec31_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: out_sel = dec58_dec58_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: out_sel = dec62_dec62_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h16: out_sel = dec22_dec22_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h11: out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: out_sel = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + out_sel = 3'h5; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + out_sel = 3'h5; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + out_sel = 3'h5; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + out_sel = 3'h5; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h02: out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h03: out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: out_sel = 3'h2; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000000???????????????0100000000?: out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'd1610612736: out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000001???????????????0000000011?: out_sel = 3'h1; endcase @@ -70727,144 +77366,168 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: cr_in = dec19_dec19_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: cr_in = dec30_dec30_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: cr_in = dec31_dec31_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: cr_in = dec58_dec58_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: cr_in = dec62_dec62_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h16: cr_in = dec22_dec22_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h11: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: cr_in = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h02: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h03: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: cr_in = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000000???????????????0100000000?: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'd1610612736: cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000001???????????????0000000011?: cr_in = 3'h0; endcase @@ -70872,144 +77535,168 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: cr_out = dec19_dec19_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: cr_out = dec30_dec30_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: cr_out = dec31_dec31_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: cr_out = dec58_dec58_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: cr_out = dec62_dec62_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h16: cr_out = dec22_dec22_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h11: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: cr_out = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: cr_out = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h02: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h03: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: cr_out = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000000???????????????0100000000?: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'd1610612736: cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000001???????????????0000000011?: cr_out = 3'h0; endcase @@ -71017,144 +77704,168 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: sv_in1 = dec19_dec19_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: sv_in1 = dec30_dec30_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: sv_in1 = dec31_dec31_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: sv_in1 = dec58_dec58_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: sv_in1 = dec62_dec62_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h16: sv_in1 = dec22_dec22_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h11: sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: sv_in1 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + sv_in1 = 3'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + sv_in1 = 3'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: sv_in1 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: sv_in1 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: sv_in1 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: sv_in1 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + sv_in1 = 3'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + sv_in1 = 3'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: sv_in1 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: sv_in1 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h02: sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h03: sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: sv_in1 = 3'h2; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000000???????????????0100000000?: sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'd1610612736: sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000001???????????????0000000011?: sv_in1 = 3'h0; endcase @@ -71162,144 +77873,168 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: sv_in2 = dec19_dec19_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: sv_in2 = dec30_dec30_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: sv_in2 = dec31_dec31_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: sv_in2 = dec58_dec58_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: sv_in2 = dec62_dec62_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h16: sv_in2 = dec22_dec22_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h11: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: sv_in2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + sv_in2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h02: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h03: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: sv_in2 = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000000???????????????0100000000?: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'd1610612736: sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000001???????????????0000000011?: sv_in2 = 3'h0; endcase @@ -71307,144 +78042,168 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: sv_in3 = dec19_dec19_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: sv_in3 = dec30_dec30_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: sv_in3 = dec31_dec31_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: sv_in3 = dec58_dec58_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: sv_in3 = dec62_dec62_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h16: sv_in3 = dec22_dec22_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h11: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: sv_in3 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: sv_in3 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: sv_in3 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + sv_in3 = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + sv_in3 = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + sv_in3 = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + sv_in3 = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: sv_in3 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: sv_in3 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h02: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h03: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: sv_in3 = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000000???????????????0100000000?: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'd1610612736: sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000001???????????????0000000011?: sv_in3 = 3'h0; endcase @@ -71452,144 +78211,168 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: sv_out = dec19_dec19_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: sv_out = dec30_dec30_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: sv_out = dec31_dec31_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: sv_out = dec58_dec58_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: sv_out = dec62_dec62_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h16: sv_out = dec22_dec22_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h11: sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h02: sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h03: sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: sv_out = 3'h1; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000000???????????????0100000000?: sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'd1610612736: sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000001???????????????0000000011?: sv_out = 3'h0; endcase @@ -71597,144 +78380,168 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: sv_out2 = dec19_dec19_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: sv_out2 = dec30_dec30_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: sv_out2 = dec31_dec31_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: sv_out2 = dec58_dec58_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: sv_out2 = dec62_dec62_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h16: sv_out2 = dec22_dec22_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h11: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: sv_out2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + sv_out2 = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + sv_out2 = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: sv_out2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: sv_out2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: sv_out2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: sv_out2 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + sv_out2 = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + sv_out2 = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: sv_out2 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: sv_out2 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h02: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h03: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: sv_out2 = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000000???????????????0100000000?: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'd1610612736: sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000001???????????????0000000011?: sv_out2 = 3'h0; endcase @@ -71742,144 +78549,168 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: sv_cr_in = dec19_dec19_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: sv_cr_in = dec30_dec30_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: sv_cr_in = dec31_dec31_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: sv_cr_in = dec58_dec58_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: sv_cr_in = dec62_dec62_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h16: sv_cr_in = dec22_dec22_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h11: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h02: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h03: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: sv_cr_in = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000000???????????????0100000000?: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'd1610612736: sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000001???????????????0000000011?: sv_cr_in = 3'h0; endcase @@ -71887,144 +78718,168 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: sv_cr_out = dec19_dec19_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: sv_cr_out = dec30_dec30_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: sv_cr_out = dec31_dec31_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: sv_cr_out = dec58_dec58_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: sv_cr_out = dec62_dec62_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h16: sv_cr_out = dec22_dec22_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h11: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h02: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h03: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: sv_cr_out = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000000???????????????0100000000?: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'd1610612736: sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000001???????????????0000000011?: sv_cr_out = 3'h0; endcase @@ -72032,144 +78887,168 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: ldst_len = dec19_dec19_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: ldst_len = dec30_dec30_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: ldst_len = dec31_dec31_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: ldst_len = dec58_dec58_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: ldst_len = dec62_dec62_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h16: ldst_len = dec22_dec22_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h11: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h02: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h03: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: ldst_len = 4'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000000???????????????0100000000?: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'd1610612736: ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000001???????????????0000000011?: ldst_len = 4'h0; endcase @@ -72177,144 +79056,168 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: upd = dec19_dec19_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: upd = dec30_dec30_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: upd = dec31_dec31_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: upd = dec58_dec58_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: upd = dec62_dec62_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h16: upd = dec22_dec22_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h11: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h02: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h03: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: upd = 2'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000000???????????????0100000000?: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'd1610612736: upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000001???????????????0000000011?: upd = 2'h0; endcase @@ -72322,144 +79225,168 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: rc_sel = dec19_dec19_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: rc_sel = dec30_dec30_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: rc_sel = dec31_dec31_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: rc_sel = dec58_dec58_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: rc_sel = dec62_dec62_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h16: rc_sel = dec22_dec22_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: rc_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h11: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: rc_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: rc_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h02: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h03: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: rc_sel = 2'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000000???????????????0100000000?: rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'd1610612736: rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000001???????????????0000000011?: rc_sel = 2'h0; endcase @@ -72467,144 +79394,168 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: cry_in = dec19_dec19_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: cry_in = dec30_dec30_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: cry_in = dec31_dec31_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: cry_in = dec58_dec58_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: cry_in = dec62_dec62_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h16: cry_in = dec22_dec22_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h11: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h02: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h03: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: cry_in = 2'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000000???????????????0100000000?: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'd1610612736: cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000001???????????????0000000011?: cry_in = 2'h0; endcase @@ -72612,144 +79563,168 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: inv_a = dec19_dec19_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: inv_a = dec30_dec30_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: inv_a = dec31_dec31_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: inv_a = dec58_dec58_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: inv_a = dec62_dec62_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h16: inv_a = dec22_dec22_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h11: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h02: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h03: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: inv_a = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000000???????????????0100000000?: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'd1610612736: inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000001???????????????0000000011?: inv_a = 1'h0; endcase @@ -72757,144 +79732,168 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: inv_out = dec19_dec19_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: inv_out = dec30_dec30_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: inv_out = dec31_dec31_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: inv_out = dec58_dec58_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: inv_out = dec62_dec62_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h16: inv_out = dec22_dec22_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h11: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h02: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h03: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: inv_out = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000000???????????????0100000000?: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'd1610612736: inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000001???????????????0000000011?: inv_out = 1'h0; endcase @@ -72902,144 +79901,168 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: cry_out = dec19_dec19_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: cry_out = dec30_dec30_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: cry_out = dec31_dec31_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: cry_out = dec58_dec58_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: cry_out = dec62_dec62_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h16: cry_out = dec22_dec22_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h11: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h02: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h03: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: cry_out = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000000???????????????0100000000?: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'd1610612736: cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000001???????????????0000000011?: cry_out = 1'h0; endcase @@ -73047,144 +80070,168 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: br = dec19_dec19_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: br = dec30_dec30_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: br = dec31_dec31_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: br = dec58_dec58_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: br = dec62_dec62_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h16: br = dec22_dec22_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h11: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h02: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h03: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: br = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000000???????????????0100000000?: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'd1610612736: br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000001???????????????0000000011?: br = 1'h0; endcase @@ -73192,144 +80239,168 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: sgn_ext = dec19_dec19_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: sgn_ext = dec30_dec30_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: sgn_ext = dec31_dec31_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: sgn_ext = dec58_dec58_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: sgn_ext = dec62_dec62_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h16: sgn_ext = dec22_dec22_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h11: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: sgn_ext = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: sgn_ext = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h02: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h03: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: sgn_ext = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000000???????????????0100000000?: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'd1610612736: sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000001???????????????0000000011?: sgn_ext = 1'h0; endcase @@ -73337,144 +80408,168 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: rsrv = dec19_dec19_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: rsrv = dec30_dec30_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: rsrv = dec31_dec31_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: rsrv = dec58_dec58_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: rsrv = dec62_dec62_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h16: rsrv = dec22_dec22_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h11: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h02: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h03: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: rsrv = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000000???????????????0100000000?: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'd1610612736: rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000001???????????????0000000011?: rsrv = 1'h0; endcase @@ -73482,144 +80577,168 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: is_32b = dec19_dec19_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: is_32b = dec30_dec30_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: is_32b = dec31_dec31_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: is_32b = dec58_dec58_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: is_32b = dec62_dec62_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h16: is_32b = dec22_dec22_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h11: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h02: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h03: is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: is_32b = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000000???????????????0100000000?: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'd1610612736: is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000001???????????????0000000011?: is_32b = 1'h0; endcase @@ -73627,144 +80746,168 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: sgn = dec19_dec19_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: sgn = dec30_dec30_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: sgn = dec31_dec31_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: sgn = dec58_dec58_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: sgn = dec62_dec62_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h16: sgn = dec22_dec22_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h11: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h02: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h03: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: sgn = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000000???????????????0100000000?: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'd1610612736: sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000001???????????????0000000011?: sgn = 1'h0; endcase @@ -73772,144 +80915,168 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: lk = dec19_dec19_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: lk = dec30_dec30_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: lk = dec31_dec31_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: lk = dec58_dec58_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: lk = dec62_dec62_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h16: lk = dec22_dec22_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h11: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: lk = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: lk = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h02: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h03: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: lk = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000000???????????????0100000000?: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'd1610612736: lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000001???????????????0000000011?: lk = 1'h0; endcase @@ -73917,434 +81084,506 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un always @* begin if (\initial ) begin end sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: sgl_pipe = dec19_dec19_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: sgl_pipe = dec30_dec30_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: sgl_pipe = dec31_dec31_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: sgl_pipe = dec58_dec58_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: sgl_pipe = dec62_dec62_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h16: sgl_pipe = dec22_dec22_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h11: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + sgl_pipe = 1'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h02: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h03: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: sgl_pipe = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000000???????????????0100000000?: sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'd1610612736: sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000001???????????????0000000011?: sgl_pipe = 1'h1; endcase end always @* begin if (\initial ) begin end - function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: function_unit = dec19_dec19_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: function_unit = dec30_dec30_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: function_unit = dec31_dec31_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: function_unit = dec58_dec58_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: function_unit = dec62_dec62_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h16: function_unit = dec22_dec22_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: - function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: - function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: - function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: - function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h11: - function_unit = 14'h0080; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0080; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: - function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: - function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: - function_unit = 14'h0020; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0020; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: - function_unit = 14'h0020; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0020; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: - function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: - function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: - function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: - function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: - function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: - function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: - function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: - function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: - function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: - function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: - function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0100; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: - function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: - function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: - function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: - function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: - function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: - function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: - function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: - function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: - function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: - function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: - function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: - function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h02: - function_unit = 14'h0080; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0080; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h03: - function_unit = 14'h0080; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0080; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: - function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: - function_unit = 14'h0010; + function_unit = 15'h0010; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000000???????????????0100000000?: - function_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0000; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'd1610612736: - function_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + function_unit = 15'h0000; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000001???????????????0000000011?: - function_unit = 14'h0000; + function_unit = 15'h0000; endcase end always @* begin if (\initial ) begin end internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h13: internal_op = dec19_dec19_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1e: internal_op = dec30_dec30_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1f: internal_op = dec31_dec31_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3a: internal_op = dec58_dec58_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h3e: internal_op = dec62_dec62_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h16: internal_op = dec22_dec22_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0c: internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0d: internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0e: internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0f: internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h11: internal_op = 7'h49; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1c: internal_op = 7'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1d: internal_op = 7'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h12: internal_op = 7'h06; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h10: internal_op = 7'h07; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0b: internal_op = 7'h0a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h0a: internal_op = 7'h0a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h22: internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h23: internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h32: + internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h33: + internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h30: + internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h31: + internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2a: internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2b: internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h28: internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h29: internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h20: internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h21: internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h07: internal_op = 7'h32; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h18: internal_op = 7'h35; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h19: internal_op = 7'h35; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h14: internal_op = 7'h38; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h15: internal_op = 7'h38; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h17: internal_op = 7'h38; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h26: internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h27: internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h36: + internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h37: + internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h34: + internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 6'h35: + internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2c: internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h2d: internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h24: internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h25: internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h08: internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h02: internal_op = 7'h3f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h03: internal_op = 7'h3f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1a: internal_op = 7'h43; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 6'h1b: internal_op = 7'h43; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (\opcode_switch$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000000???????????????0100000000?: internal_op = 7'h05; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'd1610612736: internal_op = 7'h01; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 32'b000001???????????????0000000011?: internal_op = 7'h44; endcase @@ -74681,6 +81920,11 @@ module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_un assign RA = opcode_in[20:16]; assign RT = opcode_in[25:21]; assign RS = opcode_in[25:21]; + assign FRC = opcode_in[10:6]; + assign FRB = opcode_in[15:11]; + assign FRA = opcode_in[20:16]; + assign FRT = opcode_in[25:21]; + assign FRS = opcode_in[25:21]; assign PO = opcode_in[31:26]; assign opcode_in = \$2 ; assign \opcode_switch$1 = opcode_in; @@ -74701,20 +81945,20 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec19_SV_Etype; reg [1:0] dec19_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec19_SV_Ptype; reg [1:0] dec19_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec19_asmcode; reg [7:0] dec19_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec19_br; reg dec19_br; (* enum_base_type = "CRInSel" *) @@ -74726,7 +81970,7 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec19_cr_in; reg [2:0] dec19_cr_in; (* enum_base_type = "CROutSel" *) @@ -74736,17 +81980,17 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec19_cr_out; reg [2:0] dec19_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec19_cry_in; reg [1:0] dec19_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec19_cry_out; reg dec19_cry_out; (* enum_base_type = "Form" *) @@ -74780,34 +82024,37 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec19_form; reg [4:0] dec19_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] dec19_function_unit; - reg [13:0] dec19_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] dec19_function_unit; + reg [14:0] dec19_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec19_in1_sel; reg [2:0] dec19_in1_sel; (* enum_base_type = "In2Sel" *) @@ -74825,16 +82072,19 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec19_in2_sel; reg [3:0] dec19_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [1:0] dec19_in3_sel; - reg [1:0] dec19_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [2:0] dec19_in3_sel; + reg [2:0] dec19_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -74910,16 +82160,18 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec19_internal_op; reg [6:0] dec19_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec19_inv_a; reg dec19_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec19_inv_out; reg dec19_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec19_is_32b; reg dec19_is_32b; (* enum_base_type = "LdstLen" *) @@ -74928,10 +82180,10 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec19_ldst_len; reg [3:0] dec19_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec19_lk; reg dec19_lk; (* enum_base_type = "OutSel" *) @@ -74940,26 +82192,27 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec19_out_sel; reg [2:0] dec19_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec19_rc_sel; reg [1:0] dec19_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec19_rsrv; reg dec19_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec19_sgl_pipe; reg dec19_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec19_sgn; reg dec19_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec19_sgn_ext; reg dec19_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -74969,7 +82222,7 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec19_sv_cr_in; reg [2:0] dec19_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -74979,7 +82232,7 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec19_sv_cr_out; reg [2:0] dec19_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -74989,7 +82242,7 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec19_sv_in1; reg [2:0] dec19_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -74999,7 +82252,7 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec19_sv_in2; reg [2:0] dec19_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -75009,7 +82262,7 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec19_sv_in3; reg [2:0] dec19_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -75019,7 +82272,7 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec19_sv_out; reg [2:0] dec19_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -75029,7 +82282,7 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec19_sv_out2; reg [2:0] dec19_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -75037,113 +82290,113 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec19_upd; reg [1:0] dec19_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [9:0] opcode_switch; always @* begin if (\initial ) begin end - dec19_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec19_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: - dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec19_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: - dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec19_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: - dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec19_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: - dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec19_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: - dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec19_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: - dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec19_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: - dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec19_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: - dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec19_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: - dec19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec19_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: - dec19_function_unit = 14'h0020; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec19_function_unit = 15'h0020; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: - dec19_function_unit = 14'h0020; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec19_function_unit = 15'h0020; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: - dec19_function_unit = 14'h0020; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec19_function_unit = 15'h0020; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: - dec19_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec19_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h012: - dec19_function_unit = 14'h0080; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec19_function_unit = 15'h0080; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h112: - dec19_function_unit = 14'h0080; + dec19_function_unit = 15'h0080; endcase end always @* begin if (\initial ) begin end dec19_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: dec19_cr_in = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: dec19_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: dec19_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: dec19_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: dec19_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: dec19_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: dec19_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: dec19_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: dec19_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: dec19_cr_in = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: dec19_cr_in = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: dec19_cr_in = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: dec19_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h012: dec19_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h112: dec19_cr_in = 3'h0; endcase @@ -75151,51 +82404,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: dec19_cr_out = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: dec19_cr_out = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: dec19_cr_out = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: dec19_cr_out = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: dec19_cr_out = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: dec19_cr_out = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: dec19_cr_out = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: dec19_cr_out = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: dec19_cr_out = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: dec19_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: dec19_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: dec19_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: dec19_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h012: dec19_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h112: dec19_cr_out = 3'h0; endcase @@ -75203,51 +82456,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: dec19_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: dec19_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: dec19_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: dec19_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: dec19_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: dec19_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: dec19_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: dec19_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: dec19_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: dec19_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: dec19_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: dec19_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: dec19_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h012: dec19_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h112: dec19_sv_in1 = 3'h0; endcase @@ -75255,51 +82508,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: dec19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: dec19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: dec19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: dec19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: dec19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: dec19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: dec19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: dec19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: dec19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: dec19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: dec19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: dec19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: dec19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h012: dec19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h112: dec19_sv_in2 = 3'h0; endcase @@ -75307,51 +82560,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: dec19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: dec19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: dec19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: dec19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: dec19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: dec19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: dec19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: dec19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: dec19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: dec19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: dec19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: dec19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: dec19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h012: dec19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h112: dec19_sv_in3 = 3'h0; endcase @@ -75359,51 +82612,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: dec19_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: dec19_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: dec19_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: dec19_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: dec19_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: dec19_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: dec19_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: dec19_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: dec19_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: dec19_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: dec19_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: dec19_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: dec19_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h012: dec19_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h112: dec19_sv_out = 3'h0; endcase @@ -75411,51 +82664,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: dec19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: dec19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: dec19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: dec19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: dec19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: dec19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: dec19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: dec19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: dec19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: dec19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: dec19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: dec19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: dec19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h012: dec19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h112: dec19_sv_out2 = 3'h0; endcase @@ -75463,51 +82716,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: dec19_sv_cr_in = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: dec19_sv_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: dec19_sv_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: dec19_sv_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: dec19_sv_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: dec19_sv_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: dec19_sv_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: dec19_sv_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: dec19_sv_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: dec19_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: dec19_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: dec19_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: dec19_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h012: dec19_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h112: dec19_sv_cr_in = 3'h0; endcase @@ -75515,51 +82768,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: dec19_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: dec19_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: dec19_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: dec19_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: dec19_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: dec19_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: dec19_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: dec19_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: dec19_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: dec19_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: dec19_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: dec19_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: dec19_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h012: dec19_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h112: dec19_sv_cr_out = 3'h0; endcase @@ -75567,51 +82820,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: dec19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: dec19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: dec19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: dec19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: dec19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: dec19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: dec19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: dec19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: dec19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: dec19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: dec19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: dec19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: dec19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h012: dec19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h112: dec19_ldst_len = 4'h0; endcase @@ -75619,51 +82872,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: dec19_internal_op = 7'h2a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: dec19_internal_op = 7'h45; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: dec19_internal_op = 7'h45; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: dec19_internal_op = 7'h45; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: dec19_internal_op = 7'h45; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: dec19_internal_op = 7'h45; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: dec19_internal_op = 7'h45; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: dec19_internal_op = 7'h45; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: dec19_internal_op = 7'h45; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: dec19_internal_op = 7'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: dec19_internal_op = 7'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: dec19_internal_op = 7'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: dec19_internal_op = 7'h24; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h012: dec19_internal_op = 7'h46; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h112: dec19_internal_op = 7'h46; endcase @@ -75671,51 +82924,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: dec19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: dec19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: dec19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: dec19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: dec19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: dec19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: dec19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: dec19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: dec19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: dec19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: dec19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: dec19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: dec19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h012: dec19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h112: dec19_upd = 2'h0; endcase @@ -75723,51 +82976,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h012: dec19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h112: dec19_rc_sel = 2'h0; endcase @@ -75775,51 +83028,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: dec19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: dec19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: dec19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: dec19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: dec19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: dec19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: dec19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: dec19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: dec19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: dec19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: dec19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: dec19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: dec19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h012: dec19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h112: dec19_cry_in = 2'h0; endcase @@ -75827,103 +83080,103 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: - dec19_asmcode = 8'h6c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec19_asmcode = 8'h8c; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: dec19_asmcode = 8'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: dec19_asmcode = 8'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: dec19_asmcode = 8'h27; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: dec19_asmcode = 8'h28; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: dec19_asmcode = 8'h29; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: dec19_asmcode = 8'h2a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: dec19_asmcode = 8'h2b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: dec19_asmcode = 8'h2c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: dec19_asmcode = 8'h16; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: dec19_asmcode = 8'h17; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: dec19_asmcode = 8'h18; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: - dec19_asmcode = 8'h4c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec19_asmcode = 8'h62; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h012: - dec19_asmcode = 8'h91; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec19_asmcode = 8'hb1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h112: - dec19_asmcode = 8'h48; + dec19_asmcode = 8'h5e; endcase end always @* begin if (\initial ) begin end dec19_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: dec19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: dec19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: dec19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: dec19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: dec19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: dec19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: dec19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: dec19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: dec19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: dec19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: dec19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: dec19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: dec19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h012: dec19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h112: dec19_inv_a = 1'h0; endcase @@ -75931,51 +83184,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: dec19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: dec19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: dec19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: dec19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: dec19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: dec19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: dec19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: dec19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: dec19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: dec19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: dec19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: dec19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: dec19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h012: dec19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h112: dec19_inv_out = 1'h0; endcase @@ -75983,51 +83236,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: dec19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: dec19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: dec19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: dec19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: dec19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: dec19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: dec19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: dec19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: dec19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: dec19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: dec19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: dec19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: dec19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h012: dec19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h112: dec19_cry_out = 1'h0; endcase @@ -76035,51 +83288,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: dec19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: dec19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: dec19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: dec19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: dec19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: dec19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: dec19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: dec19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: dec19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: dec19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: dec19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: dec19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: dec19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h012: dec19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h112: dec19_br = 1'h0; endcase @@ -76087,51 +83340,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: dec19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: dec19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: dec19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: dec19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: dec19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: dec19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: dec19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: dec19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: dec19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: dec19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: dec19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: dec19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: dec19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h012: dec19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h112: dec19_sgn_ext = 1'h0; endcase @@ -76139,51 +83392,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: dec19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: dec19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: dec19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: dec19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: dec19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: dec19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: dec19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: dec19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: dec19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: dec19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: dec19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: dec19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: dec19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h012: dec19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h112: dec19_rsrv = 1'h0; endcase @@ -76191,51 +83444,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: dec19_form = 5'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: dec19_form = 5'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: dec19_form = 5'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: dec19_form = 5'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: dec19_form = 5'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: dec19_form = 5'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: dec19_form = 5'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: dec19_form = 5'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: dec19_form = 5'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: dec19_form = 5'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: dec19_form = 5'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: dec19_form = 5'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: dec19_form = 5'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h012: dec19_form = 5'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h112: dec19_form = 5'h09; endcase @@ -76243,51 +83496,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: dec19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: dec19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: dec19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: dec19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: dec19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: dec19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: dec19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: dec19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: dec19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: dec19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: dec19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: dec19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: dec19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h012: dec19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h112: dec19_is_32b = 1'h0; endcase @@ -76295,51 +83548,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: dec19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: dec19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: dec19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: dec19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: dec19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: dec19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: dec19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: dec19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: dec19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: dec19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: dec19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: dec19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: dec19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h012: dec19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h112: dec19_sgn = 1'h0; endcase @@ -76347,51 +83600,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: dec19_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: dec19_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: dec19_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: dec19_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: dec19_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: dec19_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: dec19_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: dec19_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: dec19_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: dec19_lk = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: dec19_lk = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: dec19_lk = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: dec19_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h012: dec19_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h112: dec19_lk = 1'h0; endcase @@ -76399,51 +83652,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: dec19_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: dec19_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: dec19_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: dec19_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: dec19_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: dec19_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: dec19_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: dec19_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: dec19_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: dec19_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: dec19_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: dec19_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: dec19_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h012: dec19_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h112: dec19_sgl_pipe = 1'h0; endcase @@ -76451,51 +83704,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: dec19_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: dec19_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: dec19_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: dec19_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: dec19_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: dec19_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: dec19_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: dec19_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: dec19_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: dec19_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: dec19_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: dec19_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: dec19_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h012: dec19_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h112: dec19_SV_Etype = 2'h0; endcase @@ -76503,51 +83756,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: dec19_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: dec19_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: dec19_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: dec19_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: dec19_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: dec19_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: dec19_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: dec19_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: dec19_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: dec19_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: dec19_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: dec19_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: dec19_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h012: dec19_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h112: dec19_SV_Ptype = 2'h0; endcase @@ -76555,51 +83808,51 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: dec19_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: dec19_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: dec19_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: dec19_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: dec19_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: dec19_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: dec19_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: dec19_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: dec19_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: dec19_in1_sel = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: dec19_in1_sel = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: dec19_in1_sel = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: dec19_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h012: dec19_in1_sel = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h112: dec19_in1_sel = 3'h3; endcase @@ -76607,155 +83860,155 @@ module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, always @* begin if (\initial ) begin end dec19_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: dec19_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: dec19_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: dec19_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: dec19_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: dec19_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: dec19_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: dec19_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: dec19_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: dec19_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: dec19_in2_sel = 4'hc; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: dec19_in2_sel = 4'hc; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: dec19_in2_sel = 4'hc; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: dec19_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h012: dec19_in2_sel = 4'hc; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h112: dec19_in2_sel = 4'hc; endcase end always @* begin if (\initial ) begin end - dec19_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec19_in3_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: - dec19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec19_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: - dec19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec19_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: - dec19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec19_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: - dec19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec19_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: - dec19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec19_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: - dec19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec19_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: - dec19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec19_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: - dec19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec19_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: - dec19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec19_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: - dec19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec19_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: - dec19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec19_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: - dec19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec19_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: - dec19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec19_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h012: - dec19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec19_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h112: - dec19_in3_sel = 2'h0; + dec19_in3_sel = 3'h0; endcase end always @* begin if (\initial ) begin end dec19_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h000: dec19_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h101: dec19_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h081: dec19_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h121: dec19_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0e1: dec19_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h021: dec19_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1c1: dec19_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h1a1: dec19_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h0c1: dec19_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h210: dec19_out_sel = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h010: dec19_out_sel = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h230: dec19_out_sel = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h096: dec19_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h012: dec19_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 10'h112: dec19_out_sel = 3'h0; endcase @@ -76765,209 +84018,238 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.dec2" *) (* generator = "nMigen" *) -module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, rego_ok, ea, ea_ok, reg1, reg1_ok, reg2, reg2_ok, reg3, reg3_ok, spro, spro_ok, spr1, spr1_ok, xer_in, xer_out, fast1, fast1_ok, fast2, fast2_ok, fasto1, fasto1_ok, fasto2, fasto2_ok, cr_in1, cr_in1_ok, cr_in2, cr_in2_ok, \cr_in2$1 , \cr_in2_ok$2 , cr_out, cr_out_ok, msr, cia, insn, insn_type, fn_unit, lk, rc, rc_ok, oe, oe_ok, input_carry, traptype, \exc_$signal , \exc_$signal$3 , \exc_$signal$4 , \exc_$signal$5 , \exc_$signal$6 , \exc_$signal$7 , \exc_$signal$8 , \exc_$signal$9 , trapaddr, cr_rd, cr_rd_ok, cr_wr, cr_wr_ok, is_32bit, sv_a_nz, cur_eint); +module dec2(bigendian, cur_pc, cur_msr, cur_dec, cur_cur_svstep, cur_cur_subvl, cur_cur_dststep, cur_cur_srcstep, cur_cur_vl, cur_cur_maxvl, raw_opcode_in, asmcode, rego, rego_ok, ea, ea_ok, reg1, reg1_ok, reg2, reg2_ok, reg3, reg3_ok, spro, spro_ok, spr1, spr1_ok, xer_in, xer_out, fast1, fast1_ok, fast2, fast2_ok, fast3, fast3_ok, fasto1, fasto1_ok, fasto2, fasto2_ok, fasto3, fasto3_ok, cr_in1, cr_in1_ok, cr_in2, cr_in2_ok, \cr_in2$1 , \cr_in2_ok$2 , cr_out, cr_out_ok, sv_pred_sz, sv_pred_dz, sv_saturate, SV_Ptype, msr, cia, svstate, insn, insn_type, fn_unit, lk, rc, rc_ok, oe, oe_ok, input_carry, traptype, \exc_$signal , \exc_$signal$3 , \exc_$signal$4 , \exc_$signal$5 , \exc_$signal$6 , \exc_$signal$7 , \exc_$signal$8 , \exc_$signal$9 , trapaddr, cr_rd, cr_rd_ok, cr_wr, cr_wr_ok, is_32bit, cur_eint); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [6:0] \$100 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [6:0] \$102 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [6:0] \$104 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1218" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1274" *) wire \$106 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1276" *) wire \$108 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1278" *) wire \$110 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1226" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1282" *) wire \$112 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1249" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1305" *) wire \$114 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1250" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1306" *) wire \$116 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1251" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1307" *) wire \$118 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1252" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1308" *) wire \$120 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1300" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1356" *) wire \$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1357" *) wire \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1357" *) wire \$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1310" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1369" *) wire \$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$37 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$39 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$41 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$43 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$45 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$47 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$49 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:885" *) wire \$51 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) wire \$53 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) wire \$55 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$57 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$59 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$61 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$63 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$65 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) wire \$67 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) wire \$69 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$71 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$73 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$75 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$77 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$79 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$81 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$83 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [6:0] \$90 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [6:0] \$92 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [6:0] \$94 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [6:0] \$96 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [6:0] \$98 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [1:0] SV_Ptype; + reg [1:0] SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:104" *) output [7:0] asmcode; reg [7:0] asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:479" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:46" *) output [63:0] cia; reg [63:0] cia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [6:0] cr_in1; reg [6:0] cr_in1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_in1_ok; reg cr_in1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [6:0] cr_in2; reg [6:0] cr_in2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [6:0] \cr_in2$1 ; reg [6:0] \cr_in2$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_in2_ok; reg cr_in2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output \cr_in2_ok$2 ; reg \cr_in2_ok$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [6:0] cr_out; reg [6:0] cr_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_out_ok; reg cr_out_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [7:0] cr_rd; reg [7:0] cr_rd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_rd_ok; reg cr_rd_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [7:0] cr_wr; reg [7:0] cr_wr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_wr_ok; reg cr_wr_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:28" *) + input [6:0] cur_cur_dststep; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:31" *) + input [6:0] cur_cur_maxvl; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:29" *) + input [6:0] cur_cur_srcstep; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:27" *) + input [1:0] cur_cur_subvl; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:26" *) + input [1:0] cur_cur_svstep; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:30" *) + input [6:0] cur_cur_vl; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:19" *) input [63:0] cur_dec; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:18" *) input cur_eint; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:17" *) input [63:0] cur_msr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:16" *) input [63:0] cur_pc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \dec2_exc_$signal ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \dec2_exc_$signal$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \dec2_exc_$signal$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \dec2_exc_$signal$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \dec2_exc_$signal$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \dec2_exc_$signal$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \dec2_exc_$signal$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \dec2_exc_$signal$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] dec_BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] dec_BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] dec_BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] dec_BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] dec_BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] dec_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] dec_FRA; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] dec_FRB; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] dec_FRC; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] dec_FRS; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [4:0] dec_FRT; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [7:0] dec_FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire dec_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire dec_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] dec_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] dec_RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] dec_RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] dec_RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire dec_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] dec_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [4:0] dec_XL_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [9:0] dec_XL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] dec_X_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) wire [2:0] dec_X_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [2:0] dec_a_fast_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_a_fast_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [4:0] dec_a_reg_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_a_reg_a_ok; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -76975,7 +84257,9 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:110" *) wire [2:0] dec_a_sel_in; (* enum_base_type = "SPR" *) (* enum_value_0000000001 = "XER" *) @@ -77091,21 +84375,21 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_1110000000 = "PPR" *) (* enum_value_1110000010 = "PPR32" *) (* enum_value_1111111111 = "PIR" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [9:0] dec_a_spr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_a_spr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:115" *) wire dec_a_sv_nz; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [7:0] dec_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [2:0] dec_b_fast_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_b_fast_b_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [6:0] dec_b_reg_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_b_reg_b_ok; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -77122,18 +84406,21 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:222" *) wire [3:0] dec_b_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [4:0] dec_c_reg_c; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_c_reg_c_ok; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315" *) - wire [1:0] dec_c_sel_in; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:331" *) + wire [2:0] dec_c_sel_in; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -77143,25 +84430,25 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_cr_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [2:0] dec_cr_in_cr_bitfield; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [2:0] dec_cr_in_cr_bitfield_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_cr_in_cr_bitfield_b_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [2:0] dec_cr_in_cr_bitfield_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_cr_in_cr_bitfield_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_cr_in_cr_bitfield_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [7:0] dec_cr_in_cr_fxm; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_cr_in_cr_fxm_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:571" *) wire [31:0] dec_cr_in_insn_in; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -77172,7 +84459,7 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:542" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:570" *) wire [2:0] dec_cr_in_sel_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -77181,19 +84468,19 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_cr_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [2:0] dec_cr_out_cr_bitfield; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_cr_out_cr_bitfield_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [7:0] dec_cr_out_cr_fxm; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_cr_out_cr_fxm_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:646" *) wire [31:0] dec_cr_out_insn_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:644" *) wire dec_cr_out_rc_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -77202,38 +84489,41 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:617" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:645" *) wire [2:0] dec_cr_out_sel_in; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_cry_in; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -77250,14 +84540,17 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -77333,31 +84626,37 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1244" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1300" *) wire dec_irq_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_is_32b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_lk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [2:0] dec_o2_fast_o2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_o2_fast_o2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [2:0] dec_o2_fast_o3; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire dec_o2_fast_o3_ok; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:441" *) wire dec_o2_lk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [4:0] dec_o2_reg_o2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_o2_reg_o2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [2:0] dec_o_fast_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_o_fast_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [4:0] dec_o_reg_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_o_reg_o_ok; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -77365,7 +84664,8 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:351" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:373" *) wire [2:0] dec_o_sel_in; (* enum_base_type = "SPR" *) (* enum_value_0000000001 = "XER" *) @@ -77481,21 +84781,21 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_1110000000 = "PPR" *) (* enum_value_1110000010 = "PPR32" *) (* enum_value_1111111111 = "PIR" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [9:0] dec_o_spr_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_o_spr_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_oe_oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_oe_oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:527" *) wire [1:0] dec_oe_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] dec_opcode_in; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -77503,130 +84803,144 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_out_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_rc_rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_rc_rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_rc_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:490" *) wire [1:0] dec_rc_sel_in; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [6:0] ea; reg [6:0] ea; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output ea_ok; reg ea_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) output \exc_$signal ; reg \exc_$signal ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) output \exc_$signal$3 ; reg \exc_$signal$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) output \exc_$signal$4 ; reg \exc_$signal$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) output \exc_$signal$5 ; reg \exc_$signal$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) output \exc_$signal$6 ; reg \exc_$signal$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) output \exc_$signal$7 ; reg \exc_$signal$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) output \exc_$signal$8 ; reg \exc_$signal$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) output \exc_$signal$9 ; reg \exc_$signal$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1243" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1299" *) wire ext_irq_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [2:0] fast1; reg [2:0] fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output fast1_ok; reg fast1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [2:0] fast2; reg [2:0] fast2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output fast2_ok; reg fast2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [2:0] fast3; + reg [2:0] fast3; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output fast3_ok; + reg fast3_ok; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [2:0] fasto1; reg [2:0] fasto1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output fasto1_ok; reg fasto1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [2:0] fasto2; reg [2:0] fasto2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output fasto2_ok; reg fasto2_ok; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [2:0] fasto3; + reg [2:0] fasto3; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output fasto3_ok; + reg fasto3_ok; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" *) - output [13:0] fn_unit; - reg [13:0] fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1246" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:52" *) + output [14:0] fn_unit; + reg [14:0] fn_unit; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1302" *) wire illeg_ok; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:56" *) output [1:0] input_carry; reg [1:0] input_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:50" *) output [31:0] insn; reg [31:0] insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:491" *) wire [31:0] insn_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:528" *) wire [31:0] \insn_in$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:111" *) wire [31:0] \insn_in$85 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:210" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:223" *) wire [31:0] \insn_in$86 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:316" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:332" *) wire [31:0] \insn_in$87 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:352" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:374" *) wire [31:0] \insn_in$88 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:442" *) wire [31:0] \insn_in$89 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -77703,62 +85017,64 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:51" *) output [6:0] insn_type; reg [6:0] insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:62" *) output is_32bit; reg is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:884" *) wire is_mmu_spr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:53" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:52" *) reg is_priv_insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:883" *) wire is_spr_mv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:53" *) output lk; reg lk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:45" *) output [63:0] msr; reg [63:0] msr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output oe; reg oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output oe_ok; reg oe_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1245" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1301" *) wire priv_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:478" *) input [31:0] raw_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output rc; reg rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output rc_ok; reg rc_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [6:0] reg1; reg [6:0] reg1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output reg1_ok; reg reg1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [6:0] reg2; reg [6:0] reg2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output reg2_ok; reg reg2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [6:0] reg3; reg [6:0] reg3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output reg3_ok; reg reg3_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [6:0] rego; reg [6:0] rego; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output rego_ok; reg rego_ok; (* enum_base_type = "OutSel" *) @@ -77767,9 +85083,10 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:415" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:440" *) wire [2:0] sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:878" *) wire [9:0] spr; (* enum_base_type = "SPR" *) (* enum_value_0000000001 = "XER" *) @@ -77885,10 +85202,10 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_1110000000 = "PPR" *) (* enum_value_1110000010 = "PPR32" *) (* enum_value_1111111111 = "PIR" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [9:0] spr1; reg [9:0] spr1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output spr1_ok; reg spr1_ok; (* enum_base_type = "SPR" *) @@ -78005,67 +85322,91 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_1110000000 = "PPR" *) (* enum_value_1110000010 = "PPR32" *) (* enum_value_1111111111 = "PIR" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [9:0] spro; reg [9:0] spro; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output spro_ok; reg spro_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) - input sv_a_nz; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:747" *) + wire sv_a_nz; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output sv_pred_dz; + reg sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output sv_pred_sz; + reg sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + output [1:0] sv_saturate; + reg [1:0] sv_saturate; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:47" *) + output [31:0] svstate; + reg [31:0] svstate; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:104" *) wire [7:0] tmp_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [6:0] tmp_cr_in1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire tmp_cr_in1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [6:0] tmp_cr_in2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [6:0] \tmp_cr_in2$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire tmp_cr_in2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire \tmp_cr_in2_ok$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [6:0] tmp_cr_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire tmp_cr_out_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [6:0] tmp_ea; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire tmp_ea_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [2:0] tmp_fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire tmp_fast1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [2:0] tmp_fast2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire tmp_fast2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [2:0] tmp_fast3; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire tmp_fast3_ok; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [2:0] tmp_fasto1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire tmp_fasto1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [2:0] tmp_fasto2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire tmp_fasto2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [2:0] tmp_fasto3; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire tmp_fasto3_ok; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [6:0] tmp_reg1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire tmp_reg1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [6:0] tmp_reg2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire tmp_reg2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [6:0] tmp_reg3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire tmp_reg3_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [6:0] tmp_rego; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire tmp_rego_ok; (* enum_base_type = "SPR" *) (* enum_value_0000000001 = "XER" *) @@ -78181,9 +85522,9 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_1110000000 = "PPR" *) (* enum_value_1110000010 = "PPR32" *) (* enum_value_1111111111 = "PIR" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [9:0] tmp_spr1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire tmp_spr1_ok; (* enum_base_type = "SPR" *) (* enum_value_0000000001 = "XER" *) @@ -78299,60 +85640,77 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_1110000000 = "PPR" *) (* enum_value_1110000010 = "PPR32" *) (* enum_value_1111111111 = "PIR" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [9:0] tmp_spro; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire tmp_spro_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] tmp_tmp__SV_Ptype; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire tmp_tmp__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire tmp_tmp__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] tmp_tmp__sv_saturate; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:46" *) wire [63:0] tmp_tmp_cia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [7:0] tmp_tmp_cr_rd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire tmp_tmp_cr_rd_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [7:0] tmp_tmp_cr_wr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire tmp_tmp_cr_wr_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \tmp_tmp_exc_$signal ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \tmp_tmp_exc_$signal$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \tmp_tmp_exc_$signal$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \tmp_tmp_exc_$signal$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \tmp_tmp_exc_$signal$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \tmp_tmp_exc_$signal$25 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \tmp_tmp_exc_$signal$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \tmp_tmp_exc_$signal$27 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" *) - reg [13:0] tmp_tmp_fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:52" *) + reg [14:0] tmp_tmp_fn_unit; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:56" *) wire [1:0] tmp_tmp_input_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:50" *) wire [31:0] tmp_tmp_insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -78429,86 +85787,90 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:51" *) reg [6:0] tmp_tmp_insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:62" *) wire tmp_tmp_is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:53" *) reg tmp_tmp_lk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:45" *) wire [63:0] tmp_tmp_msr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire tmp_tmp_oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire tmp_tmp_oe_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire tmp_tmp_rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire tmp_tmp_rc_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:47" *) + wire [31:0] tmp_tmp_svstate; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:59" *) reg [12:0] tmp_tmp_trapaddr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:57" *) wire [7:0] tmp_tmp_traptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:114" *) reg [2:0] tmp_xer_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:115" *) reg tmp_xer_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:59" *) output [12:0] trapaddr; reg [12:0] trapaddr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:57" *) output [7:0] traptype; reg [7:0] traptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:114" *) output [2:0] xer_in; reg [2:0] xer_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:115" *) output xer_out; reg xer_out; - assign \$100 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) dec_cr_in_cr_bitfield_b; - assign \$102 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) dec_cr_in_cr_bitfield_o; - assign \$104 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) dec_cr_out_cr_bitfield; - assign \$106 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1218" *) 7'h2e; - assign \$108 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220" *) 7'h0a; - assign \$110 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222" *) 7'h31; - assign \$112 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1226" *) 7'h3f; - assign \$114 = cur_eint & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1249" *) cur_msr[15]; - assign \$116 = cur_dec[63] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1250" *) cur_msr[15]; - assign \$118 = is_priv_insn & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1251" *) cur_msr[14]; - assign \$120 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1252" *) 7'h00; - assign \$28 = insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1300" *) 7'h3f; - assign \$30 = insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" *) 7'h49; - assign \$32 = \$28 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" *) \$30 ; - assign \$34 = insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1310" *) 7'h46; - assign \$37 = dec_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$39 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$37 ; - assign \$41 = \$39 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$43 = dec_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; - assign \$45 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$43 ; - assign \$47 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$49 = \$45 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$47 ; - assign \$51 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31; - assign \$53 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e; - assign \$55 = \$51 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$53 ; - assign \$57 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12; - assign \$59 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13; - assign \$61 = \$57 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$59 ; - assign \$63 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0; - assign \$65 = \$61 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$63 ; - assign \$67 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30; - assign \$69 = \$65 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$67 ; - assign \$71 = dec_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$73 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$71 ; - assign \$75 = \$73 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$77 = dec_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; - assign \$79 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$77 ; - assign \$81 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$83 = \$79 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$81 ; - assign \$90 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) dec_a_reg_a; - assign \$92 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) dec_c_reg_c; - assign \$94 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) dec_o_reg_o; - assign \$96 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) dec_o2_reg_o2; - assign \$98 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) dec_cr_in_cr_bitfield; + assign \$100 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) dec_cr_in_cr_bitfield_b; + assign \$102 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) dec_cr_in_cr_bitfield_o; + assign \$104 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) dec_cr_out_cr_bitfield; + assign \$106 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1274" *) 7'h2e; + assign \$108 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1276" *) 7'h0a; + assign \$110 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1278" *) 7'h31; + assign \$112 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1282" *) 7'h3f; + assign \$114 = cur_eint & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1305" *) cur_msr[15]; + assign \$116 = cur_dec[63] & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1306" *) cur_msr[15]; + assign \$118 = is_priv_insn & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1307" *) cur_msr[14]; + assign \$120 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1308" *) 7'h00; + assign \$28 = insn_type == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1356" *) 7'h3f; + assign \$30 = insn_type == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1357" *) 7'h49; + assign \$32 = \$28 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1357" *) \$30 ; + assign \$34 = insn_type == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1369" *) 7'h46; + assign \$37 = dec_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) 15'h0400; + assign \$39 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) \$37 ; + assign \$41 = \$39 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) is_mmu_spr; + assign \$43 = dec_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) 15'h0800; + assign \$45 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$43 ; + assign \$47 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) is_mmu_spr; + assign \$49 = \$45 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$47 ; + assign \$51 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:885" *) 7'h31; + assign \$53 = dec_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) 7'h2e; + assign \$55 = \$51 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) \$53 ; + assign \$57 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 5'h12; + assign \$59 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 5'h13; + assign \$61 = \$57 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) \$59 ; + assign \$63 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 10'h2d0; + assign \$65 = \$61 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) \$63 ; + assign \$67 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) 6'h30; + assign \$69 = \$65 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) \$67 ; + assign \$71 = dec_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) 15'h0400; + assign \$73 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) \$71 ; + assign \$75 = \$73 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) is_mmu_spr; + assign \$77 = dec_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) 15'h0800; + assign \$79 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$77 ; + assign \$81 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) is_mmu_spr; + assign \$83 = \$79 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$81 ; + assign \$90 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) dec_a_reg_a; + assign \$92 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) dec_c_reg_c; + assign \$94 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) dec_o_reg_o; + assign \$96 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) dec_o2_reg_o2; + assign \$98 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) dec_cr_in_cr_bitfield; \dec$171 dec ( .BA(dec_BA), .BB(dec_BB), @@ -78516,6 +85878,11 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r .BI(dec_BI), .BO(dec_BO), .BT(dec_BT), + .FRA(dec_FRA), + .FRB(dec_FRB), + .FRC(dec_FRC), + .FRS(dec_FRS), + .FRT(dec_FRT), .FXM(dec_FXM), .LK(dec_LK), .OE(dec_OE), @@ -78549,6 +85916,8 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r ); dec_a dec_a ( .BO(dec_BO), + .FRA(dec_FRA), + .FRS(dec_FRS), .RA(dec_RA), .RS(dec_RS), .SPR(dec_SPR), @@ -78564,6 +85933,7 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r .sv_nz(dec_a_sv_nz) ); dec_b dec_b ( + .FRB(dec_FRB), .RB(dec_RB), .RS(dec_RS), .XL_XO(dec_XL_XO), @@ -78575,6 +85945,8 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r .sel_in(dec_b_sel_in) ); dec_c dec_c ( + .FRC(dec_FRC), + .FRS(dec_FRS), .RB(dec_RB), .RS(dec_RS), .reg_c(dec_c_reg_c), @@ -78616,6 +85988,7 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r ); dec_o dec_o ( .BO(dec_BO), + .FRT(dec_FRT), .RA(dec_RA), .RT(dec_RT), .SPR(dec_SPR), @@ -78632,6 +86005,8 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r .RA(dec_RA), .fast_o2(dec_o2_fast_o2), .fast_o2_ok(dec_o2_fast_o2_ok), + .fast_o3(dec_o2_fast_o3), + .fast_o3_ok(dec_o2_fast_o3_ok), .internal_op(dec_internal_op), .lk(dec_o2_lk), .reg_o2(dec_o2_reg_o2), @@ -78654,15 +86029,15 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) casez ({ \$83 , \$75 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" */ 2'b?1: - tmp_tmp_fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + tmp_tmp_fn_unit = 15'h0000; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" */ 2'b1?: - tmp_tmp_fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" */ + tmp_tmp_fn_unit = 15'h0000; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:900" */ default: tmp_tmp_fn_unit = dec_function_unit; endcase @@ -78670,38 +86045,25 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r always @* begin if (\initial ) begin end tmp_tmp_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:898" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:948" *) casez (dec_lk) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:898" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:948" */ 1'h1: tmp_tmp_lk = dec_LK; endcase end - always @* begin - if (\initial ) begin end - tmp_tmp_insn_type = dec_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) - casez ({ \$49 , \$41 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ - 2'b?1: - tmp_tmp_insn_type = 7'h00; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ - 2'b1?: - tmp_tmp_insn_type = 7'h00; - endcase - end always @* begin if (\initial ) begin end tmp_xer_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1218" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1274" *) casez (\$106 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1218" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1274" */ 1'h1: tmp_xer_in = 3'h7; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1276" *) casez (\$108 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1276" */ 1'h1: tmp_xer_in = 3'h1; endcase @@ -78709,9 +86071,9 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r always @* begin if (\initial ) begin end tmp_xer_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1278" *) casez (\$110 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1278" */ 1'h1: tmp_xer_out = 1'h1; endcase @@ -78719,9 +86081,9 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r always @* begin if (\initial ) begin end tmp_tmp_trapaddr = 13'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1226" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1282" *) casez (\$112 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1226" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1282" */ 1'h1: tmp_tmp_trapaddr = 13'h0070; endcase @@ -78729,183 +86091,209 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r always @* begin if (\initial ) begin end is_priv_insn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:54" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:53" *) casez (dec_internal_op) /* \nmigen.decoding = "OP_ATTN/5|OP_MFMSR/71|OP_MTMSRD/72|OP_MTMSR/74|OP_RFID/70" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:56" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:55" */ 7'h05, 7'h47, 7'h48, 7'h4a, 7'h46: is_priv_insn = 1'h1; /* \nmigen.decoding = "OP_TLBIE/75" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:58" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:57" */ 7'h4b: is_priv_insn = 1'h1; /* \nmigen.decoding = "OP_MFSPR/46|OP_MTSPR/49" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:58" */ 7'h2e, 7'h31: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:60" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:59" *) casez (tmp_tmp_insn[20]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:60" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:59" */ 1'h1: is_priv_insn = 1'h1; endcase endcase end + always @* begin + if (\initial ) begin end + tmp_tmp_insn_type = dec_internal_op; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) + casez ({ \$49 , \$41 }) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" */ + 2'b?1: + tmp_tmp_insn_type = 7'h00; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" */ + 2'b1?: + tmp_tmp_insn_type = 7'h00; + endcase + end always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1256" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1312" *) casez ({ illeg_ok, priv_ok, ext_irq_ok, dec_irq_ok, \dec2_exc_$signal }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1256" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1312" */ 5'b????1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1257" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1313" *) casez ({ \dec2_exc_$signal$13 , \dec2_exc_$signal$12 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1257" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1313" */ 2'b?1: begin - { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, cia, msr, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto2_ok, fasto2, fasto1_ok, fasto1, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 358'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; insn = dec_opcode_in; insn_type = 7'h3f; - fn_unit = 14'h0080; + fn_unit = 15'h0080; trapaddr = 13'h0060; traptype = 8'h02; msr = cur_msr; cia = cur_pc; + svstate = { cur_cur_maxvl, cur_cur_vl, cur_cur_srcstep, cur_cur_dststep, cur_cur_subvl, cur_cur_svstep }; end - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1259" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1315" */ 2'b1?: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1316" *) casez (\dec2_exc_$signal$14 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1260" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1316" */ 1'h1: begin - { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, cia, msr, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto2_ok, fasto2, fasto1_ok, fasto1, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 358'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; insn = dec_opcode_in; insn_type = 7'h3f; - fn_unit = 14'h0080; + fn_unit = 15'h0080; trapaddr = 13'h0048; traptype = 8'h02; msr = cur_msr; cia = cur_pc; + svstate = { cur_cur_maxvl, cur_cur_vl, cur_cur_srcstep, cur_cur_dststep, cur_cur_subvl, cur_cur_svstep }; end - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1262" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1318" */ default: begin - { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, cia, msr, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto2_ok, fasto2, fasto1_ok, fasto1, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 358'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; insn = dec_opcode_in; insn_type = 7'h3f; - fn_unit = 14'h0080; + fn_unit = 15'h0080; trapaddr = 13'h0040; traptype = 8'h40; - { \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal } = { \dec2_exc_$signal$14 , \dec2_exc_$signal$18 , \dec2_exc_$signal$17 , \dec2_exc_$signal$16 , \dec2_exc_$signal$15 , \dec2_exc_$signal$13 , \dec2_exc_$signal$12 , \dec2_exc_$signal }; + { \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal } = { \dec2_exc_$signal , \dec2_exc_$signal$14 , \dec2_exc_$signal$18 , \dec2_exc_$signal$17 , \dec2_exc_$signal$16 , \dec2_exc_$signal$15 , \dec2_exc_$signal$13 , \dec2_exc_$signal$12 }; msr = cur_msr; cia = cur_pc; + svstate = { cur_cur_maxvl, cur_cur_vl, cur_cur_srcstep, cur_cur_dststep, cur_cur_subvl, cur_cur_svstep }; end endcase - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1265" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1321" */ default: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1266" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1322" *) casez (\dec2_exc_$signal$14 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1266" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1322" */ 1'h1: begin - { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, cia, msr, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto2_ok, fasto2, fasto1_ok, fasto1, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 358'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; insn = dec_opcode_in; insn_type = 7'h3f; - fn_unit = 14'h0080; + fn_unit = 15'h0080; trapaddr = 13'h0038; traptype = 8'h02; msr = cur_msr; cia = cur_pc; + svstate = { cur_cur_maxvl, cur_cur_vl, cur_cur_srcstep, cur_cur_dststep, cur_cur_subvl, cur_cur_svstep }; end - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1268" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1324" */ default: begin - { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, cia, msr, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto2_ok, fasto2, fasto1_ok, fasto1, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 358'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; insn = dec_opcode_in; insn_type = 7'h3f; - fn_unit = 14'h0080; + fn_unit = 15'h0080; trapaddr = 13'h0030; traptype = 8'h02; msr = cur_msr; cia = cur_pc; + svstate = { cur_cur_maxvl, cur_cur_vl, cur_cur_srcstep, cur_cur_dststep, cur_cur_subvl, cur_cur_svstep }; end endcase endcase - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1272" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1328" */ 5'b???1?: begin - { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, cia, msr, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto2_ok, fasto2, fasto1_ok, fasto1, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 358'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; insn = dec_opcode_in; insn_type = 7'h3f; - fn_unit = 14'h0080; + fn_unit = 15'h0080; trapaddr = 13'h0090; traptype = 8'h20; msr = cur_msr; cia = cur_pc; + svstate = { cur_cur_maxvl, cur_cur_vl, cur_cur_srcstep, cur_cur_dststep, cur_cur_subvl, cur_cur_svstep }; end - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1276" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1332" */ 5'b??1??: begin - { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, cia, msr, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto2_ok, fasto2, fasto1_ok, fasto1, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 358'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; insn = dec_opcode_in; insn_type = 7'h3f; - fn_unit = 14'h0080; + fn_unit = 15'h0080; trapaddr = 13'h0050; traptype = 8'h10; msr = cur_msr; cia = cur_pc; + svstate = { cur_cur_maxvl, cur_cur_vl, cur_cur_srcstep, cur_cur_dststep, cur_cur_subvl, cur_cur_svstep }; end - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1280" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1336" */ 5'b?1???: begin - { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, cia, msr, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto2_ok, fasto2, fasto1_ok, fasto1, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 358'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; insn = dec_opcode_in; insn_type = 7'h3f; - fn_unit = 14'h0080; + fn_unit = 15'h0080; trapaddr = 13'h0070; traptype = 8'h02; msr = cur_msr; cia = cur_pc; + svstate = { cur_cur_maxvl, cur_cur_vl, cur_cur_srcstep, cur_cur_dststep, cur_cur_subvl, cur_cur_svstep }; end - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1287" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1343" */ 5'h1?: begin - { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, cia, msr, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto2_ok, fasto2, fasto1_ok, fasto1, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 358'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = 405'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; insn = dec_opcode_in; insn_type = 7'h3f; - fn_unit = 14'h0080; + fn_unit = 15'h0080; trapaddr = 13'h0070; traptype = 8'h80; msr = cur_msr; cia = cur_pc; + svstate = { cur_cur_maxvl, cur_cur_vl, cur_cur_srcstep, cur_cur_dststep, cur_cur_subvl, cur_cur_svstep }; end - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1292" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1348" */ default: - { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, cia, msr, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto2_ok, fasto2, fasto1_ok, fasto1, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = { tmp_tmp_is_32bit, tmp_tmp_cr_wr_ok, tmp_tmp_cr_wr, tmp_tmp_cr_rd_ok, tmp_tmp_cr_rd, tmp_tmp_trapaddr, \tmp_tmp_exc_$signal$27 , \tmp_tmp_exc_$signal$26 , \tmp_tmp_exc_$signal$25 , \tmp_tmp_exc_$signal$24 , \tmp_tmp_exc_$signal$23 , \tmp_tmp_exc_$signal$22 , \tmp_tmp_exc_$signal$21 , \tmp_tmp_exc_$signal , tmp_tmp_traptype, tmp_tmp_input_carry, tmp_tmp_oe_ok, tmp_tmp_oe, tmp_tmp_rc_ok, tmp_tmp_rc, tmp_tmp_lk, tmp_tmp_fn_unit, tmp_tmp_insn_type, tmp_tmp_insn, tmp_tmp_cia, tmp_tmp_msr, tmp_cr_out_ok, tmp_cr_out, \tmp_cr_in2_ok$20 , \tmp_cr_in2$19 , tmp_cr_in2_ok, tmp_cr_in2, tmp_cr_in1_ok, tmp_cr_in1, tmp_fasto2_ok, tmp_fasto2, tmp_fasto1_ok, tmp_fasto1, tmp_fast2_ok, tmp_fast2, tmp_fast1_ok, tmp_fast1, tmp_xer_out, tmp_xer_in, tmp_spr1_ok, tmp_spr1, tmp_spro_ok, tmp_spro, tmp_reg3_ok, tmp_reg3, tmp_reg2_ok, tmp_reg2, tmp_reg1_ok, tmp_reg1, tmp_ea_ok, tmp_ea, tmp_rego_ok, tmp_rego, tmp_asmcode }; + { is_32bit, cr_wr_ok, cr_wr, cr_rd_ok, cr_rd, trapaddr, \exc_$signal$9 , \exc_$signal$8 , \exc_$signal$7 , \exc_$signal$6 , \exc_$signal$5 , \exc_$signal$4 , \exc_$signal$3 , \exc_$signal , traptype, input_carry, oe_ok, oe, rc_ok, rc, lk, fn_unit, insn_type, insn, svstate, cia, msr, SV_Ptype, sv_saturate, sv_pred_dz, sv_pred_sz, cr_out_ok, cr_out, \cr_in2_ok$2 , \cr_in2$1 , cr_in2_ok, cr_in2, cr_in1_ok, cr_in1, fasto3_ok, fasto3, fasto2_ok, fasto2, fasto1_ok, fasto1, fast3_ok, fast3, fast2_ok, fast2, fast1_ok, fast1, xer_out, xer_in, spr1_ok, spr1, spro_ok, spro, reg3_ok, reg3, reg2_ok, reg2, reg1_ok, reg1, ea_ok, ea, rego_ok, rego, asmcode } = { tmp_tmp_is_32bit, tmp_tmp_cr_wr_ok, tmp_tmp_cr_wr, tmp_tmp_cr_rd_ok, tmp_tmp_cr_rd, tmp_tmp_trapaddr, \tmp_tmp_exc_$signal$27 , \tmp_tmp_exc_$signal$26 , \tmp_tmp_exc_$signal$25 , \tmp_tmp_exc_$signal$24 , \tmp_tmp_exc_$signal$23 , \tmp_tmp_exc_$signal$22 , \tmp_tmp_exc_$signal$21 , \tmp_tmp_exc_$signal , tmp_tmp_traptype, tmp_tmp_input_carry, tmp_tmp_oe_ok, tmp_tmp_oe, tmp_tmp_rc_ok, tmp_tmp_rc, tmp_tmp_lk, tmp_tmp_fn_unit, tmp_tmp_insn_type, tmp_tmp_insn, tmp_tmp_svstate, tmp_tmp_cia, tmp_tmp_msr, tmp_tmp__SV_Ptype, tmp_tmp__sv_saturate, tmp_tmp__sv_pred_dz, tmp_tmp__sv_pred_sz, tmp_cr_out_ok, tmp_cr_out, \tmp_cr_in2_ok$20 , \tmp_cr_in2$19 , tmp_cr_in2_ok, tmp_cr_in2, tmp_cr_in1_ok, tmp_cr_in1, tmp_fasto3_ok, tmp_fasto3, tmp_fasto2_ok, tmp_fasto2, tmp_fasto1_ok, tmp_fasto1, tmp_fast3_ok, tmp_fast3, tmp_fast2_ok, tmp_fast2, tmp_fast1_ok, tmp_fast1, tmp_xer_out, tmp_xer_in, tmp_spr1_ok, tmp_spr1, tmp_spro_ok, tmp_spro, tmp_reg3_ok, tmp_reg3, tmp_reg2_ok, tmp_reg2, tmp_reg1_ok, tmp_reg1, tmp_ea_ok, tmp_ea, tmp_rego_ok, tmp_rego, tmp_asmcode }; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1357" *) casez (\$32 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1357" */ 1'h1: begin fasto1 = 3'h3; fasto1_ok = 1'h1; fasto2 = 3'h4; fasto2_ok = 1'h1; + fasto3 = 3'h0; + fasto3_ok = 1'h1; end endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1310" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1369" *) casez (\$34 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1310" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:1369" */ 1'h1: begin fast1 = 3'h3; fast1_ok = 1'h1; fast2 = 3'h4; fast2_ok = 1'h1; + fast3 = 3'h0; + fast3_ok = 1'h1; end endcase begin @@ -78921,6 +86309,12 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r assign \dec2_exc_$signal$17 = 1'h0; assign \dec2_exc_$signal$18 = 1'h0; assign tmp_asmcode = 8'h00; + assign tmp_fast3 = 3'h0; + assign tmp_fast3_ok = 1'h0; + assign tmp_tmp__sv_pred_sz = 1'h0; + assign tmp_tmp__sv_pred_dz = 1'h0; + assign tmp_tmp__sv_saturate = 2'h0; + assign tmp_tmp__SV_Ptype = 2'h0; assign tmp_tmp_traptype = 8'h00; assign \tmp_tmp_exc_$signal = 1'h0; assign \tmp_tmp_exc_$signal$21 = 1'h0; @@ -78930,10 +86324,12 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r assign \tmp_tmp_exc_$signal$25 = 1'h0; assign \tmp_tmp_exc_$signal$26 = 1'h0; assign \tmp_tmp_exc_$signal$27 = 1'h0; + assign sv_a_nz = 1'h0; assign illeg_ok = \$120 ; assign priv_ok = \$118 ; assign dec_irq_ok = \$116 ; assign ext_irq_ok = \$114 ; + assign { tmp_fasto3_ok, tmp_fasto3 } = { dec_o2_fast_o3_ok, dec_o2_fast_o3 }; assign { tmp_fasto2_ok, tmp_fasto2 } = { dec_o2_fast_o2_ok, dec_o2_fast_o2 }; assign { tmp_fasto1_ok, tmp_fasto1 } = { dec_o_fast_o_ok, dec_o_fast_o }; assign { tmp_fast2_ok, tmp_fast2 } = { dec_b_fast_b_ok, dec_b_fast_b }; @@ -78977,7 +86373,7 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r assign \insn_in$86 = dec_opcode_in; assign \insn_in$85 = dec_opcode_in; assign tmp_tmp_insn = dec_opcode_in; - assign dec_a_sv_nz = sv_a_nz; + assign dec_a_sv_nz = 1'h0; assign tmp_tmp_is_32bit = dec_is_32b; assign tmp_tmp_input_carry = dec_cry_in; assign { tmp_tmp_oe_ok, tmp_tmp_oe } = { dec_oe_oe_ok, dec_oe_oe }; @@ -78985,6 +86381,7 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r assign is_mmu_spr = \$69 ; assign is_spr_mv = \$55 ; assign spr = { dec_SPR[4:0], dec_SPR[9:5] }; + assign tmp_tmp_svstate = { cur_cur_maxvl, cur_cur_vl, cur_cur_srcstep, cur_cur_dststep, cur_cur_subvl, cur_cur_svstep }; assign tmp_tmp_cia = cur_pc; assign tmp_tmp_msr = cur_msr; assign dec_oe_sel_in = dec_rc_sel; @@ -79001,20 +86398,20 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec22_SV_Etype; reg [1:0] dec22_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec22_SV_Ptype; reg [1:0] dec22_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec22_asmcode; reg [7:0] dec22_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec22_br; reg dec22_br; (* enum_base_type = "CRInSel" *) @@ -79026,7 +86423,7 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec22_cr_in; reg [2:0] dec22_cr_in; (* enum_base_type = "CROutSel" *) @@ -79036,17 +86433,17 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec22_cr_out; reg [2:0] dec22_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec22_cry_in; reg [1:0] dec22_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec22_cry_out; reg dec22_cry_out; (* enum_base_type = "Form" *) @@ -79080,34 +86477,37 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec22_form; reg [4:0] dec22_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] dec22_function_unit; - reg [13:0] dec22_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] dec22_function_unit; + reg [14:0] dec22_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec22_in1_sel; reg [2:0] dec22_in1_sel; (* enum_base_type = "In2Sel" *) @@ -79125,16 +86525,19 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec22_in2_sel; reg [3:0] dec22_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [1:0] dec22_in3_sel; - reg [1:0] dec22_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [2:0] dec22_in3_sel; + reg [2:0] dec22_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -79210,16 +86613,18 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec22_internal_op; reg [6:0] dec22_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec22_inv_a; reg dec22_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec22_inv_out; reg dec22_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec22_is_32b; reg dec22_is_32b; (* enum_base_type = "LdstLen" *) @@ -79228,10 +86633,10 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec22_ldst_len; reg [3:0] dec22_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec22_lk; reg dec22_lk; (* enum_base_type = "OutSel" *) @@ -79240,26 +86645,27 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec22_out_sel; reg [2:0] dec22_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec22_rc_sel; reg [1:0] dec22_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec22_rsrv; reg dec22_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec22_sgl_pipe; reg dec22_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec22_sgn; reg dec22_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec22_sgn_ext; reg dec22_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -79269,7 +86675,7 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec22_sv_cr_in; reg [2:0] dec22_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -79279,7 +86685,7 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec22_sv_cr_out; reg [2:0] dec22_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -79289,7 +86695,7 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec22_sv_in1; reg [2:0] dec22_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -79299,7 +86705,7 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec22_sv_in2; reg [2:0] dec22_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -79309,7 +86715,7 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec22_sv_in3; reg [2:0] dec22_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -79319,7 +86725,7 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec22_sv_out; reg [2:0] dec22_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -79329,7 +86735,7 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec22_sv_out2; reg [2:0] dec22_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -79337,29 +86743,29 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec22_upd; reg [1:0] dec22_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [3:0] opcode_switch; always @* begin if (\initial ) begin end - dec22_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec22_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: - dec22_function_unit = 14'h2000; + dec22_function_unit = 15'h2000; endcase end always @* begin if (\initial ) begin end dec22_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec22_cr_in = 3'h0; endcase @@ -79367,9 +86773,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec22_cr_out = 3'h1; endcase @@ -79377,9 +86783,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec22_sv_in1 = 3'h0; endcase @@ -79387,9 +86793,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec22_sv_in2 = 3'h0; endcase @@ -79397,9 +86803,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec22_sv_in3 = 3'h0; endcase @@ -79407,9 +86813,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec22_sv_out = 3'h0; endcase @@ -79417,9 +86823,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec22_sv_out2 = 3'h0; endcase @@ -79427,9 +86833,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec22_sv_cr_in = 3'h0; endcase @@ -79437,9 +86843,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec22_sv_cr_out = 3'h0; endcase @@ -79447,9 +86853,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec22_ldst_len = 4'h0; endcase @@ -79457,9 +86863,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec22_internal_op = 7'h4c; endcase @@ -79467,9 +86873,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec22_upd = 2'h0; endcase @@ -79477,9 +86883,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec22_rc_sel = 2'h2; endcase @@ -79487,9 +86893,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec22_cry_in = 2'h0; endcase @@ -79497,19 +86903,19 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: - dec22_asmcode = 8'h9c; + dec22_asmcode = 8'hbc; endcase end always @* begin if (\initial ) begin end dec22_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec22_inv_a = 1'h0; endcase @@ -79517,9 +86923,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec22_inv_out = 1'h0; endcase @@ -79527,9 +86933,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec22_cry_out = 1'h0; endcase @@ -79537,9 +86943,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec22_br = 1'h0; endcase @@ -79547,9 +86953,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec22_sgn_ext = 1'h0; endcase @@ -79557,9 +86963,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec22_rsrv = 1'h0; endcase @@ -79567,9 +86973,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec22_form = 5'h1d; endcase @@ -79577,9 +86983,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec22_is_32b = 1'h0; endcase @@ -79587,9 +86993,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec22_sgn = 1'h0; endcase @@ -79597,9 +87003,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec22_lk = 1'h0; endcase @@ -79607,9 +87013,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec22_sgl_pipe = 1'h0; endcase @@ -79617,9 +87023,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec22_SV_Etype = 2'h0; endcase @@ -79627,9 +87033,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec22_SV_Ptype = 2'h0; endcase @@ -79637,9 +87043,9 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec22_in1_sel = 3'h2; endcase @@ -79647,29 +87053,29 @@ module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, always @* begin if (\initial ) begin end dec22_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec22_in2_sel = 4'h0; endcase end always @* begin if (\initial ) begin end - dec22_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec22_in3_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: - dec22_in3_sel = 2'h0; + dec22_in3_sel = 3'h0; endcase end always @* begin if (\initial ) begin end dec22_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec22_out_sel = 3'h4; endcase @@ -79685,20 +87091,20 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec30_SV_Etype; reg [1:0] dec30_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec30_SV_Ptype; reg [1:0] dec30_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec30_asmcode; reg [7:0] dec30_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec30_br; reg dec30_br; (* enum_base_type = "CRInSel" *) @@ -79710,7 +87116,7 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec30_cr_in; reg [2:0] dec30_cr_in; (* enum_base_type = "CROutSel" *) @@ -79720,17 +87126,17 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec30_cr_out; reg [2:0] dec30_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec30_cry_in; reg [1:0] dec30_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec30_cry_out; reg dec30_cry_out; (* enum_base_type = "Form" *) @@ -79764,34 +87170,37 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec30_form; reg [4:0] dec30_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] dec30_function_unit; - reg [13:0] dec30_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] dec30_function_unit; + reg [14:0] dec30_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec30_in1_sel; reg [2:0] dec30_in1_sel; (* enum_base_type = "In2Sel" *) @@ -79809,16 +87218,19 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec30_in2_sel; reg [3:0] dec30_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [1:0] dec30_in3_sel; - reg [1:0] dec30_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [2:0] dec30_in3_sel; + reg [2:0] dec30_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -79894,16 +87306,18 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec30_internal_op; reg [6:0] dec30_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec30_inv_a; reg dec30_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec30_inv_out; reg dec30_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec30_is_32b; reg dec30_is_32b; (* enum_base_type = "LdstLen" *) @@ -79912,10 +87326,10 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec30_ldst_len; reg [3:0] dec30_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec30_lk; reg dec30_lk; (* enum_base_type = "OutSel" *) @@ -79924,26 +87338,27 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec30_out_sel; reg [2:0] dec30_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec30_rc_sel; reg [1:0] dec30_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec30_rsrv; reg dec30_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec30_sgl_pipe; reg dec30_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec30_sgn; reg dec30_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec30_sgn_ext; reg dec30_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -79953,7 +87368,7 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec30_sv_cr_in; reg [2:0] dec30_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -79963,7 +87378,7 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec30_sv_cr_out; reg [2:0] dec30_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -79973,7 +87388,7 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec30_sv_in1; reg [2:0] dec30_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -79983,7 +87398,7 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec30_sv_in2; reg [2:0] dec30_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -79993,7 +87408,7 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec30_sv_in3; reg [2:0] dec30_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -80003,7 +87418,7 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec30_sv_out; reg [2:0] dec30_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -80013,7 +87428,7 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec30_sv_out2; reg [2:0] dec30_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -80021,83 +87436,83 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec30_upd; reg [1:0] dec30_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [3:0] opcode_switch; always @* begin if (\initial ) begin end - dec30_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec30_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: - dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec30_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: - dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec30_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: - dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec30_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: - dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec30_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: - dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec30_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: - dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec30_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: - dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec30_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: - dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec30_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: - dec30_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec30_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: - dec30_function_unit = 14'h0008; + dec30_function_unit = 15'h0008; endcase end always @* begin if (\initial ) begin end dec30_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: dec30_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: dec30_cr_in = 3'h0; endcase @@ -80105,36 +87520,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: dec30_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: dec30_cr_out = 3'h1; endcase @@ -80142,36 +87557,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: dec30_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: dec30_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec30_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: dec30_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: dec30_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: dec30_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: dec30_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: dec30_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: dec30_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: dec30_sv_in1 = 3'h0; endcase @@ -80179,36 +87594,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: dec30_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: dec30_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec30_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: dec30_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: dec30_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: dec30_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: dec30_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: dec30_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: dec30_sv_in2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: dec30_sv_in2 = 3'h2; endcase @@ -80216,36 +87631,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: dec30_sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: dec30_sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec30_sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: dec30_sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: dec30_sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: dec30_sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: dec30_sv_in3 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: dec30_sv_in3 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: dec30_sv_in3 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: dec30_sv_in3 = 3'h3; endcase @@ -80253,36 +87668,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: dec30_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: dec30_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec30_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: dec30_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: dec30_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: dec30_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: dec30_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: dec30_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: dec30_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: dec30_sv_out = 3'h1; endcase @@ -80290,36 +87705,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: dec30_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: dec30_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec30_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: dec30_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: dec30_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: dec30_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: dec30_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: dec30_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: dec30_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: dec30_sv_out2 = 3'h0; endcase @@ -80327,36 +87742,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: dec30_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: dec30_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec30_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: dec30_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: dec30_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: dec30_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: dec30_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: dec30_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: dec30_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: dec30_sv_cr_in = 3'h0; endcase @@ -80364,36 +87779,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: dec30_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: dec30_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec30_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: dec30_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: dec30_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: dec30_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: dec30_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: dec30_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: dec30_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: dec30_sv_cr_out = 3'h1; endcase @@ -80401,36 +87816,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: dec30_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: dec30_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec30_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: dec30_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: dec30_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: dec30_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: dec30_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: dec30_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: dec30_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: dec30_ldst_len = 4'h0; endcase @@ -80438,36 +87853,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: dec30_internal_op = 7'h38; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: dec30_internal_op = 7'h38; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec30_internal_op = 7'h39; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: dec30_internal_op = 7'h39; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: dec30_internal_op = 7'h3a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: dec30_internal_op = 7'h3a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: dec30_internal_op = 7'h38; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: dec30_internal_op = 7'h38; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: dec30_internal_op = 7'h39; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: dec30_internal_op = 7'h3a; endcase @@ -80475,36 +87890,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: dec30_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: dec30_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec30_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: dec30_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: dec30_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: dec30_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: dec30_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: dec30_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: dec30_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: dec30_upd = 2'h0; endcase @@ -80512,36 +87927,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: dec30_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: dec30_rc_sel = 2'h2; endcase @@ -80549,36 +87964,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: dec30_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: dec30_cry_in = 2'h0; endcase @@ -80586,73 +88001,73 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: - dec30_asmcode = 8'h94; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec30_asmcode = 8'hb4; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: - dec30_asmcode = 8'h94; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec30_asmcode = 8'hb4; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: - dec30_asmcode = 8'h95; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec30_asmcode = 8'hb5; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: - dec30_asmcode = 8'h95; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec30_asmcode = 8'hb5; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: - dec30_asmcode = 8'h96; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec30_asmcode = 8'hb6; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: - dec30_asmcode = 8'h96; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec30_asmcode = 8'hb6; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: - dec30_asmcode = 8'h97; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec30_asmcode = 8'hb7; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: - dec30_asmcode = 8'h97; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec30_asmcode = 8'hb7; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: - dec30_asmcode = 8'h92; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec30_asmcode = 8'hb2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: - dec30_asmcode = 8'h93; + dec30_asmcode = 8'hb3; endcase end always @* begin if (\initial ) begin end dec30_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: dec30_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: dec30_inv_a = 1'h0; endcase @@ -80660,36 +88075,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: dec30_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: dec30_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec30_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: dec30_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: dec30_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: dec30_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: dec30_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: dec30_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: dec30_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: dec30_inv_out = 1'h0; endcase @@ -80697,36 +88112,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: dec30_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: dec30_cry_out = 1'h0; endcase @@ -80734,36 +88149,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: dec30_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: dec30_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec30_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: dec30_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: dec30_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: dec30_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: dec30_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: dec30_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: dec30_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: dec30_br = 1'h0; endcase @@ -80771,36 +88186,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: dec30_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: dec30_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec30_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: dec30_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: dec30_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: dec30_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: dec30_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: dec30_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: dec30_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: dec30_sgn_ext = 1'h0; endcase @@ -80808,36 +88223,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: dec30_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: dec30_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec30_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: dec30_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: dec30_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: dec30_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: dec30_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: dec30_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: dec30_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: dec30_rsrv = 1'h0; endcase @@ -80845,36 +88260,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: dec30_form = 5'h14; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: dec30_form = 5'h14; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec30_form = 5'h15; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: dec30_form = 5'h15; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: dec30_form = 5'h14; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: dec30_form = 5'h14; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: dec30_form = 5'h14; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: dec30_form = 5'h14; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: dec30_form = 5'h14; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: dec30_form = 5'h14; endcase @@ -80882,36 +88297,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: dec30_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: dec30_is_32b = 1'h0; endcase @@ -80919,36 +88334,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: dec30_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: dec30_sgn = 1'h0; endcase @@ -80956,36 +88371,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: dec30_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: dec30_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec30_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: dec30_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: dec30_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: dec30_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: dec30_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: dec30_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: dec30_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: dec30_lk = 1'h0; endcase @@ -80993,36 +88408,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: dec30_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: dec30_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec30_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: dec30_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: dec30_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: dec30_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: dec30_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: dec30_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: dec30_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: dec30_sgl_pipe = 1'h0; endcase @@ -81030,36 +88445,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: dec30_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: dec30_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec30_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: dec30_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: dec30_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: dec30_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: dec30_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: dec30_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: dec30_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: dec30_SV_Etype = 2'h2; endcase @@ -81067,36 +88482,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: dec30_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: dec30_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec30_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: dec30_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: dec30_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: dec30_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: dec30_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: dec30_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: dec30_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: dec30_SV_Ptype = 2'h1; endcase @@ -81104,36 +88519,36 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: dec30_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: dec30_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec30_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: dec30_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: dec30_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: dec30_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: dec30_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: dec30_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: dec30_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: dec30_in1_sel = 3'h0; endcase @@ -81141,110 +88556,110 @@ module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, always @* begin if (\initial ) begin end dec30_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: dec30_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: dec30_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec30_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: dec30_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: dec30_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: dec30_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: dec30_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: dec30_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: dec30_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: dec30_in2_sel = 4'h1; endcase end always @* begin if (\initial ) begin end - dec30_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec30_in3_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: - dec30_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec30_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: - dec30_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec30_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: - dec30_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec30_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: - dec30_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec30_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: - dec30_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec30_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: - dec30_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec30_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: - dec30_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec30_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: - dec30_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec30_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: - dec30_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec30_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: - dec30_in3_sel = 2'h1; + dec30_in3_sel = 3'h1; endcase end always @* begin if (\initial ) begin end dec30_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h4: dec30_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h5: dec30_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h0: dec30_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h1: dec30_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h2: dec30_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h3: dec30_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h6: dec30_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h7: dec30_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h8: dec30_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 4'h9: dec30_out_sel = 3'h2; endcase @@ -81260,20 +88675,20 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_SV_Etype; reg [1:0] dec31_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_SV_Ptype; reg [1:0] dec31_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_asmcode; reg [7:0] dec31_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_br; reg dec31_br; (* enum_base_type = "CRInSel" *) @@ -81285,7 +88700,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_cr_in; reg [2:0] dec31_cr_in; (* enum_base_type = "CROutSel" *) @@ -81295,34 +88710,34 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_cr_out; reg [2:0] dec31_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_cry_in; reg [1:0] dec31_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_cry_out; reg dec31_cry_out; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub0_dec31_dec_sub0_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub0_dec31_dec_sub0_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [7:0] dec31_dec_sub0_dec31_dec_sub0_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub0_dec31_dec_sub0_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -81333,7 +88748,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub0_dec31_dec_sub0_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -81342,15 +88757,15 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub0_dec31_dec_sub0_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub0_dec31_dec_sub0_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub0_dec31_dec_sub0_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -81383,32 +88798,35 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [4:0] dec31_dec_sub0_dec31_dec_sub0_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec31_dec_sub0_dec31_dec_sub0_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec31_dec_sub0_dec31_dec_sub0_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub0_dec31_dec_sub0_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -81425,326 +88843,17 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub0_dec31_dec_sub0_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub0_dec31_dec_sub0_in3_sel; - (* enum_base_type = "MicrOp" *) - (* enum_value_0000000 = "OP_ILLEGAL" *) - (* enum_value_0000001 = "OP_NOP" *) - (* enum_value_0000010 = "OP_ADD" *) - (* enum_value_0000011 = "OP_ADDPCIS" *) - (* enum_value_0000100 = "OP_AND" *) - (* enum_value_0000101 = "OP_ATTN" *) - (* enum_value_0000110 = "OP_B" *) - (* enum_value_0000111 = "OP_BC" *) - (* enum_value_0001000 = "OP_BCREG" *) - (* enum_value_0001001 = "OP_BPERM" *) - (* enum_value_0001010 = "OP_CMP" *) - (* enum_value_0001011 = "OP_CMPB" *) - (* enum_value_0001100 = "OP_CMPEQB" *) - (* enum_value_0001101 = "OP_CMPRB" *) - (* enum_value_0001110 = "OP_CNTZ" *) - (* enum_value_0001111 = "OP_CRAND" *) - (* enum_value_0010000 = "OP_CRANDC" *) - (* enum_value_0010001 = "OP_CREQV" *) - (* enum_value_0010010 = "OP_CRNAND" *) - (* enum_value_0010011 = "OP_CRNOR" *) - (* enum_value_0010100 = "OP_CROR" *) - (* enum_value_0010101 = "OP_CRORC" *) - (* enum_value_0010110 = "OP_CRXOR" *) - (* enum_value_0010111 = "OP_DARN" *) - (* enum_value_0011000 = "OP_DCBF" *) - (* enum_value_0011001 = "OP_DCBST" *) - (* enum_value_0011010 = "OP_DCBT" *) - (* enum_value_0011011 = "OP_DCBTST" *) - (* enum_value_0011100 = "OP_DCBZ" *) - (* enum_value_0011101 = "OP_DIV" *) - (* enum_value_0011110 = "OP_DIVE" *) - (* enum_value_0011111 = "OP_EXTS" *) - (* enum_value_0100000 = "OP_EXTSWSLI" *) - (* enum_value_0100001 = "OP_ICBI" *) - (* enum_value_0100010 = "OP_ICBT" *) - (* enum_value_0100011 = "OP_ISEL" *) - (* enum_value_0100100 = "OP_ISYNC" *) - (* enum_value_0100101 = "OP_LOAD" *) - (* enum_value_0100110 = "OP_STORE" *) - (* enum_value_0100111 = "OP_MADDHD" *) - (* enum_value_0101000 = "OP_MADDHDU" *) - (* enum_value_0101001 = "OP_MADDLD" *) - (* enum_value_0101010 = "OP_MCRF" *) - (* enum_value_0101011 = "OP_MCRXR" *) - (* enum_value_0101100 = "OP_MCRXRX" *) - (* enum_value_0101101 = "OP_MFCR" *) - (* enum_value_0101110 = "OP_MFSPR" *) - (* enum_value_0101111 = "OP_MOD" *) - (* enum_value_0110000 = "OP_MTCRF" *) - (* enum_value_0110001 = "OP_MTSPR" *) - (* enum_value_0110010 = "OP_MUL_L64" *) - (* enum_value_0110011 = "OP_MUL_H64" *) - (* enum_value_0110100 = "OP_MUL_H32" *) - (* enum_value_0110101 = "OP_OR" *) - (* enum_value_0110110 = "OP_POPCNT" *) - (* enum_value_0110111 = "OP_PRTY" *) - (* enum_value_0111000 = "OP_RLC" *) - (* enum_value_0111001 = "OP_RLCL" *) - (* enum_value_0111010 = "OP_RLCR" *) - (* enum_value_0111011 = "OP_SETB" *) - (* enum_value_0111100 = "OP_SHL" *) - (* enum_value_0111101 = "OP_SHR" *) - (* enum_value_0111110 = "OP_SYNC" *) - (* enum_value_0111111 = "OP_TRAP" *) - (* enum_value_1000011 = "OP_XOR" *) - (* enum_value_1000100 = "OP_SIM_CONFIG" *) - (* enum_value_1000101 = "OP_CROP" *) - (* enum_value_1000110 = "OP_RFID" *) - (* enum_value_1000111 = "OP_MFMSR" *) - (* enum_value_1001000 = "OP_MTMSRD" *) - (* enum_value_1001001 = "OP_SC" *) - (* enum_value_1001010 = "OP_MTMSR" *) - (* enum_value_1001011 = "OP_TLBIE" *) - (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [6:0] dec31_dec_sub0_dec31_dec_sub0_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub0_dec31_dec_sub0_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub0_dec31_dec_sub0_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub0_dec31_dec_sub0_is_32b; - (* enum_base_type = "LdstLen" *) - (* enum_value_0000 = "NONE" *) - (* enum_value_0001 = "is1B" *) - (* enum_value_0010 = "is2B" *) - (* enum_value_0100 = "is4B" *) - (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub0_dec31_dec_sub0_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub0_dec31_dec_sub0_lk; - (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) - (* enum_value_001 = "RT" *) - (* enum_value_010 = "RA" *) - (* enum_value_011 = "SPR" *) - (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub0_dec31_dec_sub0_out_sel; - (* enum_base_type = "RC" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "ONE" *) - (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub0_dec31_dec_sub0_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub0_dec31_dec_sub0_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub0_dec31_dec_sub0_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub0_dec31_dec_sub0_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub0_dec31_dec_sub0_sgn_ext; - (* enum_base_type = "SVEXTRA" *) - (* enum_value_000 = "NONE" *) - (* enum_value_001 = "Idx0" *) - (* enum_value_010 = "Idx1" *) - (* enum_value_011 = "Idx2" *) - (* enum_value_100 = "Idx3" *) - (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_cr_in; - (* enum_base_type = "SVEXTRA" *) - (* enum_value_000 = "NONE" *) - (* enum_value_001 = "Idx0" *) - (* enum_value_010 = "Idx1" *) - (* enum_value_011 = "Idx2" *) - (* enum_value_100 = "Idx3" *) - (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_cr_out; - (* enum_base_type = "SVEXTRA" *) - (* enum_value_000 = "NONE" *) - (* enum_value_001 = "Idx0" *) - (* enum_value_010 = "Idx1" *) - (* enum_value_011 = "Idx2" *) - (* enum_value_100 = "Idx3" *) - (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_in1; - (* enum_base_type = "SVEXTRA" *) - (* enum_value_000 = "NONE" *) - (* enum_value_001 = "Idx0" *) - (* enum_value_010 = "Idx1" *) - (* enum_value_011 = "Idx2" *) - (* enum_value_100 = "Idx3" *) - (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_in2; - (* enum_base_type = "SVEXTRA" *) - (* enum_value_000 = "NONE" *) - (* enum_value_001 = "Idx0" *) - (* enum_value_010 = "Idx1" *) - (* enum_value_011 = "Idx2" *) - (* enum_value_100 = "Idx3" *) - (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_in3; - (* enum_base_type = "SVEXTRA" *) - (* enum_value_000 = "NONE" *) - (* enum_value_001 = "Idx0" *) - (* enum_value_010 = "Idx1" *) - (* enum_value_011 = "Idx2" *) - (* enum_value_100 = "Idx3" *) - (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_out; - (* enum_base_type = "SVEXTRA" *) - (* enum_value_000 = "NONE" *) - (* enum_value_001 = "Idx0" *) - (* enum_value_010 = "Idx1" *) - (* enum_value_011 = "Idx2" *) - (* enum_value_100 = "Idx3" *) - (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_out2; - (* enum_base_type = "LDSTMode" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "update" *) - (* enum_value_10 = "cix" *) - (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub0_dec31_dec_sub0_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) - wire [31:0] dec31_dec_sub0_opcode_in; - (* enum_base_type = "SVEtype" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "EXTRA2" *) - (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub10_dec31_dec_sub10_SV_Etype; - (* enum_base_type = "SVPtype" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "P1" *) - (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub10_dec31_dec_sub10_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [7:0] dec31_dec_sub10_dec31_dec_sub10_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub10_dec31_dec_sub10_br; - (* enum_base_type = "CRInSel" *) - (* enum_value_000 = "NONE" *) - (* enum_value_001 = "CR0" *) - (* enum_value_010 = "BI" *) - (* enum_value_011 = "BFA" *) - (* enum_value_100 = "BA_BB" *) - (* enum_value_101 = "BC" *) - (* enum_value_110 = "WHOLE_REG" *) - (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub10_dec31_dec_sub10_cr_in; - (* enum_base_type = "CROutSel" *) - (* enum_value_000 = "NONE" *) - (* enum_value_001 = "CR0" *) - (* enum_value_010 = "BF" *) - (* enum_value_011 = "BT" *) - (* enum_value_100 = "WHOLE_REG" *) - (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub10_dec31_dec_sub10_cr_out; - (* enum_base_type = "CryIn" *) - (* enum_value_00 = "ZERO" *) - (* enum_value_01 = "ONE" *) - (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub10_dec31_dec_sub10_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub10_dec31_dec_sub10_cry_out; - (* enum_base_type = "Form" *) - (* enum_value_00000 = "NONE" *) - (* enum_value_00001 = "I" *) - (* enum_value_00010 = "B" *) - (* enum_value_00011 = "SC" *) - (* enum_value_00100 = "D" *) - (* enum_value_00101 = "DS" *) - (* enum_value_00110 = "DQ" *) - (* enum_value_00111 = "DX" *) - (* enum_value_01000 = "X" *) - (* enum_value_01001 = "XL" *) - (* enum_value_01010 = "XFX" *) - (* enum_value_01011 = "XFL" *) - (* enum_value_01100 = "XX1" *) - (* enum_value_01101 = "XX2" *) - (* enum_value_01110 = "XX3" *) - (* enum_value_01111 = "XX4" *) - (* enum_value_10000 = "XS" *) - (* enum_value_10001 = "XO" *) - (* enum_value_10010 = "A" *) - (* enum_value_10011 = "M" *) - (* enum_value_10100 = "MD" *) - (* enum_value_10101 = "MDS" *) - (* enum_value_10110 = "VA" *) - (* enum_value_10111 = "VC" *) - (* enum_value_11000 = "VX" *) - (* enum_value_11001 = "EVX" *) - (* enum_value_11010 = "EVS" *) - (* enum_value_11011 = "Z22" *) - (* enum_value_11100 = "Z23" *) - (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [4:0] dec31_dec_sub10_dec31_dec_sub10_form; - (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec31_dec_sub10_dec31_dec_sub10_function_unit; - (* enum_base_type = "In1Sel" *) - (* enum_value_000 = "NONE" *) - (* enum_value_001 = "RA" *) - (* enum_value_010 = "RA_OR_ZERO" *) - (* enum_value_011 = "SPR" *) - (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub10_dec31_dec_sub10_in1_sel; - (* enum_base_type = "In2Sel" *) - (* enum_value_0000 = "NONE" *) - (* enum_value_0001 = "RB" *) - (* enum_value_0010 = "CONST_UI" *) - (* enum_value_0011 = "CONST_SI" *) - (* enum_value_0100 = "CONST_UI_HI" *) - (* enum_value_0101 = "CONST_SI_HI" *) - (* enum_value_0110 = "CONST_LI" *) - (* enum_value_0111 = "CONST_BD" *) - (* enum_value_1000 = "CONST_DS" *) - (* enum_value_1001 = "CONST_M1" *) - (* enum_value_1010 = "CONST_SH" *) - (* enum_value_1011 = "CONST_SH32" *) - (* enum_value_1100 = "SPR" *) - (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub10_dec31_dec_sub10_in2_sel; - (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub10_dec31_dec_sub10_in3_sel; + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub0_dec31_dec_sub0_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -81820,46 +88929,49 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [6:0] dec31_dec_sub10_dec31_dec_sub10_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub10_dec31_dec_sub10_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub10_dec31_dec_sub10_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub10_dec31_dec_sub10_is_32b; + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub0_dec31_dec_sub0_internal_op; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub0_dec31_dec_sub0_inv_a; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub0_dec31_dec_sub0_inv_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub0_dec31_dec_sub0_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "is1B" *) (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub10_dec31_dec_sub10_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub10_dec31_dec_sub10_lk; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub0_dec31_dec_sub0_ldst_len; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub0_dec31_dec_sub0_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RT" *) (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub10_dec31_dec_sub10_out_sel; + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub0_dec31_dec_sub0_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub10_dec31_dec_sub10_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub10_dec31_dec_sub10_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub10_dec31_dec_sub10_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub10_dec31_dec_sub10_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub10_dec31_dec_sub10_sgn_ext; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub0_dec31_dec_sub0_rc_sel; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub0_dec31_dec_sub0_rsrv; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub0_dec31_dec_sub0_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub0_dec31_dec_sub0_sgn; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub0_dec31_dec_sub0_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -81867,8 +88979,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_cr_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -81876,8 +88988,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_cr_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -81885,8 +88997,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_in1; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -81894,8 +89006,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_in2; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -81903,8 +89015,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_in3; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -81912,8 +89024,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -81921,33 +89033,33 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_out2; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub10_dec31_dec_sub10_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) - wire [31:0] dec31_dec_sub10_opcode_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub0_dec31_dec_sub0_upd; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) + wire [31:0] dec31_dec_sub0_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub11_dec31_dec_sub11_SV_Etype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub10_dec31_dec_sub10_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub11_dec31_dec_sub11_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [7:0] dec31_dec_sub11_dec31_dec_sub11_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub11_dec31_dec_sub11_br; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub10_dec31_dec_sub10_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub10_dec31_dec_sub10_asmcode; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub10_dec31_dec_sub10_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -81957,8 +89069,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub11_dec31_dec_sub11_cr_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub10_dec31_dec_sub10_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -81966,16 +89078,16 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub11_dec31_dec_sub11_cr_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub10_dec31_dec_sub10_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub11_dec31_dec_sub11_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub11_dec31_dec_sub11_cry_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub10_dec31_dec_sub10_cry_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub10_dec31_dec_sub10_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) (* enum_value_00001 = "I" *) @@ -82007,33 +89119,36 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [4:0] dec31_dec_sub11_dec31_dec_sub11_form; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub10_dec31_dec_sub10_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec31_dec_sub11_dec31_dec_sub11_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec31_dec_sub10_dec31_dec_sub10_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub11_dec31_dec_sub11_in1_sel; + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub10_dec31_dec_sub10_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -82049,14 +89164,17 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub11_dec31_dec_sub11_in2_sel; + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub10_dec31_dec_sub10_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub11_dec31_dec_sub11_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub10_dec31_dec_sub10_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -82132,46 +89250,49 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [6:0] dec31_dec_sub11_dec31_dec_sub11_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub11_dec31_dec_sub11_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub11_dec31_dec_sub11_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub11_dec31_dec_sub11_is_32b; + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub10_dec31_dec_sub10_internal_op; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub10_dec31_dec_sub10_inv_a; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub10_dec31_dec_sub10_inv_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub10_dec31_dec_sub10_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "is1B" *) (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub11_dec31_dec_sub11_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub11_dec31_dec_sub11_lk; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub10_dec31_dec_sub10_ldst_len; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub10_dec31_dec_sub10_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RT" *) (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub11_dec31_dec_sub11_out_sel; + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub10_dec31_dec_sub10_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub11_dec31_dec_sub11_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub11_dec31_dec_sub11_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub11_dec31_dec_sub11_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub11_dec31_dec_sub11_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub11_dec31_dec_sub11_sgn_ext; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub10_dec31_dec_sub10_rc_sel; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub10_dec31_dec_sub10_rsrv; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub10_dec31_dec_sub10_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub10_dec31_dec_sub10_sgn; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub10_dec31_dec_sub10_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -82179,8 +89300,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_cr_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -82188,8 +89309,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_cr_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -82197,8 +89318,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_in1; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -82206,8 +89327,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_in2; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -82215,8 +89336,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_in3; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -82224,8 +89345,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -82233,33 +89354,33 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_out2; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub11_dec31_dec_sub11_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) - wire [31:0] dec31_dec_sub11_opcode_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub10_dec31_dec_sub10_upd; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) + wire [31:0] dec31_dec_sub10_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub15_dec31_dec_sub15_SV_Etype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub11_dec31_dec_sub11_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub15_dec31_dec_sub15_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [7:0] dec31_dec_sub15_dec31_dec_sub15_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub15_dec31_dec_sub15_br; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub11_dec31_dec_sub11_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub11_dec31_dec_sub11_asmcode; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub11_dec31_dec_sub11_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -82269,8 +89390,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub15_dec31_dec_sub15_cr_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub11_dec31_dec_sub11_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -82278,16 +89399,16 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub15_dec31_dec_sub15_cr_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub11_dec31_dec_sub11_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub15_dec31_dec_sub15_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub15_dec31_dec_sub15_cry_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub11_dec31_dec_sub11_cry_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub11_dec31_dec_sub11_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) (* enum_value_00001 = "I" *) @@ -82319,33 +89440,36 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [4:0] dec31_dec_sub15_dec31_dec_sub15_form; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub11_dec31_dec_sub11_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec31_dec_sub15_dec31_dec_sub15_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec31_dec_sub11_dec31_dec_sub11_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub15_dec31_dec_sub15_in1_sel; + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub11_dec31_dec_sub11_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -82361,14 +89485,17 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub15_dec31_dec_sub15_in2_sel; + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub11_dec31_dec_sub11_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub15_dec31_dec_sub15_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub11_dec31_dec_sub11_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -82444,46 +89571,49 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [6:0] dec31_dec_sub15_dec31_dec_sub15_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub15_dec31_dec_sub15_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub15_dec31_dec_sub15_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub15_dec31_dec_sub15_is_32b; + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub11_dec31_dec_sub11_internal_op; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub11_dec31_dec_sub11_inv_a; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub11_dec31_dec_sub11_inv_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub11_dec31_dec_sub11_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "is1B" *) (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub15_dec31_dec_sub15_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub15_dec31_dec_sub15_lk; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub11_dec31_dec_sub11_ldst_len; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub11_dec31_dec_sub11_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RT" *) (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub15_dec31_dec_sub15_out_sel; + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub11_dec31_dec_sub11_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub15_dec31_dec_sub15_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub15_dec31_dec_sub15_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub15_dec31_dec_sub15_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub15_dec31_dec_sub15_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub15_dec31_dec_sub15_sgn_ext; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub11_dec31_dec_sub11_rc_sel; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub11_dec31_dec_sub11_rsrv; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub11_dec31_dec_sub11_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub11_dec31_dec_sub11_sgn; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub11_dec31_dec_sub11_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -82491,8 +89621,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_cr_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -82500,8 +89630,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_cr_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -82509,8 +89639,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_in1; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -82518,8 +89648,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_in2; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -82527,8 +89657,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_in3; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -82536,8 +89666,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -82545,33 +89675,33 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_out2; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub15_dec31_dec_sub15_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) - wire [31:0] dec31_dec_sub15_opcode_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub11_dec31_dec_sub11_upd; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) + wire [31:0] dec31_dec_sub11_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub16_dec31_dec_sub16_SV_Etype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub15_dec31_dec_sub15_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub16_dec31_dec_sub16_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [7:0] dec31_dec_sub16_dec31_dec_sub16_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub16_dec31_dec_sub16_br; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub15_dec31_dec_sub15_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub15_dec31_dec_sub15_asmcode; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub15_dec31_dec_sub15_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -82581,8 +89711,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub16_dec31_dec_sub16_cr_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub15_dec31_dec_sub15_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -82590,16 +89720,16 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub16_dec31_dec_sub16_cr_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub15_dec31_dec_sub15_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub16_dec31_dec_sub16_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub16_dec31_dec_sub16_cry_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub15_dec31_dec_sub15_cry_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub15_dec31_dec_sub15_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) (* enum_value_00001 = "I" *) @@ -82631,33 +89761,36 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [4:0] dec31_dec_sub16_dec31_dec_sub16_form; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub15_dec31_dec_sub15_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec31_dec_sub16_dec31_dec_sub16_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec31_dec_sub15_dec31_dec_sub15_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub16_dec31_dec_sub16_in1_sel; + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub15_dec31_dec_sub15_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -82673,14 +89806,17 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub16_dec31_dec_sub16_in2_sel; + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub15_dec31_dec_sub15_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub16_dec31_dec_sub16_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub15_dec31_dec_sub15_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -82756,46 +89892,49 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [6:0] dec31_dec_sub16_dec31_dec_sub16_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub16_dec31_dec_sub16_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub16_dec31_dec_sub16_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub16_dec31_dec_sub16_is_32b; + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub15_dec31_dec_sub15_internal_op; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub15_dec31_dec_sub15_inv_a; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub15_dec31_dec_sub15_inv_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub15_dec31_dec_sub15_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "is1B" *) (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub16_dec31_dec_sub16_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub16_dec31_dec_sub16_lk; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub15_dec31_dec_sub15_ldst_len; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub15_dec31_dec_sub15_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RT" *) (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub16_dec31_dec_sub16_out_sel; + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub15_dec31_dec_sub15_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub16_dec31_dec_sub16_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub16_dec31_dec_sub16_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub16_dec31_dec_sub16_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub16_dec31_dec_sub16_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub16_dec31_dec_sub16_sgn_ext; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub15_dec31_dec_sub15_rc_sel; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub15_dec31_dec_sub15_rsrv; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub15_dec31_dec_sub15_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub15_dec31_dec_sub15_sgn; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub15_dec31_dec_sub15_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -82803,8 +89942,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_cr_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -82812,8 +89951,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_cr_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -82821,8 +89960,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_in1; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -82830,8 +89969,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_in2; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -82839,8 +89978,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_in3; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -82848,8 +89987,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -82857,33 +89996,33 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_out2; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub16_dec31_dec_sub16_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) - wire [31:0] dec31_dec_sub16_opcode_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub15_dec31_dec_sub15_upd; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) + wire [31:0] dec31_dec_sub15_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub18_dec31_dec_sub18_SV_Etype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub16_dec31_dec_sub16_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub18_dec31_dec_sub18_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [7:0] dec31_dec_sub18_dec31_dec_sub18_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub18_dec31_dec_sub18_br; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub16_dec31_dec_sub16_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub16_dec31_dec_sub16_asmcode; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub16_dec31_dec_sub16_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -82893,8 +90032,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub18_dec31_dec_sub18_cr_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub16_dec31_dec_sub16_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -82902,16 +90041,16 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub18_dec31_dec_sub18_cr_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub16_dec31_dec_sub16_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub18_dec31_dec_sub18_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub18_dec31_dec_sub18_cry_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub16_dec31_dec_sub16_cry_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub16_dec31_dec_sub16_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) (* enum_value_00001 = "I" *) @@ -82943,33 +90082,36 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [4:0] dec31_dec_sub18_dec31_dec_sub18_form; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub16_dec31_dec_sub16_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec31_dec_sub18_dec31_dec_sub18_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec31_dec_sub16_dec31_dec_sub16_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub18_dec31_dec_sub18_in1_sel; + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub16_dec31_dec_sub16_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -82985,14 +90127,17 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub18_dec31_dec_sub18_in2_sel; + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub16_dec31_dec_sub16_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub18_dec31_dec_sub18_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub16_dec31_dec_sub16_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -83068,46 +90213,49 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [6:0] dec31_dec_sub18_dec31_dec_sub18_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub18_dec31_dec_sub18_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub18_dec31_dec_sub18_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub18_dec31_dec_sub18_is_32b; + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub16_dec31_dec_sub16_internal_op; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub16_dec31_dec_sub16_inv_a; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub16_dec31_dec_sub16_inv_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub16_dec31_dec_sub16_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "is1B" *) (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub18_dec31_dec_sub18_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub18_dec31_dec_sub18_lk; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub16_dec31_dec_sub16_ldst_len; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub16_dec31_dec_sub16_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RT" *) (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub18_dec31_dec_sub18_out_sel; + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub16_dec31_dec_sub16_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub18_dec31_dec_sub18_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub18_dec31_dec_sub18_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub18_dec31_dec_sub18_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub18_dec31_dec_sub18_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub18_dec31_dec_sub18_sgn_ext; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub16_dec31_dec_sub16_rc_sel; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub16_dec31_dec_sub16_rsrv; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub16_dec31_dec_sub16_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub16_dec31_dec_sub16_sgn; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub16_dec31_dec_sub16_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -83115,8 +90263,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_cr_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -83124,8 +90272,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_cr_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -83133,8 +90281,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_in1; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -83142,8 +90290,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_in2; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -83151,8 +90299,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_in3; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -83160,8 +90308,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -83169,33 +90317,33 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_out2; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub18_dec31_dec_sub18_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) - wire [31:0] dec31_dec_sub18_opcode_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub16_dec31_dec_sub16_upd; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) + wire [31:0] dec31_dec_sub16_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub19_dec31_dec_sub19_SV_Etype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub18_dec31_dec_sub18_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub19_dec31_dec_sub19_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [7:0] dec31_dec_sub19_dec31_dec_sub19_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub19_dec31_dec_sub19_br; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub18_dec31_dec_sub18_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub18_dec31_dec_sub18_asmcode; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub18_dec31_dec_sub18_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -83205,8 +90353,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub19_dec31_dec_sub19_cr_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub18_dec31_dec_sub18_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -83214,16 +90362,16 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub19_dec31_dec_sub19_cr_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub18_dec31_dec_sub18_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub19_dec31_dec_sub19_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub19_dec31_dec_sub19_cry_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub18_dec31_dec_sub18_cry_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub18_dec31_dec_sub18_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) (* enum_value_00001 = "I" *) @@ -83255,33 +90403,36 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [4:0] dec31_dec_sub19_dec31_dec_sub19_form; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub18_dec31_dec_sub18_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec31_dec_sub19_dec31_dec_sub19_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec31_dec_sub18_dec31_dec_sub18_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub19_dec31_dec_sub19_in1_sel; + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub18_dec31_dec_sub18_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -83297,14 +90448,17 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub19_dec31_dec_sub19_in2_sel; + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub18_dec31_dec_sub18_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub19_dec31_dec_sub19_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub18_dec31_dec_sub18_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -83380,46 +90534,49 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [6:0] dec31_dec_sub19_dec31_dec_sub19_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub19_dec31_dec_sub19_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub19_dec31_dec_sub19_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub19_dec31_dec_sub19_is_32b; + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub18_dec31_dec_sub18_internal_op; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub18_dec31_dec_sub18_inv_a; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub18_dec31_dec_sub18_inv_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub18_dec31_dec_sub18_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "is1B" *) (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub19_dec31_dec_sub19_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub19_dec31_dec_sub19_lk; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub18_dec31_dec_sub18_ldst_len; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub18_dec31_dec_sub18_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RT" *) (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub19_dec31_dec_sub19_out_sel; + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub18_dec31_dec_sub18_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub19_dec31_dec_sub19_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub19_dec31_dec_sub19_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub19_dec31_dec_sub19_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub19_dec31_dec_sub19_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub19_dec31_dec_sub19_sgn_ext; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub18_dec31_dec_sub18_rc_sel; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub18_dec31_dec_sub18_rsrv; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub18_dec31_dec_sub18_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub18_dec31_dec_sub18_sgn; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub18_dec31_dec_sub18_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -83427,8 +90584,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_cr_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -83436,8 +90593,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_cr_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -83445,8 +90602,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_in1; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -83454,8 +90611,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_in2; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -83463,8 +90620,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_in3; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -83472,8 +90629,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -83481,33 +90638,33 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_out2; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub19_dec31_dec_sub19_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) - wire [31:0] dec31_dec_sub19_opcode_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub18_dec31_dec_sub18_upd; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) + wire [31:0] dec31_dec_sub18_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub20_dec31_dec_sub20_SV_Etype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub19_dec31_dec_sub19_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub20_dec31_dec_sub20_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [7:0] dec31_dec_sub20_dec31_dec_sub20_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub20_dec31_dec_sub20_br; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub19_dec31_dec_sub19_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub19_dec31_dec_sub19_asmcode; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub19_dec31_dec_sub19_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -83517,8 +90674,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub20_dec31_dec_sub20_cr_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub19_dec31_dec_sub19_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -83526,16 +90683,16 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub20_dec31_dec_sub20_cr_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub19_dec31_dec_sub19_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub20_dec31_dec_sub20_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub20_dec31_dec_sub20_cry_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub19_dec31_dec_sub19_cry_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub19_dec31_dec_sub19_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) (* enum_value_00001 = "I" *) @@ -83567,33 +90724,36 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [4:0] dec31_dec_sub20_dec31_dec_sub20_form; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub19_dec31_dec_sub19_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec31_dec_sub20_dec31_dec_sub20_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec31_dec_sub19_dec31_dec_sub19_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub20_dec31_dec_sub20_in1_sel; + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub19_dec31_dec_sub19_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -83609,14 +90769,17 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub20_dec31_dec_sub20_in2_sel; + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub19_dec31_dec_sub19_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub20_dec31_dec_sub20_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub19_dec31_dec_sub19_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -83692,46 +90855,49 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [6:0] dec31_dec_sub20_dec31_dec_sub20_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub20_dec31_dec_sub20_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub20_dec31_dec_sub20_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub20_dec31_dec_sub20_is_32b; + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub19_dec31_dec_sub19_internal_op; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub19_dec31_dec_sub19_inv_a; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub19_dec31_dec_sub19_inv_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub19_dec31_dec_sub19_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "is1B" *) (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub20_dec31_dec_sub20_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub20_dec31_dec_sub20_lk; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub19_dec31_dec_sub19_ldst_len; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub19_dec31_dec_sub19_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RT" *) (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub20_dec31_dec_sub20_out_sel; + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub19_dec31_dec_sub19_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub20_dec31_dec_sub20_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub20_dec31_dec_sub20_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub20_dec31_dec_sub20_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub20_dec31_dec_sub20_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub20_dec31_dec_sub20_sgn_ext; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub19_dec31_dec_sub19_rc_sel; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub19_dec31_dec_sub19_rsrv; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub19_dec31_dec_sub19_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub19_dec31_dec_sub19_sgn; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub19_dec31_dec_sub19_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -83739,8 +90905,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_cr_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -83748,8 +90914,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_cr_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -83757,8 +90923,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_in1; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -83766,8 +90932,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_in2; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -83775,8 +90941,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_in3; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -83784,8 +90950,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -83793,33 +90959,33 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_out2; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub20_dec31_dec_sub20_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) - wire [31:0] dec31_dec_sub20_opcode_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub19_dec31_dec_sub19_upd; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) + wire [31:0] dec31_dec_sub19_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub21_dec31_dec_sub21_SV_Etype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub20_dec31_dec_sub20_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub21_dec31_dec_sub21_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [7:0] dec31_dec_sub21_dec31_dec_sub21_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub21_dec31_dec_sub21_br; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub20_dec31_dec_sub20_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub20_dec31_dec_sub20_asmcode; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub20_dec31_dec_sub20_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -83829,8 +90995,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub21_dec31_dec_sub21_cr_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub20_dec31_dec_sub20_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -83838,16 +91004,16 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub21_dec31_dec_sub21_cr_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub20_dec31_dec_sub20_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub21_dec31_dec_sub21_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub21_dec31_dec_sub21_cry_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub20_dec31_dec_sub20_cry_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub20_dec31_dec_sub20_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) (* enum_value_00001 = "I" *) @@ -83879,33 +91045,36 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [4:0] dec31_dec_sub21_dec31_dec_sub21_form; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub20_dec31_dec_sub20_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec31_dec_sub21_dec31_dec_sub21_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec31_dec_sub20_dec31_dec_sub20_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub21_dec31_dec_sub21_in1_sel; + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub20_dec31_dec_sub20_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -83921,14 +91090,17 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub21_dec31_dec_sub21_in2_sel; + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub20_dec31_dec_sub20_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub21_dec31_dec_sub21_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub20_dec31_dec_sub20_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -84004,46 +91176,49 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [6:0] dec31_dec_sub21_dec31_dec_sub21_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub21_dec31_dec_sub21_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub21_dec31_dec_sub21_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub21_dec31_dec_sub21_is_32b; + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub20_dec31_dec_sub20_internal_op; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub20_dec31_dec_sub20_inv_a; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub20_dec31_dec_sub20_inv_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub20_dec31_dec_sub20_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "is1B" *) (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub21_dec31_dec_sub21_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub21_dec31_dec_sub21_lk; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub20_dec31_dec_sub20_ldst_len; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub20_dec31_dec_sub20_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RT" *) (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub21_dec31_dec_sub21_out_sel; + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub20_dec31_dec_sub20_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub21_dec31_dec_sub21_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub21_dec31_dec_sub21_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub21_dec31_dec_sub21_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub21_dec31_dec_sub21_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub21_dec31_dec_sub21_sgn_ext; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub20_dec31_dec_sub20_rc_sel; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub20_dec31_dec_sub20_rsrv; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub20_dec31_dec_sub20_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub20_dec31_dec_sub20_sgn; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub20_dec31_dec_sub20_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -84051,8 +91226,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_cr_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -84060,8 +91235,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_cr_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -84069,8 +91244,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_in1; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -84078,8 +91253,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_in2; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -84087,8 +91262,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_in3; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -84096,8 +91271,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -84105,33 +91280,33 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_out2; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub21_dec31_dec_sub21_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) - wire [31:0] dec31_dec_sub21_opcode_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub20_dec31_dec_sub20_upd; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) + wire [31:0] dec31_dec_sub20_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub22_dec31_dec_sub22_SV_Etype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub21_dec31_dec_sub21_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub22_dec31_dec_sub22_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [7:0] dec31_dec_sub22_dec31_dec_sub22_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub22_dec31_dec_sub22_br; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub21_dec31_dec_sub21_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub21_dec31_dec_sub21_asmcode; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub21_dec31_dec_sub21_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -84141,8 +91316,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub22_dec31_dec_sub22_cr_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub21_dec31_dec_sub21_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -84150,16 +91325,16 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub22_dec31_dec_sub22_cr_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub21_dec31_dec_sub21_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub22_dec31_dec_sub22_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub22_dec31_dec_sub22_cry_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub21_dec31_dec_sub21_cry_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub21_dec31_dec_sub21_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) (* enum_value_00001 = "I" *) @@ -84191,33 +91366,36 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [4:0] dec31_dec_sub22_dec31_dec_sub22_form; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub21_dec31_dec_sub21_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec31_dec_sub22_dec31_dec_sub22_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec31_dec_sub21_dec31_dec_sub21_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub22_dec31_dec_sub22_in1_sel; + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub21_dec31_dec_sub21_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -84233,14 +91411,17 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub22_dec31_dec_sub22_in2_sel; + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub21_dec31_dec_sub21_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub22_dec31_dec_sub22_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub21_dec31_dec_sub21_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -84316,46 +91497,49 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [6:0] dec31_dec_sub22_dec31_dec_sub22_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub22_dec31_dec_sub22_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub22_dec31_dec_sub22_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub22_dec31_dec_sub22_is_32b; + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub21_dec31_dec_sub21_internal_op; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub21_dec31_dec_sub21_inv_a; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub21_dec31_dec_sub21_inv_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub21_dec31_dec_sub21_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "is1B" *) (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub22_dec31_dec_sub22_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub22_dec31_dec_sub22_lk; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub21_dec31_dec_sub21_ldst_len; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub21_dec31_dec_sub21_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RT" *) (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub22_dec31_dec_sub22_out_sel; + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub21_dec31_dec_sub21_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub22_dec31_dec_sub22_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub22_dec31_dec_sub22_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub22_dec31_dec_sub22_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub22_dec31_dec_sub22_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub22_dec31_dec_sub22_sgn_ext; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub21_dec31_dec_sub21_rc_sel; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub21_dec31_dec_sub21_rsrv; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub21_dec31_dec_sub21_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub21_dec31_dec_sub21_sgn; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub21_dec31_dec_sub21_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -84363,8 +91547,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_cr_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -84372,8 +91556,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_cr_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -84381,8 +91565,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_in1; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -84390,8 +91574,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_in2; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -84399,8 +91583,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_in3; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -84408,8 +91592,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -84417,33 +91601,33 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_out2; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub22_dec31_dec_sub22_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) - wire [31:0] dec31_dec_sub22_opcode_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub21_dec31_dec_sub21_upd; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) + wire [31:0] dec31_dec_sub21_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub23_dec31_dec_sub23_SV_Etype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub22_dec31_dec_sub22_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub23_dec31_dec_sub23_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [7:0] dec31_dec_sub23_dec31_dec_sub23_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub23_dec31_dec_sub23_br; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub22_dec31_dec_sub22_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub22_dec31_dec_sub22_asmcode; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub22_dec31_dec_sub22_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -84453,8 +91637,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub23_dec31_dec_sub23_cr_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub22_dec31_dec_sub22_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -84462,16 +91646,16 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub23_dec31_dec_sub23_cr_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub22_dec31_dec_sub22_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub23_dec31_dec_sub23_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub23_dec31_dec_sub23_cry_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub22_dec31_dec_sub22_cry_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub22_dec31_dec_sub22_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) (* enum_value_00001 = "I" *) @@ -84503,33 +91687,36 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [4:0] dec31_dec_sub23_dec31_dec_sub23_form; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub22_dec31_dec_sub22_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec31_dec_sub23_dec31_dec_sub23_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec31_dec_sub22_dec31_dec_sub22_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub23_dec31_dec_sub23_in1_sel; + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub22_dec31_dec_sub22_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -84545,14 +91732,17 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub23_dec31_dec_sub23_in2_sel; + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub22_dec31_dec_sub22_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub23_dec31_dec_sub23_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub22_dec31_dec_sub22_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -84628,46 +91818,49 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [6:0] dec31_dec_sub23_dec31_dec_sub23_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub23_dec31_dec_sub23_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub23_dec31_dec_sub23_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub23_dec31_dec_sub23_is_32b; + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub22_dec31_dec_sub22_internal_op; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub22_dec31_dec_sub22_inv_a; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub22_dec31_dec_sub22_inv_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub22_dec31_dec_sub22_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "is1B" *) (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub23_dec31_dec_sub23_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub23_dec31_dec_sub23_lk; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub22_dec31_dec_sub22_ldst_len; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub22_dec31_dec_sub22_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RT" *) (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub23_dec31_dec_sub23_out_sel; + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub22_dec31_dec_sub22_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub23_dec31_dec_sub23_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub23_dec31_dec_sub23_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub23_dec31_dec_sub23_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub23_dec31_dec_sub23_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub23_dec31_dec_sub23_sgn_ext; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub22_dec31_dec_sub22_rc_sel; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub22_dec31_dec_sub22_rsrv; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub22_dec31_dec_sub22_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub22_dec31_dec_sub22_sgn; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub22_dec31_dec_sub22_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -84675,8 +91868,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_cr_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -84684,8 +91877,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_cr_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -84693,8 +91886,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_in1; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -84702,8 +91895,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_in2; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -84711,8 +91904,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_in3; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -84720,8 +91913,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -84729,33 +91922,33 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_out2; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub23_dec31_dec_sub23_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) - wire [31:0] dec31_dec_sub23_opcode_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub22_dec31_dec_sub22_upd; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) + wire [31:0] dec31_dec_sub22_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub24_dec31_dec_sub24_SV_Etype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub23_dec31_dec_sub23_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub24_dec31_dec_sub24_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [7:0] dec31_dec_sub24_dec31_dec_sub24_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub24_dec31_dec_sub24_br; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub23_dec31_dec_sub23_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub23_dec31_dec_sub23_asmcode; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub23_dec31_dec_sub23_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -84765,8 +91958,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub24_dec31_dec_sub24_cr_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub23_dec31_dec_sub23_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -84774,16 +91967,16 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub24_dec31_dec_sub24_cr_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub23_dec31_dec_sub23_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub24_dec31_dec_sub24_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub24_dec31_dec_sub24_cry_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub23_dec31_dec_sub23_cry_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub23_dec31_dec_sub23_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) (* enum_value_00001 = "I" *) @@ -84815,33 +92008,36 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [4:0] dec31_dec_sub24_dec31_dec_sub24_form; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub23_dec31_dec_sub23_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec31_dec_sub24_dec31_dec_sub24_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec31_dec_sub23_dec31_dec_sub23_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub24_dec31_dec_sub24_in1_sel; + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub23_dec31_dec_sub23_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -84857,14 +92053,17 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub24_dec31_dec_sub24_in2_sel; + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub23_dec31_dec_sub23_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub24_dec31_dec_sub24_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub23_dec31_dec_sub23_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -84940,46 +92139,49 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [6:0] dec31_dec_sub24_dec31_dec_sub24_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub24_dec31_dec_sub24_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub24_dec31_dec_sub24_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub24_dec31_dec_sub24_is_32b; + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub23_dec31_dec_sub23_internal_op; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub23_dec31_dec_sub23_inv_a; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub23_dec31_dec_sub23_inv_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub23_dec31_dec_sub23_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "is1B" *) (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub24_dec31_dec_sub24_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub24_dec31_dec_sub24_lk; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub23_dec31_dec_sub23_ldst_len; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub23_dec31_dec_sub23_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RT" *) (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub24_dec31_dec_sub24_out_sel; + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub23_dec31_dec_sub23_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub24_dec31_dec_sub24_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub24_dec31_dec_sub24_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub24_dec31_dec_sub24_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub24_dec31_dec_sub24_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub24_dec31_dec_sub24_sgn_ext; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub23_dec31_dec_sub23_rc_sel; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub23_dec31_dec_sub23_rsrv; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub23_dec31_dec_sub23_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub23_dec31_dec_sub23_sgn; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub23_dec31_dec_sub23_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -84987,8 +92189,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_cr_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -84996,8 +92198,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_cr_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -85005,8 +92207,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_in1; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -85014,8 +92216,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_in2; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -85023,8 +92225,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_in3; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -85032,8 +92234,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -85041,33 +92243,33 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_out2; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub24_dec31_dec_sub24_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) - wire [31:0] dec31_dec_sub24_opcode_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub23_dec31_dec_sub23_upd; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) + wire [31:0] dec31_dec_sub23_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub26_dec31_dec_sub26_SV_Etype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub24_dec31_dec_sub24_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub26_dec31_dec_sub26_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [7:0] dec31_dec_sub26_dec31_dec_sub26_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub26_dec31_dec_sub26_br; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub24_dec31_dec_sub24_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub24_dec31_dec_sub24_asmcode; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub24_dec31_dec_sub24_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -85077,8 +92279,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub26_dec31_dec_sub26_cr_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub24_dec31_dec_sub24_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -85086,16 +92288,16 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub26_dec31_dec_sub26_cr_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub24_dec31_dec_sub24_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub26_dec31_dec_sub26_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub26_dec31_dec_sub26_cry_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub24_dec31_dec_sub24_cry_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub24_dec31_dec_sub24_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) (* enum_value_00001 = "I" *) @@ -85127,33 +92329,36 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [4:0] dec31_dec_sub26_dec31_dec_sub26_form; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub24_dec31_dec_sub24_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec31_dec_sub26_dec31_dec_sub26_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec31_dec_sub24_dec31_dec_sub24_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub26_dec31_dec_sub26_in1_sel; + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub24_dec31_dec_sub24_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -85169,14 +92374,17 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub26_dec31_dec_sub26_in2_sel; + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub24_dec31_dec_sub24_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub26_dec31_dec_sub26_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub24_dec31_dec_sub24_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -85252,46 +92460,49 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [6:0] dec31_dec_sub26_dec31_dec_sub26_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub26_dec31_dec_sub26_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub26_dec31_dec_sub26_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub26_dec31_dec_sub26_is_32b; + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub24_dec31_dec_sub24_internal_op; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub24_dec31_dec_sub24_inv_a; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub24_dec31_dec_sub24_inv_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub24_dec31_dec_sub24_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "is1B" *) (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub26_dec31_dec_sub26_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub26_dec31_dec_sub26_lk; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub24_dec31_dec_sub24_ldst_len; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub24_dec31_dec_sub24_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RT" *) (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub26_dec31_dec_sub26_out_sel; + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub24_dec31_dec_sub24_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub26_dec31_dec_sub26_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub26_dec31_dec_sub26_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub26_dec31_dec_sub26_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub26_dec31_dec_sub26_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub26_dec31_dec_sub26_sgn_ext; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub24_dec31_dec_sub24_rc_sel; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub24_dec31_dec_sub24_rsrv; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub24_dec31_dec_sub24_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub24_dec31_dec_sub24_sgn; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub24_dec31_dec_sub24_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -85299,8 +92510,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_cr_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -85308,8 +92519,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_cr_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -85317,8 +92528,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_in1; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -85326,8 +92537,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_in2; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -85335,8 +92546,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_in3; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -85344,8 +92555,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -85353,33 +92564,33 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_out2; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub26_dec31_dec_sub26_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) - wire [31:0] dec31_dec_sub26_opcode_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub24_dec31_dec_sub24_upd; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) + wire [31:0] dec31_dec_sub24_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub27_dec31_dec_sub27_SV_Etype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub26_dec31_dec_sub26_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub27_dec31_dec_sub27_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [7:0] dec31_dec_sub27_dec31_dec_sub27_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub27_dec31_dec_sub27_br; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub26_dec31_dec_sub26_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub26_dec31_dec_sub26_asmcode; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub26_dec31_dec_sub26_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -85389,8 +92600,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub27_dec31_dec_sub27_cr_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub26_dec31_dec_sub26_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -85398,16 +92609,16 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub27_dec31_dec_sub27_cr_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub26_dec31_dec_sub26_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub27_dec31_dec_sub27_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub27_dec31_dec_sub27_cry_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub26_dec31_dec_sub26_cry_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub26_dec31_dec_sub26_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) (* enum_value_00001 = "I" *) @@ -85439,33 +92650,36 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [4:0] dec31_dec_sub27_dec31_dec_sub27_form; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub26_dec31_dec_sub26_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec31_dec_sub27_dec31_dec_sub27_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec31_dec_sub26_dec31_dec_sub26_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub27_dec31_dec_sub27_in1_sel; + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub26_dec31_dec_sub26_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -85481,14 +92695,17 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub27_dec31_dec_sub27_in2_sel; + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub26_dec31_dec_sub26_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub27_dec31_dec_sub27_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub26_dec31_dec_sub26_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -85564,46 +92781,49 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [6:0] dec31_dec_sub27_dec31_dec_sub27_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub27_dec31_dec_sub27_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub27_dec31_dec_sub27_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub27_dec31_dec_sub27_is_32b; + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub26_dec31_dec_sub26_internal_op; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub26_dec31_dec_sub26_inv_a; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub26_dec31_dec_sub26_inv_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub26_dec31_dec_sub26_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "is1B" *) (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub27_dec31_dec_sub27_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub27_dec31_dec_sub27_lk; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub26_dec31_dec_sub26_ldst_len; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub26_dec31_dec_sub26_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RT" *) (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub27_dec31_dec_sub27_out_sel; + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub26_dec31_dec_sub26_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub27_dec31_dec_sub27_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub27_dec31_dec_sub27_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub27_dec31_dec_sub27_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub27_dec31_dec_sub27_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub27_dec31_dec_sub27_sgn_ext; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub26_dec31_dec_sub26_rc_sel; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub26_dec31_dec_sub26_rsrv; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub26_dec31_dec_sub26_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub26_dec31_dec_sub26_sgn; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub26_dec31_dec_sub26_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -85611,8 +92831,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_cr_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -85620,8 +92840,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_cr_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -85629,8 +92849,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_in1; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -85638,8 +92858,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_in2; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -85647,8 +92867,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_in3; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -85656,8 +92876,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -85665,33 +92885,33 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_out2; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub27_dec31_dec_sub27_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) - wire [31:0] dec31_dec_sub27_opcode_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub26_dec31_dec_sub26_upd; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) + wire [31:0] dec31_dec_sub26_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub28_dec31_dec_sub28_SV_Etype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub27_dec31_dec_sub27_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub28_dec31_dec_sub28_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [7:0] dec31_dec_sub28_dec31_dec_sub28_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub28_dec31_dec_sub28_br; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub27_dec31_dec_sub27_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub27_dec31_dec_sub27_asmcode; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub27_dec31_dec_sub27_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -85701,8 +92921,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub28_dec31_dec_sub28_cr_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub27_dec31_dec_sub27_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -85710,16 +92930,16 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub28_dec31_dec_sub28_cr_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub27_dec31_dec_sub27_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub28_dec31_dec_sub28_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub28_dec31_dec_sub28_cry_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub27_dec31_dec_sub27_cry_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub27_dec31_dec_sub27_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) (* enum_value_00001 = "I" *) @@ -85751,33 +92971,36 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [4:0] dec31_dec_sub28_dec31_dec_sub28_form; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub27_dec31_dec_sub27_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec31_dec_sub28_dec31_dec_sub28_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec31_dec_sub27_dec31_dec_sub27_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub28_dec31_dec_sub28_in1_sel; + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub27_dec31_dec_sub27_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -85793,14 +93016,17 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub28_dec31_dec_sub28_in2_sel; + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub27_dec31_dec_sub27_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub28_dec31_dec_sub28_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub27_dec31_dec_sub27_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -85876,46 +93102,49 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [6:0] dec31_dec_sub28_dec31_dec_sub28_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub28_dec31_dec_sub28_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub28_dec31_dec_sub28_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub28_dec31_dec_sub28_is_32b; + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub27_dec31_dec_sub27_internal_op; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub27_dec31_dec_sub27_inv_a; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub27_dec31_dec_sub27_inv_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub27_dec31_dec_sub27_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "is1B" *) (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub28_dec31_dec_sub28_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub28_dec31_dec_sub28_lk; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub27_dec31_dec_sub27_ldst_len; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub27_dec31_dec_sub27_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RT" *) (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub28_dec31_dec_sub28_out_sel; + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub27_dec31_dec_sub27_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub28_dec31_dec_sub28_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub28_dec31_dec_sub28_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub28_dec31_dec_sub28_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub28_dec31_dec_sub28_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub28_dec31_dec_sub28_sgn_ext; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub27_dec31_dec_sub27_rc_sel; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub27_dec31_dec_sub27_rsrv; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub27_dec31_dec_sub27_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub27_dec31_dec_sub27_sgn; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub27_dec31_dec_sub27_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -85923,8 +93152,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_cr_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -85932,8 +93161,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_cr_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -85941,8 +93170,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_in1; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -85950,8 +93179,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_in2; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -85959,8 +93188,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_in3; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -85968,8 +93197,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -85977,33 +93206,33 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_out2; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub28_dec31_dec_sub28_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) - wire [31:0] dec31_dec_sub28_opcode_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub27_dec31_dec_sub27_upd; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) + wire [31:0] dec31_dec_sub27_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub4_dec31_dec_sub4_SV_Etype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub28_dec31_dec_sub28_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub4_dec31_dec_sub4_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [7:0] dec31_dec_sub4_dec31_dec_sub4_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub4_dec31_dec_sub4_br; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub28_dec31_dec_sub28_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub28_dec31_dec_sub28_asmcode; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub28_dec31_dec_sub28_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -86013,8 +93242,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub4_dec31_dec_sub4_cr_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub28_dec31_dec_sub28_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -86022,16 +93251,16 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub4_dec31_dec_sub4_cr_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub28_dec31_dec_sub28_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub4_dec31_dec_sub4_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub4_dec31_dec_sub4_cry_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub28_dec31_dec_sub28_cry_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub28_dec31_dec_sub28_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) (* enum_value_00001 = "I" *) @@ -86063,33 +93292,36 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [4:0] dec31_dec_sub4_dec31_dec_sub4_form; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub28_dec31_dec_sub28_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec31_dec_sub4_dec31_dec_sub4_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec31_dec_sub28_dec31_dec_sub28_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub4_dec31_dec_sub4_in1_sel; + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub28_dec31_dec_sub28_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -86105,14 +93337,17 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub4_dec31_dec_sub4_in2_sel; + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub28_dec31_dec_sub28_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub4_dec31_dec_sub4_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub28_dec31_dec_sub28_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -86188,46 +93423,49 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [6:0] dec31_dec_sub4_dec31_dec_sub4_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub4_dec31_dec_sub4_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub4_dec31_dec_sub4_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub4_dec31_dec_sub4_is_32b; + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub28_dec31_dec_sub28_internal_op; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub28_dec31_dec_sub28_inv_a; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub28_dec31_dec_sub28_inv_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub28_dec31_dec_sub28_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "is1B" *) (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub4_dec31_dec_sub4_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub4_dec31_dec_sub4_lk; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub28_dec31_dec_sub28_ldst_len; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub28_dec31_dec_sub28_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RT" *) (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub4_dec31_dec_sub4_out_sel; + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub28_dec31_dec_sub28_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub4_dec31_dec_sub4_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub4_dec31_dec_sub4_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub4_dec31_dec_sub4_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub4_dec31_dec_sub4_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub4_dec31_dec_sub4_sgn_ext; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub28_dec31_dec_sub28_rc_sel; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub28_dec31_dec_sub28_rsrv; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub28_dec31_dec_sub28_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub28_dec31_dec_sub28_sgn; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub28_dec31_dec_sub28_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -86235,8 +93473,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_cr_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -86244,8 +93482,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_cr_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -86253,8 +93491,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_in1; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -86262,8 +93500,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_in2; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -86271,8 +93509,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_in3; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -86280,8 +93518,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -86289,33 +93527,33 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_out2; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub4_dec31_dec_sub4_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) - wire [31:0] dec31_dec_sub4_opcode_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub28_dec31_dec_sub28_upd; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) + wire [31:0] dec31_dec_sub28_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub8_dec31_dec_sub8_SV_Etype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub4_dec31_dec_sub4_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub8_dec31_dec_sub8_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [7:0] dec31_dec_sub8_dec31_dec_sub8_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub8_dec31_dec_sub8_br; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub4_dec31_dec_sub4_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub4_dec31_dec_sub4_asmcode; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub4_dec31_dec_sub4_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -86325,8 +93563,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub8_dec31_dec_sub8_cr_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub4_dec31_dec_sub4_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -86334,16 +93572,16 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub8_dec31_dec_sub8_cr_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub4_dec31_dec_sub4_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub8_dec31_dec_sub8_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub8_dec31_dec_sub8_cry_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub4_dec31_dec_sub4_cry_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub4_dec31_dec_sub4_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) (* enum_value_00001 = "I" *) @@ -86375,33 +93613,36 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [4:0] dec31_dec_sub8_dec31_dec_sub8_form; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub4_dec31_dec_sub4_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec31_dec_sub8_dec31_dec_sub8_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec31_dec_sub4_dec31_dec_sub4_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub8_dec31_dec_sub8_in1_sel; + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub4_dec31_dec_sub4_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -86417,14 +93658,17 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub8_dec31_dec_sub8_in2_sel; + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub4_dec31_dec_sub4_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub8_dec31_dec_sub8_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub4_dec31_dec_sub4_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -86500,46 +93744,49 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [6:0] dec31_dec_sub8_dec31_dec_sub8_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub8_dec31_dec_sub8_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub8_dec31_dec_sub8_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub8_dec31_dec_sub8_is_32b; + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub4_dec31_dec_sub4_internal_op; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub4_dec31_dec_sub4_inv_a; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub4_dec31_dec_sub4_inv_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub4_dec31_dec_sub4_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "is1B" *) (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub8_dec31_dec_sub8_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub8_dec31_dec_sub8_lk; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub4_dec31_dec_sub4_ldst_len; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub4_dec31_dec_sub4_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RT" *) (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub8_dec31_dec_sub8_out_sel; + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub4_dec31_dec_sub4_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub8_dec31_dec_sub8_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub8_dec31_dec_sub8_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub8_dec31_dec_sub8_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub8_dec31_dec_sub8_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub8_dec31_dec_sub8_sgn_ext; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub4_dec31_dec_sub4_rc_sel; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub4_dec31_dec_sub4_rsrv; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub4_dec31_dec_sub4_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub4_dec31_dec_sub4_sgn; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub4_dec31_dec_sub4_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -86547,8 +93794,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_cr_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -86556,8 +93803,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_cr_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -86565,8 +93812,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_in1; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -86574,8 +93821,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_in2; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -86583,8 +93830,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_in3; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -86592,8 +93839,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "Idx0" *) @@ -86601,33 +93848,33 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_out2; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub8_dec31_dec_sub8_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) - wire [31:0] dec31_dec_sub8_opcode_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub4_dec31_dec_sub4_upd; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) + wire [31:0] dec31_dec_sub4_opcode_in; (* enum_base_type = "SVEtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub9_dec31_dec_sub9_SV_Etype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub8_dec31_dec_sub8_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub9_dec31_dec_sub9_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [7:0] dec31_dec_sub9_dec31_dec_sub9_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub9_dec31_dec_sub9_br; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub8_dec31_dec_sub8_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub8_dec31_dec_sub8_asmcode; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub8_dec31_dec_sub8_br; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -86637,8 +93884,8 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub9_dec31_dec_sub9_cr_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub8_dec31_dec_sub8_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "CR0" *) @@ -86646,16 +93893,16 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub9_dec31_dec_sub9_cr_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub8_dec31_dec_sub8_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub9_dec31_dec_sub9_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) - wire dec31_dec_sub9_dec31_dec_sub9_cry_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub8_dec31_dec_sub8_cry_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub8_dec31_dec_sub8_cry_out; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) (* enum_value_00001 = "I" *) @@ -86687,33 +93934,36 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [4:0] dec31_dec_sub9_dec31_dec_sub9_form; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub8_dec31_dec_sub8_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec31_dec_sub9_dec31_dec_sub9_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec31_dec_sub8_dec31_dec_sub8_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [2:0] dec31_dec_sub9_dec31_dec_sub9_in1_sel; + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub8_dec31_dec_sub8_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -86729,14 +93979,17 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [3:0] dec31_dec_sub9_dec31_dec_sub9_in2_sel; + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub8_dec31_dec_sub8_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [1:0] dec31_dec_sub9_dec31_dec_sub9_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub8_dec31_dec_sub8_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -86812,13 +94065,336 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [6:0] dec31_dec_sub8_dec31_dec_sub8_internal_op; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub8_dec31_dec_sub8_inv_a; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub8_dec31_dec_sub8_inv_out; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub8_dec31_dec_sub8_is_32b; + (* enum_base_type = "LdstLen" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "is1B" *) + (* enum_value_0010 = "is2B" *) + (* enum_value_0100 = "is4B" *) + (* enum_value_1000 = "is8B" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub8_dec31_dec_sub8_ldst_len; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub8_dec31_dec_sub8_lk; + (* enum_base_type = "OutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RT" *) + (* enum_value_010 = "RA" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RT_OR_ZERO" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub8_dec31_dec_sub8_out_sel; + (* enum_base_type = "RC" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "RC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub8_dec31_dec_sub8_rc_sel; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub8_dec31_dec_sub8_rsrv; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub8_dec31_dec_sub8_sgl_pipe; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub8_dec31_dec_sub8_sgn; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub8_dec31_dec_sub8_sgn_ext; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_cr_in; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_cr_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_in1; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_in2; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_in3; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_out; + (* enum_base_type = "SVEXTRA" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "Idx0" *) + (* enum_value_010 = "Idx1" *) + (* enum_value_011 = "Idx2" *) + (* enum_value_100 = "Idx3" *) + (* enum_value_101 = "Idx_1_2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_out2; + (* enum_base_type = "LDSTMode" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "update" *) + (* enum_value_10 = "cix" *) + (* enum_value_11 = "cx" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub8_dec31_dec_sub8_upd; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) + wire [31:0] dec31_dec_sub8_opcode_in; + (* enum_base_type = "SVEtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "EXTRA2" *) + (* enum_value_10 = "EXTRA3" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub9_dec31_dec_sub9_SV_Etype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub9_dec31_dec_sub9_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [7:0] dec31_dec_sub9_dec31_dec_sub9_asmcode; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub9_dec31_dec_sub9_br; + (* enum_base_type = "CRInSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BI" *) + (* enum_value_011 = "BFA" *) + (* enum_value_100 = "BA_BB" *) + (* enum_value_101 = "BC" *) + (* enum_value_110 = "WHOLE_REG" *) + (* enum_value_111 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub9_dec31_dec_sub9_cr_in; + (* enum_base_type = "CROutSel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "CR0" *) + (* enum_value_010 = "BF" *) + (* enum_value_011 = "BT" *) + (* enum_value_100 = "WHOLE_REG" *) + (* enum_value_101 = "CR1" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub9_dec31_dec_sub9_cr_out; + (* enum_base_type = "CryIn" *) + (* enum_value_00 = "ZERO" *) + (* enum_value_01 = "ONE" *) + (* enum_value_10 = "CA" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [1:0] dec31_dec_sub9_dec31_dec_sub9_cry_in; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) + wire dec31_dec_sub9_dec31_dec_sub9_cry_out; + (* enum_base_type = "Form" *) + (* enum_value_00000 = "NONE" *) + (* enum_value_00001 = "I" *) + (* enum_value_00010 = "B" *) + (* enum_value_00011 = "SC" *) + (* enum_value_00100 = "D" *) + (* enum_value_00101 = "DS" *) + (* enum_value_00110 = "DQ" *) + (* enum_value_00111 = "DX" *) + (* enum_value_01000 = "X" *) + (* enum_value_01001 = "XL" *) + (* enum_value_01010 = "XFX" *) + (* enum_value_01011 = "XFL" *) + (* enum_value_01100 = "XX1" *) + (* enum_value_01101 = "XX2" *) + (* enum_value_01110 = "XX3" *) + (* enum_value_01111 = "XX4" *) + (* enum_value_10000 = "XS" *) + (* enum_value_10001 = "XO" *) + (* enum_value_10010 = "A" *) + (* enum_value_10011 = "M" *) + (* enum_value_10100 = "MD" *) + (* enum_value_10101 = "MDS" *) + (* enum_value_10110 = "VA" *) + (* enum_value_10111 = "VC" *) + (* enum_value_11000 = "VX" *) + (* enum_value_11001 = "EVX" *) + (* enum_value_11010 = "EVS" *) + (* enum_value_11011 = "Z22" *) + (* enum_value_11100 = "Z23" *) + (* enum_value_11101 = "SVL" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [4:0] dec31_dec_sub9_dec31_dec_sub9_form; + (* enum_base_type = "Function" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec31_dec_sub9_dec31_dec_sub9_function_unit; + (* enum_base_type = "In1Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RA" *) + (* enum_value_010 = "RA_OR_ZERO" *) + (* enum_value_011 = "SPR" *) + (* enum_value_100 = "RS" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub9_dec31_dec_sub9_in1_sel; + (* enum_base_type = "In2Sel" *) + (* enum_value_0000 = "NONE" *) + (* enum_value_0001 = "RB" *) + (* enum_value_0010 = "CONST_UI" *) + (* enum_value_0011 = "CONST_SI" *) + (* enum_value_0100 = "CONST_UI_HI" *) + (* enum_value_0101 = "CONST_SI_HI" *) + (* enum_value_0110 = "CONST_LI" *) + (* enum_value_0111 = "CONST_BD" *) + (* enum_value_1000 = "CONST_DS" *) + (* enum_value_1001 = "CONST_M1" *) + (* enum_value_1010 = "CONST_SH" *) + (* enum_value_1011 = "CONST_SH32" *) + (* enum_value_1100 = "SPR" *) + (* enum_value_1101 = "RS" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [3:0] dec31_dec_sub9_dec31_dec_sub9_in2_sel; + (* enum_base_type = "In3Sel" *) + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [2:0] dec31_dec_sub9_dec31_dec_sub9_in3_sel; + (* enum_base_type = "MicrOp" *) + (* enum_value_0000000 = "OP_ILLEGAL" *) + (* enum_value_0000001 = "OP_NOP" *) + (* enum_value_0000010 = "OP_ADD" *) + (* enum_value_0000011 = "OP_ADDPCIS" *) + (* enum_value_0000100 = "OP_AND" *) + (* enum_value_0000101 = "OP_ATTN" *) + (* enum_value_0000110 = "OP_B" *) + (* enum_value_0000111 = "OP_BC" *) + (* enum_value_0001000 = "OP_BCREG" *) + (* enum_value_0001001 = "OP_BPERM" *) + (* enum_value_0001010 = "OP_CMP" *) + (* enum_value_0001011 = "OP_CMPB" *) + (* enum_value_0001100 = "OP_CMPEQB" *) + (* enum_value_0001101 = "OP_CMPRB" *) + (* enum_value_0001110 = "OP_CNTZ" *) + (* enum_value_0001111 = "OP_CRAND" *) + (* enum_value_0010000 = "OP_CRANDC" *) + (* enum_value_0010001 = "OP_CREQV" *) + (* enum_value_0010010 = "OP_CRNAND" *) + (* enum_value_0010011 = "OP_CRNOR" *) + (* enum_value_0010100 = "OP_CROR" *) + (* enum_value_0010101 = "OP_CRORC" *) + (* enum_value_0010110 = "OP_CRXOR" *) + (* enum_value_0010111 = "OP_DARN" *) + (* enum_value_0011000 = "OP_DCBF" *) + (* enum_value_0011001 = "OP_DCBST" *) + (* enum_value_0011010 = "OP_DCBT" *) + (* enum_value_0011011 = "OP_DCBTST" *) + (* enum_value_0011100 = "OP_DCBZ" *) + (* enum_value_0011101 = "OP_DIV" *) + (* enum_value_0011110 = "OP_DIVE" *) + (* enum_value_0011111 = "OP_EXTS" *) + (* enum_value_0100000 = "OP_EXTSWSLI" *) + (* enum_value_0100001 = "OP_ICBI" *) + (* enum_value_0100010 = "OP_ICBT" *) + (* enum_value_0100011 = "OP_ISEL" *) + (* enum_value_0100100 = "OP_ISYNC" *) + (* enum_value_0100101 = "OP_LOAD" *) + (* enum_value_0100110 = "OP_STORE" *) + (* enum_value_0100111 = "OP_MADDHD" *) + (* enum_value_0101000 = "OP_MADDHDU" *) + (* enum_value_0101001 = "OP_MADDLD" *) + (* enum_value_0101010 = "OP_MCRF" *) + (* enum_value_0101011 = "OP_MCRXR" *) + (* enum_value_0101100 = "OP_MCRXRX" *) + (* enum_value_0101101 = "OP_MFCR" *) + (* enum_value_0101110 = "OP_MFSPR" *) + (* enum_value_0101111 = "OP_MOD" *) + (* enum_value_0110000 = "OP_MTCRF" *) + (* enum_value_0110001 = "OP_MTSPR" *) + (* enum_value_0110010 = "OP_MUL_L64" *) + (* enum_value_0110011 = "OP_MUL_H64" *) + (* enum_value_0110100 = "OP_MUL_H32" *) + (* enum_value_0110101 = "OP_OR" *) + (* enum_value_0110110 = "OP_POPCNT" *) + (* enum_value_0110111 = "OP_PRTY" *) + (* enum_value_0111000 = "OP_RLC" *) + (* enum_value_0111001 = "OP_RLCL" *) + (* enum_value_0111010 = "OP_RLCR" *) + (* enum_value_0111011 = "OP_SETB" *) + (* enum_value_0111100 = "OP_SHL" *) + (* enum_value_0111101 = "OP_SHR" *) + (* enum_value_0111110 = "OP_SYNC" *) + (* enum_value_0111111 = "OP_TRAP" *) + (* enum_value_1000011 = "OP_XOR" *) + (* enum_value_1000100 = "OP_SIM_CONFIG" *) + (* enum_value_1000101 = "OP_CROP" *) + (* enum_value_1000110 = "OP_RFID" *) + (* enum_value_1000111 = "OP_MFMSR" *) + (* enum_value_1001000 = "OP_MTMSRD" *) + (* enum_value_1001001 = "OP_SC" *) + (* enum_value_1001010 = "OP_MTMSR" *) + (* enum_value_1001011 = "OP_TLBIE" *) + (* enum_value_1001100 = "OP_SETVL" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec31_dec_sub9_dec31_dec_sub9_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub9_dec31_dec_sub9_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub9_dec31_dec_sub9_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub9_dec31_dec_sub9_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -86826,9 +94402,9 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec31_dec_sub9_dec31_dec_sub9_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub9_dec31_dec_sub9_lk; (* enum_base_type = "OutSel" *) (* enum_value_000 = "NONE" *) @@ -86836,21 +94412,22 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub9_dec31_dec_sub9_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub9_dec31_dec_sub9_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub9_dec31_dec_sub9_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub9_dec31_dec_sub9_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub9_dec31_dec_sub9_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec31_dec_sub9_dec31_dec_sub9_sgn_ext; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -86859,7 +94436,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub9_dec31_dec_sub9_sv_cr_in; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -86868,7 +94445,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub9_dec31_dec_sub9_sv_cr_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -86877,7 +94454,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub9_dec31_dec_sub9_sv_in1; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -86886,7 +94463,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub9_dec31_dec_sub9_sv_in2; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -86895,7 +94472,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub9_dec31_dec_sub9_sv_in3; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -86904,7 +94481,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub9_dec31_dec_sub9_sv_out; (* enum_base_type = "SVEXTRA" *) (* enum_value_000 = "NONE" *) @@ -86913,16 +94490,16 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec31_dec_sub9_dec31_dec_sub9_sv_out2; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec31_dec_sub9_dec31_dec_sub9_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] dec31_dec_sub9_opcode_in; (* enum_base_type = "Form" *) (* enum_value_00000 = "NONE" *) @@ -86955,34 +94532,37 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_form; reg [4:0] dec31_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] dec31_function_unit; - reg [13:0] dec31_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] dec31_function_unit; + reg [14:0] dec31_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_in1_sel; reg [2:0] dec31_in1_sel; (* enum_base_type = "In2Sel" *) @@ -87000,16 +94580,19 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_in2_sel; reg [3:0] dec31_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [1:0] dec31_in3_sel; - reg [1:0] dec31_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [2:0] dec31_in3_sel; + reg [2:0] dec31_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -87085,16 +94668,18 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_internal_op; reg [6:0] dec31_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_inv_a; reg dec31_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_inv_out; reg dec31_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_is_32b; reg dec31_is_32b; (* enum_base_type = "LdstLen" *) @@ -87103,10 +94688,10 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_ldst_len; reg [3:0] dec31_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_lk; reg dec31_lk; (* enum_base_type = "OutSel" *) @@ -87115,26 +94700,27 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_out_sel; reg [2:0] dec31_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_rc_sel; reg [1:0] dec31_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_rsrv; reg dec31_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_sgl_pipe; reg dec31_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_sgn; reg dec31_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_sgn_ext; reg dec31_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -87144,7 +94730,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_sv_cr_in; reg [2:0] dec31_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -87154,7 +94740,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_sv_cr_out; reg [2:0] dec31_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -87164,7 +94750,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_sv_in1; reg [2:0] dec31_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -87174,7 +94760,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_sv_in2; reg [2:0] dec31_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -87184,7 +94770,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_sv_in3; reg [2:0] dec31_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -87194,7 +94780,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_sv_out; reg [2:0] dec31_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -87204,7 +94790,7 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_sv_out2; reg [2:0] dec31_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -87212,14 +94798,14 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_upd; reg [1:0] dec31_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:355" *) wire [4:0] opc_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [9:0] opcode_switch; dec31_dec_sub0 dec31_dec_sub0 ( .dec31_dec_sub0_SV_Etype(dec31_dec_sub0_dec31_dec_sub0_SV_Etype), @@ -87871,61 +95457,61 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, ); always @* begin if (\initial ) begin end - dec31_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_function_unit = dec31_dec_sub10_dec31_dec_sub10_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_function_unit = dec31_dec_sub28_dec31_dec_sub28_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_function_unit = dec31_dec_sub0_dec31_dec_sub0_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_function_unit = dec31_dec_sub26_dec31_dec_sub26_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_function_unit = dec31_dec_sub19_dec31_dec_sub19_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_function_unit = dec31_dec_sub22_dec31_dec_sub22_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_function_unit = dec31_dec_sub9_dec31_dec_sub9_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_function_unit = dec31_dec_sub11_dec31_dec_sub11_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_function_unit = dec31_dec_sub27_dec31_dec_sub27_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_function_unit = dec31_dec_sub15_dec31_dec_sub15_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_function_unit = dec31_dec_sub20_dec31_dec_sub20_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_function_unit = dec31_dec_sub21_dec31_dec_sub21_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_function_unit = dec31_dec_sub23_dec31_dec_sub23_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_function_unit = dec31_dec_sub16_dec31_dec_sub16_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_function_unit = dec31_dec_sub18_dec31_dec_sub18_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_function_unit = dec31_dec_sub8_dec31_dec_sub8_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_function_unit = dec31_dec_sub24_dec31_dec_sub24_function_unit; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_function_unit = dec31_dec_sub4_dec31_dec_sub4_function_unit; endcase @@ -87933,60 +95519,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_internal_op = dec31_dec_sub10_dec31_dec_sub10_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_internal_op = dec31_dec_sub28_dec31_dec_sub28_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_internal_op = dec31_dec_sub0_dec31_dec_sub0_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_internal_op = dec31_dec_sub26_dec31_dec_sub26_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_internal_op = dec31_dec_sub19_dec31_dec_sub19_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_internal_op = dec31_dec_sub22_dec31_dec_sub22_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_internal_op = dec31_dec_sub9_dec31_dec_sub9_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_internal_op = dec31_dec_sub11_dec31_dec_sub11_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_internal_op = dec31_dec_sub27_dec31_dec_sub27_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_internal_op = dec31_dec_sub15_dec31_dec_sub15_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_internal_op = dec31_dec_sub20_dec31_dec_sub20_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_internal_op = dec31_dec_sub21_dec31_dec_sub21_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_internal_op = dec31_dec_sub23_dec31_dec_sub23_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_internal_op = dec31_dec_sub16_dec31_dec_sub16_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_internal_op = dec31_dec_sub18_dec31_dec_sub18_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_internal_op = dec31_dec_sub8_dec31_dec_sub8_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_internal_op = dec31_dec_sub24_dec31_dec_sub24_internal_op; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_internal_op = dec31_dec_sub4_dec31_dec_sub4_internal_op; endcase @@ -87994,60 +95580,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_form = dec31_dec_sub10_dec31_dec_sub10_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_form = dec31_dec_sub28_dec31_dec_sub28_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_form = dec31_dec_sub0_dec31_dec_sub0_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_form = dec31_dec_sub26_dec31_dec_sub26_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_form = dec31_dec_sub19_dec31_dec_sub19_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_form = dec31_dec_sub22_dec31_dec_sub22_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_form = dec31_dec_sub9_dec31_dec_sub9_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_form = dec31_dec_sub11_dec31_dec_sub11_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_form = dec31_dec_sub27_dec31_dec_sub27_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_form = dec31_dec_sub15_dec31_dec_sub15_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_form = dec31_dec_sub20_dec31_dec_sub20_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_form = dec31_dec_sub21_dec31_dec_sub21_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_form = dec31_dec_sub23_dec31_dec_sub23_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_form = dec31_dec_sub16_dec31_dec_sub16_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_form = dec31_dec_sub18_dec31_dec_sub18_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_form = dec31_dec_sub8_dec31_dec_sub8_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_form = dec31_dec_sub24_dec31_dec_sub24_form; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_form = dec31_dec_sub4_dec31_dec_sub4_form; endcase @@ -88055,60 +95641,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_asmcode = dec31_dec_sub10_dec31_dec_sub10_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_asmcode = dec31_dec_sub28_dec31_dec_sub28_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_asmcode = dec31_dec_sub0_dec31_dec_sub0_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_asmcode = dec31_dec_sub26_dec31_dec_sub26_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_asmcode = dec31_dec_sub19_dec31_dec_sub19_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_asmcode = dec31_dec_sub22_dec31_dec_sub22_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_asmcode = dec31_dec_sub9_dec31_dec_sub9_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_asmcode = dec31_dec_sub11_dec31_dec_sub11_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_asmcode = dec31_dec_sub27_dec31_dec_sub27_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_asmcode = dec31_dec_sub15_dec31_dec_sub15_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_asmcode = dec31_dec_sub20_dec31_dec_sub20_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_asmcode = dec31_dec_sub21_dec31_dec_sub21_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_asmcode = dec31_dec_sub23_dec31_dec_sub23_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_asmcode = dec31_dec_sub16_dec31_dec_sub16_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_asmcode = dec31_dec_sub18_dec31_dec_sub18_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_asmcode = dec31_dec_sub8_dec31_dec_sub8_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_asmcode = dec31_dec_sub24_dec31_dec_sub24_asmcode; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_asmcode = dec31_dec_sub4_dec31_dec_sub4_asmcode; endcase @@ -88116,60 +95702,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_SV_Etype = dec31_dec_sub10_dec31_dec_sub10_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_SV_Etype = dec31_dec_sub28_dec31_dec_sub28_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_SV_Etype = dec31_dec_sub0_dec31_dec_sub0_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_SV_Etype = dec31_dec_sub26_dec31_dec_sub26_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_SV_Etype = dec31_dec_sub19_dec31_dec_sub19_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_SV_Etype = dec31_dec_sub22_dec31_dec_sub22_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_SV_Etype = dec31_dec_sub9_dec31_dec_sub9_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_SV_Etype = dec31_dec_sub11_dec31_dec_sub11_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_SV_Etype = dec31_dec_sub27_dec31_dec_sub27_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_SV_Etype = dec31_dec_sub15_dec31_dec_sub15_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_SV_Etype = dec31_dec_sub20_dec31_dec_sub20_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_SV_Etype = dec31_dec_sub21_dec31_dec_sub21_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_SV_Etype = dec31_dec_sub23_dec31_dec_sub23_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_SV_Etype = dec31_dec_sub16_dec31_dec_sub16_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_SV_Etype = dec31_dec_sub18_dec31_dec_sub18_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_SV_Etype = dec31_dec_sub8_dec31_dec_sub8_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_SV_Etype = dec31_dec_sub24_dec31_dec_sub24_SV_Etype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_SV_Etype = dec31_dec_sub4_dec31_dec_sub4_SV_Etype; endcase @@ -88177,60 +95763,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_SV_Ptype = dec31_dec_sub10_dec31_dec_sub10_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_SV_Ptype = dec31_dec_sub28_dec31_dec_sub28_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_SV_Ptype = dec31_dec_sub0_dec31_dec_sub0_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_SV_Ptype = dec31_dec_sub26_dec31_dec_sub26_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_SV_Ptype = dec31_dec_sub19_dec31_dec_sub19_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_SV_Ptype = dec31_dec_sub22_dec31_dec_sub22_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_SV_Ptype = dec31_dec_sub9_dec31_dec_sub9_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_SV_Ptype = dec31_dec_sub11_dec31_dec_sub11_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_SV_Ptype = dec31_dec_sub27_dec31_dec_sub27_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_SV_Ptype = dec31_dec_sub15_dec31_dec_sub15_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_SV_Ptype = dec31_dec_sub20_dec31_dec_sub20_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_SV_Ptype = dec31_dec_sub21_dec31_dec_sub21_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_SV_Ptype = dec31_dec_sub23_dec31_dec_sub23_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_SV_Ptype = dec31_dec_sub16_dec31_dec_sub16_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_SV_Ptype = dec31_dec_sub18_dec31_dec_sub18_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_SV_Ptype = dec31_dec_sub8_dec31_dec_sub8_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_SV_Ptype = dec31_dec_sub24_dec31_dec_sub24_SV_Ptype; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_SV_Ptype = dec31_dec_sub4_dec31_dec_sub4_SV_Ptype; endcase @@ -88238,60 +95824,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_in1_sel = dec31_dec_sub10_dec31_dec_sub10_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_in1_sel = dec31_dec_sub28_dec31_dec_sub28_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_in1_sel = dec31_dec_sub0_dec31_dec_sub0_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_in1_sel = dec31_dec_sub26_dec31_dec_sub26_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_in1_sel = dec31_dec_sub19_dec31_dec_sub19_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_in1_sel = dec31_dec_sub22_dec31_dec_sub22_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_in1_sel = dec31_dec_sub9_dec31_dec_sub9_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_in1_sel = dec31_dec_sub11_dec31_dec_sub11_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_in1_sel = dec31_dec_sub27_dec31_dec_sub27_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_in1_sel = dec31_dec_sub15_dec31_dec_sub15_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_in1_sel = dec31_dec_sub20_dec31_dec_sub20_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_in1_sel = dec31_dec_sub21_dec31_dec_sub21_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_in1_sel = dec31_dec_sub23_dec31_dec_sub23_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_in1_sel = dec31_dec_sub16_dec31_dec_sub16_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_in1_sel = dec31_dec_sub18_dec31_dec_sub18_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_in1_sel = dec31_dec_sub8_dec31_dec_sub8_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_in1_sel = dec31_dec_sub24_dec31_dec_sub24_in1_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_in1_sel = dec31_dec_sub4_dec31_dec_sub4_in1_sel; endcase @@ -88299,121 +95885,121 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_in2_sel = dec31_dec_sub10_dec31_dec_sub10_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_in2_sel = dec31_dec_sub28_dec31_dec_sub28_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_in2_sel = dec31_dec_sub0_dec31_dec_sub0_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_in2_sel = dec31_dec_sub26_dec31_dec_sub26_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_in2_sel = dec31_dec_sub19_dec31_dec_sub19_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_in2_sel = dec31_dec_sub22_dec31_dec_sub22_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_in2_sel = dec31_dec_sub9_dec31_dec_sub9_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_in2_sel = dec31_dec_sub11_dec31_dec_sub11_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_in2_sel = dec31_dec_sub27_dec31_dec_sub27_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_in2_sel = dec31_dec_sub15_dec31_dec_sub15_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_in2_sel = dec31_dec_sub20_dec31_dec_sub20_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_in2_sel = dec31_dec_sub21_dec31_dec_sub21_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_in2_sel = dec31_dec_sub23_dec31_dec_sub23_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_in2_sel = dec31_dec_sub16_dec31_dec_sub16_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_in2_sel = dec31_dec_sub18_dec31_dec_sub18_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_in2_sel = dec31_dec_sub8_dec31_dec_sub8_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_in2_sel = dec31_dec_sub24_dec31_dec_sub24_in2_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_in2_sel = dec31_dec_sub4_dec31_dec_sub4_in2_sel; endcase end always @* begin if (\initial ) begin end - dec31_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_in3_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_in3_sel = dec31_dec_sub10_dec31_dec_sub10_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_in3_sel = dec31_dec_sub28_dec31_dec_sub28_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_in3_sel = dec31_dec_sub0_dec31_dec_sub0_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_in3_sel = dec31_dec_sub26_dec31_dec_sub26_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_in3_sel = dec31_dec_sub19_dec31_dec_sub19_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_in3_sel = dec31_dec_sub22_dec31_dec_sub22_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_in3_sel = dec31_dec_sub9_dec31_dec_sub9_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_in3_sel = dec31_dec_sub11_dec31_dec_sub11_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_in3_sel = dec31_dec_sub27_dec31_dec_sub27_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_in3_sel = dec31_dec_sub15_dec31_dec_sub15_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_in3_sel = dec31_dec_sub20_dec31_dec_sub20_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_in3_sel = dec31_dec_sub21_dec31_dec_sub21_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_in3_sel = dec31_dec_sub23_dec31_dec_sub23_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_in3_sel = dec31_dec_sub16_dec31_dec_sub16_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_in3_sel = dec31_dec_sub18_dec31_dec_sub18_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_in3_sel = dec31_dec_sub8_dec31_dec_sub8_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_in3_sel = dec31_dec_sub24_dec31_dec_sub24_in3_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_in3_sel = dec31_dec_sub4_dec31_dec_sub4_in3_sel; endcase @@ -88421,60 +96007,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_out_sel = dec31_dec_sub10_dec31_dec_sub10_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_out_sel = dec31_dec_sub28_dec31_dec_sub28_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_out_sel = dec31_dec_sub0_dec31_dec_sub0_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_out_sel = dec31_dec_sub26_dec31_dec_sub26_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_out_sel = dec31_dec_sub19_dec31_dec_sub19_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_out_sel = dec31_dec_sub22_dec31_dec_sub22_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_out_sel = dec31_dec_sub9_dec31_dec_sub9_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_out_sel = dec31_dec_sub11_dec31_dec_sub11_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_out_sel = dec31_dec_sub27_dec31_dec_sub27_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_out_sel = dec31_dec_sub15_dec31_dec_sub15_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_out_sel = dec31_dec_sub20_dec31_dec_sub20_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_out_sel = dec31_dec_sub21_dec31_dec_sub21_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_out_sel = dec31_dec_sub23_dec31_dec_sub23_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_out_sel = dec31_dec_sub16_dec31_dec_sub16_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_out_sel = dec31_dec_sub18_dec31_dec_sub18_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_out_sel = dec31_dec_sub8_dec31_dec_sub8_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_out_sel = dec31_dec_sub24_dec31_dec_sub24_out_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_out_sel = dec31_dec_sub4_dec31_dec_sub4_out_sel; endcase @@ -88482,60 +96068,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_cr_in = dec31_dec_sub10_dec31_dec_sub10_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_cr_in = dec31_dec_sub28_dec31_dec_sub28_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_cr_in = dec31_dec_sub0_dec31_dec_sub0_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_cr_in = dec31_dec_sub26_dec31_dec_sub26_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_cr_in = dec31_dec_sub19_dec31_dec_sub19_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_cr_in = dec31_dec_sub22_dec31_dec_sub22_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_cr_in = dec31_dec_sub9_dec31_dec_sub9_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_cr_in = dec31_dec_sub11_dec31_dec_sub11_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_cr_in = dec31_dec_sub27_dec31_dec_sub27_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_cr_in = dec31_dec_sub15_dec31_dec_sub15_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_cr_in = dec31_dec_sub20_dec31_dec_sub20_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_cr_in = dec31_dec_sub21_dec31_dec_sub21_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_cr_in = dec31_dec_sub23_dec31_dec_sub23_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_cr_in = dec31_dec_sub16_dec31_dec_sub16_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_cr_in = dec31_dec_sub18_dec31_dec_sub18_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_cr_in = dec31_dec_sub8_dec31_dec_sub8_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_cr_in = dec31_dec_sub24_dec31_dec_sub24_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_cr_in = dec31_dec_sub4_dec31_dec_sub4_cr_in; endcase @@ -88543,60 +96129,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_cr_out = dec31_dec_sub10_dec31_dec_sub10_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_cr_out = dec31_dec_sub28_dec31_dec_sub28_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_cr_out = dec31_dec_sub0_dec31_dec_sub0_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_cr_out = dec31_dec_sub26_dec31_dec_sub26_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_cr_out = dec31_dec_sub19_dec31_dec_sub19_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_cr_out = dec31_dec_sub22_dec31_dec_sub22_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_cr_out = dec31_dec_sub9_dec31_dec_sub9_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_cr_out = dec31_dec_sub11_dec31_dec_sub11_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_cr_out = dec31_dec_sub27_dec31_dec_sub27_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_cr_out = dec31_dec_sub15_dec31_dec_sub15_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_cr_out = dec31_dec_sub20_dec31_dec_sub20_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_cr_out = dec31_dec_sub21_dec31_dec_sub21_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_cr_out = dec31_dec_sub23_dec31_dec_sub23_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_cr_out = dec31_dec_sub16_dec31_dec_sub16_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_cr_out = dec31_dec_sub18_dec31_dec_sub18_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_cr_out = dec31_dec_sub8_dec31_dec_sub8_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_cr_out = dec31_dec_sub24_dec31_dec_sub24_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_cr_out = dec31_dec_sub4_dec31_dec_sub4_cr_out; endcase @@ -88604,60 +96190,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_sv_in1 = dec31_dec_sub10_dec31_dec_sub10_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_sv_in1 = dec31_dec_sub28_dec31_dec_sub28_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_sv_in1 = dec31_dec_sub0_dec31_dec_sub0_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_sv_in1 = dec31_dec_sub26_dec31_dec_sub26_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_sv_in1 = dec31_dec_sub19_dec31_dec_sub19_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_sv_in1 = dec31_dec_sub22_dec31_dec_sub22_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_sv_in1 = dec31_dec_sub9_dec31_dec_sub9_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_sv_in1 = dec31_dec_sub11_dec31_dec_sub11_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_sv_in1 = dec31_dec_sub27_dec31_dec_sub27_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_sv_in1 = dec31_dec_sub15_dec31_dec_sub15_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_sv_in1 = dec31_dec_sub20_dec31_dec_sub20_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_sv_in1 = dec31_dec_sub21_dec31_dec_sub21_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_sv_in1 = dec31_dec_sub23_dec31_dec_sub23_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_sv_in1 = dec31_dec_sub16_dec31_dec_sub16_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_sv_in1 = dec31_dec_sub18_dec31_dec_sub18_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_sv_in1 = dec31_dec_sub8_dec31_dec_sub8_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_sv_in1 = dec31_dec_sub24_dec31_dec_sub24_sv_in1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_sv_in1 = dec31_dec_sub4_dec31_dec_sub4_sv_in1; endcase @@ -88665,60 +96251,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_sv_in2 = dec31_dec_sub10_dec31_dec_sub10_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_sv_in2 = dec31_dec_sub28_dec31_dec_sub28_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_sv_in2 = dec31_dec_sub0_dec31_dec_sub0_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_sv_in2 = dec31_dec_sub26_dec31_dec_sub26_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_sv_in2 = dec31_dec_sub19_dec31_dec_sub19_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_sv_in2 = dec31_dec_sub22_dec31_dec_sub22_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_sv_in2 = dec31_dec_sub9_dec31_dec_sub9_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_sv_in2 = dec31_dec_sub11_dec31_dec_sub11_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_sv_in2 = dec31_dec_sub27_dec31_dec_sub27_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_sv_in2 = dec31_dec_sub15_dec31_dec_sub15_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_sv_in2 = dec31_dec_sub20_dec31_dec_sub20_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_sv_in2 = dec31_dec_sub21_dec31_dec_sub21_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_sv_in2 = dec31_dec_sub23_dec31_dec_sub23_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_sv_in2 = dec31_dec_sub16_dec31_dec_sub16_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_sv_in2 = dec31_dec_sub18_dec31_dec_sub18_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_sv_in2 = dec31_dec_sub8_dec31_dec_sub8_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_sv_in2 = dec31_dec_sub24_dec31_dec_sub24_sv_in2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_sv_in2 = dec31_dec_sub4_dec31_dec_sub4_sv_in2; endcase @@ -88726,60 +96312,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_sv_in3 = dec31_dec_sub10_dec31_dec_sub10_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_sv_in3 = dec31_dec_sub28_dec31_dec_sub28_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_sv_in3 = dec31_dec_sub0_dec31_dec_sub0_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_sv_in3 = dec31_dec_sub26_dec31_dec_sub26_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_sv_in3 = dec31_dec_sub19_dec31_dec_sub19_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_sv_in3 = dec31_dec_sub22_dec31_dec_sub22_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_sv_in3 = dec31_dec_sub9_dec31_dec_sub9_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_sv_in3 = dec31_dec_sub11_dec31_dec_sub11_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_sv_in3 = dec31_dec_sub27_dec31_dec_sub27_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_sv_in3 = dec31_dec_sub15_dec31_dec_sub15_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_sv_in3 = dec31_dec_sub20_dec31_dec_sub20_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_sv_in3 = dec31_dec_sub21_dec31_dec_sub21_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_sv_in3 = dec31_dec_sub23_dec31_dec_sub23_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_sv_in3 = dec31_dec_sub16_dec31_dec_sub16_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_sv_in3 = dec31_dec_sub18_dec31_dec_sub18_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_sv_in3 = dec31_dec_sub8_dec31_dec_sub8_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_sv_in3 = dec31_dec_sub24_dec31_dec_sub24_sv_in3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_sv_in3 = dec31_dec_sub4_dec31_dec_sub4_sv_in3; endcase @@ -88787,60 +96373,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_sv_out = dec31_dec_sub10_dec31_dec_sub10_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_sv_out = dec31_dec_sub28_dec31_dec_sub28_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_sv_out = dec31_dec_sub0_dec31_dec_sub0_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_sv_out = dec31_dec_sub26_dec31_dec_sub26_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_sv_out = dec31_dec_sub19_dec31_dec_sub19_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_sv_out = dec31_dec_sub22_dec31_dec_sub22_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_sv_out = dec31_dec_sub9_dec31_dec_sub9_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_sv_out = dec31_dec_sub11_dec31_dec_sub11_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_sv_out = dec31_dec_sub27_dec31_dec_sub27_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_sv_out = dec31_dec_sub15_dec31_dec_sub15_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_sv_out = dec31_dec_sub20_dec31_dec_sub20_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_sv_out = dec31_dec_sub21_dec31_dec_sub21_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_sv_out = dec31_dec_sub23_dec31_dec_sub23_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_sv_out = dec31_dec_sub16_dec31_dec_sub16_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_sv_out = dec31_dec_sub18_dec31_dec_sub18_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_sv_out = dec31_dec_sub8_dec31_dec_sub8_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_sv_out = dec31_dec_sub24_dec31_dec_sub24_sv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_sv_out = dec31_dec_sub4_dec31_dec_sub4_sv_out; endcase @@ -88848,60 +96434,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_sv_out2 = dec31_dec_sub10_dec31_dec_sub10_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_sv_out2 = dec31_dec_sub28_dec31_dec_sub28_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_sv_out2 = dec31_dec_sub0_dec31_dec_sub0_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_sv_out2 = dec31_dec_sub26_dec31_dec_sub26_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_sv_out2 = dec31_dec_sub19_dec31_dec_sub19_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_sv_out2 = dec31_dec_sub22_dec31_dec_sub22_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_sv_out2 = dec31_dec_sub9_dec31_dec_sub9_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_sv_out2 = dec31_dec_sub11_dec31_dec_sub11_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_sv_out2 = dec31_dec_sub27_dec31_dec_sub27_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_sv_out2 = dec31_dec_sub15_dec31_dec_sub15_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_sv_out2 = dec31_dec_sub20_dec31_dec_sub20_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_sv_out2 = dec31_dec_sub21_dec31_dec_sub21_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_sv_out2 = dec31_dec_sub23_dec31_dec_sub23_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_sv_out2 = dec31_dec_sub16_dec31_dec_sub16_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_sv_out2 = dec31_dec_sub18_dec31_dec_sub18_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_sv_out2 = dec31_dec_sub8_dec31_dec_sub8_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_sv_out2 = dec31_dec_sub24_dec31_dec_sub24_sv_out2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_sv_out2 = dec31_dec_sub4_dec31_dec_sub4_sv_out2; endcase @@ -88909,60 +96495,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_sv_cr_in = dec31_dec_sub10_dec31_dec_sub10_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_sv_cr_in = dec31_dec_sub28_dec31_dec_sub28_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_sv_cr_in = dec31_dec_sub0_dec31_dec_sub0_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_sv_cr_in = dec31_dec_sub26_dec31_dec_sub26_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_sv_cr_in = dec31_dec_sub19_dec31_dec_sub19_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_sv_cr_in = dec31_dec_sub22_dec31_dec_sub22_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_sv_cr_in = dec31_dec_sub9_dec31_dec_sub9_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_sv_cr_in = dec31_dec_sub11_dec31_dec_sub11_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_sv_cr_in = dec31_dec_sub27_dec31_dec_sub27_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_sv_cr_in = dec31_dec_sub15_dec31_dec_sub15_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_sv_cr_in = dec31_dec_sub20_dec31_dec_sub20_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_sv_cr_in = dec31_dec_sub21_dec31_dec_sub21_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_sv_cr_in = dec31_dec_sub23_dec31_dec_sub23_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_sv_cr_in = dec31_dec_sub16_dec31_dec_sub16_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_sv_cr_in = dec31_dec_sub18_dec31_dec_sub18_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_sv_cr_in = dec31_dec_sub8_dec31_dec_sub8_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_sv_cr_in = dec31_dec_sub24_dec31_dec_sub24_sv_cr_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_sv_cr_in = dec31_dec_sub4_dec31_dec_sub4_sv_cr_in; endcase @@ -88970,60 +96556,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_sv_cr_out = dec31_dec_sub10_dec31_dec_sub10_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_sv_cr_out = dec31_dec_sub28_dec31_dec_sub28_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_sv_cr_out = dec31_dec_sub0_dec31_dec_sub0_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_sv_cr_out = dec31_dec_sub26_dec31_dec_sub26_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_sv_cr_out = dec31_dec_sub19_dec31_dec_sub19_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_sv_cr_out = dec31_dec_sub22_dec31_dec_sub22_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_sv_cr_out = dec31_dec_sub9_dec31_dec_sub9_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_sv_cr_out = dec31_dec_sub11_dec31_dec_sub11_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_sv_cr_out = dec31_dec_sub27_dec31_dec_sub27_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_sv_cr_out = dec31_dec_sub15_dec31_dec_sub15_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_sv_cr_out = dec31_dec_sub20_dec31_dec_sub20_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_sv_cr_out = dec31_dec_sub21_dec31_dec_sub21_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_sv_cr_out = dec31_dec_sub23_dec31_dec_sub23_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_sv_cr_out = dec31_dec_sub16_dec31_dec_sub16_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_sv_cr_out = dec31_dec_sub18_dec31_dec_sub18_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_sv_cr_out = dec31_dec_sub8_dec31_dec_sub8_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_sv_cr_out = dec31_dec_sub24_dec31_dec_sub24_sv_cr_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_sv_cr_out = dec31_dec_sub4_dec31_dec_sub4_sv_cr_out; endcase @@ -89031,60 +96617,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_ldst_len = dec31_dec_sub10_dec31_dec_sub10_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_ldst_len = dec31_dec_sub28_dec31_dec_sub28_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_ldst_len = dec31_dec_sub0_dec31_dec_sub0_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_ldst_len = dec31_dec_sub26_dec31_dec_sub26_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_ldst_len = dec31_dec_sub19_dec31_dec_sub19_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_ldst_len = dec31_dec_sub22_dec31_dec_sub22_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_ldst_len = dec31_dec_sub9_dec31_dec_sub9_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_ldst_len = dec31_dec_sub11_dec31_dec_sub11_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_ldst_len = dec31_dec_sub27_dec31_dec_sub27_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_ldst_len = dec31_dec_sub15_dec31_dec_sub15_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_ldst_len = dec31_dec_sub20_dec31_dec_sub20_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_ldst_len = dec31_dec_sub21_dec31_dec_sub21_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_ldst_len = dec31_dec_sub23_dec31_dec_sub23_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_ldst_len = dec31_dec_sub16_dec31_dec_sub16_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_ldst_len = dec31_dec_sub18_dec31_dec_sub18_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_ldst_len = dec31_dec_sub8_dec31_dec_sub8_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_ldst_len = dec31_dec_sub24_dec31_dec_sub24_ldst_len; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_ldst_len = dec31_dec_sub4_dec31_dec_sub4_ldst_len; endcase @@ -89092,60 +96678,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_upd = dec31_dec_sub10_dec31_dec_sub10_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_upd = dec31_dec_sub28_dec31_dec_sub28_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_upd = dec31_dec_sub0_dec31_dec_sub0_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_upd = dec31_dec_sub26_dec31_dec_sub26_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_upd = dec31_dec_sub19_dec31_dec_sub19_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_upd = dec31_dec_sub22_dec31_dec_sub22_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_upd = dec31_dec_sub9_dec31_dec_sub9_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_upd = dec31_dec_sub11_dec31_dec_sub11_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_upd = dec31_dec_sub27_dec31_dec_sub27_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_upd = dec31_dec_sub15_dec31_dec_sub15_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_upd = dec31_dec_sub20_dec31_dec_sub20_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_upd = dec31_dec_sub21_dec31_dec_sub21_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_upd = dec31_dec_sub23_dec31_dec_sub23_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_upd = dec31_dec_sub16_dec31_dec_sub16_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_upd = dec31_dec_sub18_dec31_dec_sub18_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_upd = dec31_dec_sub8_dec31_dec_sub8_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_upd = dec31_dec_sub24_dec31_dec_sub24_upd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_upd = dec31_dec_sub4_dec31_dec_sub4_upd; endcase @@ -89153,60 +96739,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_rc_sel = dec31_dec_sub10_dec31_dec_sub10_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_rc_sel = dec31_dec_sub28_dec31_dec_sub28_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_rc_sel = dec31_dec_sub0_dec31_dec_sub0_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_rc_sel = dec31_dec_sub26_dec31_dec_sub26_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_rc_sel = dec31_dec_sub19_dec31_dec_sub19_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_rc_sel = dec31_dec_sub22_dec31_dec_sub22_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_rc_sel = dec31_dec_sub9_dec31_dec_sub9_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_rc_sel = dec31_dec_sub11_dec31_dec_sub11_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_rc_sel = dec31_dec_sub27_dec31_dec_sub27_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_rc_sel = dec31_dec_sub15_dec31_dec_sub15_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_rc_sel = dec31_dec_sub20_dec31_dec_sub20_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_rc_sel = dec31_dec_sub21_dec31_dec_sub21_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_rc_sel = dec31_dec_sub23_dec31_dec_sub23_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_rc_sel = dec31_dec_sub16_dec31_dec_sub16_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_rc_sel = dec31_dec_sub18_dec31_dec_sub18_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_rc_sel = dec31_dec_sub8_dec31_dec_sub8_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_rc_sel = dec31_dec_sub24_dec31_dec_sub24_rc_sel; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_rc_sel = dec31_dec_sub4_dec31_dec_sub4_rc_sel; endcase @@ -89214,60 +96800,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_cry_in = dec31_dec_sub10_dec31_dec_sub10_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_cry_in = dec31_dec_sub28_dec31_dec_sub28_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_cry_in = dec31_dec_sub0_dec31_dec_sub0_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_cry_in = dec31_dec_sub26_dec31_dec_sub26_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_cry_in = dec31_dec_sub19_dec31_dec_sub19_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_cry_in = dec31_dec_sub22_dec31_dec_sub22_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_cry_in = dec31_dec_sub9_dec31_dec_sub9_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_cry_in = dec31_dec_sub11_dec31_dec_sub11_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_cry_in = dec31_dec_sub27_dec31_dec_sub27_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_cry_in = dec31_dec_sub15_dec31_dec_sub15_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_cry_in = dec31_dec_sub20_dec31_dec_sub20_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_cry_in = dec31_dec_sub21_dec31_dec_sub21_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_cry_in = dec31_dec_sub23_dec31_dec_sub23_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_cry_in = dec31_dec_sub16_dec31_dec_sub16_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_cry_in = dec31_dec_sub18_dec31_dec_sub18_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_cry_in = dec31_dec_sub8_dec31_dec_sub8_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_cry_in = dec31_dec_sub24_dec31_dec_sub24_cry_in; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_cry_in = dec31_dec_sub4_dec31_dec_sub4_cry_in; endcase @@ -89275,60 +96861,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_inv_a = dec31_dec_sub10_dec31_dec_sub10_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_inv_a = dec31_dec_sub28_dec31_dec_sub28_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_inv_a = dec31_dec_sub0_dec31_dec_sub0_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_inv_a = dec31_dec_sub26_dec31_dec_sub26_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_inv_a = dec31_dec_sub19_dec31_dec_sub19_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_inv_a = dec31_dec_sub22_dec31_dec_sub22_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_inv_a = dec31_dec_sub9_dec31_dec_sub9_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_inv_a = dec31_dec_sub11_dec31_dec_sub11_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_inv_a = dec31_dec_sub27_dec31_dec_sub27_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_inv_a = dec31_dec_sub15_dec31_dec_sub15_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_inv_a = dec31_dec_sub20_dec31_dec_sub20_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_inv_a = dec31_dec_sub21_dec31_dec_sub21_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_inv_a = dec31_dec_sub23_dec31_dec_sub23_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_inv_a = dec31_dec_sub16_dec31_dec_sub16_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_inv_a = dec31_dec_sub18_dec31_dec_sub18_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_inv_a = dec31_dec_sub8_dec31_dec_sub8_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_inv_a = dec31_dec_sub24_dec31_dec_sub24_inv_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_inv_a = dec31_dec_sub4_dec31_dec_sub4_inv_a; endcase @@ -89336,60 +96922,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_inv_out = dec31_dec_sub10_dec31_dec_sub10_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_inv_out = dec31_dec_sub28_dec31_dec_sub28_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_inv_out = dec31_dec_sub0_dec31_dec_sub0_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_inv_out = dec31_dec_sub26_dec31_dec_sub26_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_inv_out = dec31_dec_sub19_dec31_dec_sub19_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_inv_out = dec31_dec_sub22_dec31_dec_sub22_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_inv_out = dec31_dec_sub9_dec31_dec_sub9_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_inv_out = dec31_dec_sub11_dec31_dec_sub11_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_inv_out = dec31_dec_sub27_dec31_dec_sub27_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_inv_out = dec31_dec_sub15_dec31_dec_sub15_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_inv_out = dec31_dec_sub20_dec31_dec_sub20_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_inv_out = dec31_dec_sub21_dec31_dec_sub21_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_inv_out = dec31_dec_sub23_dec31_dec_sub23_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_inv_out = dec31_dec_sub16_dec31_dec_sub16_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_inv_out = dec31_dec_sub18_dec31_dec_sub18_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_inv_out = dec31_dec_sub8_dec31_dec_sub8_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_inv_out = dec31_dec_sub24_dec31_dec_sub24_inv_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_inv_out = dec31_dec_sub4_dec31_dec_sub4_inv_out; endcase @@ -89397,60 +96983,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_cry_out = dec31_dec_sub10_dec31_dec_sub10_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_cry_out = dec31_dec_sub28_dec31_dec_sub28_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_cry_out = dec31_dec_sub0_dec31_dec_sub0_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_cry_out = dec31_dec_sub26_dec31_dec_sub26_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_cry_out = dec31_dec_sub19_dec31_dec_sub19_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_cry_out = dec31_dec_sub22_dec31_dec_sub22_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_cry_out = dec31_dec_sub9_dec31_dec_sub9_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_cry_out = dec31_dec_sub11_dec31_dec_sub11_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_cry_out = dec31_dec_sub27_dec31_dec_sub27_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_cry_out = dec31_dec_sub15_dec31_dec_sub15_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_cry_out = dec31_dec_sub20_dec31_dec_sub20_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_cry_out = dec31_dec_sub21_dec31_dec_sub21_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_cry_out = dec31_dec_sub23_dec31_dec_sub23_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_cry_out = dec31_dec_sub16_dec31_dec_sub16_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_cry_out = dec31_dec_sub18_dec31_dec_sub18_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_cry_out = dec31_dec_sub8_dec31_dec_sub8_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_cry_out = dec31_dec_sub24_dec31_dec_sub24_cry_out; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_cry_out = dec31_dec_sub4_dec31_dec_sub4_cry_out; endcase @@ -89458,60 +97044,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_br = dec31_dec_sub10_dec31_dec_sub10_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_br = dec31_dec_sub28_dec31_dec_sub28_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_br = dec31_dec_sub0_dec31_dec_sub0_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_br = dec31_dec_sub26_dec31_dec_sub26_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_br = dec31_dec_sub19_dec31_dec_sub19_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_br = dec31_dec_sub22_dec31_dec_sub22_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_br = dec31_dec_sub9_dec31_dec_sub9_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_br = dec31_dec_sub11_dec31_dec_sub11_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_br = dec31_dec_sub27_dec31_dec_sub27_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_br = dec31_dec_sub15_dec31_dec_sub15_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_br = dec31_dec_sub20_dec31_dec_sub20_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_br = dec31_dec_sub21_dec31_dec_sub21_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_br = dec31_dec_sub23_dec31_dec_sub23_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_br = dec31_dec_sub16_dec31_dec_sub16_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_br = dec31_dec_sub18_dec31_dec_sub18_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_br = dec31_dec_sub8_dec31_dec_sub8_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_br = dec31_dec_sub24_dec31_dec_sub24_br; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_br = dec31_dec_sub4_dec31_dec_sub4_br; endcase @@ -89519,60 +97105,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_sgn_ext = dec31_dec_sub10_dec31_dec_sub10_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_sgn_ext = dec31_dec_sub28_dec31_dec_sub28_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_sgn_ext = dec31_dec_sub0_dec31_dec_sub0_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_sgn_ext = dec31_dec_sub26_dec31_dec_sub26_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_sgn_ext = dec31_dec_sub19_dec31_dec_sub19_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_sgn_ext = dec31_dec_sub22_dec31_dec_sub22_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_sgn_ext = dec31_dec_sub9_dec31_dec_sub9_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_sgn_ext = dec31_dec_sub11_dec31_dec_sub11_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_sgn_ext = dec31_dec_sub27_dec31_dec_sub27_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_sgn_ext = dec31_dec_sub15_dec31_dec_sub15_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_sgn_ext = dec31_dec_sub20_dec31_dec_sub20_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_sgn_ext = dec31_dec_sub21_dec31_dec_sub21_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_sgn_ext = dec31_dec_sub23_dec31_dec_sub23_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_sgn_ext = dec31_dec_sub16_dec31_dec_sub16_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_sgn_ext = dec31_dec_sub18_dec31_dec_sub18_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_sgn_ext = dec31_dec_sub8_dec31_dec_sub8_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_sgn_ext = dec31_dec_sub24_dec31_dec_sub24_sgn_ext; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_sgn_ext = dec31_dec_sub4_dec31_dec_sub4_sgn_ext; endcase @@ -89580,60 +97166,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_rsrv = dec31_dec_sub10_dec31_dec_sub10_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_rsrv = dec31_dec_sub28_dec31_dec_sub28_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_rsrv = dec31_dec_sub0_dec31_dec_sub0_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_rsrv = dec31_dec_sub26_dec31_dec_sub26_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_rsrv = dec31_dec_sub19_dec31_dec_sub19_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_rsrv = dec31_dec_sub22_dec31_dec_sub22_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_rsrv = dec31_dec_sub9_dec31_dec_sub9_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_rsrv = dec31_dec_sub11_dec31_dec_sub11_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_rsrv = dec31_dec_sub27_dec31_dec_sub27_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_rsrv = dec31_dec_sub15_dec31_dec_sub15_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_rsrv = dec31_dec_sub20_dec31_dec_sub20_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_rsrv = dec31_dec_sub21_dec31_dec_sub21_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_rsrv = dec31_dec_sub23_dec31_dec_sub23_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_rsrv = dec31_dec_sub16_dec31_dec_sub16_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_rsrv = dec31_dec_sub18_dec31_dec_sub18_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_rsrv = dec31_dec_sub8_dec31_dec_sub8_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_rsrv = dec31_dec_sub24_dec31_dec_sub24_rsrv; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_rsrv = dec31_dec_sub4_dec31_dec_sub4_rsrv; endcase @@ -89641,60 +97227,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_is_32b = dec31_dec_sub10_dec31_dec_sub10_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_is_32b = dec31_dec_sub28_dec31_dec_sub28_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_is_32b = dec31_dec_sub0_dec31_dec_sub0_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_is_32b = dec31_dec_sub26_dec31_dec_sub26_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_is_32b = dec31_dec_sub19_dec31_dec_sub19_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_is_32b = dec31_dec_sub22_dec31_dec_sub22_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_is_32b = dec31_dec_sub9_dec31_dec_sub9_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_is_32b = dec31_dec_sub11_dec31_dec_sub11_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_is_32b = dec31_dec_sub27_dec31_dec_sub27_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_is_32b = dec31_dec_sub15_dec31_dec_sub15_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_is_32b = dec31_dec_sub20_dec31_dec_sub20_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_is_32b = dec31_dec_sub21_dec31_dec_sub21_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_is_32b = dec31_dec_sub23_dec31_dec_sub23_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_is_32b = dec31_dec_sub16_dec31_dec_sub16_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_is_32b = dec31_dec_sub18_dec31_dec_sub18_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_is_32b = dec31_dec_sub8_dec31_dec_sub8_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_is_32b = dec31_dec_sub24_dec31_dec_sub24_is_32b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_is_32b = dec31_dec_sub4_dec31_dec_sub4_is_32b; endcase @@ -89702,60 +97288,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_sgn = dec31_dec_sub10_dec31_dec_sub10_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_sgn = dec31_dec_sub28_dec31_dec_sub28_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_sgn = dec31_dec_sub0_dec31_dec_sub0_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_sgn = dec31_dec_sub26_dec31_dec_sub26_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_sgn = dec31_dec_sub19_dec31_dec_sub19_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_sgn = dec31_dec_sub22_dec31_dec_sub22_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_sgn = dec31_dec_sub9_dec31_dec_sub9_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_sgn = dec31_dec_sub11_dec31_dec_sub11_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_sgn = dec31_dec_sub27_dec31_dec_sub27_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_sgn = dec31_dec_sub15_dec31_dec_sub15_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_sgn = dec31_dec_sub20_dec31_dec_sub20_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_sgn = dec31_dec_sub21_dec31_dec_sub21_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_sgn = dec31_dec_sub23_dec31_dec_sub23_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_sgn = dec31_dec_sub16_dec31_dec_sub16_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_sgn = dec31_dec_sub18_dec31_dec_sub18_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_sgn = dec31_dec_sub8_dec31_dec_sub8_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_sgn = dec31_dec_sub24_dec31_dec_sub24_sgn; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_sgn = dec31_dec_sub4_dec31_dec_sub4_sgn; endcase @@ -89763,60 +97349,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_lk = dec31_dec_sub10_dec31_dec_sub10_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_lk = dec31_dec_sub28_dec31_dec_sub28_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_lk = dec31_dec_sub0_dec31_dec_sub0_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_lk = dec31_dec_sub26_dec31_dec_sub26_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_lk = dec31_dec_sub19_dec31_dec_sub19_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_lk = dec31_dec_sub22_dec31_dec_sub22_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_lk = dec31_dec_sub9_dec31_dec_sub9_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_lk = dec31_dec_sub11_dec31_dec_sub11_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_lk = dec31_dec_sub27_dec31_dec_sub27_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_lk = dec31_dec_sub15_dec31_dec_sub15_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_lk = dec31_dec_sub20_dec31_dec_sub20_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_lk = dec31_dec_sub21_dec31_dec_sub21_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_lk = dec31_dec_sub23_dec31_dec_sub23_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_lk = dec31_dec_sub16_dec31_dec_sub16_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_lk = dec31_dec_sub18_dec31_dec_sub18_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_lk = dec31_dec_sub8_dec31_dec_sub8_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_lk = dec31_dec_sub24_dec31_dec_sub24_lk; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_lk = dec31_dec_sub4_dec31_dec_sub4_lk; endcase @@ -89824,60 +97410,60 @@ module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, always @* begin if (\initial ) begin end dec31_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opc_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_sgl_pipe = dec31_dec_sub10_dec31_dec_sub10_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_sgl_pipe = dec31_dec_sub28_dec31_dec_sub28_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_sgl_pipe = dec31_dec_sub0_dec31_dec_sub0_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_sgl_pipe = dec31_dec_sub26_dec31_dec_sub26_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_sgl_pipe = dec31_dec_sub19_dec31_dec_sub19_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_sgl_pipe = dec31_dec_sub22_dec31_dec_sub22_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_sgl_pipe = dec31_dec_sub9_dec31_dec_sub9_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_sgl_pipe = dec31_dec_sub11_dec31_dec_sub11_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_sgl_pipe = dec31_dec_sub27_dec31_dec_sub27_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_sgl_pipe = dec31_dec_sub15_dec31_dec_sub15_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_sgl_pipe = dec31_dec_sub20_dec31_dec_sub20_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_sgl_pipe = dec31_dec_sub21_dec31_dec_sub21_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_sgl_pipe = dec31_dec_sub23_dec31_dec_sub23_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_sgl_pipe = dec31_dec_sub16_dec31_dec_sub16_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_sgl_pipe = dec31_dec_sub18_dec31_dec_sub18_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_sgl_pipe = dec31_dec_sub8_dec31_dec_sub8_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_sgl_pipe = dec31_dec_sub24_dec31_dec_sub24_sgl_pipe; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_sgl_pipe = dec31_dec_sub4_dec31_dec_sub4_sgl_pipe; endcase @@ -89912,20 +97498,20 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub0_SV_Etype; reg [1:0] dec31_dec_sub0_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub0_SV_Ptype; reg [1:0] dec31_dec_sub0_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub0_asmcode; reg [7:0] dec31_dec_sub0_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub0_br; reg dec31_dec_sub0_br; (* enum_base_type = "CRInSel" *) @@ -89937,7 +97523,7 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub0_cr_in; reg [2:0] dec31_dec_sub0_cr_in; (* enum_base_type = "CROutSel" *) @@ -89947,17 +97533,17 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub0_cr_out; reg [2:0] dec31_dec_sub0_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub0_cry_in; reg [1:0] dec31_dec_sub0_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub0_cry_out; reg dec31_dec_sub0_cry_out; (* enum_base_type = "Form" *) @@ -89991,34 +97577,37 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub0_form; reg [4:0] dec31_dec_sub0_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] dec31_dec_sub0_function_unit; - reg [13:0] dec31_dec_sub0_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] dec31_dec_sub0_function_unit; + reg [14:0] dec31_dec_sub0_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub0_in1_sel; reg [2:0] dec31_dec_sub0_in1_sel; (* enum_base_type = "In2Sel" *) @@ -90036,16 +97625,19 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub0_in2_sel; reg [3:0] dec31_dec_sub0_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [1:0] dec31_dec_sub0_in3_sel; - reg [1:0] dec31_dec_sub0_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub0_in3_sel; + reg [2:0] dec31_dec_sub0_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -90121,16 +97713,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub0_internal_op; reg [6:0] dec31_dec_sub0_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub0_inv_a; reg dec31_dec_sub0_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub0_inv_out; reg dec31_dec_sub0_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub0_is_32b; reg dec31_dec_sub0_is_32b; (* enum_base_type = "LdstLen" *) @@ -90139,10 +97733,10 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub0_ldst_len; reg [3:0] dec31_dec_sub0_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub0_lk; reg dec31_dec_sub0_lk; (* enum_base_type = "OutSel" *) @@ -90151,26 +97745,27 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub0_out_sel; reg [2:0] dec31_dec_sub0_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub0_rc_sel; reg [1:0] dec31_dec_sub0_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub0_rsrv; reg dec31_dec_sub0_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub0_sgl_pipe; reg dec31_dec_sub0_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub0_sgn; reg dec31_dec_sub0_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub0_sgn_ext; reg dec31_dec_sub0_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -90180,7 +97775,7 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub0_sv_cr_in; reg [2:0] dec31_dec_sub0_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -90190,7 +97785,7 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub0_sv_cr_out; reg [2:0] dec31_dec_sub0_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -90200,7 +97795,7 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub0_sv_in1; reg [2:0] dec31_dec_sub0_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -90210,7 +97805,7 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub0_sv_in2; reg [2:0] dec31_dec_sub0_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -90220,7 +97815,7 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub0_sv_in3; reg [2:0] dec31_dec_sub0_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -90230,7 +97825,7 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub0_sv_out; reg [2:0] dec31_dec_sub0_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -90240,7 +97835,7 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub0_sv_out2; reg [2:0] dec31_dec_sub0_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -90248,47 +97843,47 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub0_upd; reg [1:0] dec31_dec_sub0_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - dec31_dec_sub0_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub0_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub0_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub0_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - dec31_dec_sub0_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub0_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: - dec31_dec_sub0_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub0_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - dec31_dec_sub0_function_unit = 14'h0040; + dec31_dec_sub0_function_unit = 15'h0040; endcase end always @* begin if (\initial ) begin end dec31_dec_sub0_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub0_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub0_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub0_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub0_cr_in = 3'h3; endcase @@ -90296,18 +97891,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub0_cr_out = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub0_cr_out = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub0_cr_out = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub0_cr_out = 3'h0; endcase @@ -90315,18 +97910,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub0_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub0_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub0_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub0_sv_in1 = 3'h0; endcase @@ -90334,18 +97929,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub0_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub0_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub0_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub0_sv_in2 = 3'h0; endcase @@ -90353,18 +97948,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub0_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub0_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub0_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub0_sv_in3 = 3'h0; endcase @@ -90372,18 +97967,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub0_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub0_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub0_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub0_sv_out = 3'h1; endcase @@ -90391,18 +97986,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub0_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub0_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub0_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub0_sv_out2 = 3'h0; endcase @@ -90410,18 +98005,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub0_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub0_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub0_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub0_sv_cr_in = 3'h2; endcase @@ -90429,18 +98024,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub0_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub0_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub0_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub0_sv_cr_out = 3'h0; endcase @@ -90448,18 +98043,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub0_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub0_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub0_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub0_ldst_len = 4'h0; endcase @@ -90467,18 +98062,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub0_internal_op = 7'h0a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub0_internal_op = 7'h0c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub0_internal_op = 7'h0a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub0_internal_op = 7'h3b; endcase @@ -90486,18 +98081,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub0_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub0_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub0_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub0_upd = 2'h0; endcase @@ -90505,18 +98100,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub0_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub0_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub0_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub0_rc_sel = 2'h0; endcase @@ -90524,18 +98119,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub0_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub0_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub0_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub0_cry_in = 2'h0; endcase @@ -90543,37 +98138,37 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub0_asmcode = 8'h1a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub0_asmcode = 8'h1c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub0_asmcode = 8'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - dec31_dec_sub0_asmcode = 8'h9b; + dec31_dec_sub0_asmcode = 8'hbb; endcase end always @* begin if (\initial ) begin end dec31_dec_sub0_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub0_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub0_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub0_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub0_inv_a = 1'h0; endcase @@ -90581,18 +98176,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub0_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub0_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub0_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub0_inv_out = 1'h0; endcase @@ -90600,18 +98195,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub0_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub0_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub0_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub0_cry_out = 1'h0; endcase @@ -90619,18 +98214,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub0_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub0_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub0_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub0_br = 1'h0; endcase @@ -90638,18 +98233,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub0_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub0_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub0_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub0_sgn_ext = 1'h0; endcase @@ -90657,18 +98252,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub0_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub0_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub0_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub0_rsrv = 1'h0; endcase @@ -90676,18 +98271,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub0_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub0_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub0_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub0_form = 5'h18; endcase @@ -90695,18 +98290,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub0_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub0_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub0_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub0_is_32b = 1'h0; endcase @@ -90714,18 +98309,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub0_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub0_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub0_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub0_sgn = 1'h0; endcase @@ -90733,18 +98328,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub0_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub0_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub0_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub0_lk = 1'h0; endcase @@ -90752,18 +98347,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub0_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub0_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub0_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub0_sgl_pipe = 1'h0; endcase @@ -90771,18 +98366,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub0_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub0_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub0_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub0_SV_Etype = 2'h2; endcase @@ -90790,18 +98385,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub0_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub0_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub0_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub0_SV_Ptype = 2'h2; endcase @@ -90809,18 +98404,18 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub0_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub0_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub0_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub0_in1_sel = 3'h0; endcase @@ -90828,56 +98423,56 @@ module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub0_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub0_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub0_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub0_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub0_in2_sel = 4'h0; endcase end always @* begin if (\initial ) begin end - dec31_dec_sub0_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub0_in3_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub0_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub0_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - dec31_dec_sub0_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub0_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: - dec31_dec_sub0_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub0_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - dec31_dec_sub0_in3_sel = 2'h0; + dec31_dec_sub0_in3_sel = 3'h0; endcase end always @* begin if (\initial ) begin end dec31_dec_sub0_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub0_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub0_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub0_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub0_out_sel = 3'h1; endcase @@ -90893,20 +98488,20 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub10_SV_Etype; reg [1:0] dec31_dec_sub10_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub10_SV_Ptype; reg [1:0] dec31_dec_sub10_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub10_asmcode; reg [7:0] dec31_dec_sub10_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub10_br; reg dec31_dec_sub10_br; (* enum_base_type = "CRInSel" *) @@ -90918,7 +98513,7 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub10_cr_in; reg [2:0] dec31_dec_sub10_cr_in; (* enum_base_type = "CROutSel" *) @@ -90928,17 +98523,17 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub10_cr_out; reg [2:0] dec31_dec_sub10_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub10_cry_in; reg [1:0] dec31_dec_sub10_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub10_cry_out; reg dec31_dec_sub10_cry_out; (* enum_base_type = "Form" *) @@ -90972,34 +98567,37 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub10_form; reg [4:0] dec31_dec_sub10_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] dec31_dec_sub10_function_unit; - reg [13:0] dec31_dec_sub10_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] dec31_dec_sub10_function_unit; + reg [14:0] dec31_dec_sub10_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub10_in1_sel; reg [2:0] dec31_dec_sub10_in1_sel; (* enum_base_type = "In2Sel" *) @@ -91017,16 +98615,19 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub10_in2_sel; reg [3:0] dec31_dec_sub10_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [1:0] dec31_dec_sub10_in3_sel; - reg [1:0] dec31_dec_sub10_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub10_in3_sel; + reg [2:0] dec31_dec_sub10_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -91102,16 +98703,18 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub10_internal_op; reg [6:0] dec31_dec_sub10_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub10_inv_a; reg dec31_dec_sub10_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub10_inv_out; reg dec31_dec_sub10_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub10_is_32b; reg dec31_dec_sub10_is_32b; (* enum_base_type = "LdstLen" *) @@ -91120,10 +98723,10 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub10_ldst_len; reg [3:0] dec31_dec_sub10_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub10_lk; reg dec31_dec_sub10_lk; (* enum_base_type = "OutSel" *) @@ -91132,26 +98735,27 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub10_out_sel; reg [2:0] dec31_dec_sub10_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub10_rc_sel; reg [1:0] dec31_dec_sub10_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub10_rsrv; reg dec31_dec_sub10_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub10_sgl_pipe; reg dec31_dec_sub10_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub10_sgn; reg dec31_dec_sub10_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub10_sgn_ext; reg dec31_dec_sub10_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -91161,7 +98765,7 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub10_sv_cr_in; reg [2:0] dec31_dec_sub10_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -91171,7 +98775,7 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub10_sv_cr_out; reg [2:0] dec31_dec_sub10_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -91181,7 +98785,7 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub10_sv_in1; reg [2:0] dec31_dec_sub10_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -91191,7 +98795,7 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub10_sv_in2; reg [2:0] dec31_dec_sub10_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -91201,7 +98805,7 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub10_sv_in3; reg [2:0] dec31_dec_sub10_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -91211,7 +98815,7 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub10_sv_out; reg [2:0] dec31_dec_sub10_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -91221,7 +98825,7 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub10_sv_out2; reg [2:0] dec31_dec_sub10_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -91229,83 +98833,83 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub10_upd; reg [1:0] dec31_dec_sub10_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - dec31_dec_sub10_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub10_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: - dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub10_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub10_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub10_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub10_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub10_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: - dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub10_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub10_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: - dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub10_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: - dec31_dec_sub10_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub10_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: - dec31_dec_sub10_function_unit = 14'h0002; + dec31_dec_sub10_function_unit = 15'h0002; endcase end always @* begin if (\initial ) begin end dec31_dec_sub10_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub10_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub10_cr_in = 3'h0; endcase @@ -91313,36 +98917,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub10_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub10_cr_out = 3'h1; endcase @@ -91350,36 +98954,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub10_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub10_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub10_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub10_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub10_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub10_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub10_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub10_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub10_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub10_sv_in1 = 3'h2; endcase @@ -91387,36 +98991,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub10_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub10_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub10_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub10_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub10_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub10_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub10_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub10_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub10_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub10_sv_in2 = 3'h0; endcase @@ -91424,36 +99028,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub10_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub10_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub10_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub10_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub10_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub10_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub10_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub10_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub10_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub10_sv_in3 = 3'h0; endcase @@ -91461,36 +99065,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub10_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub10_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub10_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub10_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub10_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub10_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub10_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub10_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub10_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub10_sv_out = 3'h1; endcase @@ -91498,36 +99102,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub10_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub10_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub10_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub10_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub10_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub10_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub10_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub10_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub10_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub10_sv_out2 = 3'h0; endcase @@ -91535,36 +99139,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub10_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub10_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub10_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub10_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub10_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub10_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub10_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub10_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub10_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub10_sv_cr_in = 3'h0; endcase @@ -91572,36 +99176,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub10_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub10_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub10_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub10_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub10_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub10_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub10_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub10_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub10_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub10_sv_cr_out = 3'h1; endcase @@ -91609,36 +99213,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub10_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub10_ldst_len = 4'h0; endcase @@ -91646,36 +99250,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub10_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub10_internal_op = 7'h02; endcase @@ -91683,36 +99287,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub10_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub10_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub10_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub10_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub10_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub10_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub10_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub10_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub10_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub10_upd = 2'h0; endcase @@ -91720,36 +99324,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub10_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub10_rc_sel = 2'h2; endcase @@ -91757,36 +99361,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub10_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub10_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub10_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub10_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub10_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub10_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub10_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub10_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub10_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub10_cry_in = 2'h2; endcase @@ -91794,36 +99398,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub10_asmcode = 8'h01; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub10_asmcode = 8'h0c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub10_asmcode = 8'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub10_asmcode = 8'h03; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub10_asmcode = 8'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub10_asmcode = 8'h05; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub10_asmcode = 8'h0a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub10_asmcode = 8'h0b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub10_asmcode = 8'h0d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub10_asmcode = 8'h0e; endcase @@ -91831,36 +99435,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub10_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub10_inv_a = 1'h0; endcase @@ -91868,36 +99472,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub10_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub10_inv_out = 1'h0; endcase @@ -91905,36 +99509,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub10_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub10_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub10_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub10_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub10_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub10_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub10_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub10_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub10_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub10_cry_out = 1'h1; endcase @@ -91942,36 +99546,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub10_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub10_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub10_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub10_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub10_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub10_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub10_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub10_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub10_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub10_br = 1'h0; endcase @@ -91979,36 +99583,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub10_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub10_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub10_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub10_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub10_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub10_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub10_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub10_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub10_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub10_sgn_ext = 1'h0; endcase @@ -92016,36 +99620,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub10_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub10_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub10_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub10_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub10_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub10_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub10_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub10_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub10_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub10_rsrv = 1'h0; endcase @@ -92053,36 +99657,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub10_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub10_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub10_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub10_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub10_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub10_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub10_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub10_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub10_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub10_form = 5'h11; endcase @@ -92090,36 +99694,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub10_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub10_is_32b = 1'h0; endcase @@ -92127,36 +99731,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub10_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub10_sgn = 1'h0; endcase @@ -92164,36 +99768,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub10_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub10_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub10_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub10_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub10_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub10_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub10_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub10_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub10_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub10_lk = 1'h0; endcase @@ -92201,36 +99805,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub10_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub10_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub10_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub10_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub10_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub10_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub10_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub10_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub10_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub10_sgl_pipe = 1'h0; endcase @@ -92238,36 +99842,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub10_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub10_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub10_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub10_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub10_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub10_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub10_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub10_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub10_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub10_SV_Etype = 2'h2; endcase @@ -92275,36 +99879,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub10_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub10_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub10_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub10_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub10_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub10_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub10_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub10_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub10_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub10_SV_Ptype = 2'h2; endcase @@ -92312,36 +99916,36 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub10_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub10_in1_sel = 3'h1; endcase @@ -92349,110 +99953,110 @@ module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_o always @* begin if (\initial ) begin end dec31_dec_sub10_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub10_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub10_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub10_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub10_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub10_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub10_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub10_in2_sel = 4'h9; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub10_in2_sel = 4'h9; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub10_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub10_in2_sel = 4'h0; endcase end always @* begin if (\initial ) begin end - dec31_dec_sub10_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub10_in3_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: - dec31_dec_sub10_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub10_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - dec31_dec_sub10_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub10_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub10_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub10_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - dec31_dec_sub10_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub10_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - dec31_dec_sub10_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub10_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: - dec31_dec_sub10_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub10_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - dec31_dec_sub10_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub10_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: - dec31_dec_sub10_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub10_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: - dec31_dec_sub10_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub10_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: - dec31_dec_sub10_in3_sel = 2'h0; + dec31_dec_sub10_in3_sel = 3'h0; endcase end always @* begin if (\initial ) begin end dec31_dec_sub10_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub10_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub10_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub10_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub10_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub10_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub10_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub10_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub10_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub10_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub10_out_sel = 3'h1; endcase @@ -92468,20 +100072,20 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub11_SV_Etype; reg [1:0] dec31_dec_sub11_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub11_SV_Ptype; reg [1:0] dec31_dec_sub11_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub11_asmcode; reg [7:0] dec31_dec_sub11_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub11_br; reg dec31_dec_sub11_br; (* enum_base_type = "CRInSel" *) @@ -92493,7 +100097,7 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub11_cr_in; reg [2:0] dec31_dec_sub11_cr_in; (* enum_base_type = "CROutSel" *) @@ -92503,17 +100107,17 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub11_cr_out; reg [2:0] dec31_dec_sub11_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub11_cry_in; reg [1:0] dec31_dec_sub11_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub11_cry_out; reg dec31_dec_sub11_cry_out; (* enum_base_type = "Form" *) @@ -92547,34 +100151,37 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub11_form; reg [4:0] dec31_dec_sub11_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] dec31_dec_sub11_function_unit; - reg [13:0] dec31_dec_sub11_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] dec31_dec_sub11_function_unit; + reg [14:0] dec31_dec_sub11_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub11_in1_sel; reg [2:0] dec31_dec_sub11_in1_sel; (* enum_base_type = "In2Sel" *) @@ -92592,16 +100199,19 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub11_in2_sel; reg [3:0] dec31_dec_sub11_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [1:0] dec31_dec_sub11_in3_sel; - reg [1:0] dec31_dec_sub11_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub11_in3_sel; + reg [2:0] dec31_dec_sub11_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -92677,16 +100287,18 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub11_internal_op; reg [6:0] dec31_dec_sub11_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub11_inv_a; reg dec31_dec_sub11_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub11_inv_out; reg dec31_dec_sub11_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub11_is_32b; reg dec31_dec_sub11_is_32b; (* enum_base_type = "LdstLen" *) @@ -92695,10 +100307,10 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub11_ldst_len; reg [3:0] dec31_dec_sub11_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub11_lk; reg dec31_dec_sub11_lk; (* enum_base_type = "OutSel" *) @@ -92707,26 +100319,27 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub11_out_sel; reg [2:0] dec31_dec_sub11_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub11_rc_sel; reg [1:0] dec31_dec_sub11_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub11_rsrv; reg dec31_dec_sub11_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub11_sgl_pipe; reg dec31_dec_sub11_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub11_sgn; reg dec31_dec_sub11_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub11_sgn_ext; reg dec31_dec_sub11_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -92736,7 +100349,7 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub11_sv_cr_in; reg [2:0] dec31_dec_sub11_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -92746,7 +100359,7 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub11_sv_cr_out; reg [2:0] dec31_dec_sub11_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -92756,7 +100369,7 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub11_sv_in1; reg [2:0] dec31_dec_sub11_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -92766,7 +100379,7 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub11_sv_in2; reg [2:0] dec31_dec_sub11_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -92776,7 +100389,7 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub11_sv_in3; reg [2:0] dec31_dec_sub11_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -92786,7 +100399,7 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub11_sv_out; reg [2:0] dec31_dec_sub11_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -92796,7 +100409,7 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub11_sv_out2; reg [2:0] dec31_dec_sub11_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -92804,119 +100417,119 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub11_upd; reg [1:0] dec31_dec_sub11_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - dec31_dec_sub11_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub11_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: - dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: - dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: - dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: - dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: - dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: - dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: - dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: - dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: - dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - dec31_dec_sub11_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: - dec31_dec_sub11_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_function_unit = 15'h0100; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub11_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_function_unit = 15'h0100; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: - dec31_dec_sub11_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_function_unit = 15'h0100; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - dec31_dec_sub11_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_function_unit = 15'h0100; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - dec31_dec_sub11_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_function_unit = 15'h0100; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: - dec31_dec_sub11_function_unit = 14'h0100; + dec31_dec_sub11_function_unit = 15'h0100; endcase end always @* begin if (\initial ) begin end dec31_dec_sub11_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub11_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub11_cr_in = 3'h0; endcase @@ -92924,54 +100537,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub11_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub11_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub11_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub11_cr_out = 3'h1; endcase @@ -92979,54 +100592,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub11_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub11_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub11_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub11_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub11_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub11_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub11_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub11_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub11_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub11_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub11_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub11_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub11_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub11_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub11_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub11_sv_in1 = 3'h2; endcase @@ -93034,54 +100647,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub11_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub11_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub11_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub11_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub11_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub11_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub11_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub11_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub11_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub11_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub11_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub11_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub11_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub11_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub11_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub11_sv_in2 = 3'h3; endcase @@ -93089,54 +100702,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub11_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub11_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub11_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub11_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub11_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub11_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub11_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub11_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub11_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub11_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub11_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub11_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub11_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub11_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub11_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub11_sv_in3 = 3'h0; endcase @@ -93144,54 +100757,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub11_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub11_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub11_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub11_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub11_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub11_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub11_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub11_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub11_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub11_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub11_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub11_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub11_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub11_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub11_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub11_sv_out = 3'h1; endcase @@ -93199,54 +100812,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub11_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub11_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub11_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub11_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub11_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub11_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub11_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub11_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub11_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub11_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub11_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub11_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub11_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub11_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub11_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub11_sv_out2 = 3'h0; endcase @@ -93254,54 +100867,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub11_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub11_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub11_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub11_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub11_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub11_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub11_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub11_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub11_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub11_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub11_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub11_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub11_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub11_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub11_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub11_sv_cr_in = 3'h0; endcase @@ -93309,54 +100922,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub11_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub11_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub11_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub11_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub11_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub11_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub11_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub11_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub11_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub11_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub11_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub11_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub11_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub11_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub11_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub11_sv_cr_out = 3'h1; endcase @@ -93364,54 +100977,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub11_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub11_ldst_len = 4'h0; endcase @@ -93419,54 +101032,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub11_internal_op = 7'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub11_internal_op = 7'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub11_internal_op = 7'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub11_internal_op = 7'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub11_internal_op = 7'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub11_internal_op = 7'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub11_internal_op = 7'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub11_internal_op = 7'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub11_internal_op = 7'h2f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub11_internal_op = 7'h2f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub11_internal_op = 7'h34; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub11_internal_op = 7'h34; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub11_internal_op = 7'h34; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub11_internal_op = 7'h34; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub11_internal_op = 7'h32; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub11_internal_op = 7'h32; endcase @@ -93474,54 +101087,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub11_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub11_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub11_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub11_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub11_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub11_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub11_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub11_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub11_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub11_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub11_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub11_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub11_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub11_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub11_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub11_upd = 2'h0; endcase @@ -93529,54 +101142,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub11_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub11_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub11_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub11_rc_sel = 2'h2; endcase @@ -93584,54 +101197,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub11_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub11_cry_in = 2'h0; endcase @@ -93639,109 +101252,109 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub11_asmcode = 8'h3e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub11_asmcode = 8'h3f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub11_asmcode = 8'h3c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub11_asmcode = 8'h3d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub11_asmcode = 8'h41; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub11_asmcode = 8'h42; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub11_asmcode = 8'h3b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub11_asmcode = 8'h40; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: - dec31_dec_sub11_asmcode = 8'h75; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_asmcode = 8'h95; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - dec31_dec_sub11_asmcode = 8'h73; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_asmcode = 8'h93; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: - dec31_dec_sub11_asmcode = 8'h7c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_asmcode = 8'h9c; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub11_asmcode = 8'h7d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_asmcode = 8'h9d; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: - dec31_dec_sub11_asmcode = 8'h7c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_asmcode = 8'h9c; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - dec31_dec_sub11_asmcode = 8'h7d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_asmcode = 8'h9d; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - dec31_dec_sub11_asmcode = 8'h81; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_asmcode = 8'ha1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: - dec31_dec_sub11_asmcode = 8'h82; + dec31_dec_sub11_asmcode = 8'ha2; endcase end always @* begin if (\initial ) begin end dec31_dec_sub11_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub11_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub11_inv_a = 1'h0; endcase @@ -93749,54 +101362,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub11_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub11_inv_out = 1'h0; endcase @@ -93804,54 +101417,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub11_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub11_cry_out = 1'h0; endcase @@ -93859,54 +101472,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub11_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub11_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub11_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub11_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub11_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub11_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub11_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub11_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub11_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub11_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub11_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub11_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub11_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub11_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub11_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub11_br = 1'h0; endcase @@ -93914,54 +101527,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub11_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub11_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub11_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub11_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub11_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub11_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub11_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub11_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub11_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub11_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub11_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub11_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub11_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub11_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub11_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub11_sgn_ext = 1'h0; endcase @@ -93969,54 +101582,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub11_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub11_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub11_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub11_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub11_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub11_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub11_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub11_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub11_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub11_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub11_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub11_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub11_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub11_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub11_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub11_rsrv = 1'h0; endcase @@ -94024,54 +101637,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub11_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub11_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub11_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub11_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub11_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub11_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub11_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub11_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub11_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub11_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub11_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub11_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub11_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub11_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub11_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub11_form = 5'h11; endcase @@ -94079,54 +101692,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub11_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub11_is_32b = 1'h1; endcase @@ -94134,54 +101747,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub11_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub11_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub11_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub11_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub11_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub11_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub11_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub11_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub11_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub11_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub11_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub11_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub11_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub11_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub11_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub11_sgn = 1'h1; endcase @@ -94189,54 +101802,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub11_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub11_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub11_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub11_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub11_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub11_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub11_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub11_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub11_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub11_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub11_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub11_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub11_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub11_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub11_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub11_lk = 1'h0; endcase @@ -94244,54 +101857,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub11_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub11_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub11_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub11_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub11_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub11_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub11_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub11_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub11_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub11_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub11_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub11_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub11_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub11_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub11_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub11_sgl_pipe = 1'h0; endcase @@ -94299,54 +101912,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub11_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub11_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub11_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub11_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub11_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub11_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub11_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub11_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub11_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub11_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub11_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub11_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub11_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub11_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub11_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub11_SV_Etype = 2'h2; endcase @@ -94354,54 +101967,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub11_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub11_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub11_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub11_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub11_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub11_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub11_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub11_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub11_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub11_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub11_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub11_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub11_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub11_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub11_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub11_SV_Ptype = 2'h1; endcase @@ -94409,54 +102022,54 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub11_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub11_in1_sel = 3'h1; endcase @@ -94464,164 +102077,164 @@ module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_o always @* begin if (\initial ) begin end dec31_dec_sub11_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub11_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub11_in2_sel = 4'h1; endcase end always @* begin if (\initial ) begin end - dec31_dec_sub11_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub11_in3_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: - dec31_dec_sub11_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: - dec31_dec_sub11_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: - dec31_dec_sub11_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: - dec31_dec_sub11_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: - dec31_dec_sub11_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: - dec31_dec_sub11_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: - dec31_dec_sub11_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: - dec31_dec_sub11_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: - dec31_dec_sub11_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - dec31_dec_sub11_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: - dec31_dec_sub11_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub11_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: - dec31_dec_sub11_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - dec31_dec_sub11_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - dec31_dec_sub11_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub11_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: - dec31_dec_sub11_in3_sel = 2'h0; + dec31_dec_sub11_in3_sel = 3'h0; endcase end always @* begin if (\initial ) begin end dec31_dec_sub11_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub11_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub11_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub11_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub11_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub11_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub11_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub11_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub11_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub11_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub11_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub11_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub11_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub11_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub11_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub11_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub11_out_sel = 3'h1; endcase @@ -94637,20 +102250,20 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub15_SV_Etype; reg [1:0] dec31_dec_sub15_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub15_SV_Ptype; reg [1:0] dec31_dec_sub15_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub15_asmcode; reg [7:0] dec31_dec_sub15_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub15_br; reg dec31_dec_sub15_br; (* enum_base_type = "CRInSel" *) @@ -94662,7 +102275,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub15_cr_in; reg [2:0] dec31_dec_sub15_cr_in; (* enum_base_type = "CROutSel" *) @@ -94672,17 +102285,17 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub15_cr_out; reg [2:0] dec31_dec_sub15_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub15_cry_in; reg [1:0] dec31_dec_sub15_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub15_cry_out; reg dec31_dec_sub15_cry_out; (* enum_base_type = "Form" *) @@ -94716,34 +102329,37 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub15_form; reg [4:0] dec31_dec_sub15_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] dec31_dec_sub15_function_unit; - reg [13:0] dec31_dec_sub15_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] dec31_dec_sub15_function_unit; + reg [14:0] dec31_dec_sub15_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub15_in1_sel; reg [2:0] dec31_dec_sub15_in1_sel; (* enum_base_type = "In2Sel" *) @@ -94761,16 +102377,19 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub15_in2_sel; reg [3:0] dec31_dec_sub15_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [1:0] dec31_dec_sub15_in3_sel; - reg [1:0] dec31_dec_sub15_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub15_in3_sel; + reg [2:0] dec31_dec_sub15_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -94846,16 +102465,18 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub15_internal_op; reg [6:0] dec31_dec_sub15_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub15_inv_a; reg dec31_dec_sub15_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub15_inv_out; reg dec31_dec_sub15_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub15_is_32b; reg dec31_dec_sub15_is_32b; (* enum_base_type = "LdstLen" *) @@ -94864,10 +102485,10 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub15_ldst_len; reg [3:0] dec31_dec_sub15_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub15_lk; reg dec31_dec_sub15_lk; (* enum_base_type = "OutSel" *) @@ -94876,26 +102497,27 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub15_out_sel; reg [2:0] dec31_dec_sub15_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub15_rc_sel; reg [1:0] dec31_dec_sub15_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub15_rsrv; reg dec31_dec_sub15_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub15_sgl_pipe; reg dec31_dec_sub15_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub15_sgn; reg dec31_dec_sub15_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub15_sgn_ext; reg dec31_dec_sub15_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -94905,7 +102527,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub15_sv_cr_in; reg [2:0] dec31_dec_sub15_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -94915,7 +102537,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub15_sv_cr_out; reg [2:0] dec31_dec_sub15_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -94925,7 +102547,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub15_sv_in1; reg [2:0] dec31_dec_sub15_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -94935,7 +102557,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub15_sv_in2; reg [2:0] dec31_dec_sub15_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -94945,7 +102567,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub15_sv_in3; reg [2:0] dec31_dec_sub15_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -94955,7 +102577,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub15_sv_out; reg [2:0] dec31_dec_sub15_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -94965,7 +102587,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub15_sv_out2; reg [2:0] dec31_dec_sub15_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -94973,215 +102595,215 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub15_upd; reg [1:0] dec31_dec_sub15_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: - dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: - dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: - dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: - dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: - dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: - dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: - dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: - dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: - dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: - dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: - dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: - dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: - dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: - dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: - dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: - dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: - dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: - dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: - dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: - dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: - dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: - dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: - dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: - dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: - dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: - dec31_dec_sub15_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: - dec31_dec_sub15_function_unit = 14'h0040; + dec31_dec_sub15_function_unit = 15'h0040; endcase end always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub15_cr_in = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub15_cr_in = 3'h5; endcase @@ -95189,102 +102811,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub15_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub15_cr_out = 3'h0; endcase @@ -95292,102 +102914,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub15_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub15_sv_in1 = 3'h2; endcase @@ -95395,102 +103017,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub15_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub15_sv_in2 = 3'h3; endcase @@ -95498,102 +103120,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub15_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub15_sv_in3 = 3'h0; endcase @@ -95601,102 +103223,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub15_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub15_sv_out = 3'h1; endcase @@ -95704,102 +103326,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub15_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub15_sv_out2 = 3'h0; endcase @@ -95807,102 +103429,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub15_sv_cr_in = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub15_sv_cr_in = 3'h4; endcase @@ -95910,102 +103532,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub15_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub15_sv_cr_out = 3'h0; endcase @@ -96013,102 +103635,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub15_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub15_ldst_len = 4'h0; endcase @@ -96116,102 +103738,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub15_internal_op = 7'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub15_internal_op = 7'h23; endcase @@ -96219,102 +103841,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub15_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub15_upd = 2'h0; endcase @@ -96322,102 +103944,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub15_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub15_rc_sel = 2'h0; endcase @@ -96425,102 +104047,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub15_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub15_cry_in = 2'h0; endcase @@ -96528,205 +104150,205 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_asmcode = 8'h61; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: - dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_asmcode = 8'h61; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: - dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_asmcode = 8'h61; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: - dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_asmcode = 8'h61; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_asmcode = 8'h61; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: - dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_asmcode = 8'h61; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: - dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_asmcode = 8'h61; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_asmcode = 8'h61; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: - dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_asmcode = 8'h61; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: - dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_asmcode = 8'h61; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: - dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_asmcode = 8'h61; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: - dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_asmcode = 8'h61; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: - dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_asmcode = 8'h61; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: - dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_asmcode = 8'h61; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: - dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_asmcode = 8'h61; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: - dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_asmcode = 8'h61; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_asmcode = 8'h61; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: - dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_asmcode = 8'h61; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: - dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_asmcode = 8'h61; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: - dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_asmcode = 8'h61; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: - dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_asmcode = 8'h61; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: - dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_asmcode = 8'h61; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: - dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_asmcode = 8'h61; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: - dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_asmcode = 8'h61; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_asmcode = 8'h61; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: - dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_asmcode = 8'h61; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: - dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_asmcode = 8'h61; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: - dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_asmcode = 8'h61; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: - dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_asmcode = 8'h61; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: - dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_asmcode = 8'h61; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: - dec31_dec_sub15_asmcode = 8'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_asmcode = 8'h61; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: - dec31_dec_sub15_asmcode = 8'h4b; + dec31_dec_sub15_asmcode = 8'h61; endcase end always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub15_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub15_inv_a = 1'h0; endcase @@ -96734,102 +104356,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub15_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub15_inv_out = 1'h0; endcase @@ -96837,102 +104459,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub15_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub15_cry_out = 1'h0; endcase @@ -96940,102 +104562,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub15_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub15_br = 1'h0; endcase @@ -97043,102 +104665,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub15_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub15_sgn_ext = 1'h0; endcase @@ -97146,102 +104768,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub15_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub15_rsrv = 1'h0; endcase @@ -97249,102 +104871,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub15_form = 5'h12; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub15_form = 5'h12; endcase @@ -97352,102 +104974,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub15_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub15_is_32b = 1'h0; endcase @@ -97455,102 +105077,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub15_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub15_sgn = 1'h0; endcase @@ -97558,102 +105180,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub15_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub15_lk = 1'h0; endcase @@ -97661,102 +105283,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub15_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub15_sgl_pipe = 1'h1; endcase @@ -97764,102 +105386,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub15_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub15_SV_Etype = 2'h1; endcase @@ -97867,102 +105489,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub15_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub15_SV_Ptype = 2'h1; endcase @@ -97970,102 +105592,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub15_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub15_in1_sel = 3'h2; endcase @@ -98073,102 +105695,102 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub15_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub15_in2_sel = 4'h1; endcase @@ -98176,205 +105798,205 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: - dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: - dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: - dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: - dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: - dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: - dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: - dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: - dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: - dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: - dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: - dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: - dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: - dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: - dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: - dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: - dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: - dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: - dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: - dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: - dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: - dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: - dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: - dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: - dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: - dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: - dec31_dec_sub15_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub15_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: - dec31_dec_sub15_in3_sel = 2'h0; + dec31_dec_sub15_in3_sel = 3'h0; endcase end always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub15_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub15_out_sel = 3'h1; endcase @@ -98390,20 +106012,20 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub16_SV_Etype; reg [1:0] dec31_dec_sub16_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub16_SV_Ptype; reg [1:0] dec31_dec_sub16_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub16_asmcode; reg [7:0] dec31_dec_sub16_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub16_br; reg dec31_dec_sub16_br; (* enum_base_type = "CRInSel" *) @@ -98415,7 +106037,7 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub16_cr_in; reg [2:0] dec31_dec_sub16_cr_in; (* enum_base_type = "CROutSel" *) @@ -98425,17 +106047,17 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub16_cr_out; reg [2:0] dec31_dec_sub16_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub16_cry_in; reg [1:0] dec31_dec_sub16_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub16_cry_out; reg dec31_dec_sub16_cry_out; (* enum_base_type = "Form" *) @@ -98469,34 +106091,37 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub16_form; reg [4:0] dec31_dec_sub16_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] dec31_dec_sub16_function_unit; - reg [13:0] dec31_dec_sub16_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] dec31_dec_sub16_function_unit; + reg [14:0] dec31_dec_sub16_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub16_in1_sel; reg [2:0] dec31_dec_sub16_in1_sel; (* enum_base_type = "In2Sel" *) @@ -98514,16 +106139,19 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub16_in2_sel; reg [3:0] dec31_dec_sub16_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [1:0] dec31_dec_sub16_in3_sel; - reg [1:0] dec31_dec_sub16_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub16_in3_sel; + reg [2:0] dec31_dec_sub16_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -98599,16 +106227,18 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub16_internal_op; reg [6:0] dec31_dec_sub16_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub16_inv_a; reg dec31_dec_sub16_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub16_inv_out; reg dec31_dec_sub16_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub16_is_32b; reg dec31_dec_sub16_is_32b; (* enum_base_type = "LdstLen" *) @@ -98617,10 +106247,10 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub16_ldst_len; reg [3:0] dec31_dec_sub16_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub16_lk; reg dec31_dec_sub16_lk; (* enum_base_type = "OutSel" *) @@ -98629,26 +106259,27 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub16_out_sel; reg [2:0] dec31_dec_sub16_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub16_rc_sel; reg [1:0] dec31_dec_sub16_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub16_rsrv; reg dec31_dec_sub16_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub16_sgl_pipe; reg dec31_dec_sub16_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub16_sgn; reg dec31_dec_sub16_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub16_sgn_ext; reg dec31_dec_sub16_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -98658,7 +106289,7 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub16_sv_cr_in; reg [2:0] dec31_dec_sub16_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -98668,7 +106299,7 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub16_sv_cr_out; reg [2:0] dec31_dec_sub16_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -98678,7 +106309,7 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub16_sv_in1; reg [2:0] dec31_dec_sub16_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -98688,7 +106319,7 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub16_sv_in2; reg [2:0] dec31_dec_sub16_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -98698,7 +106329,7 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub16_sv_in3; reg [2:0] dec31_dec_sub16_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -98708,7 +106339,7 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub16_sv_out; reg [2:0] dec31_dec_sub16_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -98718,7 +106349,7 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub16_sv_out2; reg [2:0] dec31_dec_sub16_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -98726,29 +106357,29 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub16_upd; reg [1:0] dec31_dec_sub16_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - dec31_dec_sub16_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub16_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - dec31_dec_sub16_function_unit = 14'h0040; + dec31_dec_sub16_function_unit = 15'h0040; endcase end always @* begin if (\initial ) begin end dec31_dec_sub16_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub16_cr_in = 3'h6; endcase @@ -98756,9 +106387,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub16_cr_out = 3'h4; endcase @@ -98766,9 +106397,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub16_sv_in1 = 3'h2; endcase @@ -98776,9 +106407,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub16_sv_in2 = 3'h0; endcase @@ -98786,9 +106417,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub16_sv_in3 = 3'h0; endcase @@ -98796,9 +106427,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub16_sv_out = 3'h0; endcase @@ -98806,9 +106437,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub16_sv_out2 = 3'h0; endcase @@ -98816,9 +106447,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub16_sv_cr_in = 3'h0; endcase @@ -98826,9 +106457,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub16_sv_cr_out = 3'h0; endcase @@ -98836,9 +106467,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub16_ldst_len = 4'h0; endcase @@ -98846,9 +106477,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub16_internal_op = 7'h30; endcase @@ -98856,9 +106487,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub16_upd = 2'h0; endcase @@ -98866,9 +106497,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub16_rc_sel = 2'h0; endcase @@ -98876,9 +106507,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub16_cry_in = 2'h0; endcase @@ -98886,19 +106517,19 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - dec31_dec_sub16_asmcode = 8'h76; + dec31_dec_sub16_asmcode = 8'h96; endcase end always @* begin if (\initial ) begin end dec31_dec_sub16_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub16_inv_a = 1'h0; endcase @@ -98906,9 +106537,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub16_inv_out = 1'h0; endcase @@ -98916,9 +106547,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub16_cry_out = 1'h0; endcase @@ -98926,9 +106557,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub16_br = 1'h0; endcase @@ -98936,9 +106567,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub16_sgn_ext = 1'h0; endcase @@ -98946,9 +106577,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub16_rsrv = 1'h0; endcase @@ -98956,9 +106587,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub16_form = 5'h0a; endcase @@ -98966,9 +106597,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub16_is_32b = 1'h0; endcase @@ -98976,9 +106607,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub16_sgn = 1'h0; endcase @@ -98986,9 +106617,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub16_lk = 1'h0; endcase @@ -98996,9 +106627,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub16_sgl_pipe = 1'h0; endcase @@ -99006,9 +106637,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub16_SV_Etype = 2'h1; endcase @@ -99016,9 +106647,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub16_SV_Ptype = 2'h2; endcase @@ -99026,9 +106657,9 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub16_in1_sel = 3'h4; endcase @@ -99036,29 +106667,29 @@ module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_o always @* begin if (\initial ) begin end dec31_dec_sub16_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub16_in2_sel = 4'h0; endcase end always @* begin if (\initial ) begin end - dec31_dec_sub16_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub16_in3_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - dec31_dec_sub16_in3_sel = 2'h0; + dec31_dec_sub16_in3_sel = 3'h0; endcase end always @* begin if (\initial ) begin end dec31_dec_sub16_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub16_out_sel = 3'h0; endcase @@ -99074,20 +106705,20 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub18_SV_Etype; reg [1:0] dec31_dec_sub18_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub18_SV_Ptype; reg [1:0] dec31_dec_sub18_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub18_asmcode; reg [7:0] dec31_dec_sub18_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub18_br; reg dec31_dec_sub18_br; (* enum_base_type = "CRInSel" *) @@ -99099,7 +106730,7 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub18_cr_in; reg [2:0] dec31_dec_sub18_cr_in; (* enum_base_type = "CROutSel" *) @@ -99109,17 +106740,17 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub18_cr_out; reg [2:0] dec31_dec_sub18_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub18_cry_in; reg [1:0] dec31_dec_sub18_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub18_cry_out; reg dec31_dec_sub18_cry_out; (* enum_base_type = "Form" *) @@ -99153,34 +106784,37 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub18_form; reg [4:0] dec31_dec_sub18_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] dec31_dec_sub18_function_unit; - reg [13:0] dec31_dec_sub18_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] dec31_dec_sub18_function_unit; + reg [14:0] dec31_dec_sub18_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub18_in1_sel; reg [2:0] dec31_dec_sub18_in1_sel; (* enum_base_type = "In2Sel" *) @@ -99198,16 +106832,19 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub18_in2_sel; reg [3:0] dec31_dec_sub18_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [1:0] dec31_dec_sub18_in3_sel; - reg [1:0] dec31_dec_sub18_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub18_in3_sel; + reg [2:0] dec31_dec_sub18_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -99283,16 +106920,18 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub18_internal_op; reg [6:0] dec31_dec_sub18_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub18_inv_a; reg dec31_dec_sub18_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub18_inv_out; reg dec31_dec_sub18_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub18_is_32b; reg dec31_dec_sub18_is_32b; (* enum_base_type = "LdstLen" *) @@ -99301,10 +106940,10 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub18_ldst_len; reg [3:0] dec31_dec_sub18_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub18_lk; reg dec31_dec_sub18_lk; (* enum_base_type = "OutSel" *) @@ -99313,26 +106952,27 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub18_out_sel; reg [2:0] dec31_dec_sub18_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub18_rc_sel; reg [1:0] dec31_dec_sub18_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub18_rsrv; reg dec31_dec_sub18_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub18_sgl_pipe; reg dec31_dec_sub18_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub18_sgn; reg dec31_dec_sub18_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub18_sgn_ext; reg dec31_dec_sub18_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -99342,7 +106982,7 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub18_sv_cr_in; reg [2:0] dec31_dec_sub18_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -99352,7 +106992,7 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub18_sv_cr_out; reg [2:0] dec31_dec_sub18_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -99362,7 +107002,7 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub18_sv_in1; reg [2:0] dec31_dec_sub18_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -99372,7 +107012,7 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub18_sv_in2; reg [2:0] dec31_dec_sub18_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -99382,7 +107022,7 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub18_sv_in3; reg [2:0] dec31_dec_sub18_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -99392,7 +107032,7 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub18_sv_out; reg [2:0] dec31_dec_sub18_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -99402,7 +107042,7 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub18_sv_out2; reg [2:0] dec31_dec_sub18_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -99410,53 +107050,53 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub18_upd; reg [1:0] dec31_dec_sub18_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - dec31_dec_sub18_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub18_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: - dec31_dec_sub18_function_unit = 14'h0080; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub18_function_unit = 15'h0080; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - dec31_dec_sub18_function_unit = 14'h0080; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub18_function_unit = 15'h0080; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: - dec31_dec_sub18_function_unit = 14'h0800; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub18_function_unit = 15'h0800; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: - dec31_dec_sub18_function_unit = 14'h0800; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub18_function_unit = 15'h0800; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: - dec31_dec_sub18_function_unit = 14'h0800; + dec31_dec_sub18_function_unit = 15'h0800; endcase end always @* begin if (\initial ) begin end dec31_dec_sub18_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub18_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub18_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub18_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub18_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub18_cr_in = 3'h0; endcase @@ -99464,21 +107104,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub18_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub18_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub18_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub18_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub18_cr_out = 3'h0; endcase @@ -99486,21 +107126,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub18_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub18_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub18_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub18_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub18_sv_in1 = 3'h0; endcase @@ -99508,21 +107148,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub18_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub18_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub18_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub18_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub18_sv_in2 = 3'h0; endcase @@ -99530,21 +107170,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub18_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub18_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub18_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub18_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub18_sv_in3 = 3'h0; endcase @@ -99552,21 +107192,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub18_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub18_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub18_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub18_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub18_sv_out = 3'h0; endcase @@ -99574,21 +107214,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub18_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub18_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub18_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub18_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub18_sv_out2 = 3'h0; endcase @@ -99596,21 +107236,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub18_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub18_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub18_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub18_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub18_sv_cr_in = 3'h0; endcase @@ -99618,21 +107258,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub18_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub18_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub18_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub18_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub18_sv_cr_out = 3'h0; endcase @@ -99640,21 +107280,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub18_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub18_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub18_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub18_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub18_ldst_len = 4'h0; endcase @@ -99662,21 +107302,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub18_internal_op = 7'h48; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub18_internal_op = 7'h4a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub18_internal_op = 7'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub18_internal_op = 7'h4b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub18_internal_op = 7'h4b; endcase @@ -99684,21 +107324,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub18_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub18_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub18_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub18_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub18_upd = 2'h0; endcase @@ -99706,21 +107346,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub18_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub18_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub18_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub18_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub18_rc_sel = 2'h0; endcase @@ -99728,21 +107368,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub18_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub18_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub18_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub18_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub18_cry_in = 2'h0; endcase @@ -99750,43 +107390,43 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: - dec31_dec_sub18_asmcode = 8'h78; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub18_asmcode = 8'h98; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - dec31_dec_sub18_asmcode = 8'h77; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub18_asmcode = 8'h97; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: - dec31_dec_sub18_asmcode = 8'h9e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub18_asmcode = 8'hbe; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: - dec31_dec_sub18_asmcode = 8'hcd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub18_asmcode = 8'hf6; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: - dec31_dec_sub18_asmcode = 8'hce; + dec31_dec_sub18_asmcode = 8'hf7; endcase end always @* begin if (\initial ) begin end dec31_dec_sub18_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub18_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub18_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub18_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub18_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub18_inv_a = 1'h0; endcase @@ -99794,21 +107434,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub18_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub18_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub18_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub18_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub18_inv_out = 1'h0; endcase @@ -99816,21 +107456,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub18_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub18_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub18_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub18_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub18_cry_out = 1'h0; endcase @@ -99838,21 +107478,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub18_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub18_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub18_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub18_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub18_br = 1'h0; endcase @@ -99860,21 +107500,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub18_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub18_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub18_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub18_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub18_sgn_ext = 1'h0; endcase @@ -99882,21 +107522,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub18_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub18_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub18_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub18_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub18_rsrv = 1'h0; endcase @@ -99904,21 +107544,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub18_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub18_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub18_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub18_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub18_form = 5'h08; endcase @@ -99926,21 +107566,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub18_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub18_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub18_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub18_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub18_is_32b = 1'h0; endcase @@ -99948,21 +107588,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub18_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub18_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub18_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub18_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub18_sgn = 1'h0; endcase @@ -99970,21 +107610,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub18_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub18_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub18_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub18_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub18_lk = 1'h0; endcase @@ -99992,21 +107632,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub18_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub18_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub18_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub18_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub18_sgl_pipe = 1'h0; endcase @@ -100014,21 +107654,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub18_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub18_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub18_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub18_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub18_SV_Etype = 2'h0; endcase @@ -100036,21 +107676,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub18_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub18_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub18_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub18_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub18_SV_Ptype = 2'h0; endcase @@ -100058,21 +107698,21 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub18_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub18_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub18_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub18_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub18_in1_sel = 3'h0; endcase @@ -100080,65 +107720,65 @@ module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_o always @* begin if (\initial ) begin end dec31_dec_sub18_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub18_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub18_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub18_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub18_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub18_in2_sel = 4'h1; endcase end always @* begin if (\initial ) begin end - dec31_dec_sub18_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub18_in3_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: - dec31_dec_sub18_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub18_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - dec31_dec_sub18_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub18_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: - dec31_dec_sub18_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub18_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: - dec31_dec_sub18_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub18_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: - dec31_dec_sub18_in3_sel = 2'h0; + dec31_dec_sub18_in3_sel = 3'h0; endcase end always @* begin if (\initial ) begin end dec31_dec_sub18_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub18_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub18_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub18_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub18_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub18_out_sel = 3'h0; endcase @@ -100154,20 +107794,20 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub19_SV_Etype; reg [1:0] dec31_dec_sub19_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub19_SV_Ptype; reg [1:0] dec31_dec_sub19_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub19_asmcode; reg [7:0] dec31_dec_sub19_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub19_br; reg dec31_dec_sub19_br; (* enum_base_type = "CRInSel" *) @@ -100179,7 +107819,7 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub19_cr_in; reg [2:0] dec31_dec_sub19_cr_in; (* enum_base_type = "CROutSel" *) @@ -100189,17 +107829,17 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub19_cr_out; reg [2:0] dec31_dec_sub19_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub19_cry_in; reg [1:0] dec31_dec_sub19_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub19_cry_out; reg dec31_dec_sub19_cry_out; (* enum_base_type = "Form" *) @@ -100233,34 +107873,37 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub19_form; reg [4:0] dec31_dec_sub19_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] dec31_dec_sub19_function_unit; - reg [13:0] dec31_dec_sub19_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] dec31_dec_sub19_function_unit; + reg [14:0] dec31_dec_sub19_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub19_in1_sel; reg [2:0] dec31_dec_sub19_in1_sel; (* enum_base_type = "In2Sel" *) @@ -100278,16 +107921,19 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub19_in2_sel; reg [3:0] dec31_dec_sub19_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [1:0] dec31_dec_sub19_in3_sel; - reg [1:0] dec31_dec_sub19_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub19_in3_sel; + reg [2:0] dec31_dec_sub19_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -100363,16 +108009,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub19_internal_op; reg [6:0] dec31_dec_sub19_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub19_inv_a; reg dec31_dec_sub19_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub19_inv_out; reg dec31_dec_sub19_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub19_is_32b; reg dec31_dec_sub19_is_32b; (* enum_base_type = "LdstLen" *) @@ -100381,10 +108029,10 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub19_ldst_len; reg [3:0] dec31_dec_sub19_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub19_lk; reg dec31_dec_sub19_lk; (* enum_base_type = "OutSel" *) @@ -100393,26 +108041,27 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub19_out_sel; reg [2:0] dec31_dec_sub19_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub19_rc_sel; reg [1:0] dec31_dec_sub19_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub19_rsrv; reg dec31_dec_sub19_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub19_sgl_pipe; reg dec31_dec_sub19_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub19_sgn; reg dec31_dec_sub19_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub19_sgn_ext; reg dec31_dec_sub19_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -100422,7 +108071,7 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub19_sv_cr_in; reg [2:0] dec31_dec_sub19_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -100432,7 +108081,7 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub19_sv_cr_out; reg [2:0] dec31_dec_sub19_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -100442,7 +108091,7 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub19_sv_in1; reg [2:0] dec31_dec_sub19_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -100452,7 +108101,7 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub19_sv_in2; reg [2:0] dec31_dec_sub19_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -100462,7 +108111,7 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub19_sv_in3; reg [2:0] dec31_dec_sub19_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -100472,7 +108121,7 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub19_sv_out; reg [2:0] dec31_dec_sub19_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -100482,7 +108131,7 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub19_sv_out2; reg [2:0] dec31_dec_sub19_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -100490,47 +108139,47 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub19_upd; reg [1:0] dec31_dec_sub19_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - dec31_dec_sub19_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub19_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub19_function_unit = 14'h0040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub19_function_unit = 15'h0040; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: - dec31_dec_sub19_function_unit = 14'h0080; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub19_function_unit = 15'h0080; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: - dec31_dec_sub19_function_unit = 14'h0400; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub19_function_unit = 15'h0400; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: - dec31_dec_sub19_function_unit = 14'h0400; + dec31_dec_sub19_function_unit = 15'h0400; endcase end always @* begin if (\initial ) begin end dec31_dec_sub19_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub19_cr_in = 3'h6; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub19_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub19_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub19_cr_in = 3'h0; endcase @@ -100538,18 +108187,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub19_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub19_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub19_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub19_cr_out = 3'h0; endcase @@ -100557,18 +108206,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub19_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub19_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub19_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub19_sv_in1 = 3'h2; endcase @@ -100576,18 +108225,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub19_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub19_sv_in2 = 3'h0; endcase @@ -100595,18 +108244,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub19_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub19_sv_in3 = 3'h0; endcase @@ -100614,18 +108263,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub19_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub19_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub19_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub19_sv_out = 3'h1; endcase @@ -100633,18 +108282,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub19_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub19_sv_out2 = 3'h0; endcase @@ -100652,18 +108301,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub19_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub19_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub19_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub19_sv_cr_in = 3'h0; endcase @@ -100671,18 +108320,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub19_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub19_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub19_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub19_sv_cr_out = 3'h0; endcase @@ -100690,18 +108339,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub19_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub19_ldst_len = 4'h0; endcase @@ -100709,18 +108358,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub19_internal_op = 7'h2d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub19_internal_op = 7'h47; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub19_internal_op = 7'h2e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub19_internal_op = 7'h31; endcase @@ -100728,18 +108377,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub19_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub19_upd = 2'h0; endcase @@ -100747,18 +108396,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub19_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub19_rc_sel = 2'h0; endcase @@ -100766,18 +108415,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub19_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub19_cry_in = 2'h0; endcase @@ -100785,37 +108434,37 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub19_asmcode = 8'h6f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub19_asmcode = 8'h8f; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: - dec31_dec_sub19_asmcode = 8'h70; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub19_asmcode = 8'h90; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: - dec31_dec_sub19_asmcode = 8'h71; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub19_asmcode = 8'h91; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: - dec31_dec_sub19_asmcode = 8'h79; + dec31_dec_sub19_asmcode = 8'h99; endcase end always @* begin if (\initial ) begin end dec31_dec_sub19_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub19_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub19_inv_a = 1'h0; endcase @@ -100823,18 +108472,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub19_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub19_inv_out = 1'h0; endcase @@ -100842,18 +108491,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub19_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub19_cry_out = 1'h0; endcase @@ -100861,18 +108510,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub19_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub19_br = 1'h0; endcase @@ -100880,18 +108529,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub19_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub19_sgn_ext = 1'h0; endcase @@ -100899,18 +108548,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub19_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub19_rsrv = 1'h0; endcase @@ -100918,18 +108567,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub19_form = 5'h0a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub19_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub19_form = 5'h0a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub19_form = 5'h0a; endcase @@ -100937,18 +108586,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub19_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub19_is_32b = 1'h0; endcase @@ -100956,18 +108605,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub19_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub19_sgn = 1'h0; endcase @@ -100975,18 +108624,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub19_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub19_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub19_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub19_lk = 1'h0; endcase @@ -100994,18 +108643,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub19_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub19_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub19_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub19_sgl_pipe = 1'h0; endcase @@ -101013,18 +108662,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub19_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub19_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub19_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub19_SV_Etype = 2'h2; endcase @@ -101032,18 +108681,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub19_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub19_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub19_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub19_SV_Ptype = 2'h2; endcase @@ -101051,18 +108700,18 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub19_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub19_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub19_in1_sel = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub19_in1_sel = 3'h4; endcase @@ -101070,56 +108719,56 @@ module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_o always @* begin if (\initial ) begin end dec31_dec_sub19_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub19_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub19_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub19_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub19_in2_sel = 4'h0; endcase end always @* begin if (\initial ) begin end - dec31_dec_sub19_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub19_in3_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub19_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: - dec31_dec_sub19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub19_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: - dec31_dec_sub19_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub19_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: - dec31_dec_sub19_in3_sel = 2'h0; + dec31_dec_sub19_in3_sel = 3'h0; endcase end always @* begin if (\initial ) begin end dec31_dec_sub19_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub19_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub19_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub19_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub19_out_sel = 3'h3; endcase @@ -101135,20 +108784,20 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub20_SV_Etype; reg [1:0] dec31_dec_sub20_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub20_SV_Ptype; reg [1:0] dec31_dec_sub20_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub20_asmcode; reg [7:0] dec31_dec_sub20_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub20_br; reg dec31_dec_sub20_br; (* enum_base_type = "CRInSel" *) @@ -101160,7 +108809,7 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub20_cr_in; reg [2:0] dec31_dec_sub20_cr_in; (* enum_base_type = "CROutSel" *) @@ -101170,17 +108819,17 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub20_cr_out; reg [2:0] dec31_dec_sub20_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub20_cry_in; reg [1:0] dec31_dec_sub20_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub20_cry_out; reg dec31_dec_sub20_cry_out; (* enum_base_type = "Form" *) @@ -101214,34 +108863,37 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub20_form; reg [4:0] dec31_dec_sub20_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] dec31_dec_sub20_function_unit; - reg [13:0] dec31_dec_sub20_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] dec31_dec_sub20_function_unit; + reg [14:0] dec31_dec_sub20_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub20_in1_sel; reg [2:0] dec31_dec_sub20_in1_sel; (* enum_base_type = "In2Sel" *) @@ -101259,16 +108911,19 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub20_in2_sel; reg [3:0] dec31_dec_sub20_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [1:0] dec31_dec_sub20_in3_sel; - reg [1:0] dec31_dec_sub20_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub20_in3_sel; + reg [2:0] dec31_dec_sub20_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -101344,16 +108999,18 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub20_internal_op; reg [6:0] dec31_dec_sub20_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub20_inv_a; reg dec31_dec_sub20_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub20_inv_out; reg dec31_dec_sub20_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub20_is_32b; reg dec31_dec_sub20_is_32b; (* enum_base_type = "LdstLen" *) @@ -101362,10 +109019,10 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub20_ldst_len; reg [3:0] dec31_dec_sub20_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub20_lk; reg dec31_dec_sub20_lk; (* enum_base_type = "OutSel" *) @@ -101374,26 +109031,27 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub20_out_sel; reg [2:0] dec31_dec_sub20_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub20_rc_sel; reg [1:0] dec31_dec_sub20_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub20_rsrv; reg dec31_dec_sub20_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub20_sgl_pipe; reg dec31_dec_sub20_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub20_sgn; reg dec31_dec_sub20_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub20_sgn_ext; reg dec31_dec_sub20_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -101403,7 +109061,7 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub20_sv_cr_in; reg [2:0] dec31_dec_sub20_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -101413,7 +109071,7 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub20_sv_cr_out; reg [2:0] dec31_dec_sub20_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -101423,7 +109081,7 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub20_sv_in1; reg [2:0] dec31_dec_sub20_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -101433,7 +109091,7 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub20_sv_in2; reg [2:0] dec31_dec_sub20_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -101443,7 +109101,7 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub20_sv_in3; reg [2:0] dec31_dec_sub20_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -101453,7 +109111,7 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub20_sv_out; reg [2:0] dec31_dec_sub20_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -101463,7 +109121,7 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub20_sv_out2; reg [2:0] dec31_dec_sub20_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -101471,59 +109129,59 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub20_upd; reg [1:0] dec31_dec_sub20_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - dec31_dec_sub20_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub20_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: - dec31_dec_sub20_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub20_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: - dec31_dec_sub20_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub20_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - dec31_dec_sub20_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub20_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: - dec31_dec_sub20_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub20_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub20_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub20_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: - dec31_dec_sub20_function_unit = 14'h0004; + dec31_dec_sub20_function_unit = 15'h0004; endcase end always @* begin if (\initial ) begin end dec31_dec_sub20_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub20_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub20_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub20_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub20_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub20_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub20_cr_in = 3'h0; endcase @@ -101531,24 +109189,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub20_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub20_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub20_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub20_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub20_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub20_cr_out = 3'h0; endcase @@ -101556,24 +109214,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub20_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub20_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub20_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub20_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub20_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub20_sv_in1 = 3'h2; endcase @@ -101581,24 +109239,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub20_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub20_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub20_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub20_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub20_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub20_sv_in2 = 3'h3; endcase @@ -101606,24 +109264,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub20_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub20_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub20_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub20_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub20_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub20_sv_in3 = 3'h1; endcase @@ -101631,24 +109289,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub20_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub20_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub20_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub20_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub20_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub20_sv_out = 3'h0; endcase @@ -101656,24 +109314,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub20_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub20_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub20_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub20_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub20_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub20_sv_out2 = 3'h0; endcase @@ -101681,24 +109339,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub20_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub20_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub20_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub20_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub20_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub20_sv_cr_in = 3'h0; endcase @@ -101706,24 +109364,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub20_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub20_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub20_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub20_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub20_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub20_sv_cr_out = 3'h0; endcase @@ -101731,24 +109389,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub20_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub20_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub20_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub20_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub20_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub20_ldst_len = 4'h8; endcase @@ -101756,24 +109414,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub20_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub20_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub20_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub20_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub20_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub20_internal_op = 7'h26; endcase @@ -101781,24 +109439,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub20_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub20_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub20_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub20_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub20_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub20_upd = 2'h0; endcase @@ -101806,24 +109464,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub20_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub20_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub20_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub20_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub20_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub20_rc_sel = 2'h0; endcase @@ -101831,24 +109489,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub20_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub20_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub20_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub20_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub20_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub20_cry_in = 2'h0; endcase @@ -101856,49 +109514,49 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: - dec31_dec_sub20_asmcode = 8'h4d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub20_asmcode = 8'h63; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: - dec31_dec_sub20_asmcode = 8'h53; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub20_asmcode = 8'h69; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - dec31_dec_sub20_asmcode = 8'h54; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub20_asmcode = 8'h6a; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: - dec31_dec_sub20_asmcode = 8'h59; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub20_asmcode = 8'h79; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub20_asmcode = 8'h63; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub20_asmcode = 8'h83; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: - dec31_dec_sub20_asmcode = 8'hae; + dec31_dec_sub20_asmcode = 8'hce; endcase end always @* begin if (\initial ) begin end dec31_dec_sub20_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub20_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub20_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub20_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub20_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub20_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub20_inv_a = 1'h0; endcase @@ -101906,24 +109564,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub20_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub20_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub20_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub20_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub20_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub20_inv_out = 1'h0; endcase @@ -101931,24 +109589,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub20_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub20_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub20_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub20_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub20_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub20_cry_out = 1'h0; endcase @@ -101956,24 +109614,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub20_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub20_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub20_br = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub20_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub20_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub20_br = 1'h1; endcase @@ -101981,24 +109639,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub20_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub20_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub20_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub20_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub20_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub20_sgn_ext = 1'h0; endcase @@ -102006,24 +109664,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub20_rsrv = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub20_rsrv = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub20_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub20_rsrv = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub20_rsrv = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub20_rsrv = 1'h0; endcase @@ -102031,24 +109689,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub20_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub20_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub20_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub20_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub20_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub20_form = 5'h08; endcase @@ -102056,24 +109714,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub20_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub20_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub20_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub20_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub20_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub20_is_32b = 1'h0; endcase @@ -102081,24 +109739,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub20_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub20_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub20_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub20_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub20_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub20_sgn = 1'h0; endcase @@ -102106,24 +109764,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub20_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub20_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub20_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub20_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub20_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub20_lk = 1'h0; endcase @@ -102131,24 +109789,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub20_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub20_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub20_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub20_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub20_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub20_sgl_pipe = 1'h1; endcase @@ -102156,24 +109814,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub20_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub20_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub20_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub20_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub20_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub20_SV_Etype = 2'h1; endcase @@ -102181,24 +109839,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub20_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub20_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub20_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub20_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub20_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub20_SV_Ptype = 2'h2; endcase @@ -102206,24 +109864,24 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub20_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub20_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub20_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub20_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub20_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub20_in1_sel = 3'h2; endcase @@ -102231,74 +109889,74 @@ module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_o always @* begin if (\initial ) begin end dec31_dec_sub20_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub20_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub20_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub20_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub20_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub20_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub20_in2_sel = 4'h1; endcase end always @* begin if (\initial ) begin end - dec31_dec_sub20_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub20_in3_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: - dec31_dec_sub20_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub20_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: - dec31_dec_sub20_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub20_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - dec31_dec_sub20_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub20_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: - dec31_dec_sub20_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub20_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub20_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub20_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: - dec31_dec_sub20_in3_sel = 2'h1; + dec31_dec_sub20_in3_sel = 3'h1; endcase end always @* begin if (\initial ) begin end dec31_dec_sub20_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub20_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub20_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub20_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub20_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub20_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub20_out_sel = 3'h0; endcase @@ -102314,20 +109972,20 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub21_SV_Etype; reg [1:0] dec31_dec_sub21_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub21_SV_Ptype; reg [1:0] dec31_dec_sub21_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub21_asmcode; reg [7:0] dec31_dec_sub21_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub21_br; reg dec31_dec_sub21_br; (* enum_base_type = "CRInSel" *) @@ -102339,7 +109997,7 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub21_cr_in; reg [2:0] dec31_dec_sub21_cr_in; (* enum_base_type = "CROutSel" *) @@ -102349,17 +110007,17 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub21_cr_out; reg [2:0] dec31_dec_sub21_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub21_cry_in; reg [1:0] dec31_dec_sub21_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub21_cry_out; reg dec31_dec_sub21_cry_out; (* enum_base_type = "Form" *) @@ -102393,34 +110051,37 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub21_form; reg [4:0] dec31_dec_sub21_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] dec31_dec_sub21_function_unit; - reg [13:0] dec31_dec_sub21_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] dec31_dec_sub21_function_unit; + reg [14:0] dec31_dec_sub21_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub21_in1_sel; reg [2:0] dec31_dec_sub21_in1_sel; (* enum_base_type = "In2Sel" *) @@ -102438,16 +110099,19 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub21_in2_sel; reg [3:0] dec31_dec_sub21_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [1:0] dec31_dec_sub21_in3_sel; - reg [1:0] dec31_dec_sub21_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub21_in3_sel; + reg [2:0] dec31_dec_sub21_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -102523,16 +110187,18 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub21_internal_op; reg [6:0] dec31_dec_sub21_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub21_inv_a; reg dec31_dec_sub21_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub21_inv_out; reg dec31_dec_sub21_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub21_is_32b; reg dec31_dec_sub21_is_32b; (* enum_base_type = "LdstLen" *) @@ -102541,10 +110207,10 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub21_ldst_len; reg [3:0] dec31_dec_sub21_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub21_lk; reg dec31_dec_sub21_lk; (* enum_base_type = "OutSel" *) @@ -102553,26 +110219,27 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub21_out_sel; reg [2:0] dec31_dec_sub21_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub21_rc_sel; reg [1:0] dec31_dec_sub21_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub21_rsrv; reg dec31_dec_sub21_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub21_sgl_pipe; reg dec31_dec_sub21_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub21_sgn; reg dec31_dec_sub21_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub21_sgn_ext; reg dec31_dec_sub21_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -102582,7 +110249,7 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub21_sv_cr_in; reg [2:0] dec31_dec_sub21_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -102592,7 +110259,7 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub21_sv_cr_out; reg [2:0] dec31_dec_sub21_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -102602,7 +110269,7 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub21_sv_in1; reg [2:0] dec31_dec_sub21_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -102612,7 +110279,7 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub21_sv_in2; reg [2:0] dec31_dec_sub21_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -102622,7 +110289,7 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub21_sv_in3; reg [2:0] dec31_dec_sub21_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -102632,7 +110299,7 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub21_sv_out; reg [2:0] dec31_dec_sub21_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -102642,7 +110309,7 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub21_sv_out2; reg [2:0] dec31_dec_sub21_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -102650,107 +110317,107 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub21_upd; reg [1:0] dec31_dec_sub21_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - dec31_dec_sub21_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub21_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: - dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: - dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: - dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: - dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: - dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: - dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: - dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: - dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: - dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: - dec31_dec_sub21_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: - dec31_dec_sub21_function_unit = 14'h0004; + dec31_dec_sub21_function_unit = 15'h0004; endcase end always @* begin if (\initial ) begin end dec31_dec_sub21_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub21_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub21_cr_in = 3'h0; endcase @@ -102758,48 +110425,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub21_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub21_cr_out = 3'h0; endcase @@ -102807,48 +110474,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub21_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub21_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub21_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub21_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub21_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub21_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub21_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub21_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub21_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub21_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: - dec31_dec_sub21_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub21_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub21_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub21_sv_in1 = 3'h2; endcase @@ -102856,48 +110523,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub21_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub21_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub21_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub21_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub21_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub21_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub21_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub21_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub21_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub21_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub21_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub21_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub21_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub21_sv_in2 = 3'h3; endcase @@ -102905,48 +110572,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub21_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub21_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub21_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub21_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub21_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub21_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub21_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub21_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub21_sv_in3 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub21_sv_in3 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: - dec31_dec_sub21_sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub21_sv_in3 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub21_sv_in3 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub21_sv_in3 = 3'h1; endcase @@ -102954,48 +110621,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub21_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub21_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub21_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub21_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub21_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub21_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub21_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub21_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub21_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub21_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub21_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub21_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub21_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub21_sv_out = 3'h0; endcase @@ -103003,48 +110670,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub21_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub21_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub21_sv_out2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub21_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub21_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub21_sv_out2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub21_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub21_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub21_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub21_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub21_sv_out2 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub21_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub21_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub21_sv_out2 = 3'h0; endcase @@ -103052,48 +110719,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub21_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub21_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub21_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub21_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub21_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub21_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub21_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub21_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub21_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub21_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub21_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub21_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub21_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub21_sv_cr_in = 3'h0; endcase @@ -103101,48 +110768,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub21_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub21_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub21_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub21_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub21_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub21_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub21_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub21_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub21_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub21_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub21_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub21_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub21_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub21_sv_cr_out = 3'h0; endcase @@ -103150,48 +110817,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub21_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub21_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub21_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub21_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub21_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub21_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub21_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub21_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub21_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub21_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub21_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub21_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub21_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub21_ldst_len = 4'h4; endcase @@ -103199,48 +110866,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub21_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub21_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub21_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub21_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub21_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub21_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub21_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub21_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub21_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub21_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub21_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub21_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub21_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub21_internal_op = 7'h26; endcase @@ -103248,48 +110915,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub21_upd = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub21_upd = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub21_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub21_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub21_upd = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub21_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub21_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub21_upd = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub21_upd = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub21_upd = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub21_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub21_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub21_upd = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub21_upd = 2'h2; endcase @@ -103297,48 +110964,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub21_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub21_rc_sel = 2'h0; endcase @@ -103346,48 +111013,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub21_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub21_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub21_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub21_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub21_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub21_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub21_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub21_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub21_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub21_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub21_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub21_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub21_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub21_cry_in = 2'h0; endcase @@ -103395,48 +111062,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub21_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub21_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub21_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub21_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub21_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub21_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub21_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub21_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub21_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub21_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub21_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub21_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub21_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub21_inv_a = 1'h0; endcase @@ -103444,48 +111111,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub21_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub21_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub21_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub21_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub21_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub21_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub21_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub21_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub21_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub21_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub21_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub21_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub21_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub21_inv_out = 1'h0; endcase @@ -103493,48 +111160,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub21_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub21_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub21_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub21_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub21_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub21_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub21_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub21_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub21_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub21_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub21_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub21_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub21_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub21_cry_out = 1'h0; endcase @@ -103542,48 +111209,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub21_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub21_br = 1'h0; endcase @@ -103591,48 +111258,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub21_sgn_ext = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub21_sgn_ext = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub21_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub21_sgn_ext = 1'h0; endcase @@ -103640,48 +111307,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub21_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub21_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub21_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub21_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub21_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub21_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub21_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub21_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub21_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub21_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub21_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub21_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub21_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub21_rsrv = 1'h0; endcase @@ -103689,48 +111356,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub21_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub21_is_32b = 1'h0; endcase @@ -103738,48 +111405,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub21_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub21_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub21_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub21_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub21_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub21_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub21_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub21_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub21_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub21_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub21_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub21_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub21_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub21_form = 5'h08; endcase @@ -103787,48 +111454,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub21_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub21_sgn = 1'h0; endcase @@ -103836,48 +111503,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub21_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub21_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub21_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub21_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub21_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub21_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub21_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub21_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub21_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub21_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub21_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub21_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub21_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub21_lk = 1'h0; endcase @@ -103885,48 +111552,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub21_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub21_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub21_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub21_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub21_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub21_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub21_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub21_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub21_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub21_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub21_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub21_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub21_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub21_sgl_pipe = 1'h1; endcase @@ -103934,91 +111601,91 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: - dec31_dec_sub21_asmcode = 8'h56; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_asmcode = 8'h6c; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub21_asmcode = 8'h57; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_asmcode = 8'h6d; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: - dec31_dec_sub21_asmcode = 8'h64; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_asmcode = 8'h84; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: - dec31_dec_sub21_asmcode = 8'h65; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_asmcode = 8'h85; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - dec31_dec_sub21_asmcode = 8'h68; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_asmcode = 8'h88; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: - dec31_dec_sub21_asmcode = 8'ha8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_asmcode = 8'hc8; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: - dec31_dec_sub21_asmcode = 8'hb1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_asmcode = 8'hd1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - dec31_dec_sub21_asmcode = 8'hb2; + dec31_dec_sub21_asmcode = 8'hd2; endcase end always @* begin if (\initial ) begin end dec31_dec_sub21_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub21_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub21_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub21_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub21_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub21_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub21_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub21_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub21_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub21_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub21_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub21_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub21_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub21_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub21_SV_Etype = 2'h1; endcase @@ -104026,48 +111693,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub21_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub21_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub21_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub21_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub21_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub21_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub21_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub21_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub21_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub21_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub21_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub21_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub21_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub21_SV_Ptype = 2'h2; endcase @@ -104075,48 +111742,48 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub21_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub21_in1_sel = 3'h2; endcase @@ -104124,146 +111791,146 @@ module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_o always @* begin if (\initial ) begin end dec31_dec_sub21_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub21_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub21_in2_sel = 4'h1; endcase end always @* begin if (\initial ) begin end - dec31_dec_sub21_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub21_in3_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: - dec31_dec_sub21_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: - dec31_dec_sub21_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: - dec31_dec_sub21_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub21_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: - dec31_dec_sub21_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: - dec31_dec_sub21_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: - dec31_dec_sub21_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - dec31_dec_sub21_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: - dec31_dec_sub21_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: - dec31_dec_sub21_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: - dec31_dec_sub21_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - dec31_dec_sub21_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: - dec31_dec_sub21_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub21_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: - dec31_dec_sub21_in3_sel = 2'h1; + dec31_dec_sub21_in3_sel = 3'h1; endcase end always @* begin if (\initial ) begin end dec31_dec_sub21_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1a: dec31_dec_sub21_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub21_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub21_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub21_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub21_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub21_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub21_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub21_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub21_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub21_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub21_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub21_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub21_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub21_out_sel = 3'h0; endcase @@ -104279,20 +111946,20 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub22_SV_Etype; reg [1:0] dec31_dec_sub22_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub22_SV_Ptype; reg [1:0] dec31_dec_sub22_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub22_asmcode; reg [7:0] dec31_dec_sub22_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub22_br; reg dec31_dec_sub22_br; (* enum_base_type = "CRInSel" *) @@ -104304,7 +111971,7 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub22_cr_in; reg [2:0] dec31_dec_sub22_cr_in; (* enum_base_type = "CROutSel" *) @@ -104314,17 +111981,17 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub22_cr_out; reg [2:0] dec31_dec_sub22_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub22_cry_in; reg [1:0] dec31_dec_sub22_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub22_cry_out; reg dec31_dec_sub22_cry_out; (* enum_base_type = "Form" *) @@ -104358,34 +112025,37 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub22_form; reg [4:0] dec31_dec_sub22_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] dec31_dec_sub22_function_unit; - reg [13:0] dec31_dec_sub22_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] dec31_dec_sub22_function_unit; + reg [14:0] dec31_dec_sub22_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub22_in1_sel; reg [2:0] dec31_dec_sub22_in1_sel; (* enum_base_type = "In2Sel" *) @@ -104403,16 +112073,19 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub22_in2_sel; reg [3:0] dec31_dec_sub22_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [1:0] dec31_dec_sub22_in3_sel; - reg [1:0] dec31_dec_sub22_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub22_in3_sel; + reg [2:0] dec31_dec_sub22_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -104488,16 +112161,18 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub22_internal_op; reg [6:0] dec31_dec_sub22_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub22_inv_a; reg dec31_dec_sub22_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub22_inv_out; reg dec31_dec_sub22_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub22_is_32b; reg dec31_dec_sub22_is_32b; (* enum_base_type = "LdstLen" *) @@ -104506,10 +112181,10 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub22_ldst_len; reg [3:0] dec31_dec_sub22_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub22_lk; reg dec31_dec_sub22_lk; (* enum_base_type = "OutSel" *) @@ -104518,26 +112193,27 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub22_out_sel; reg [2:0] dec31_dec_sub22_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub22_rc_sel; reg [1:0] dec31_dec_sub22_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub22_rsrv; reg dec31_dec_sub22_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub22_sgl_pipe; reg dec31_dec_sub22_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub22_sgn; reg dec31_dec_sub22_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub22_sgn_ext; reg dec31_dec_sub22_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -104547,7 +112223,7 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub22_sv_cr_in; reg [2:0] dec31_dec_sub22_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -104557,7 +112233,7 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub22_sv_cr_out; reg [2:0] dec31_dec_sub22_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -104567,7 +112243,7 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub22_sv_in1; reg [2:0] dec31_dec_sub22_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -104577,7 +112253,7 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub22_sv_in2; reg [2:0] dec31_dec_sub22_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -104587,7 +112263,7 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub22_sv_in3; reg [2:0] dec31_dec_sub22_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -104597,7 +112273,7 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub22_sv_out; reg [2:0] dec31_dec_sub22_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -104607,7 +112283,7 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub22_sv_out2; reg [2:0] dec31_dec_sub22_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -104615,119 +112291,119 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub22_upd; reg [1:0] dec31_dec_sub22_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - dec31_dec_sub22_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub22_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: - dec31_dec_sub22_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: - dec31_dec_sub22_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: - dec31_dec_sub22_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - dec31_dec_sub22_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: - dec31_dec_sub22_function_unit = 14'h0800; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_function_unit = 15'h0800; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: - dec31_dec_sub22_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub22_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - dec31_dec_sub22_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - dec31_dec_sub22_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: - dec31_dec_sub22_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: - dec31_dec_sub22_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: - dec31_dec_sub22_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: - dec31_dec_sub22_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: - dec31_dec_sub22_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - dec31_dec_sub22_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: - dec31_dec_sub22_function_unit = 14'h0002; + dec31_dec_sub22_function_unit = 15'h0002; endcase end always @* begin if (\initial ) begin end dec31_dec_sub22_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub22_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub22_cr_in = 3'h0; endcase @@ -104735,54 +112411,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub22_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub22_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub22_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub22_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub22_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub22_cr_out = 3'h0; endcase @@ -104790,54 +112466,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub22_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub22_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub22_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub22_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub22_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub22_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub22_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub22_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub22_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub22_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub22_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub22_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub22_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub22_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub22_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub22_sv_in1 = 3'h0; endcase @@ -104845,54 +112521,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub22_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub22_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub22_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub22_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub22_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub22_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub22_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub22_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub22_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub22_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub22_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub22_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub22_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub22_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub22_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub22_sv_in2 = 3'h0; endcase @@ -104900,54 +112576,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub22_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub22_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub22_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub22_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub22_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub22_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub22_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub22_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub22_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: - dec31_dec_sub22_sv_in3 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: - dec31_dec_sub22_sv_in3 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub22_sv_in3 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: - dec31_dec_sub22_sv_in3 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub22_sv_in3 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - dec31_dec_sub22_sv_in3 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub22_sv_in3 = 3'h0; endcase @@ -104955,54 +112631,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub22_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub22_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub22_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub22_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub22_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub22_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub22_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub22_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub22_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub22_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub22_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub22_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub22_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub22_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub22_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub22_sv_out = 3'h0; endcase @@ -105010,54 +112686,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub22_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub22_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub22_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub22_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub22_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub22_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub22_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub22_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub22_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub22_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub22_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub22_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub22_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub22_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub22_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub22_sv_out2 = 3'h0; endcase @@ -105065,54 +112741,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub22_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub22_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub22_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub22_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub22_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub22_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub22_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub22_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub22_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub22_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub22_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub22_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub22_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub22_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub22_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub22_sv_cr_in = 3'h0; endcase @@ -105120,54 +112796,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub22_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub22_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub22_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub22_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub22_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub22_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub22_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub22_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub22_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: - dec31_dec_sub22_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: - dec31_dec_sub22_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub22_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: - dec31_dec_sub22_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub22_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - dec31_dec_sub22_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub22_sv_cr_out = 3'h0; endcase @@ -105175,54 +112851,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub22_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub22_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub22_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub22_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub22_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub22_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub22_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub22_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub22_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub22_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub22_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub22_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub22_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub22_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub22_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub22_ldst_len = 4'h0; endcase @@ -105230,54 +112906,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub22_internal_op = 7'h01; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub22_internal_op = 7'h01; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub22_internal_op = 7'h01; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub22_internal_op = 7'h01; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub22_internal_op = 7'h1c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub22_internal_op = 7'h21; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub22_internal_op = 7'h01; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub22_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub22_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub22_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub22_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub22_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub22_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub22_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub22_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub22_internal_op = 7'h01; endcase @@ -105285,54 +112961,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub22_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub22_upd = 2'h0; endcase @@ -105340,54 +113016,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub22_rc_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub22_rc_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub22_rc_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub22_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub22_rc_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub22_rc_sel = 2'h0; endcase @@ -105395,54 +113071,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub22_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub22_cry_in = 2'h0; endcase @@ -105450,109 +113126,109 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub22_asmcode = 8'h2e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub22_asmcode = 8'h2f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub22_asmcode = 8'h30; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub22_asmcode = 8'h31; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub22_asmcode = 8'h32; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: - dec31_dec_sub22_asmcode = 8'h49; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_asmcode = 8'h5f; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub22_asmcode = 8'h4a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_asmcode = 8'h60; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - dec31_dec_sub22_asmcode = 8'h5d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_asmcode = 8'h7d; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - dec31_dec_sub22_asmcode = 8'h66; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_asmcode = 8'h86; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: - dec31_dec_sub22_asmcode = 8'ha9; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_asmcode = 8'hc9; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: - dec31_dec_sub22_asmcode = 8'haf; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_asmcode = 8'hcf; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: - dec31_dec_sub22_asmcode = 8'hb4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_asmcode = 8'hdd; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: - dec31_dec_sub22_asmcode = 8'hb5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_asmcode = 8'hde; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: - dec31_dec_sub22_asmcode = 8'hba; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_asmcode = 8'he3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - dec31_dec_sub22_asmcode = 8'hbb; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_asmcode = 8'he4; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: - dec31_dec_sub22_asmcode = 8'hca; + dec31_dec_sub22_asmcode = 8'hf3; endcase end always @* begin if (\initial ) begin end dec31_dec_sub22_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub22_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub22_inv_a = 1'h0; endcase @@ -105560,54 +113236,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub22_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub22_inv_out = 1'h0; endcase @@ -105615,54 +113291,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub22_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub22_cry_out = 1'h0; endcase @@ -105670,54 +113346,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub22_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub22_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub22_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub22_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub22_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub22_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub22_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub22_br = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub22_br = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub22_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub22_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub22_br = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub22_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub22_br = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub22_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub22_br = 1'h0; endcase @@ -105725,54 +113401,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub22_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub22_sgn_ext = 1'h0; endcase @@ -105780,54 +113456,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub22_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub22_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub22_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub22_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub22_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub22_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub22_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub22_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub22_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub22_rsrv = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub22_rsrv = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub22_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub22_rsrv = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub22_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub22_rsrv = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub22_rsrv = 1'h0; endcase @@ -105835,54 +113511,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub22_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub22_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub22_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub22_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub22_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub22_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub22_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub22_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub22_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub22_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub22_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub22_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub22_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub22_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub22_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub22_form = 5'h08; endcase @@ -105890,54 +113566,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub22_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub22_is_32b = 1'h0; endcase @@ -105945,54 +113621,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub22_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub22_sgn = 1'h0; endcase @@ -106000,54 +113676,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub22_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub22_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub22_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub22_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub22_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub22_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub22_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub22_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub22_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub22_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub22_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub22_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub22_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub22_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub22_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub22_lk = 1'h0; endcase @@ -106055,54 +113731,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub22_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub22_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub22_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub22_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub22_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub22_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub22_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub22_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub22_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub22_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub22_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub22_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub22_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub22_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub22_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub22_sgl_pipe = 1'h1; endcase @@ -106110,54 +113786,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub22_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub22_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub22_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub22_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub22_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub22_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub22_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub22_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub22_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub22_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub22_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub22_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub22_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub22_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub22_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub22_SV_Etype = 2'h0; endcase @@ -106165,54 +113841,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub22_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub22_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub22_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub22_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub22_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub22_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub22_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub22_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub22_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub22_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub22_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub22_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub22_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub22_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub22_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub22_SV_Ptype = 2'h0; endcase @@ -106220,54 +113896,54 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub22_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub22_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub22_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub22_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub22_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub22_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub22_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub22_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub22_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub22_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub22_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub22_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub22_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub22_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub22_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub22_in1_sel = 3'h0; endcase @@ -106275,164 +113951,164 @@ module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_o always @* begin if (\initial ) begin end dec31_dec_sub22_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub22_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub22_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub22_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub22_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub22_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub22_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub22_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub22_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub22_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub22_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub22_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub22_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub22_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub22_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub22_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub22_in2_sel = 4'h0; endcase end always @* begin if (\initial ) begin end - dec31_dec_sub22_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub22_in3_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: - dec31_dec_sub22_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: - dec31_dec_sub22_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: - dec31_dec_sub22_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - dec31_dec_sub22_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: - dec31_dec_sub22_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: - dec31_dec_sub22_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub22_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - dec31_dec_sub22_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - dec31_dec_sub22_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: - dec31_dec_sub22_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: - dec31_dec_sub22_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: - dec31_dec_sub22_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: - dec31_dec_sub22_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: - dec31_dec_sub22_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - dec31_dec_sub22_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub22_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: - dec31_dec_sub22_in3_sel = 2'h0; + dec31_dec_sub22_in3_sel = 3'h0; endcase end always @* begin if (\initial ) begin end dec31_dec_sub22_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub22_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub22_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub22_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub22_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub22_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub22_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub22_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub22_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub22_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h15: dec31_dec_sub22_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub22_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub22_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub22_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub22_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub22_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub22_out_sel = 3'h0; endcase @@ -106448,20 +114124,20 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub23_SV_Etype; reg [1:0] dec31_dec_sub23_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub23_SV_Ptype; reg [1:0] dec31_dec_sub23_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub23_asmcode; reg [7:0] dec31_dec_sub23_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub23_br; reg dec31_dec_sub23_br; (* enum_base_type = "CRInSel" *) @@ -106473,7 +114149,7 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub23_cr_in; reg [2:0] dec31_dec_sub23_cr_in; (* enum_base_type = "CROutSel" *) @@ -106483,17 +114159,17 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub23_cr_out; reg [2:0] dec31_dec_sub23_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub23_cry_in; reg [1:0] dec31_dec_sub23_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub23_cry_out; reg dec31_dec_sub23_cry_out; (* enum_base_type = "Form" *) @@ -106527,34 +114203,37 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub23_form; reg [4:0] dec31_dec_sub23_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] dec31_dec_sub23_function_unit; - reg [13:0] dec31_dec_sub23_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] dec31_dec_sub23_function_unit; + reg [14:0] dec31_dec_sub23_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub23_in1_sel; reg [2:0] dec31_dec_sub23_in1_sel; (* enum_base_type = "In2Sel" *) @@ -106572,16 +114251,19 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub23_in2_sel; reg [3:0] dec31_dec_sub23_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [1:0] dec31_dec_sub23_in3_sel; - reg [1:0] dec31_dec_sub23_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub23_in3_sel; + reg [2:0] dec31_dec_sub23_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -106657,16 +114339,18 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub23_internal_op; reg [6:0] dec31_dec_sub23_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub23_inv_a; reg dec31_dec_sub23_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub23_inv_out; reg dec31_dec_sub23_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub23_is_32b; reg dec31_dec_sub23_is_32b; (* enum_base_type = "LdstLen" *) @@ -106675,10 +114359,10 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub23_ldst_len; reg [3:0] dec31_dec_sub23_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub23_lk; reg dec31_dec_sub23_lk; (* enum_base_type = "OutSel" *) @@ -106687,26 +114371,27 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub23_out_sel; reg [2:0] dec31_dec_sub23_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub23_rc_sel; reg [1:0] dec31_dec_sub23_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub23_rsrv; reg dec31_dec_sub23_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub23_sgl_pipe; reg dec31_dec_sub23_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub23_sgn; reg dec31_dec_sub23_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub23_sgn_ext; reg dec31_dec_sub23_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -106716,7 +114401,7 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub23_sv_cr_in; reg [2:0] dec31_dec_sub23_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -106726,7 +114411,7 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub23_sv_cr_out; reg [2:0] dec31_dec_sub23_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -106736,7 +114421,7 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub23_sv_in1; reg [2:0] dec31_dec_sub23_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -106746,7 +114431,7 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub23_sv_in2; reg [2:0] dec31_dec_sub23_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -106756,7 +114441,7 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub23_sv_in3; reg [2:0] dec31_dec_sub23_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -106766,7 +114451,7 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub23_sv_out; reg [2:0] dec31_dec_sub23_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -106776,7 +114461,7 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub23_sv_out2; reg [2:0] dec31_dec_sub23_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -106784,107 +114469,173 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub23_upd; reg [1:0] dec31_dec_sub23_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - dec31_dec_sub23_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub23_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: - dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: - dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: - dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: - dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: - dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: - dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: - dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: - dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: - dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: - dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: - dec31_dec_sub23_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - dec31_dec_sub23_function_unit = 14'h0004; + dec31_dec_sub23_function_unit = 15'h0004; endcase end always @* begin if (\initial ) begin end dec31_dec_sub23_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + dec31_dec_sub23_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub23_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub23_cr_in = 3'h0; endcase @@ -106892,48 +114643,81 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + dec31_dec_sub23_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub23_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub23_cr_out = 3'h0; endcase @@ -106941,48 +114725,81 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub23_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub23_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + dec31_dec_sub23_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + dec31_dec_sub23_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + dec31_dec_sub23_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + dec31_dec_sub23_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + dec31_dec_sub23_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + dec31_dec_sub23_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub23_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub23_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub23_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub23_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub23_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub23_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - dec31_dec_sub23_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub23_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ - 5'h0d: + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + dec31_dec_sub23_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + dec31_dec_sub23_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + dec31_dec_sub23_sv_in1 = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: dec31_dec_sub23_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + dec31_dec_sub23_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h0d: + dec31_dec_sub23_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub23_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: - dec31_dec_sub23_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_sv_in1 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub23_sv_in1 = 3'h2; endcase @@ -106990,48 +114807,81 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub23_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub23_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + dec31_dec_sub23_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + dec31_dec_sub23_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + dec31_dec_sub23_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + dec31_dec_sub23_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + dec31_dec_sub23_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + dec31_dec_sub23_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub23_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub23_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub23_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub23_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub23_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub23_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub23_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub23_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + dec31_dec_sub23_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + dec31_dec_sub23_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + dec31_dec_sub23_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + dec31_dec_sub23_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + dec31_dec_sub23_sv_in2 = 3'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub23_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub23_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub23_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub23_sv_in2 = 3'h3; endcase @@ -107039,48 +114889,81 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub23_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub23_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + dec31_dec_sub23_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + dec31_dec_sub23_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + dec31_dec_sub23_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + dec31_dec_sub23_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + dec31_dec_sub23_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + dec31_dec_sub23_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub23_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub23_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub23_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub23_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub23_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub23_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - dec31_dec_sub23_sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub23_sv_in3 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + dec31_dec_sub23_sv_in3 = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + dec31_dec_sub23_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + dec31_dec_sub23_sv_in3 = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + dec31_dec_sub23_sv_in3 = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + dec31_dec_sub23_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: - dec31_dec_sub23_sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub23_sv_in3 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: - dec31_dec_sub23_sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_sv_in3 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub23_sv_in3 = 3'h1; endcase @@ -107088,48 +114971,81 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub23_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub23_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + dec31_dec_sub23_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + dec31_dec_sub23_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + dec31_dec_sub23_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + dec31_dec_sub23_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + dec31_dec_sub23_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + dec31_dec_sub23_sv_out = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub23_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub23_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub23_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub23_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub23_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub23_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub23_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub23_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + dec31_dec_sub23_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + dec31_dec_sub23_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + dec31_dec_sub23_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + dec31_dec_sub23_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + dec31_dec_sub23_sv_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub23_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub23_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub23_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub23_sv_out = 3'h0; endcase @@ -107137,48 +115053,81 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub23_sv_out2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub23_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + dec31_dec_sub23_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + dec31_dec_sub23_sv_out2 = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + dec31_dec_sub23_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + dec31_dec_sub23_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + dec31_dec_sub23_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + dec31_dec_sub23_sv_out2 = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub23_sv_out2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub23_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub23_sv_out2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub23_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub23_sv_out2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub23_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub23_sv_out2 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub23_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + dec31_dec_sub23_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + dec31_dec_sub23_sv_out2 = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + dec31_dec_sub23_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + dec31_dec_sub23_sv_out2 = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + dec31_dec_sub23_sv_out2 = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub23_sv_out2 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub23_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub23_sv_out2 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub23_sv_out2 = 3'h0; endcase @@ -107186,48 +115135,81 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub23_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub23_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + dec31_dec_sub23_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + dec31_dec_sub23_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + dec31_dec_sub23_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + dec31_dec_sub23_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + dec31_dec_sub23_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + dec31_dec_sub23_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub23_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub23_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub23_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub23_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub23_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub23_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub23_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub23_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + dec31_dec_sub23_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + dec31_dec_sub23_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + dec31_dec_sub23_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + dec31_dec_sub23_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + dec31_dec_sub23_sv_cr_in = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub23_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub23_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub23_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub23_sv_cr_in = 3'h0; endcase @@ -107235,48 +115217,81 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub23_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub23_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + dec31_dec_sub23_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + dec31_dec_sub23_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + dec31_dec_sub23_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + dec31_dec_sub23_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + dec31_dec_sub23_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + dec31_dec_sub23_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub23_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub23_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub23_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub23_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub23_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub23_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub23_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub23_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + dec31_dec_sub23_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + dec31_dec_sub23_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + dec31_dec_sub23_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + dec31_dec_sub23_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + dec31_dec_sub23_sv_cr_out = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub23_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub23_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub23_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub23_sv_cr_out = 3'h0; endcase @@ -107284,48 +115299,81 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub23_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub23_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + dec31_dec_sub23_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + dec31_dec_sub23_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + dec31_dec_sub23_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + dec31_dec_sub23_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + dec31_dec_sub23_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + dec31_dec_sub23_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub23_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub23_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub23_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub23_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub23_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub23_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub23_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub23_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + dec31_dec_sub23_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + dec31_dec_sub23_ldst_len = 4'h8; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + dec31_dec_sub23_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + dec31_dec_sub23_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + dec31_dec_sub23_ldst_len = 4'h4; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub23_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub23_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub23_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub23_ldst_len = 4'h4; endcase @@ -107333,48 +115381,81 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub23_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub23_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + dec31_dec_sub23_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + dec31_dec_sub23_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + dec31_dec_sub23_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + dec31_dec_sub23_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + dec31_dec_sub23_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + dec31_dec_sub23_internal_op = 7'h25; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub23_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub23_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub23_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub23_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub23_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub23_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub23_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub23_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + dec31_dec_sub23_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + dec31_dec_sub23_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + dec31_dec_sub23_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + dec31_dec_sub23_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + dec31_dec_sub23_internal_op = 7'h26; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub23_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub23_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub23_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub23_internal_op = 7'h26; endcase @@ -107382,48 +115463,81 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub23_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub23_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + dec31_dec_sub23_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + dec31_dec_sub23_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + dec31_dec_sub23_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + dec31_dec_sub23_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + dec31_dec_sub23_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + dec31_dec_sub23_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub23_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub23_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub23_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub23_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub23_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub23_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub23_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub23_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + dec31_dec_sub23_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + dec31_dec_sub23_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + dec31_dec_sub23_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + dec31_dec_sub23_upd = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + dec31_dec_sub23_upd = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub23_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub23_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub23_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub23_upd = 2'h0; endcase @@ -107431,48 +115545,81 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub23_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + dec31_dec_sub23_rc_sel = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub23_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub23_rc_sel = 2'h0; endcase @@ -107480,48 +115627,81 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub23_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub23_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + dec31_dec_sub23_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + dec31_dec_sub23_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + dec31_dec_sub23_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + dec31_dec_sub23_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + dec31_dec_sub23_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + dec31_dec_sub23_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub23_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub23_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub23_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub23_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub23_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub23_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub23_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub23_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + dec31_dec_sub23_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + dec31_dec_sub23_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + dec31_dec_sub23_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + dec31_dec_sub23_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + dec31_dec_sub23_cry_in = 2'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub23_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub23_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub23_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub23_cry_in = 2'h0; endcase @@ -107529,97 +115709,163 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: - dec31_dec_sub23_asmcode = 8'h50; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_asmcode = 8'h66; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: - dec31_dec_sub23_asmcode = 8'h51; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_asmcode = 8'h67; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + dec31_dec_sub23_asmcode = 8'h73; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + dec31_dec_sub23_asmcode = 8'h75; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + dec31_dec_sub23_asmcode = 8'h77; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + dec31_dec_sub23_asmcode = 8'h76; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + dec31_dec_sub23_asmcode = 8'h6f; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + dec31_dec_sub23_asmcode = 8'h71; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: - dec31_dec_sub23_asmcode = 8'h5b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_asmcode = 8'h7b; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: - dec31_dec_sub23_asmcode = 8'h5c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_asmcode = 8'h7c; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: - dec31_dec_sub23_asmcode = 8'h60; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_asmcode = 8'h80; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: - dec31_dec_sub23_asmcode = 8'h61; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_asmcode = 8'h81; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: - dec31_dec_sub23_asmcode = 8'h6a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_asmcode = 8'h8a; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub23_asmcode = 8'h6b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_asmcode = 8'h8b; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - dec31_dec_sub23_asmcode = 8'hab; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_asmcode = 8'hcb; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: - dec31_dec_sub23_asmcode = 8'hac; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_asmcode = 8'hcc; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + dec31_dec_sub23_asmcode = 8'hd8; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + dec31_dec_sub23_asmcode = 8'hda; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + dec31_dec_sub23_asmcode = 8'hdb; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + dec31_dec_sub23_asmcode = 8'hd4; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + /* empty */; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: - dec31_dec_sub23_asmcode = 8'hb7; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_asmcode = 8'he0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: - dec31_dec_sub23_asmcode = 8'hb8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_asmcode = 8'he1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: - dec31_dec_sub23_asmcode = 8'hbd; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_asmcode = 8'he6; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - dec31_dec_sub23_asmcode = 8'hbe; + dec31_dec_sub23_asmcode = 8'he7; endcase end always @* begin if (\initial ) begin end dec31_dec_sub23_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub23_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub23_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + dec31_dec_sub23_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + dec31_dec_sub23_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + dec31_dec_sub23_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + dec31_dec_sub23_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + dec31_dec_sub23_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + dec31_dec_sub23_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub23_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub23_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub23_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub23_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub23_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub23_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub23_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub23_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + dec31_dec_sub23_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + dec31_dec_sub23_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + dec31_dec_sub23_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + dec31_dec_sub23_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + dec31_dec_sub23_inv_a = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub23_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub23_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub23_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub23_inv_a = 1'h0; endcase @@ -107627,48 +115873,81 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub23_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub23_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + dec31_dec_sub23_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + dec31_dec_sub23_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + dec31_dec_sub23_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + dec31_dec_sub23_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + dec31_dec_sub23_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + dec31_dec_sub23_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub23_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub23_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub23_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub23_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub23_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub23_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub23_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub23_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + dec31_dec_sub23_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + dec31_dec_sub23_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + dec31_dec_sub23_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + dec31_dec_sub23_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + dec31_dec_sub23_inv_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub23_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub23_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub23_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub23_inv_out = 1'h0; endcase @@ -107676,48 +115955,81 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub23_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub23_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + dec31_dec_sub23_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + dec31_dec_sub23_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + dec31_dec_sub23_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + dec31_dec_sub23_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + dec31_dec_sub23_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + dec31_dec_sub23_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub23_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub23_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub23_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub23_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub23_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub23_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub23_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub23_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + dec31_dec_sub23_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + dec31_dec_sub23_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + dec31_dec_sub23_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + dec31_dec_sub23_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + dec31_dec_sub23_cry_out = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub23_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub23_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub23_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub23_cry_out = 1'h0; endcase @@ -107725,48 +116037,81 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + dec31_dec_sub23_br = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub23_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub23_br = 1'h0; endcase @@ -107774,48 +116119,81 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + dec31_dec_sub23_sgn_ext = 1'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub23_sgn_ext = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub23_sgn_ext = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + dec31_dec_sub23_sgn_ext = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub23_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub23_sgn_ext = 1'h0; endcase @@ -107823,48 +116201,81 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub23_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub23_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + dec31_dec_sub23_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + dec31_dec_sub23_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + dec31_dec_sub23_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + dec31_dec_sub23_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + dec31_dec_sub23_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + dec31_dec_sub23_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub23_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub23_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub23_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub23_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub23_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub23_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub23_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub23_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + dec31_dec_sub23_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + dec31_dec_sub23_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + dec31_dec_sub23_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + dec31_dec_sub23_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + dec31_dec_sub23_rsrv = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub23_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub23_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub23_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub23_rsrv = 1'h0; endcase @@ -107872,48 +116283,81 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub23_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub23_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + dec31_dec_sub23_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + dec31_dec_sub23_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + dec31_dec_sub23_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + dec31_dec_sub23_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + dec31_dec_sub23_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + dec31_dec_sub23_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub23_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub23_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub23_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub23_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub23_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub23_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub23_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub23_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + dec31_dec_sub23_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + dec31_dec_sub23_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + dec31_dec_sub23_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + dec31_dec_sub23_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + dec31_dec_sub23_form = 5'h08; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub23_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub23_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub23_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub23_form = 5'h08; endcase @@ -107921,48 +116365,81 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + dec31_dec_sub23_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + dec31_dec_sub23_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + dec31_dec_sub23_is_32b = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + dec31_dec_sub23_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + dec31_dec_sub23_is_32b = 1'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub23_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub23_is_32b = 1'h0; endcase @@ -107970,48 +116447,81 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + dec31_dec_sub23_sgn = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub23_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub23_sgn = 1'h0; endcase @@ -108019,48 +116529,81 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub23_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub23_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + dec31_dec_sub23_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + dec31_dec_sub23_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + dec31_dec_sub23_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + dec31_dec_sub23_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + dec31_dec_sub23_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + dec31_dec_sub23_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub23_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub23_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub23_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub23_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub23_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub23_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub23_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub23_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + dec31_dec_sub23_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + dec31_dec_sub23_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + dec31_dec_sub23_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + dec31_dec_sub23_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + dec31_dec_sub23_lk = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub23_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub23_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub23_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub23_lk = 1'h0; endcase @@ -108068,48 +116611,81 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub23_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub23_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + dec31_dec_sub23_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + dec31_dec_sub23_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + dec31_dec_sub23_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + dec31_dec_sub23_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + dec31_dec_sub23_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + dec31_dec_sub23_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub23_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub23_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub23_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub23_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub23_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub23_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub23_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub23_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + dec31_dec_sub23_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + dec31_dec_sub23_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + dec31_dec_sub23_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + dec31_dec_sub23_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + dec31_dec_sub23_sgl_pipe = 1'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub23_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub23_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub23_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub23_sgl_pipe = 1'h1; endcase @@ -108117,48 +116693,81 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub23_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub23_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + dec31_dec_sub23_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + dec31_dec_sub23_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + dec31_dec_sub23_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + dec31_dec_sub23_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + dec31_dec_sub23_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + dec31_dec_sub23_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub23_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub23_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub23_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub23_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub23_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub23_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub23_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub23_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + dec31_dec_sub23_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + dec31_dec_sub23_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + dec31_dec_sub23_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + dec31_dec_sub23_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + dec31_dec_sub23_SV_Etype = 2'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub23_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub23_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub23_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub23_SV_Etype = 2'h1; endcase @@ -108166,48 +116775,81 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub23_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub23_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub23_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub23_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub23_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub23_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub23_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub23_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub23_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub23_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + dec31_dec_sub23_SV_Ptype = 2'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub23_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub23_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub23_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub23_SV_Ptype = 2'h2; endcase @@ -108215,48 +116857,81 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + dec31_dec_sub23_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + dec31_dec_sub23_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + dec31_dec_sub23_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + dec31_dec_sub23_in1_sel = 3'h2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + dec31_dec_sub23_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + dec31_dec_sub23_in1_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub23_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub23_in1_sel = 3'h2; endcase @@ -108264,146 +116939,245 @@ module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_o always @* begin if (\initial ) begin end dec31_dec_sub23_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + dec31_dec_sub23_in2_sel = 4'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub23_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub23_in2_sel = 4'h1; endcase end always @* begin if (\initial ) begin end - dec31_dec_sub23_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub23_in3_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: - dec31_dec_sub23_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: - dec31_dec_sub23_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + dec31_dec_sub23_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + dec31_dec_sub23_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + dec31_dec_sub23_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + dec31_dec_sub23_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + dec31_dec_sub23_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + dec31_dec_sub23_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: - dec31_dec_sub23_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: - dec31_dec_sub23_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: - dec31_dec_sub23_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: - dec31_dec_sub23_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: - dec31_dec_sub23_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub23_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - dec31_dec_sub23_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: - dec31_dec_sub23_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + dec31_dec_sub23_in3_sel = 3'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + dec31_dec_sub23_in3_sel = 3'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + dec31_dec_sub23_in3_sel = 3'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + dec31_dec_sub23_in3_sel = 3'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + dec31_dec_sub23_in3_sel = 3'h3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: - dec31_dec_sub23_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: - dec31_dec_sub23_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: - dec31_dec_sub23_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub23_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - dec31_dec_sub23_in3_sel = 2'h1; + dec31_dec_sub23_in3_sel = 3'h1; endcase end always @* begin if (\initial ) begin end dec31_dec_sub23_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub23_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub23_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h12: + dec31_dec_sub23_out_sel = 3'h5; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h13: + dec31_dec_sub23_out_sel = 3'h5; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1a: + dec31_dec_sub23_out_sel = 3'h5; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1b: + dec31_dec_sub23_out_sel = 3'h5; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h10: + dec31_dec_sub23_out_sel = 3'h5; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h11: + dec31_dec_sub23_out_sel = 3'h5; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub23_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0a: dec31_dec_sub23_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub23_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub23_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub23_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub23_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub23_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub23_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h16: + dec31_dec_sub23_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h17: + dec31_dec_sub23_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h1e: + dec31_dec_sub23_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h14: + dec31_dec_sub23_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ + 5'h15: + dec31_dec_sub23_out_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub23_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub23_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub23_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub23_out_sel = 3'h0; endcase @@ -108419,20 +117193,20 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub24_SV_Etype; reg [1:0] dec31_dec_sub24_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub24_SV_Ptype; reg [1:0] dec31_dec_sub24_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub24_asmcode; reg [7:0] dec31_dec_sub24_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub24_br; reg dec31_dec_sub24_br; (* enum_base_type = "CRInSel" *) @@ -108444,7 +117218,7 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub24_cr_in; reg [2:0] dec31_dec_sub24_cr_in; (* enum_base_type = "CROutSel" *) @@ -108454,17 +117228,17 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub24_cr_out; reg [2:0] dec31_dec_sub24_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub24_cry_in; reg [1:0] dec31_dec_sub24_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub24_cry_out; reg dec31_dec_sub24_cry_out; (* enum_base_type = "Form" *) @@ -108498,34 +117272,37 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub24_form; reg [4:0] dec31_dec_sub24_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] dec31_dec_sub24_function_unit; - reg [13:0] dec31_dec_sub24_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] dec31_dec_sub24_function_unit; + reg [14:0] dec31_dec_sub24_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub24_in1_sel; reg [2:0] dec31_dec_sub24_in1_sel; (* enum_base_type = "In2Sel" *) @@ -108543,16 +117320,19 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub24_in2_sel; reg [3:0] dec31_dec_sub24_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [1:0] dec31_dec_sub24_in3_sel; - reg [1:0] dec31_dec_sub24_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub24_in3_sel; + reg [2:0] dec31_dec_sub24_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -108628,16 +117408,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub24_internal_op; reg [6:0] dec31_dec_sub24_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub24_inv_a; reg dec31_dec_sub24_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub24_inv_out; reg dec31_dec_sub24_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub24_is_32b; reg dec31_dec_sub24_is_32b; (* enum_base_type = "LdstLen" *) @@ -108646,10 +117428,10 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub24_ldst_len; reg [3:0] dec31_dec_sub24_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub24_lk; reg dec31_dec_sub24_lk; (* enum_base_type = "OutSel" *) @@ -108658,26 +117440,27 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub24_out_sel; reg [2:0] dec31_dec_sub24_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub24_rc_sel; reg [1:0] dec31_dec_sub24_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub24_rsrv; reg dec31_dec_sub24_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub24_sgl_pipe; reg dec31_dec_sub24_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub24_sgn; reg dec31_dec_sub24_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub24_sgn_ext; reg dec31_dec_sub24_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -108687,7 +117470,7 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub24_sv_cr_in; reg [2:0] dec31_dec_sub24_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -108697,7 +117480,7 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub24_sv_cr_out; reg [2:0] dec31_dec_sub24_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -108707,7 +117490,7 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub24_sv_in1; reg [2:0] dec31_dec_sub24_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -108717,7 +117500,7 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub24_sv_in2; reg [2:0] dec31_dec_sub24_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -108727,7 +117510,7 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub24_sv_in3; reg [2:0] dec31_dec_sub24_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -108737,7 +117520,7 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub24_sv_out; reg [2:0] dec31_dec_sub24_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -108747,7 +117530,7 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub24_sv_out2; reg [2:0] dec31_dec_sub24_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -108755,47 +117538,47 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub24_upd; reg [1:0] dec31_dec_sub24_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - dec31_dec_sub24_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub24_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub24_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub24_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - dec31_dec_sub24_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub24_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: - dec31_dec_sub24_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub24_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - dec31_dec_sub24_function_unit = 14'h0008; + dec31_dec_sub24_function_unit = 15'h0008; endcase end always @* begin if (\initial ) begin end dec31_dec_sub24_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub24_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub24_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub24_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub24_cr_in = 3'h0; endcase @@ -108803,18 +117586,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub24_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub24_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub24_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub24_cr_out = 3'h1; endcase @@ -108822,18 +117605,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub24_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub24_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub24_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub24_sv_in1 = 3'h0; endcase @@ -108841,18 +117624,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub24_sv_in2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub24_sv_in2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub24_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub24_sv_in2 = 3'h2; endcase @@ -108860,18 +117643,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub24_sv_in3 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub24_sv_in3 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub24_sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub24_sv_in3 = 3'h3; endcase @@ -108879,18 +117662,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub24_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub24_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub24_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub24_sv_out = 3'h1; endcase @@ -108898,18 +117681,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub24_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub24_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub24_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub24_sv_out2 = 3'h0; endcase @@ -108917,18 +117700,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub24_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub24_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub24_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub24_sv_cr_in = 3'h0; endcase @@ -108936,18 +117719,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub24_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub24_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub24_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub24_sv_cr_out = 3'h1; endcase @@ -108955,18 +117738,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub24_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub24_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub24_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub24_ldst_len = 4'h0; endcase @@ -108974,18 +117757,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub24_internal_op = 7'h3c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub24_internal_op = 7'h3d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub24_internal_op = 7'h3d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub24_internal_op = 7'h3d; endcase @@ -108993,18 +117776,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub24_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub24_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub24_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub24_upd = 2'h0; endcase @@ -109012,18 +117795,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub24_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub24_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub24_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub24_rc_sel = 2'h2; endcase @@ -109031,18 +117814,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub24_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub24_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub24_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub24_cry_in = 2'h0; endcase @@ -109050,37 +117833,37 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub24_asmcode = 8'ha0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub24_asmcode = 8'hc0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - dec31_dec_sub24_asmcode = 8'ha3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub24_asmcode = 8'hc3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: - dec31_dec_sub24_asmcode = 8'ha4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub24_asmcode = 8'hc4; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - dec31_dec_sub24_asmcode = 8'ha6; + dec31_dec_sub24_asmcode = 8'hc6; endcase end always @* begin if (\initial ) begin end dec31_dec_sub24_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub24_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub24_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub24_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub24_inv_a = 1'h0; endcase @@ -109088,18 +117871,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub24_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub24_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub24_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub24_inv_out = 1'h0; endcase @@ -109107,18 +117890,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub24_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub24_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub24_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub24_cry_out = 1'h0; endcase @@ -109126,18 +117909,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub24_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub24_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub24_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub24_br = 1'h0; endcase @@ -109145,18 +117928,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub24_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub24_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub24_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub24_sgn_ext = 1'h0; endcase @@ -109164,18 +117947,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub24_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub24_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub24_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub24_rsrv = 1'h0; endcase @@ -109183,18 +117966,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub24_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub24_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub24_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub24_form = 5'h08; endcase @@ -109202,18 +117985,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub24_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub24_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub24_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub24_is_32b = 1'h1; endcase @@ -109221,18 +118004,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub24_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub24_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub24_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub24_sgn = 1'h0; endcase @@ -109240,18 +118023,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub24_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub24_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub24_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub24_lk = 1'h0; endcase @@ -109259,18 +118042,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub24_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub24_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub24_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub24_sgl_pipe = 1'h0; endcase @@ -109278,18 +118061,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub24_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub24_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub24_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub24_SV_Etype = 2'h2; endcase @@ -109297,18 +118080,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub24_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub24_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub24_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub24_SV_Ptype = 2'h1; endcase @@ -109316,18 +118099,18 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub24_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub24_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub24_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub24_in1_sel = 3'h0; endcase @@ -109335,56 +118118,56 @@ module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_o always @* begin if (\initial ) begin end dec31_dec_sub24_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub24_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub24_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub24_in2_sel = 4'hb; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub24_in2_sel = 4'h1; endcase end always @* begin if (\initial ) begin end - dec31_dec_sub24_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub24_in3_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub24_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub24_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - dec31_dec_sub24_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub24_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: - dec31_dec_sub24_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub24_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - dec31_dec_sub24_in3_sel = 2'h1; + dec31_dec_sub24_in3_sel = 3'h1; endcase end always @* begin if (\initial ) begin end dec31_dec_sub24_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub24_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub24_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub24_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub24_out_sel = 3'h2; endcase @@ -109400,20 +118183,20 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub26_SV_Etype; reg [1:0] dec31_dec_sub26_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub26_SV_Ptype; reg [1:0] dec31_dec_sub26_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub26_asmcode; reg [7:0] dec31_dec_sub26_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub26_br; reg dec31_dec_sub26_br; (* enum_base_type = "CRInSel" *) @@ -109425,7 +118208,7 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub26_cr_in; reg [2:0] dec31_dec_sub26_cr_in; (* enum_base_type = "CROutSel" *) @@ -109435,17 +118218,17 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub26_cr_out; reg [2:0] dec31_dec_sub26_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub26_cry_in; reg [1:0] dec31_dec_sub26_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub26_cry_out; reg dec31_dec_sub26_cry_out; (* enum_base_type = "Form" *) @@ -109479,34 +118262,37 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub26_form; reg [4:0] dec31_dec_sub26_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] dec31_dec_sub26_function_unit; - reg [13:0] dec31_dec_sub26_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] dec31_dec_sub26_function_unit; + reg [14:0] dec31_dec_sub26_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub26_in1_sel; reg [2:0] dec31_dec_sub26_in1_sel; (* enum_base_type = "In2Sel" *) @@ -109524,16 +118310,19 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub26_in2_sel; reg [3:0] dec31_dec_sub26_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [1:0] dec31_dec_sub26_in3_sel; - reg [1:0] dec31_dec_sub26_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub26_in3_sel; + reg [2:0] dec31_dec_sub26_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -109609,16 +118398,18 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub26_internal_op; reg [6:0] dec31_dec_sub26_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub26_inv_a; reg dec31_dec_sub26_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub26_inv_out; reg dec31_dec_sub26_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub26_is_32b; reg dec31_dec_sub26_is_32b; (* enum_base_type = "LdstLen" *) @@ -109627,10 +118418,10 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub26_ldst_len; reg [3:0] dec31_dec_sub26_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub26_lk; reg dec31_dec_sub26_lk; (* enum_base_type = "OutSel" *) @@ -109639,26 +118430,27 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub26_out_sel; reg [2:0] dec31_dec_sub26_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub26_rc_sel; reg [1:0] dec31_dec_sub26_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub26_rsrv; reg dec31_dec_sub26_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub26_sgl_pipe; reg dec31_dec_sub26_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub26_sgn; reg dec31_dec_sub26_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub26_sgn_ext; reg dec31_dec_sub26_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -109668,7 +118460,7 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub26_sv_cr_in; reg [2:0] dec31_dec_sub26_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -109678,7 +118470,7 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub26_sv_cr_out; reg [2:0] dec31_dec_sub26_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -109688,7 +118480,7 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub26_sv_in1; reg [2:0] dec31_dec_sub26_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -109698,7 +118490,7 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub26_sv_in2; reg [2:0] dec31_dec_sub26_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -109708,7 +118500,7 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub26_sv_in3; reg [2:0] dec31_dec_sub26_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -109718,7 +118510,7 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub26_sv_out; reg [2:0] dec31_dec_sub26_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -109728,7 +118520,7 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub26_sv_out2; reg [2:0] dec31_dec_sub26_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -109736,113 +118528,113 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub26_upd; reg [1:0] dec31_dec_sub26_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - dec31_dec_sub26_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub26_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: - dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: - dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: - dec31_dec_sub26_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: - dec31_dec_sub26_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: - dec31_dec_sub26_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: - dec31_dec_sub26_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: - dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: - dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: - dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: - dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - dec31_dec_sub26_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - dec31_dec_sub26_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: - dec31_dec_sub26_function_unit = 14'h0008; + dec31_dec_sub26_function_unit = 15'h0008; endcase end always @* begin if (\initial ) begin end dec31_dec_sub26_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub26_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub26_cr_in = 3'h0; endcase @@ -109850,51 +118642,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub26_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub26_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub26_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub26_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub26_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub26_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub26_cr_out = 3'h1; endcase @@ -109902,51 +118694,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub26_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub26_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub26_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub26_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub26_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub26_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub26_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub26_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub26_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub26_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub26_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub26_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub26_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub26_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub26_sv_in1 = 3'h0; endcase @@ -109954,51 +118746,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub26_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub26_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub26_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub26_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub26_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub26_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub26_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub26_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub26_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub26_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub26_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub26_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub26_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub26_sv_in2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub26_sv_in2 = 3'h0; endcase @@ -110006,51 +118798,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub26_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub26_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub26_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub26_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub26_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub26_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub26_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub26_sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub26_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub26_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub26_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub26_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub26_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub26_sv_in3 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub26_sv_in3 = 3'h2; endcase @@ -110058,51 +118850,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub26_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub26_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub26_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub26_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub26_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub26_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub26_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub26_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub26_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub26_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub26_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub26_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub26_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub26_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub26_sv_out = 3'h1; endcase @@ -110110,51 +118902,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub26_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub26_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub26_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub26_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub26_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub26_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub26_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub26_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub26_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub26_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub26_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub26_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub26_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub26_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub26_sv_out2 = 3'h0; endcase @@ -110162,51 +118954,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub26_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub26_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub26_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub26_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub26_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub26_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub26_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub26_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub26_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub26_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub26_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub26_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub26_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub26_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub26_sv_cr_in = 3'h0; endcase @@ -110214,51 +119006,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub26_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub26_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub26_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub26_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub26_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub26_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub26_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub26_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub26_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub26_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub26_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub26_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub26_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub26_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub26_sv_cr_out = 3'h1; endcase @@ -110266,51 +119058,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub26_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub26_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub26_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub26_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub26_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub26_ldst_len = 4'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub26_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub26_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub26_ldst_len = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub26_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub26_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub26_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub26_ldst_len = 4'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub26_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub26_ldst_len = 4'h0; endcase @@ -110318,51 +119110,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub26_internal_op = 7'h0e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub26_internal_op = 7'h0e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub26_internal_op = 7'h0e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub26_internal_op = 7'h0e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub26_internal_op = 7'h1f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub26_internal_op = 7'h1f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub26_internal_op = 7'h1f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub26_internal_op = 7'h20; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub26_internal_op = 7'h36; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub26_internal_op = 7'h36; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub26_internal_op = 7'h36; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub26_internal_op = 7'h37; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub26_internal_op = 7'h37; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub26_internal_op = 7'h3d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub26_internal_op = 7'h3d; endcase @@ -110370,51 +119162,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub26_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub26_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub26_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub26_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub26_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub26_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub26_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub26_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub26_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub26_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub26_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub26_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub26_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub26_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub26_upd = 2'h0; endcase @@ -110422,51 +119214,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub26_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub26_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub26_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub26_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub26_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub26_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub26_rc_sel = 2'h2; endcase @@ -110474,51 +119266,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub26_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub26_cry_in = 2'h0; endcase @@ -110526,103 +119318,103 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub26_asmcode = 8'h21; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub26_asmcode = 8'h22; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub26_asmcode = 8'h23; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub26_asmcode = 8'h24; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub26_asmcode = 8'h44; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub26_asmcode = 8'h45; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub26_asmcode = 8'h46; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub26_asmcode = 8'h47; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: - dec31_dec_sub26_asmcode = 8'h8c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_asmcode = 8'hac; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: - dec31_dec_sub26_asmcode = 8'h8d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_asmcode = 8'had; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: - dec31_dec_sub26_asmcode = 8'h8e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_asmcode = 8'hae; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: - dec31_dec_sub26_asmcode = 8'h8f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_asmcode = 8'haf; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - dec31_dec_sub26_asmcode = 8'h90; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_asmcode = 8'hb0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - dec31_dec_sub26_asmcode = 8'ha1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_asmcode = 8'hc1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: - dec31_dec_sub26_asmcode = 8'ha2; + dec31_dec_sub26_asmcode = 8'hc2; endcase end always @* begin if (\initial ) begin end dec31_dec_sub26_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub26_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub26_inv_a = 1'h0; endcase @@ -110630,51 +119422,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub26_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub26_inv_out = 1'h0; endcase @@ -110682,51 +119474,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub26_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub26_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub26_cry_out = 1'h1; endcase @@ -110734,51 +119526,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub26_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub26_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub26_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub26_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub26_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub26_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub26_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub26_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub26_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub26_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub26_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub26_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub26_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub26_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub26_br = 1'h0; endcase @@ -110786,51 +119578,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub26_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub26_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub26_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub26_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub26_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub26_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub26_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub26_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub26_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub26_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub26_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub26_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub26_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub26_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub26_sgn_ext = 1'h0; endcase @@ -110838,51 +119630,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub26_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub26_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub26_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub26_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub26_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub26_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub26_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub26_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub26_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub26_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub26_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub26_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub26_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub26_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub26_rsrv = 1'h0; endcase @@ -110890,51 +119682,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub26_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub26_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub26_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub26_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub26_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub26_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub26_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub26_form = 5'h10; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub26_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub26_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub26_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub26_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub26_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub26_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub26_form = 5'h10; endcase @@ -110942,51 +119734,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub26_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub26_is_32b = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub26_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub26_is_32b = 1'h0; endcase @@ -110994,51 +119786,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub26_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub26_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub26_sgn = 1'h1; endcase @@ -111046,51 +119838,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub26_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub26_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub26_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub26_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub26_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub26_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub26_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub26_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub26_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub26_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub26_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub26_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub26_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub26_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub26_lk = 1'h0; endcase @@ -111098,51 +119890,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub26_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub26_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub26_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub26_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub26_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub26_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub26_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub26_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub26_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub26_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub26_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub26_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub26_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub26_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub26_sgl_pipe = 1'h0; endcase @@ -111150,51 +119942,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub26_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub26_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub26_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub26_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub26_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub26_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub26_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub26_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub26_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub26_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub26_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub26_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub26_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub26_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub26_SV_Etype = 2'h2; endcase @@ -111202,51 +119994,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub26_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub26_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub26_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub26_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub26_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub26_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub26_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub26_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub26_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub26_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub26_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub26_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub26_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub26_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub26_SV_Ptype = 2'h2; endcase @@ -111254,51 +120046,51 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub26_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub26_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub26_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub26_in1_sel = 3'h0; endcase @@ -111306,155 +120098,155 @@ module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_o always @* begin if (\initial ) begin end dec31_dec_sub26_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub26_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub26_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub26_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub26_in2_sel = 4'ha; endcase end always @* begin if (\initial ) begin end - dec31_dec_sub26_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub26_in3_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: - dec31_dec_sub26_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub26_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: - dec31_dec_sub26_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - dec31_dec_sub26_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: - dec31_dec_sub26_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: - dec31_dec_sub26_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: - dec31_dec_sub26_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: - dec31_dec_sub26_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: - dec31_dec_sub26_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: - dec31_dec_sub26_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: - dec31_dec_sub26_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: - dec31_dec_sub26_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - dec31_dec_sub26_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - dec31_dec_sub26_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub26_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: - dec31_dec_sub26_in3_sel = 2'h1; + dec31_dec_sub26_in3_sel = 3'h1; endcase end always @* begin if (\initial ) begin end dec31_dec_sub26_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub26_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub26_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub26_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub26_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub26_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub26_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub26_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub26_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub26_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub26_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0b: dec31_dec_sub26_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h05: dec31_dec_sub26_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub26_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub26_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub26_out_sel = 3'h2; endcase @@ -111470,20 +120262,20 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub27_SV_Etype; reg [1:0] dec31_dec_sub27_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub27_SV_Ptype; reg [1:0] dec31_dec_sub27_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub27_asmcode; reg [7:0] dec31_dec_sub27_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub27_br; reg dec31_dec_sub27_br; (* enum_base_type = "CRInSel" *) @@ -111495,7 +120287,7 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub27_cr_in; reg [2:0] dec31_dec_sub27_cr_in; (* enum_base_type = "CROutSel" *) @@ -111505,17 +120297,17 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub27_cr_out; reg [2:0] dec31_dec_sub27_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub27_cry_in; reg [1:0] dec31_dec_sub27_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub27_cry_out; reg dec31_dec_sub27_cry_out; (* enum_base_type = "Form" *) @@ -111549,34 +120341,37 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub27_form; reg [4:0] dec31_dec_sub27_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] dec31_dec_sub27_function_unit; - reg [13:0] dec31_dec_sub27_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] dec31_dec_sub27_function_unit; + reg [14:0] dec31_dec_sub27_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub27_in1_sel; reg [2:0] dec31_dec_sub27_in1_sel; (* enum_base_type = "In2Sel" *) @@ -111594,16 +120389,19 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub27_in2_sel; reg [3:0] dec31_dec_sub27_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [1:0] dec31_dec_sub27_in3_sel; - reg [1:0] dec31_dec_sub27_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub27_in3_sel; + reg [2:0] dec31_dec_sub27_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -111679,16 +120477,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub27_internal_op; reg [6:0] dec31_dec_sub27_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub27_inv_a; reg dec31_dec_sub27_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub27_inv_out; reg dec31_dec_sub27_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub27_is_32b; reg dec31_dec_sub27_is_32b; (* enum_base_type = "LdstLen" *) @@ -111697,10 +120497,10 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub27_ldst_len; reg [3:0] dec31_dec_sub27_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub27_lk; reg dec31_dec_sub27_lk; (* enum_base_type = "OutSel" *) @@ -111709,26 +120509,27 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub27_out_sel; reg [2:0] dec31_dec_sub27_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub27_rc_sel; reg [1:0] dec31_dec_sub27_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub27_rsrv; reg dec31_dec_sub27_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub27_sgl_pipe; reg dec31_dec_sub27_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub27_sgn; reg dec31_dec_sub27_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub27_sgn_ext; reg dec31_dec_sub27_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -111738,7 +120539,7 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub27_sv_cr_in; reg [2:0] dec31_dec_sub27_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -111748,7 +120549,7 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub27_sv_cr_out; reg [2:0] dec31_dec_sub27_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -111758,7 +120559,7 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub27_sv_in1; reg [2:0] dec31_dec_sub27_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -111768,7 +120569,7 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub27_sv_in2; reg [2:0] dec31_dec_sub27_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -111778,7 +120579,7 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub27_sv_in3; reg [2:0] dec31_dec_sub27_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -111788,7 +120589,7 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub27_sv_out; reg [2:0] dec31_dec_sub27_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -111798,7 +120599,7 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub27_sv_out2; reg [2:0] dec31_dec_sub27_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -111806,47 +120607,47 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub27_upd; reg [1:0] dec31_dec_sub27_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - dec31_dec_sub27_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub27_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: - dec31_dec_sub27_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub27_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub27_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub27_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: - dec31_dec_sub27_function_unit = 14'h0008; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub27_function_unit = 15'h0008; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - dec31_dec_sub27_function_unit = 14'h0008; + dec31_dec_sub27_function_unit = 15'h0008; endcase end always @* begin if (\initial ) begin end dec31_dec_sub27_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub27_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub27_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub27_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub27_cr_in = 3'h0; endcase @@ -111854,18 +120655,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub27_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub27_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub27_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub27_cr_out = 3'h1; endcase @@ -111873,18 +120674,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub27_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub27_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub27_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub27_sv_in1 = 3'h0; endcase @@ -111892,18 +120693,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub27_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub27_sv_in2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub27_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub27_sv_in2 = 3'h2; endcase @@ -111911,18 +120712,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub27_sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub27_sv_in3 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub27_sv_in3 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub27_sv_in3 = 3'h3; endcase @@ -111930,18 +120731,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub27_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub27_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub27_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub27_sv_out = 3'h1; endcase @@ -111949,18 +120750,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub27_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub27_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub27_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub27_sv_out2 = 3'h0; endcase @@ -111968,18 +120769,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub27_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub27_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub27_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub27_sv_cr_in = 3'h0; endcase @@ -111987,18 +120788,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub27_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub27_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub27_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub27_sv_cr_out = 3'h1; endcase @@ -112006,18 +120807,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub27_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub27_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub27_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub27_ldst_len = 4'h0; endcase @@ -112025,18 +120826,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub27_internal_op = 7'h20; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub27_internal_op = 7'h3c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub27_internal_op = 7'h3d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub27_internal_op = 7'h3d; endcase @@ -112044,18 +120845,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub27_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub27_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub27_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub27_upd = 2'h0; endcase @@ -112063,18 +120864,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub27_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub27_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub27_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub27_rc_sel = 2'h2; endcase @@ -112082,18 +120883,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub27_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub27_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub27_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub27_cry_in = 2'h0; endcase @@ -112101,37 +120902,37 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub27_asmcode = 8'h47; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub27_asmcode = 8'h9f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub27_asmcode = 8'hbf; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: - dec31_dec_sub27_asmcode = 8'ha2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub27_asmcode = 8'hc2; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - dec31_dec_sub27_asmcode = 8'ha5; + dec31_dec_sub27_asmcode = 8'hc5; endcase end always @* begin if (\initial ) begin end dec31_dec_sub27_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub27_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub27_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub27_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub27_inv_a = 1'h0; endcase @@ -112139,18 +120940,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub27_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub27_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub27_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub27_inv_out = 1'h0; endcase @@ -112158,18 +120959,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub27_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub27_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub27_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub27_cry_out = 1'h0; endcase @@ -112177,18 +120978,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub27_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub27_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub27_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub27_br = 1'h0; endcase @@ -112196,18 +120997,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub27_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub27_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub27_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub27_sgn_ext = 1'h0; endcase @@ -112215,18 +121016,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub27_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub27_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub27_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub27_rsrv = 1'h0; endcase @@ -112234,18 +121035,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub27_form = 5'h10; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub27_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub27_form = 5'h10; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub27_form = 5'h08; endcase @@ -112253,18 +121054,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub27_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub27_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub27_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub27_is_32b = 1'h0; endcase @@ -112272,18 +121073,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub27_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub27_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub27_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub27_sgn = 1'h0; endcase @@ -112291,18 +121092,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub27_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub27_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub27_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub27_lk = 1'h0; endcase @@ -112310,18 +121111,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub27_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub27_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub27_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub27_sgl_pipe = 1'h0; endcase @@ -112329,18 +121130,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub27_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub27_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub27_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub27_SV_Etype = 2'h2; endcase @@ -112348,18 +121149,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub27_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub27_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub27_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub27_SV_Ptype = 2'h1; endcase @@ -112367,18 +121168,18 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub27_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub27_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub27_in1_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub27_in1_sel = 3'h0; endcase @@ -112386,56 +121187,56 @@ module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_o always @* begin if (\initial ) begin end dec31_dec_sub27_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub27_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub27_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub27_in2_sel = 4'ha; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub27_in2_sel = 4'h1; endcase end always @* begin if (\initial ) begin end - dec31_dec_sub27_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub27_in3_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: - dec31_dec_sub27_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub27_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub27_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub27_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: - dec31_dec_sub27_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub27_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - dec31_dec_sub27_in3_sel = 2'h1; + dec31_dec_sub27_in3_sel = 3'h1; endcase end always @* begin if (\initial ) begin end dec31_dec_sub27_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1b: dec31_dec_sub27_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub27_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h19: dec31_dec_sub27_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub27_out_sel = 3'h2; endcase @@ -112451,20 +121252,20 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub28_SV_Etype; reg [1:0] dec31_dec_sub28_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub28_SV_Ptype; reg [1:0] dec31_dec_sub28_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub28_asmcode; reg [7:0] dec31_dec_sub28_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub28_br; reg dec31_dec_sub28_br; (* enum_base_type = "CRInSel" *) @@ -112476,7 +121277,7 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub28_cr_in; reg [2:0] dec31_dec_sub28_cr_in; (* enum_base_type = "CROutSel" *) @@ -112486,17 +121287,17 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub28_cr_out; reg [2:0] dec31_dec_sub28_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub28_cry_in; reg [1:0] dec31_dec_sub28_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub28_cry_out; reg dec31_dec_sub28_cry_out; (* enum_base_type = "Form" *) @@ -112530,34 +121331,37 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub28_form; reg [4:0] dec31_dec_sub28_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] dec31_dec_sub28_function_unit; - reg [13:0] dec31_dec_sub28_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] dec31_dec_sub28_function_unit; + reg [14:0] dec31_dec_sub28_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub28_in1_sel; reg [2:0] dec31_dec_sub28_in1_sel; (* enum_base_type = "In2Sel" *) @@ -112575,16 +121379,19 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub28_in2_sel; reg [3:0] dec31_dec_sub28_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [1:0] dec31_dec_sub28_in3_sel; - reg [1:0] dec31_dec_sub28_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub28_in3_sel; + reg [2:0] dec31_dec_sub28_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -112660,16 +121467,18 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub28_internal_op; reg [6:0] dec31_dec_sub28_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub28_inv_a; reg dec31_dec_sub28_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub28_inv_out; reg dec31_dec_sub28_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub28_is_32b; reg dec31_dec_sub28_is_32b; (* enum_base_type = "LdstLen" *) @@ -112678,10 +121487,10 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub28_ldst_len; reg [3:0] dec31_dec_sub28_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub28_lk; reg dec31_dec_sub28_lk; (* enum_base_type = "OutSel" *) @@ -112690,26 +121499,27 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub28_out_sel; reg [2:0] dec31_dec_sub28_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub28_rc_sel; reg [1:0] dec31_dec_sub28_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub28_rsrv; reg dec31_dec_sub28_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub28_sgl_pipe; reg dec31_dec_sub28_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub28_sgn; reg dec31_dec_sub28_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub28_sgn_ext; reg dec31_dec_sub28_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -112719,7 +121529,7 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub28_sv_cr_in; reg [2:0] dec31_dec_sub28_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -112729,7 +121539,7 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub28_sv_cr_out; reg [2:0] dec31_dec_sub28_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -112739,7 +121549,7 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub28_sv_in1; reg [2:0] dec31_dec_sub28_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -112749,7 +121559,7 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub28_sv_in2; reg [2:0] dec31_dec_sub28_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -112759,7 +121569,7 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub28_sv_in3; reg [2:0] dec31_dec_sub28_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -112769,7 +121579,7 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub28_sv_out; reg [2:0] dec31_dec_sub28_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -112779,7 +121589,7 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub28_sv_out2; reg [2:0] dec31_dec_sub28_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -112787,83 +121597,83 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub28_upd; reg [1:0] dec31_dec_sub28_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - dec31_dec_sub28_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub28_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub28_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: - dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub28_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub28_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: - dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub28_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: - dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub28_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: - dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub28_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: - dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub28_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: - dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub28_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: - dec31_dec_sub28_function_unit = 14'h0010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub28_function_unit = 15'h0010; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: - dec31_dec_sub28_function_unit = 14'h0010; + dec31_dec_sub28_function_unit = 15'h0010; endcase end always @* begin if (\initial ) begin end dec31_dec_sub28_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub28_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub28_cr_in = 3'h0; endcase @@ -112871,36 +121681,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub28_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub28_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub28_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub28_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub28_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub28_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub28_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub28_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub28_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub28_cr_out = 3'h1; endcase @@ -112908,36 +121718,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub28_sv_in1 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub28_sv_in1 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub28_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub28_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub28_sv_in1 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub28_sv_in1 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub28_sv_in1 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub28_sv_in1 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub28_sv_in1 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub28_sv_in1 = 3'h3; endcase @@ -112945,36 +121755,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub28_sv_in2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub28_sv_in2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub28_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub28_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub28_sv_in2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub28_sv_in2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub28_sv_in2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub28_sv_in2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub28_sv_in2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub28_sv_in2 = 3'h2; endcase @@ -112982,36 +121792,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub28_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub28_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub28_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub28_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub28_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub28_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub28_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub28_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub28_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub28_sv_in3 = 3'h0; endcase @@ -113019,36 +121829,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub28_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub28_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub28_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub28_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub28_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub28_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub28_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub28_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub28_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub28_sv_out = 3'h1; endcase @@ -113056,36 +121866,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub28_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub28_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub28_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub28_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub28_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub28_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub28_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub28_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub28_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub28_sv_out2 = 3'h0; endcase @@ -113093,36 +121903,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub28_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub28_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub28_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub28_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub28_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub28_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub28_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub28_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub28_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub28_sv_cr_in = 3'h0; endcase @@ -113130,36 +121940,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub28_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub28_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub28_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub28_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub28_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub28_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub28_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub28_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub28_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub28_sv_cr_out = 3'h1; endcase @@ -113167,36 +121977,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub28_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub28_ldst_len = 4'h0; endcase @@ -113204,36 +122014,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub28_internal_op = 7'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub28_internal_op = 7'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub28_internal_op = 7'h09; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub28_internal_op = 7'h0b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub28_internal_op = 7'h43; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub28_internal_op = 7'h04; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub28_internal_op = 7'h35; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub28_internal_op = 7'h35; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub28_internal_op = 7'h35; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub28_internal_op = 7'h43; endcase @@ -113241,36 +122051,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub28_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub28_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub28_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub28_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub28_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub28_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub28_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub28_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub28_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub28_upd = 2'h0; endcase @@ -113278,36 +122088,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub28_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub28_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub28_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub28_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub28_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub28_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub28_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub28_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub28_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub28_rc_sel = 2'h2; endcase @@ -113315,36 +122125,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub28_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub28_cry_in = 2'h0; endcase @@ -113352,73 +122162,73 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub28_asmcode = 8'h0f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub28_asmcode = 8'h10; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub28_asmcode = 8'h19; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub28_asmcode = 8'h1b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub28_asmcode = 8'h43; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: - dec31_dec_sub28_asmcode = 8'h83; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub28_asmcode = 8'ha3; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: - dec31_dec_sub28_asmcode = 8'h87; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub28_asmcode = 8'ha7; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: - dec31_dec_sub28_asmcode = 8'h88; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub28_asmcode = 8'ha8; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: - dec31_dec_sub28_asmcode = 8'h89; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub28_asmcode = 8'ha9; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: - dec31_dec_sub28_asmcode = 8'hd1; + dec31_dec_sub28_asmcode = 8'hfa; endcase end always @* begin if (\initial ) begin end dec31_dec_sub28_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub28_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub28_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub28_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub28_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub28_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub28_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub28_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub28_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub28_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub28_inv_a = 1'h0; endcase @@ -113426,36 +122236,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub28_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub28_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub28_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub28_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub28_inv_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub28_inv_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub28_inv_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub28_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub28_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub28_inv_out = 1'h0; endcase @@ -113463,36 +122273,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub28_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub28_cry_out = 1'h0; endcase @@ -113500,36 +122310,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub28_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub28_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub28_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub28_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub28_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub28_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub28_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub28_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub28_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub28_br = 1'h0; endcase @@ -113537,36 +122347,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub28_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub28_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub28_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub28_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub28_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub28_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub28_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub28_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub28_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub28_sgn_ext = 1'h0; endcase @@ -113574,36 +122384,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub28_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub28_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub28_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub28_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub28_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub28_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub28_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub28_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub28_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub28_rsrv = 1'h0; endcase @@ -113611,36 +122421,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub28_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub28_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub28_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub28_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub28_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub28_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub28_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub28_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub28_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub28_form = 5'h08; endcase @@ -113648,36 +122458,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub28_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub28_is_32b = 1'h0; endcase @@ -113685,36 +122495,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub28_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub28_sgn = 1'h0; endcase @@ -113722,36 +122532,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub28_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub28_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub28_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub28_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub28_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub28_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub28_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub28_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub28_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub28_lk = 1'h0; endcase @@ -113759,36 +122569,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub28_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub28_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub28_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub28_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub28_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub28_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub28_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub28_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub28_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub28_sgl_pipe = 1'h0; endcase @@ -113796,36 +122606,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub28_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub28_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub28_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub28_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub28_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub28_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub28_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub28_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub28_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub28_SV_Etype = 2'h2; endcase @@ -113833,36 +122643,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub28_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub28_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub28_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub28_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub28_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub28_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub28_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub28_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub28_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub28_SV_Ptype = 2'h1; endcase @@ -113870,36 +122680,36 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub28_in1_sel = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub28_in1_sel = 3'h4; endcase @@ -113907,110 +122717,110 @@ module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_o always @* begin if (\initial ) begin end dec31_dec_sub28_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub28_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub28_in2_sel = 4'h1; endcase end always @* begin if (\initial ) begin end - dec31_dec_sub28_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub28_in3_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub28_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub28_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: - dec31_dec_sub28_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub28_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - dec31_dec_sub28_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub28_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: - dec31_dec_sub28_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub28_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: - dec31_dec_sub28_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub28_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: - dec31_dec_sub28_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub28_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: - dec31_dec_sub28_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub28_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: - dec31_dec_sub28_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub28_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: - dec31_dec_sub28_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub28_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: - dec31_dec_sub28_in3_sel = 2'h0; + dec31_dec_sub28_in3_sel = 3'h0; endcase end always @* begin if (\initial ) begin end dec31_dec_sub28_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub28_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub28_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub28_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub28_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub28_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub28_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub28_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub28_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub28_out_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h09: dec31_dec_sub28_out_sel = 3'h2; endcase @@ -114026,20 +122836,20 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub4_SV_Etype; reg [1:0] dec31_dec_sub4_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub4_SV_Ptype; reg [1:0] dec31_dec_sub4_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub4_asmcode; reg [7:0] dec31_dec_sub4_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub4_br; reg dec31_dec_sub4_br; (* enum_base_type = "CRInSel" *) @@ -114051,7 +122861,7 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub4_cr_in; reg [2:0] dec31_dec_sub4_cr_in; (* enum_base_type = "CROutSel" *) @@ -114061,17 +122871,17 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub4_cr_out; reg [2:0] dec31_dec_sub4_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub4_cry_in; reg [1:0] dec31_dec_sub4_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub4_cry_out; reg dec31_dec_sub4_cry_out; (* enum_base_type = "Form" *) @@ -114105,34 +122915,37 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub4_form; reg [4:0] dec31_dec_sub4_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] dec31_dec_sub4_function_unit; - reg [13:0] dec31_dec_sub4_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] dec31_dec_sub4_function_unit; + reg [14:0] dec31_dec_sub4_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub4_in1_sel; reg [2:0] dec31_dec_sub4_in1_sel; (* enum_base_type = "In2Sel" *) @@ -114150,16 +122963,19 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub4_in2_sel; reg [3:0] dec31_dec_sub4_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [1:0] dec31_dec_sub4_in3_sel; - reg [1:0] dec31_dec_sub4_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub4_in3_sel; + reg [2:0] dec31_dec_sub4_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -114235,16 +123051,18 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub4_internal_op; reg [6:0] dec31_dec_sub4_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub4_inv_a; reg dec31_dec_sub4_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub4_inv_out; reg dec31_dec_sub4_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub4_is_32b; reg dec31_dec_sub4_is_32b; (* enum_base_type = "LdstLen" *) @@ -114253,10 +123071,10 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub4_ldst_len; reg [3:0] dec31_dec_sub4_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub4_lk; reg dec31_dec_sub4_lk; (* enum_base_type = "OutSel" *) @@ -114265,26 +123083,27 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub4_out_sel; reg [2:0] dec31_dec_sub4_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub4_rc_sel; reg [1:0] dec31_dec_sub4_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub4_rsrv; reg dec31_dec_sub4_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub4_sgl_pipe; reg dec31_dec_sub4_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub4_sgn; reg dec31_dec_sub4_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub4_sgn_ext; reg dec31_dec_sub4_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -114294,7 +123113,7 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub4_sv_cr_in; reg [2:0] dec31_dec_sub4_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -114304,7 +123123,7 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub4_sv_cr_out; reg [2:0] dec31_dec_sub4_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -114314,7 +123133,7 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub4_sv_in1; reg [2:0] dec31_dec_sub4_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -114324,7 +123143,7 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub4_sv_in2; reg [2:0] dec31_dec_sub4_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -114334,7 +123153,7 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub4_sv_in3; reg [2:0] dec31_dec_sub4_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -114344,7 +123163,7 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub4_sv_out; reg [2:0] dec31_dec_sub4_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -114354,7 +123173,7 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub4_sv_out2; reg [2:0] dec31_dec_sub4_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -114362,35 +123181,35 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub4_upd; reg [1:0] dec31_dec_sub4_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - dec31_dec_sub4_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub4_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: - dec31_dec_sub4_function_unit = 14'h0080; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub4_function_unit = 15'h0080; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub4_function_unit = 14'h0080; + dec31_dec_sub4_function_unit = 15'h0080; endcase end always @* begin if (\initial ) begin end dec31_dec_sub4_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub4_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub4_cr_in = 3'h0; endcase @@ -114398,12 +123217,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub4_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub4_cr_out = 3'h0; endcase @@ -114411,12 +123230,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub4_sv_in1 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub4_sv_in1 = 3'h0; endcase @@ -114424,12 +123243,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub4_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub4_sv_in2 = 3'h0; endcase @@ -114437,12 +123256,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub4_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub4_sv_in3 = 3'h0; endcase @@ -114450,12 +123269,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub4_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub4_sv_out = 3'h0; endcase @@ -114463,12 +123282,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub4_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub4_sv_out2 = 3'h0; endcase @@ -114476,12 +123295,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub4_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub4_sv_cr_in = 3'h0; endcase @@ -114489,12 +123308,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub4_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub4_sv_cr_out = 3'h0; endcase @@ -114502,12 +123321,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub4_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub4_ldst_len = 4'h0; endcase @@ -114515,12 +123334,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub4_internal_op = 7'h3f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub4_internal_op = 7'h3f; endcase @@ -114528,12 +123347,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub4_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub4_upd = 2'h0; endcase @@ -114541,12 +123360,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub4_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub4_rc_sel = 2'h0; endcase @@ -114554,12 +123373,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub4_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub4_cry_in = 2'h0; endcase @@ -114567,25 +123386,25 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: - dec31_dec_sub4_asmcode = 8'hcb; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub4_asmcode = 8'hf4; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub4_asmcode = 8'hcf; + dec31_dec_sub4_asmcode = 8'hf8; endcase end always @* begin if (\initial ) begin end dec31_dec_sub4_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub4_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub4_inv_a = 1'h0; endcase @@ -114593,12 +123412,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub4_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub4_inv_out = 1'h0; endcase @@ -114606,12 +123425,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub4_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub4_cry_out = 1'h0; endcase @@ -114619,12 +123438,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub4_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub4_br = 1'h0; endcase @@ -114632,12 +123451,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub4_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub4_sgn_ext = 1'h0; endcase @@ -114645,12 +123464,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub4_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub4_rsrv = 1'h0; endcase @@ -114658,12 +123477,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub4_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub4_form = 5'h08; endcase @@ -114671,12 +123490,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub4_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub4_is_32b = 1'h1; endcase @@ -114684,12 +123503,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub4_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub4_sgn = 1'h0; endcase @@ -114697,12 +123516,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub4_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub4_lk = 1'h0; endcase @@ -114710,12 +123529,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub4_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub4_sgl_pipe = 1'h1; endcase @@ -114723,12 +123542,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub4_SV_Etype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub4_SV_Etype = 2'h0; endcase @@ -114736,12 +123555,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub4_SV_Ptype = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub4_SV_Ptype = 2'h0; endcase @@ -114749,12 +123568,12 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub4_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub4_in1_sel = 3'h1; endcase @@ -114762,38 +123581,38 @@ module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub4_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub4_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub4_in2_sel = 4'h1; endcase end always @* begin if (\initial ) begin end - dec31_dec_sub4_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub4_in3_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: - dec31_dec_sub4_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub4_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub4_in3_sel = 2'h0; + dec31_dec_sub4_in3_sel = 3'h0; endcase end always @* begin if (\initial ) begin end dec31_dec_sub4_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub4_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub4_out_sel = 3'h0; endcase @@ -114809,20 +123628,20 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub8_SV_Etype; reg [1:0] dec31_dec_sub8_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub8_SV_Ptype; reg [1:0] dec31_dec_sub8_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub8_asmcode; reg [7:0] dec31_dec_sub8_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub8_br; reg dec31_dec_sub8_br; (* enum_base_type = "CRInSel" *) @@ -114834,7 +123653,7 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub8_cr_in; reg [2:0] dec31_dec_sub8_cr_in; (* enum_base_type = "CROutSel" *) @@ -114844,17 +123663,17 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub8_cr_out; reg [2:0] dec31_dec_sub8_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub8_cry_in; reg [1:0] dec31_dec_sub8_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub8_cry_out; reg dec31_dec_sub8_cry_out; (* enum_base_type = "Form" *) @@ -114888,34 +123707,37 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub8_form; reg [4:0] dec31_dec_sub8_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] dec31_dec_sub8_function_unit; - reg [13:0] dec31_dec_sub8_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] dec31_dec_sub8_function_unit; + reg [14:0] dec31_dec_sub8_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub8_in1_sel; reg [2:0] dec31_dec_sub8_in1_sel; (* enum_base_type = "In2Sel" *) @@ -114933,16 +123755,19 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub8_in2_sel; reg [3:0] dec31_dec_sub8_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [1:0] dec31_dec_sub8_in3_sel; - reg [1:0] dec31_dec_sub8_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub8_in3_sel; + reg [2:0] dec31_dec_sub8_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -115018,16 +123843,18 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub8_internal_op; reg [6:0] dec31_dec_sub8_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub8_inv_a; reg dec31_dec_sub8_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub8_inv_out; reg dec31_dec_sub8_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub8_is_32b; reg dec31_dec_sub8_is_32b; (* enum_base_type = "LdstLen" *) @@ -115036,10 +123863,10 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub8_ldst_len; reg [3:0] dec31_dec_sub8_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub8_lk; reg dec31_dec_sub8_lk; (* enum_base_type = "OutSel" *) @@ -115048,26 +123875,27 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub8_out_sel; reg [2:0] dec31_dec_sub8_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub8_rc_sel; reg [1:0] dec31_dec_sub8_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub8_rsrv; reg dec31_dec_sub8_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub8_sgl_pipe; reg dec31_dec_sub8_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub8_sgn; reg dec31_dec_sub8_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub8_sgn_ext; reg dec31_dec_sub8_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -115077,7 +123905,7 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub8_sv_cr_in; reg [2:0] dec31_dec_sub8_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -115087,7 +123915,7 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub8_sv_cr_out; reg [2:0] dec31_dec_sub8_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -115097,7 +123925,7 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub8_sv_in1; reg [2:0] dec31_dec_sub8_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -115107,7 +123935,7 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub8_sv_in2; reg [2:0] dec31_dec_sub8_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -115117,7 +123945,7 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub8_sv_in3; reg [2:0] dec31_dec_sub8_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -115127,7 +123955,7 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub8_sv_out; reg [2:0] dec31_dec_sub8_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -115137,7 +123965,7 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub8_sv_out2; reg [2:0] dec31_dec_sub8_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -115145,95 +123973,95 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub8_upd; reg [1:0] dec31_dec_sub8_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - dec31_dec_sub8_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub8_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: - dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub8_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: - dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub8_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: - dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub8_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: - dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub8_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub8_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub8_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub8_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: - dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub8_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub8_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: - dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub8_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: - dec31_dec_sub8_function_unit = 14'h0002; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub8_function_unit = 15'h0002; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: - dec31_dec_sub8_function_unit = 14'h0002; + dec31_dec_sub8_function_unit = 15'h0002; endcase end always @* begin if (\initial ) begin end dec31_dec_sub8_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub8_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub8_cr_in = 3'h0; endcase @@ -115241,42 +124069,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub8_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub8_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub8_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub8_cr_out = 3'h1; endcase @@ -115284,42 +124112,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub8_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub8_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub8_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub8_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub8_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub8_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub8_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub8_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub8_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub8_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub8_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub8_sv_in1 = 3'h2; endcase @@ -115327,42 +124155,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub8_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub8_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub8_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub8_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub8_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub8_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub8_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub8_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub8_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub8_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub8_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub8_sv_in2 = 3'h0; endcase @@ -115370,42 +124198,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub8_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub8_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub8_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub8_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub8_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub8_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub8_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub8_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub8_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub8_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub8_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub8_sv_in3 = 3'h0; endcase @@ -115413,42 +124241,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub8_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub8_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub8_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub8_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub8_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub8_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub8_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub8_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub8_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub8_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub8_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub8_sv_out = 3'h1; endcase @@ -115456,42 +124284,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub8_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub8_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub8_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub8_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub8_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub8_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub8_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub8_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub8_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub8_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub8_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub8_sv_out2 = 3'h0; endcase @@ -115499,42 +124327,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub8_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub8_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub8_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub8_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub8_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub8_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub8_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub8_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub8_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub8_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub8_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub8_sv_cr_in = 3'h0; endcase @@ -115542,42 +124370,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub8_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub8_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub8_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub8_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub8_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub8_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub8_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub8_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub8_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub8_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub8_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub8_sv_cr_out = 3'h1; endcase @@ -115585,42 +124413,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub8_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub8_ldst_len = 4'h0; endcase @@ -115628,42 +124456,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub8_internal_op = 7'h02; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub8_internal_op = 7'h02; endcase @@ -115671,42 +124499,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub8_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub8_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub8_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub8_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub8_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub8_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub8_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub8_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub8_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub8_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub8_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub8_upd = 2'h0; endcase @@ -115714,42 +124542,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub8_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub8_rc_sel = 2'h2; endcase @@ -115757,42 +124585,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub8_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub8_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub8_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub8_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub8_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub8_cry_in = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub8_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub8_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub8_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub8_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub8_cry_in = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub8_cry_in = 2'h2; endcase @@ -115800,85 +124628,85 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: - dec31_dec_sub8_asmcode = 8'h84; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub8_asmcode = 8'ha4; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: - dec31_dec_sub8_asmcode = 8'h85; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub8_asmcode = 8'ha5; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: - dec31_dec_sub8_asmcode = 8'hbf; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub8_asmcode = 8'he8; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: - dec31_dec_sub8_asmcode = 8'hc7; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub8_asmcode = 8'hf0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub8_asmcode = 8'hc0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub8_asmcode = 8'he9; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - dec31_dec_sub8_asmcode = 8'hc1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub8_asmcode = 8'hea; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - dec31_dec_sub8_asmcode = 8'hc2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub8_asmcode = 8'heb; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: - dec31_dec_sub8_asmcode = 8'hc3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub8_asmcode = 8'hec; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - dec31_dec_sub8_asmcode = 8'hc5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub8_asmcode = 8'hee; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: - dec31_dec_sub8_asmcode = 8'hc6; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub8_asmcode = 8'hef; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: - dec31_dec_sub8_asmcode = 8'hc8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub8_asmcode = 8'hf1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: - dec31_dec_sub8_asmcode = 8'hc9; + dec31_dec_sub8_asmcode = 8'hf2; endcase end always @* begin if (\initial ) begin end dec31_dec_sub8_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub8_inv_a = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub8_inv_a = 1'h1; endcase @@ -115886,42 +124714,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub8_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub8_inv_out = 1'h0; endcase @@ -115929,42 +124757,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub8_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub8_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub8_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub8_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub8_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub8_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub8_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub8_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub8_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub8_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub8_cry_out = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub8_cry_out = 1'h1; endcase @@ -115972,42 +124800,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub8_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub8_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub8_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub8_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub8_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub8_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub8_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub8_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub8_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub8_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub8_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub8_br = 1'h0; endcase @@ -116015,42 +124843,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub8_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub8_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub8_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub8_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub8_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub8_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub8_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub8_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub8_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub8_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub8_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub8_sgn_ext = 1'h0; endcase @@ -116058,42 +124886,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub8_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub8_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub8_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub8_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub8_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub8_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub8_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub8_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub8_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub8_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub8_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub8_rsrv = 1'h0; endcase @@ -116101,42 +124929,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub8_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub8_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub8_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub8_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub8_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub8_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub8_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub8_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub8_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub8_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub8_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub8_form = 5'h11; endcase @@ -116144,42 +124972,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub8_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub8_is_32b = 1'h0; endcase @@ -116187,42 +125015,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub8_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub8_sgn = 1'h0; endcase @@ -116230,42 +125058,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub8_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub8_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub8_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub8_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub8_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub8_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub8_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub8_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub8_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub8_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub8_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub8_lk = 1'h0; endcase @@ -116273,42 +125101,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub8_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub8_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub8_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub8_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub8_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub8_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub8_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub8_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub8_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub8_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub8_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub8_sgl_pipe = 1'h0; endcase @@ -116316,42 +125144,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub8_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub8_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub8_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub8_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub8_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub8_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub8_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub8_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub8_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub8_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub8_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub8_SV_Etype = 2'h2; endcase @@ -116359,42 +125187,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub8_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub8_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub8_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub8_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub8_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub8_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub8_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub8_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub8_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub8_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub8_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub8_SV_Ptype = 2'h2; endcase @@ -116402,42 +125230,42 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub8_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub8_in1_sel = 3'h1; endcase @@ -116445,128 +125273,128 @@ module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub8_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub8_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub8_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub8_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub8_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub8_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub8_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub8_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub8_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub8_in2_sel = 4'h9; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub8_in2_sel = 4'h9; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub8_in2_sel = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub8_in2_sel = 4'h0; endcase end always @* begin if (\initial ) begin end - dec31_dec_sub8_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub8_in3_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: - dec31_dec_sub8_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub8_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: - dec31_dec_sub8_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub8_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: - dec31_dec_sub8_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub8_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: - dec31_dec_sub8_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub8_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub8_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub8_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - dec31_dec_sub8_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub8_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: - dec31_dec_sub8_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub8_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: - dec31_dec_sub8_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub8_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - dec31_dec_sub8_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub8_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: - dec31_dec_sub8_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub8_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: - dec31_dec_sub8_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub8_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: - dec31_dec_sub8_in3_sel = 2'h0; + dec31_dec_sub8_in3_sel = 3'h0; endcase end always @* begin if (\initial ) begin end dec31_dec_sub8_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h03: dec31_dec_sub8_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h13: dec31_dec_sub8_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h01: dec31_dec_sub8_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h11: dec31_dec_sub8_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub8_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub8_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h04: dec31_dec_sub8_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h14: dec31_dec_sub8_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub8_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub8_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h06: dec31_dec_sub8_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h16: dec31_dec_sub8_out_sel = 3'h1; endcase @@ -116582,20 +125410,20 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub9_SV_Etype; reg [1:0] dec31_dec_sub9_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub9_SV_Ptype; reg [1:0] dec31_dec_sub9_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec31_dec_sub9_asmcode; reg [7:0] dec31_dec_sub9_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub9_br; reg dec31_dec_sub9_br; (* enum_base_type = "CRInSel" *) @@ -116607,7 +125435,7 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub9_cr_in; reg [2:0] dec31_dec_sub9_cr_in; (* enum_base_type = "CROutSel" *) @@ -116617,17 +125445,17 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub9_cr_out; reg [2:0] dec31_dec_sub9_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub9_cry_in; reg [1:0] dec31_dec_sub9_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub9_cry_out; reg dec31_dec_sub9_cry_out; (* enum_base_type = "Form" *) @@ -116661,34 +125489,37 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec31_dec_sub9_form; reg [4:0] dec31_dec_sub9_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] dec31_dec_sub9_function_unit; - reg [13:0] dec31_dec_sub9_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] dec31_dec_sub9_function_unit; + reg [14:0] dec31_dec_sub9_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub9_in1_sel; reg [2:0] dec31_dec_sub9_in1_sel; (* enum_base_type = "In2Sel" *) @@ -116706,16 +125537,19 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub9_in2_sel; reg [3:0] dec31_dec_sub9_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [1:0] dec31_dec_sub9_in3_sel; - reg [1:0] dec31_dec_sub9_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [2:0] dec31_dec_sub9_in3_sel; + reg [2:0] dec31_dec_sub9_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -116791,16 +125625,18 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec31_dec_sub9_internal_op; reg [6:0] dec31_dec_sub9_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub9_inv_a; reg dec31_dec_sub9_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub9_inv_out; reg dec31_dec_sub9_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub9_is_32b; reg dec31_dec_sub9_is_32b; (* enum_base_type = "LdstLen" *) @@ -116809,10 +125645,10 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec31_dec_sub9_ldst_len; reg [3:0] dec31_dec_sub9_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub9_lk; reg dec31_dec_sub9_lk; (* enum_base_type = "OutSel" *) @@ -116821,26 +125657,27 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub9_out_sel; reg [2:0] dec31_dec_sub9_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub9_rc_sel; reg [1:0] dec31_dec_sub9_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub9_rsrv; reg dec31_dec_sub9_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub9_sgl_pipe; reg dec31_dec_sub9_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub9_sgn; reg dec31_dec_sub9_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec31_dec_sub9_sgn_ext; reg dec31_dec_sub9_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -116850,7 +125687,7 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub9_sv_cr_in; reg [2:0] dec31_dec_sub9_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -116860,7 +125697,7 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub9_sv_cr_out; reg [2:0] dec31_dec_sub9_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -116870,7 +125707,7 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub9_sv_in1; reg [2:0] dec31_dec_sub9_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -116880,7 +125717,7 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub9_sv_in2; reg [2:0] dec31_dec_sub9_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -116890,7 +125727,7 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub9_sv_in3; reg [2:0] dec31_dec_sub9_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -116900,7 +125737,7 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub9_sv_out; reg [2:0] dec31_dec_sub9_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -116910,7 +125747,7 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec31_dec_sub9_sv_out2; reg [2:0] dec31_dec_sub9_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -116918,119 +125755,119 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec31_dec_sub9_upd; reg [1:0] dec31_dec_sub9_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - dec31_dec_sub9_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub9_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: - dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: - dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: - dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: - dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: - dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: - dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: - dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: - dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: - dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - dec31_dec_sub9_function_unit = 14'h0200; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_function_unit = 15'h0200; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: - dec31_dec_sub9_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_function_unit = 15'h0100; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub9_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_function_unit = 15'h0100; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: - dec31_dec_sub9_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_function_unit = 15'h0100; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - dec31_dec_sub9_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_function_unit = 15'h0100; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - dec31_dec_sub9_function_unit = 14'h0100; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_function_unit = 15'h0100; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: - dec31_dec_sub9_function_unit = 14'h0100; + dec31_dec_sub9_function_unit = 15'h0100; endcase end always @* begin if (\initial ) begin end dec31_dec_sub9_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub9_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub9_cr_in = 3'h0; endcase @@ -117038,54 +125875,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub9_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub9_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub9_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub9_cr_out = 3'h1; endcase @@ -117093,54 +125930,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub9_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub9_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub9_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub9_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub9_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub9_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub9_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub9_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub9_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub9_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub9_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub9_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub9_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub9_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub9_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub9_sv_in1 = 3'h2; endcase @@ -117148,54 +125985,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub9_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub9_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub9_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub9_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub9_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub9_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub9_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub9_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub9_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub9_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub9_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub9_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub9_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub9_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub9_sv_in2 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub9_sv_in2 = 3'h3; endcase @@ -117203,54 +126040,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub9_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub9_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub9_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub9_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub9_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub9_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub9_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub9_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub9_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub9_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub9_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub9_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub9_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub9_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub9_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub9_sv_in3 = 3'h0; endcase @@ -117258,54 +126095,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub9_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub9_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub9_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub9_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub9_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub9_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub9_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub9_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub9_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub9_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub9_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub9_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub9_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub9_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub9_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub9_sv_out = 3'h1; endcase @@ -117313,54 +126150,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub9_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub9_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub9_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub9_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub9_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub9_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub9_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub9_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub9_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub9_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub9_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub9_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub9_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub9_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub9_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub9_sv_out2 = 3'h0; endcase @@ -117368,54 +126205,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub9_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub9_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub9_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub9_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub9_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub9_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub9_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub9_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub9_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub9_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub9_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub9_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub9_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub9_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub9_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub9_sv_cr_in = 3'h0; endcase @@ -117423,54 +126260,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub9_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub9_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub9_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub9_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub9_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub9_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub9_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub9_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub9_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub9_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub9_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub9_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub9_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub9_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub9_sv_cr_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub9_sv_cr_out = 3'h1; endcase @@ -117478,54 +126315,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub9_ldst_len = 4'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub9_ldst_len = 4'h0; endcase @@ -117533,54 +126370,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub9_internal_op = 7'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub9_internal_op = 7'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub9_internal_op = 7'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub9_internal_op = 7'h1e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub9_internal_op = 7'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub9_internal_op = 7'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub9_internal_op = 7'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub9_internal_op = 7'h1d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub9_internal_op = 7'h2f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub9_internal_op = 7'h2f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub9_internal_op = 7'h33; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub9_internal_op = 7'h33; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub9_internal_op = 7'h33; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub9_internal_op = 7'h33; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub9_internal_op = 7'h32; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub9_internal_op = 7'h32; endcase @@ -117588,54 +126425,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub9_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub9_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub9_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub9_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub9_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub9_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub9_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub9_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub9_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub9_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub9_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub9_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub9_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub9_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub9_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub9_upd = 2'h0; endcase @@ -117643,54 +126480,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub9_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub9_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub9_rc_sel = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub9_rc_sel = 2'h2; endcase @@ -117698,54 +126535,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub9_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub9_cry_in = 2'h0; endcase @@ -117753,109 +126590,109 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub9_asmcode = 8'h36; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub9_asmcode = 8'h37; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub9_asmcode = 8'h34; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub9_asmcode = 8'h35; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub9_asmcode = 8'h39; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub9_asmcode = 8'h3a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub9_asmcode = 8'h33; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub9_asmcode = 8'h38; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: - dec31_dec_sub9_asmcode = 8'h74; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_asmcode = 8'h94; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - dec31_dec_sub9_asmcode = 8'h72; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_asmcode = 8'h92; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: - dec31_dec_sub9_asmcode = 8'h7a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_asmcode = 8'h9a; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub9_asmcode = 8'h7b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_asmcode = 8'h9b; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: - dec31_dec_sub9_asmcode = 8'h7a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_asmcode = 8'h9a; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - dec31_dec_sub9_asmcode = 8'h7b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_asmcode = 8'h9b; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - dec31_dec_sub9_asmcode = 8'h7e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_asmcode = 8'h9e; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: - dec31_dec_sub9_asmcode = 8'h7f; + dec31_dec_sub9_asmcode = 8'h9f; endcase end always @* begin if (\initial ) begin end dec31_dec_sub9_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub9_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub9_inv_a = 1'h0; endcase @@ -117863,54 +126700,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub9_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub9_inv_out = 1'h0; endcase @@ -117918,54 +126755,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub9_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub9_cry_out = 1'h0; endcase @@ -117973,54 +126810,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub9_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub9_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub9_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub9_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub9_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub9_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub9_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub9_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub9_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub9_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub9_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub9_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub9_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub9_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub9_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub9_br = 1'h0; endcase @@ -118028,54 +126865,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub9_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub9_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub9_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub9_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub9_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub9_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub9_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub9_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub9_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub9_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub9_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub9_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub9_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub9_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub9_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub9_sgn_ext = 1'h0; endcase @@ -118083,54 +126920,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub9_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub9_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub9_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub9_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub9_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub9_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub9_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub9_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub9_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub9_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub9_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub9_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub9_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub9_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub9_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub9_rsrv = 1'h0; endcase @@ -118138,54 +126975,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub9_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub9_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub9_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub9_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub9_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub9_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub9_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub9_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub9_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub9_form = 5'h08; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub9_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub9_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub9_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub9_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub9_form = 5'h11; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub9_form = 5'h11; endcase @@ -118193,54 +127030,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub9_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub9_is_32b = 1'h0; endcase @@ -118248,54 +127085,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub9_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub9_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub9_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub9_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub9_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub9_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub9_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub9_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub9_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub9_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub9_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub9_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub9_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub9_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub9_sgn = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub9_sgn = 1'h1; endcase @@ -118303,54 +127140,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub9_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub9_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub9_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub9_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub9_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub9_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub9_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub9_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub9_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub9_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub9_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub9_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub9_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub9_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub9_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub9_lk = 1'h0; endcase @@ -118358,54 +127195,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub9_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub9_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub9_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub9_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub9_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub9_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub9_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub9_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub9_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub9_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub9_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub9_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub9_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub9_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub9_sgl_pipe = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub9_sgl_pipe = 1'h0; endcase @@ -118413,54 +127250,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub9_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub9_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub9_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub9_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub9_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub9_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub9_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub9_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub9_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub9_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub9_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub9_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub9_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub9_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub9_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub9_SV_Etype = 2'h2; endcase @@ -118468,54 +127305,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub9_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub9_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub9_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub9_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub9_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub9_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub9_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub9_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub9_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub9_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub9_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub9_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub9_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub9_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub9_SV_Ptype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub9_SV_Ptype = 2'h1; endcase @@ -118523,54 +127360,54 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub9_in1_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub9_in1_sel = 3'h1; endcase @@ -118578,164 +127415,164 @@ module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, always @* begin if (\initial ) begin end dec31_dec_sub9_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub9_in2_sel = 4'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub9_in2_sel = 4'h1; endcase end always @* begin if (\initial ) begin end - dec31_dec_sub9_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec31_dec_sub9_in3_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: - dec31_dec_sub9_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: - dec31_dec_sub9_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: - dec31_dec_sub9_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: - dec31_dec_sub9_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: - dec31_dec_sub9_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: - dec31_dec_sub9_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: - dec31_dec_sub9_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: - dec31_dec_sub9_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: - dec31_dec_sub9_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: - dec31_dec_sub9_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: - dec31_dec_sub9_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: - dec31_dec_sub9_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: - dec31_dec_sub9_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: - dec31_dec_sub9_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: - dec31_dec_sub9_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec31_dec_sub9_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: - dec31_dec_sub9_in3_sel = 2'h0; + dec31_dec_sub9_in3_sel = 3'h0; endcase end always @* begin if (\initial ) begin end dec31_dec_sub9_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0c: dec31_dec_sub9_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1c: dec31_dec_sub9_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0d: dec31_dec_sub9_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1d: dec31_dec_sub9_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0e: dec31_dec_sub9_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1e: dec31_dec_sub9_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h0f: dec31_dec_sub9_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h1f: dec31_dec_sub9_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h08: dec31_dec_sub9_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h18: dec31_dec_sub9_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h02: dec31_dec_sub9_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h00: dec31_dec_sub9_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h12: dec31_dec_sub9_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h10: dec31_dec_sub9_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h07: dec31_dec_sub9_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 5'h17: dec31_dec_sub9_out_sel = 3'h1; endcase @@ -118751,20 +127588,20 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec58_SV_Etype; reg [1:0] dec58_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec58_SV_Ptype; reg [1:0] dec58_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec58_asmcode; reg [7:0] dec58_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec58_br; reg dec58_br; (* enum_base_type = "CRInSel" *) @@ -118776,7 +127613,7 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec58_cr_in; reg [2:0] dec58_cr_in; (* enum_base_type = "CROutSel" *) @@ -118786,17 +127623,17 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec58_cr_out; reg [2:0] dec58_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec58_cry_in; reg [1:0] dec58_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec58_cry_out; reg dec58_cry_out; (* enum_base_type = "Form" *) @@ -118830,34 +127667,37 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec58_form; reg [4:0] dec58_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] dec58_function_unit; - reg [13:0] dec58_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] dec58_function_unit; + reg [14:0] dec58_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec58_in1_sel; reg [2:0] dec58_in1_sel; (* enum_base_type = "In2Sel" *) @@ -118875,16 +127715,19 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec58_in2_sel; reg [3:0] dec58_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [1:0] dec58_in3_sel; - reg [1:0] dec58_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [2:0] dec58_in3_sel; + reg [2:0] dec58_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -118960,16 +127803,18 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec58_internal_op; reg [6:0] dec58_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec58_inv_a; reg dec58_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec58_inv_out; reg dec58_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec58_is_32b; reg dec58_is_32b; (* enum_base_type = "LdstLen" *) @@ -118978,10 +127823,10 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec58_ldst_len; reg [3:0] dec58_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec58_lk; reg dec58_lk; (* enum_base_type = "OutSel" *) @@ -118990,26 +127835,27 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec58_out_sel; reg [2:0] dec58_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec58_rc_sel; reg [1:0] dec58_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec58_rsrv; reg dec58_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec58_sgl_pipe; reg dec58_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec58_sgn; reg dec58_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec58_sgn_ext; reg dec58_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -119019,7 +127865,7 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec58_sv_cr_in; reg [2:0] dec58_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -119029,7 +127875,7 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec58_sv_cr_out; reg [2:0] dec58_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -119039,7 +127885,7 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec58_sv_in1; reg [2:0] dec58_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -119049,7 +127895,7 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec58_sv_in2; reg [2:0] dec58_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -119059,7 +127905,7 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec58_sv_in3; reg [2:0] dec58_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -119069,7 +127915,7 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec58_sv_out; reg [2:0] dec58_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -119079,7 +127925,7 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec58_sv_out2; reg [2:0] dec58_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -119087,41 +127933,41 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec58_upd; reg [1:0] dec58_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [1:0] opcode_switch; always @* begin if (\initial ) begin end - dec58_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec58_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: - dec58_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec58_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: - dec58_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec58_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: - dec58_function_unit = 14'h0004; + dec58_function_unit = 15'h0004; endcase end always @* begin if (\initial ) begin end dec58_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec58_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec58_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: dec58_cr_in = 3'h0; endcase @@ -119129,15 +127975,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec58_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec58_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: dec58_cr_out = 3'h0; endcase @@ -119145,15 +127991,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec58_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec58_sv_in1 = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: dec58_sv_in1 = 3'h2; endcase @@ -119161,15 +128007,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec58_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec58_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: dec58_sv_in2 = 3'h0; endcase @@ -119177,15 +128023,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec58_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec58_sv_in3 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: dec58_sv_in3 = 3'h0; endcase @@ -119193,15 +128039,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec58_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec58_sv_out = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: dec58_sv_out = 3'h1; endcase @@ -119209,15 +128055,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec58_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec58_sv_out2 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: dec58_sv_out2 = 3'h0; endcase @@ -119225,15 +128071,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec58_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec58_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: dec58_sv_cr_in = 3'h0; endcase @@ -119241,15 +128087,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec58_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec58_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: dec58_sv_cr_out = 3'h0; endcase @@ -119257,15 +128103,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec58_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec58_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: dec58_ldst_len = 4'h4; endcase @@ -119273,15 +128119,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec58_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec58_internal_op = 7'h25; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: dec58_internal_op = 7'h25; endcase @@ -119289,15 +128135,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec58_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec58_upd = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: dec58_upd = 2'h0; endcase @@ -119305,15 +128151,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec58_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec58_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: dec58_rc_sel = 2'h0; endcase @@ -119321,15 +128167,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec58_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec58_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: dec58_cry_in = 2'h0; endcase @@ -119337,31 +128183,31 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: - dec58_asmcode = 8'h52; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec58_asmcode = 8'h68; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: - dec58_asmcode = 8'h55; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec58_asmcode = 8'h6b; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: - dec58_asmcode = 8'h62; + dec58_asmcode = 8'h82; endcase end always @* begin if (\initial ) begin end dec58_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec58_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec58_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: dec58_inv_a = 1'h0; endcase @@ -119369,15 +128215,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec58_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec58_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: dec58_inv_out = 1'h0; endcase @@ -119385,15 +128231,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec58_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec58_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: dec58_cry_out = 1'h0; endcase @@ -119401,15 +128247,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec58_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec58_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: dec58_br = 1'h0; endcase @@ -119417,15 +128263,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec58_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec58_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: dec58_sgn_ext = 1'h1; endcase @@ -119433,15 +128279,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec58_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec58_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: dec58_rsrv = 1'h0; endcase @@ -119449,15 +128295,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec58_form = 5'h05; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec58_form = 5'h05; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: dec58_form = 5'h05; endcase @@ -119465,15 +128311,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec58_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec58_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: dec58_is_32b = 1'h0; endcase @@ -119481,15 +128327,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec58_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec58_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: dec58_sgn = 1'h0; endcase @@ -119497,15 +128343,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec58_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec58_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: dec58_lk = 1'h0; endcase @@ -119513,15 +128359,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec58_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec58_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: dec58_sgl_pipe = 1'h1; endcase @@ -119529,15 +128375,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec58_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec58_SV_Etype = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: dec58_SV_Etype = 2'h2; endcase @@ -119545,15 +128391,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec58_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec58_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: dec58_SV_Ptype = 2'h2; endcase @@ -119561,15 +128407,15 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec58_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec58_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: dec58_in1_sel = 3'h2; endcase @@ -119577,47 +128423,47 @@ module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, always @* begin if (\initial ) begin end dec58_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec58_in2_sel = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec58_in2_sel = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: dec58_in2_sel = 4'h8; endcase end always @* begin if (\initial ) begin end - dec58_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec58_in3_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: - dec58_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec58_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: - dec58_in3_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec58_in3_sel = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: - dec58_in3_sel = 2'h0; + dec58_in3_sel = 3'h0; endcase end always @* begin if (\initial ) begin end dec58_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec58_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec58_out_sel = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h2: dec58_out_sel = 3'h1; endcase @@ -119633,20 +128479,20 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_00 = "NONE" *) (* enum_value_01 = "EXTRA2" *) (* enum_value_10 = "EXTRA3" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec62_SV_Etype; reg [1:0] dec62_SV_Etype; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "P1" *) (* enum_value_10 = "P2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec62_SV_Ptype; reg [1:0] dec62_SV_Ptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [7:0] dec62_asmcode; reg [7:0] dec62_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec62_br; reg dec62_br; (* enum_base_type = "CRInSel" *) @@ -119658,7 +128504,7 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec62_cr_in; reg [2:0] dec62_cr_in; (* enum_base_type = "CROutSel" *) @@ -119668,17 +128514,17 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec62_cr_out; reg [2:0] dec62_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec62_cry_in; reg [1:0] dec62_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec62_cry_out; reg dec62_cry_out; (* enum_base_type = "Form" *) @@ -119712,34 +128558,37 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_11011 = "Z22" *) (* enum_value_11100 = "Z23" *) (* enum_value_11101 = "SVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [4:0] dec62_form; reg [4:0] dec62_form; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [13:0] dec62_function_unit; - reg [13:0] dec62_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [14:0] dec62_function_unit; + reg [14:0] dec62_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec62_in1_sel; reg [2:0] dec62_in1_sel; (* enum_base_type = "In2Sel" *) @@ -119757,16 +128606,19 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec62_in2_sel; reg [3:0] dec62_in2_sel; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - output [1:0] dec62_in3_sel; - reg [1:0] dec62_in3_sel; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + output [2:0] dec62_in3_sel; + reg [2:0] dec62_in3_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -119842,16 +128694,18 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [6:0] dec62_internal_op; reg [6:0] dec62_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec62_inv_a; reg dec62_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec62_inv_out; reg dec62_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec62_is_32b; reg dec62_is_32b; (* enum_base_type = "LdstLen" *) @@ -119860,10 +128714,10 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [3:0] dec62_ldst_len; reg [3:0] dec62_ldst_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec62_lk; reg dec62_lk; (* enum_base_type = "OutSel" *) @@ -119872,26 +128726,27 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec62_out_sel; reg [2:0] dec62_out_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec62_rc_sel; reg [1:0] dec62_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec62_rsrv; reg dec62_rsrv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec62_sgl_pipe; reg dec62_sgl_pipe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec62_sgn; reg dec62_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) output dec62_sgn_ext; reg dec62_sgn_ext; (* enum_base_type = "SVEXTRA" *) @@ -119901,7 +128756,7 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec62_sv_cr_in; reg [2:0] dec62_sv_cr_in; (* enum_base_type = "SVEXTRA" *) @@ -119911,7 +128766,7 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec62_sv_cr_out; reg [2:0] dec62_sv_cr_out; (* enum_base_type = "SVEXTRA" *) @@ -119921,7 +128776,7 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec62_sv_in1; reg [2:0] dec62_sv_in1; (* enum_base_type = "SVEXTRA" *) @@ -119931,7 +128786,7 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec62_sv_in2; reg [2:0] dec62_sv_in2; (* enum_base_type = "SVEXTRA" *) @@ -119941,7 +128796,7 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec62_sv_in3; reg [2:0] dec62_sv_in3; (* enum_base_type = "SVEXTRA" *) @@ -119951,7 +128806,7 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec62_sv_out; reg [2:0] dec62_sv_out; (* enum_base_type = "SVEXTRA" *) @@ -119961,7 +128816,7 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_011 = "Idx2" *) (* enum_value_100 = "Idx3" *) (* enum_value_101 = "Idx_1_2" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [2:0] dec62_sv_out2; reg [2:0] dec62_sv_out2; (* enum_base_type = "LDSTMode" *) @@ -119969,35 +128824,35 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) output [1:0] dec62_upd; reg [1:0] dec62_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) input [31:0] opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:348" *) wire [1:0] opcode_switch; always @* begin if (\initial ) begin end - dec62_function_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec62_function_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: - dec62_function_unit = 14'h0004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec62_function_unit = 15'h0004; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: - dec62_function_unit = 14'h0004; + dec62_function_unit = 15'h0004; endcase end always @* begin if (\initial ) begin end dec62_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec62_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec62_cr_in = 3'h0; endcase @@ -120005,12 +128860,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec62_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec62_cr_out = 3'h0; endcase @@ -120018,12 +128873,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_sv_in1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec62_sv_in1 = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec62_sv_in1 = 3'h3; endcase @@ -120031,12 +128886,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_sv_in2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec62_sv_in2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec62_sv_in2 = 3'h0; endcase @@ -120044,12 +128899,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_sv_in3 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec62_sv_in3 = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec62_sv_in3 = 3'h2; endcase @@ -120057,12 +128912,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_sv_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec62_sv_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec62_sv_out = 3'h0; endcase @@ -120070,12 +128925,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_sv_out2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec62_sv_out2 = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec62_sv_out2 = 3'h1; endcase @@ -120083,12 +128938,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_sv_cr_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec62_sv_cr_in = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec62_sv_cr_in = 3'h0; endcase @@ -120096,12 +128951,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_sv_cr_out = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec62_sv_cr_out = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec62_sv_cr_out = 3'h0; endcase @@ -120109,12 +128964,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_ldst_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec62_ldst_len = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec62_ldst_len = 4'h8; endcase @@ -120122,12 +128977,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_internal_op = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec62_internal_op = 7'h26; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec62_internal_op = 7'h26; endcase @@ -120135,12 +128990,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_upd = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec62_upd = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec62_upd = 2'h1; endcase @@ -120148,12 +129003,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_rc_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec62_rc_sel = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec62_rc_sel = 2'h0; endcase @@ -120161,12 +129016,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_cry_in = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec62_cry_in = 2'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec62_cry_in = 2'h0; endcase @@ -120174,25 +129029,25 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: - dec62_asmcode = 8'had; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec62_asmcode = 8'hcd; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: - dec62_asmcode = 8'hb0; + dec62_asmcode = 8'hd0; endcase end always @* begin if (\initial ) begin end dec62_inv_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec62_inv_a = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec62_inv_a = 1'h0; endcase @@ -120200,12 +129055,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_inv_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec62_inv_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec62_inv_out = 1'h0; endcase @@ -120213,12 +129068,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_cry_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec62_cry_out = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec62_cry_out = 1'h0; endcase @@ -120226,12 +129081,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_br = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec62_br = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec62_br = 1'h0; endcase @@ -120239,12 +129094,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_sgn_ext = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec62_sgn_ext = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec62_sgn_ext = 1'h0; endcase @@ -120252,12 +129107,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_rsrv = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec62_rsrv = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec62_rsrv = 1'h0; endcase @@ -120265,12 +129120,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_form = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec62_form = 5'h05; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec62_form = 5'h05; endcase @@ -120278,12 +129133,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_is_32b = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec62_is_32b = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec62_is_32b = 1'h0; endcase @@ -120291,12 +129146,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_sgn = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec62_sgn = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec62_sgn = 1'h0; endcase @@ -120304,12 +129159,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec62_lk = 1'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec62_lk = 1'h0; endcase @@ -120317,12 +129172,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_sgl_pipe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec62_sgl_pipe = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec62_sgl_pipe = 1'h1; endcase @@ -120330,12 +129185,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_SV_Etype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec62_SV_Etype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec62_SV_Etype = 2'h1; endcase @@ -120343,12 +129198,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_SV_Ptype = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec62_SV_Ptype = 2'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec62_SV_Ptype = 2'h2; endcase @@ -120356,12 +129211,12 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_in1_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec62_in1_sel = 3'h2; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec62_in1_sel = 3'h2; endcase @@ -120369,38 +129224,38 @@ module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, always @* begin if (\initial ) begin end dec62_in2_sel = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec62_in2_sel = 4'h8; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec62_in2_sel = 4'h8; endcase end always @* begin if (\initial ) begin end - dec62_in3_sel = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + dec62_in3_sel = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: - dec62_in3_sel = 2'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + dec62_in3_sel = 3'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: - dec62_in3_sel = 2'h1; + dec62_in3_sel = 3'h1; endcase end always @* begin if (\initial ) begin end dec62_out_sel = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:456" *) casez (opcode_switch) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h0: dec62_out_sel = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:458" */ 2'h1: dec62_out_sel = 3'h0; endcase @@ -120412,85 +129267,86 @@ endmodule (* generator = "nMigen" *) module dec_ALU(bigendian, sv_a_nz, ALU__insn_type, ALU__fn_unit, ALU__imm_data__data, ALU__imm_data__ok, ALU__rc__rc, ALU__rc__ok, ALU__oe__oe, ALU__oe__ok, ALU__invert_in, ALU__zero_a, ALU__invert_out, ALU__write_cr0, ALU__input_carry, ALU__output_carry, ALU__is_32bit, ALU__is_signed, ALU__data_len, ALU__insn, raw_opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:885" *) wire \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) wire \$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) wire \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) wire \$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) wire \$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$48 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [3:0] ALU__data_len; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] ALU__fn_unit; - reg [13:0] ALU__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] ALU__fn_unit; + reg [14:0] ALU__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] ALU__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output ALU__imm_data__ok; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [1:0] ALU__input_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] ALU__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -120567,53 +129423,55 @@ module dec_ALU(bigendian, sv_a_nz, ALU__insn_type, ALU__fn_unit, ALU__imm_data__ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] ALU__insn_type; reg [6:0] ALU__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output ALU__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output ALU__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output ALU__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output ALU__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output ALU__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output ALU__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output ALU__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output ALU__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output ALU__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output ALU__write_cr0; reg ALU__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output ALU__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:479" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] dec_ALU_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] dec_ALU_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [23:0] dec_ALU_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire dec_ALU_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] dec_ALU_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire dec_ALU_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] dec_ALU_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] dec_ALU_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] dec_ALU_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] dec_ALU_UI; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -120622,40 +129480,43 @@ module dec_ALU(bigendian, sv_a_nz, ALU__insn_type, ALU__fn_unit, ALU__imm_data__ (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_ALU_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_ALU_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_ALU_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec_ALU_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec_ALU_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_ALU_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -120672,7 +129533,8 @@ module dec_ALU(bigendian, sv_a_nz, ALU__insn_type, ALU__fn_unit, ALU__imm_data__ (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec_ALU_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -120749,13 +129611,15 @@ module dec_ALU(bigendian, sv_a_nz, ALU__insn_type, ALU__fn_unit, ALU__imm_data__ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec_ALU_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_ALU_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_ALU_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_ALU_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -120763,19 +129627,19 @@ module dec_ALU(bigendian, sv_a_nz, ALU__insn_type, ALU__fn_unit, ALU__imm_data__ (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec_ALU_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_ALU_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_ALU_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] dec_ALU_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:193" *) wire dec_ai_immz_out; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -120783,13 +129647,15 @@ module dec_ALU(bigendian, sv_a_nz, ALU__insn_type, ALU__fn_unit, ALU__imm_data__ (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:192" *) wire [2:0] dec_ai_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:194" *) wire dec_ai_sv_nz; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] dec_bi_imm_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_bi_imm_b_ok; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -120806,68 +129672,69 @@ module dec_ALU(bigendian, sv_a_nz, ALU__insn_type, ALU__fn_unit, ALU__imm_data__ (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" *) wire [3:0] dec_bi_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_oe_oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_oe_oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:527" *) wire [1:0] dec_oe_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] dec_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_rc_rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_rc_rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:490" *) wire [1:0] dec_rc_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:491" *) wire [31:0] insn_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:528" *) wire [31:0] \insn_in$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:884" *) wire is_mmu_spr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:883" *) wire is_spr_mv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:478" *) input [31:0] raw_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:878" *) wire [9:0] spr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:747" *) input sv_a_nz; - assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ; - assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ; - assign \$16 = dec_ALU_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31; - assign \$18 = dec_ALU_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e; - assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ; - assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12; - assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13; - assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ; - assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0; - assign \$2 = dec_ALU_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ; - assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30; - assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ; - assign \$36 = dec_ALU_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ; - assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$42 = dec_ALU_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; - assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ; - assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ; - assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ; - assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$8 = dec_ALU_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$8 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) is_mmu_spr; + assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$12 ; + assign \$16 = dec_ALU_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:885" *) 7'h31; + assign \$18 = dec_ALU_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) 7'h2e; + assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) \$18 ; + assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 5'h12; + assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 5'h13; + assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) \$24 ; + assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 10'h2d0; + assign \$2 = dec_ALU_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) 15'h0400; + assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) \$28 ; + assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) 6'h30; + assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) \$32 ; + assign \$36 = dec_ALU_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) 15'h0400; + assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) \$36 ; + assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) is_mmu_spr; + assign \$42 = dec_ALU_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) 15'h0800; + assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$42 ; + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) is_mmu_spr; + assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$46 ; + assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) \$2 ; + assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) is_mmu_spr; + assign \$8 = dec_ALU_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) 15'h0800; dec dec ( .ALU_BD(dec_ALU_BD), .ALU_DS(dec_ALU_DS), @@ -120931,14 +129798,14 @@ module dec_ALU(bigendian, sv_a_nz, ALU__insn_type, ALU__fn_unit, ALU__imm_data__ always @* begin if (\initial ) begin end ALU__write_cr0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:921" *) casez (dec_ALU_cr_out) /* \nmigen.decoding = "CR0/1|CR1/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:880" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:922" */ 3'h1, 3'h5: ALU__write_cr0 = dec_rc_rc; /* \nmigen.decoding = "BF/2|BT/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:924" */ 3'h2, 3'h3: ALU__write_cr0 = 1'h1; endcase @@ -120946,12 +129813,12 @@ module dec_ALU(bigendian, sv_a_nz, ALU__insn_type, ALU__fn_unit, ALU__imm_data__ always @* begin if (\initial ) begin end ALU__insn_type = dec_ALU_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) casez ({ \$14 , \$6 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" */ 2'b?1: ALU__insn_type = 7'h00; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" */ 2'b1?: ALU__insn_type = 7'h00; endcase @@ -120959,15 +129826,15 @@ module dec_ALU(bigendian, sv_a_nz, ALU__insn_type, ALU__fn_unit, ALU__imm_data__ always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) casez ({ \$48 , \$40 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" */ 2'b?1: - ALU__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + ALU__fn_unit = 15'h0000; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" */ 2'b1?: - ALU__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" */ + ALU__fn_unit = 15'h0000; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:900" */ default: ALU__fn_unit = dec_ALU_function_unit; endcase @@ -121000,79 +129867,80 @@ endmodule (* generator = "nMigen" *) module dec_BRANCH(raw_opcode_in, bigendian, BRANCH__cia, BRANCH__insn_type, BRANCH__fn_unit, BRANCH__insn, BRANCH__imm_data__data, BRANCH__imm_data__ok, BRANCH__lk, BRANCH__is_32bit, core_pc); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:885" *) wire \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) wire \$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) wire \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) wire \$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) wire \$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$48 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] BRANCH__cia; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] BRANCH__fn_unit; - reg [13:0] BRANCH__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] BRANCH__fn_unit; + reg [14:0] BRANCH__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] BRANCH__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output BRANCH__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] BRANCH__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -121149,37 +130017,39 @@ module dec_BRANCH(raw_opcode_in, bigendian, BRANCH__cia, BRANCH__insn_type, BRAN (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] BRANCH__insn_type; reg [6:0] BRANCH__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output BRANCH__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output BRANCH__lk; reg BRANCH__lk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:479" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:16" *) input [63:0] core_pc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] dec_BRANCH_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] dec_BRANCH_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [23:0] dec_BRANCH_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire dec_BRANCH_LK; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire dec_BRANCH_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire dec_BRANCH_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] dec_BRANCH_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] dec_BRANCH_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] dec_BRANCH_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] dec_BRANCH_UI; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -121188,25 +130058,26 @@ module dec_BRANCH(raw_opcode_in, bigendian, BRANCH__cia, BRANCH__insn_type, BRAN (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_BRANCH_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec_BRANCH_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec_BRANCH_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -121222,7 +130093,8 @@ module dec_BRANCH(raw_opcode_in, bigendian, BRANCH__cia, BRANCH__insn_type, BRAN (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec_BRANCH_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -121299,23 +130171,25 @@ module dec_BRANCH(raw_opcode_in, bigendian, BRANCH__cia, BRANCH__insn_type, BRAN (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec_BRANCH_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_BRANCH_is_32b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_BRANCH_lk; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_BRANCH_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] dec_BRANCH_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] dec_bi_imm_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_bi_imm_b_ok; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -121332,58 +130206,59 @@ module dec_BRANCH(raw_opcode_in, bigendian, BRANCH__cia, BRANCH__insn_type, BRAN (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" *) wire [3:0] dec_bi_sel_in; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:527" *) wire [1:0] dec_oe_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] dec_opcode_in; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:490" *) wire [1:0] dec_rc_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:491" *) wire [31:0] insn_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:528" *) wire [31:0] \insn_in$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:884" *) wire is_mmu_spr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:883" *) wire is_spr_mv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:478" *) input [31:0] raw_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:878" *) wire [9:0] spr; - assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ; - assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ; - assign \$16 = dec_BRANCH_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31; - assign \$18 = dec_BRANCH_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e; - assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ; - assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12; - assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13; - assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ; - assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0; - assign \$2 = dec_BRANCH_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ; - assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30; - assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ; - assign \$36 = dec_BRANCH_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ; - assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$42 = dec_BRANCH_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; - assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ; - assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ; - assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ; - assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$8 = dec_BRANCH_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$8 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) is_mmu_spr; + assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$12 ; + assign \$16 = dec_BRANCH_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:885" *) 7'h31; + assign \$18 = dec_BRANCH_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) 7'h2e; + assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) \$18 ; + assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 5'h12; + assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 5'h13; + assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) \$24 ; + assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 10'h2d0; + assign \$2 = dec_BRANCH_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) 15'h0400; + assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) \$28 ; + assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) 6'h30; + assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) \$32 ; + assign \$36 = dec_BRANCH_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) 15'h0400; + assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) \$36 ; + assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) is_mmu_spr; + assign \$42 = dec_BRANCH_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) 15'h0800; + assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$42 ; + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) is_mmu_spr; + assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$46 ; + assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) \$2 ; + assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) is_mmu_spr; + assign \$8 = dec_BRANCH_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) 15'h0800; \dec$141 dec ( .BRANCH_BD(dec_BRANCH_BD), .BRANCH_DS(dec_BRANCH_DS), @@ -121431,15 +130306,15 @@ module dec_BRANCH(raw_opcode_in, bigendian, BRANCH__cia, BRANCH__insn_type, BRAN always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) casez ({ \$48 , \$40 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" */ 2'b?1: - BRANCH__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + BRANCH__fn_unit = 15'h0000; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" */ 2'b1?: - BRANCH__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" */ + BRANCH__fn_unit = 15'h0000; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:900" */ default: BRANCH__fn_unit = dec_BRANCH_function_unit; endcase @@ -121447,9 +130322,9 @@ module dec_BRANCH(raw_opcode_in, bigendian, BRANCH__cia, BRANCH__insn_type, BRAN always @* begin if (\initial ) begin end BRANCH__lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:898" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:948" *) casez (dec_BRANCH_lk) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:898" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:948" */ 1'h1: BRANCH__lk = dec_BRANCH_LK; endcase @@ -121457,12 +130332,12 @@ module dec_BRANCH(raw_opcode_in, bigendian, BRANCH__cia, BRANCH__insn_type, BRAN always @* begin if (\initial ) begin end BRANCH__insn_type = dec_BRANCH_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) casez ({ \$14 , \$6 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" */ 2'b?1: BRANCH__insn_type = 7'h00; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" */ 2'b1?: BRANCH__insn_type = 7'h00; endcase @@ -121485,73 +130360,74 @@ endmodule (* generator = "nMigen" *) module dec_CR(bigendian, CR__insn_type, CR__fn_unit, CR__insn, raw_opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:885" *) wire \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) wire \$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) wire \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) wire \$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) wire \$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$48 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$8 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] CR__fn_unit; - reg [13:0] CR__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] CR__fn_unit; + reg [14:0] CR__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] CR__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -121628,16 +130504,18 @@ module dec_CR(bigendian, CR__insn_type, CR__fn_unit, CR__insn, raw_opcode_in); (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] CR__insn_type; reg [6:0] CR__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:479" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire dec_CR_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire dec_CR_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] dec_CR_SPR; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -121646,25 +130524,26 @@ module dec_CR(bigendian, CR__insn_type, CR__fn_unit, CR__insn, raw_opcode_in); (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_CR_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec_CR_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec_CR_function_unit; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -121740,64 +130619,66 @@ module dec_CR(bigendian, CR__insn_type, CR__fn_unit, CR__insn, raw_opcode_in); (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec_CR_internal_op; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_CR_rc_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:527" *) wire [1:0] dec_oe_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] dec_opcode_in; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:490" *) wire [1:0] dec_rc_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:491" *) wire [31:0] insn_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:528" *) wire [31:0] \insn_in$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:884" *) wire is_mmu_spr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:883" *) wire is_spr_mv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:478" *) input [31:0] raw_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:878" *) wire [9:0] spr; - assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ; - assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ; - assign \$16 = dec_CR_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31; - assign \$18 = dec_CR_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e; - assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ; - assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12; - assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13; - assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ; - assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0; - assign \$2 = dec_CR_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ; - assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30; - assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ; - assign \$36 = dec_CR_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ; - assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$42 = dec_CR_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; - assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ; - assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ; - assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ; - assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$8 = dec_CR_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$8 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) is_mmu_spr; + assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$12 ; + assign \$16 = dec_CR_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:885" *) 7'h31; + assign \$18 = dec_CR_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) 7'h2e; + assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) \$18 ; + assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 5'h12; + assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 5'h13; + assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) \$24 ; + assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 10'h2d0; + assign \$2 = dec_CR_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) 15'h0400; + assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) \$28 ; + assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) 6'h30; + assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) \$32 ; + assign \$36 = dec_CR_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) 15'h0400; + assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) \$36 ; + assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) is_mmu_spr; + assign \$42 = dec_CR_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) 15'h0800; + assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$42 ; + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) is_mmu_spr; + assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$46 ; + assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) \$2 ; + assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) is_mmu_spr; + assign \$8 = dec_CR_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) 15'h0800; \dec$138 dec ( .CR_OE(dec_CR_OE), .CR_Rc(dec_CR_Rc), @@ -121822,12 +130703,12 @@ module dec_CR(bigendian, CR__insn_type, CR__fn_unit, CR__insn, raw_opcode_in); always @* begin if (\initial ) begin end CR__insn_type = dec_CR_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) casez ({ \$14 , \$6 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" */ 2'b?1: CR__insn_type = 7'h00; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" */ 2'b1?: CR__insn_type = 7'h00; endcase @@ -121835,15 +130716,15 @@ module dec_CR(bigendian, CR__insn_type, CR__fn_unit, CR__insn, raw_opcode_in); always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) casez ({ \$48 , \$40 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" */ 2'b?1: - CR__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + CR__fn_unit = 15'h0000; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" */ 2'b1?: - CR__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" */ + CR__fn_unit = 15'h0000; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:900" */ default: CR__fn_unit = dec_CR_function_unit; endcase @@ -121862,85 +130743,86 @@ endmodule (* generator = "nMigen" *) module dec_DIV(bigendian, sv_a_nz, DIV__insn_type, DIV__fn_unit, DIV__imm_data__data, DIV__imm_data__ok, DIV__rc__rc, DIV__rc__ok, DIV__oe__oe, DIV__oe__ok, DIV__invert_in, DIV__zero_a, DIV__input_carry, DIV__invert_out, DIV__write_cr0, DIV__output_carry, DIV__is_32bit, DIV__is_signed, DIV__data_len, DIV__insn, raw_opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:885" *) wire \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) wire \$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) wire \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) wire \$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) wire \$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$48 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [3:0] DIV__data_len; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] DIV__fn_unit; - reg [13:0] DIV__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] DIV__fn_unit; + reg [14:0] DIV__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] DIV__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output DIV__imm_data__ok; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [1:0] DIV__input_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] DIV__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -122017,53 +130899,55 @@ module dec_DIV(bigendian, sv_a_nz, DIV__insn_type, DIV__fn_unit, DIV__imm_data__ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] DIV__insn_type; reg [6:0] DIV__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output DIV__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output DIV__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output DIV__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output DIV__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output DIV__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output DIV__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output DIV__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output DIV__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output DIV__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output DIV__write_cr0; reg DIV__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output DIV__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:479" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] dec_DIV_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] dec_DIV_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [23:0] dec_DIV_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire dec_DIV_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] dec_DIV_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire dec_DIV_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] dec_DIV_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] dec_DIV_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] dec_DIV_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] dec_DIV_UI; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -122072,40 +130956,43 @@ module dec_DIV(bigendian, sv_a_nz, DIV__insn_type, DIV__fn_unit, DIV__imm_data__ (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_DIV_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_DIV_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_DIV_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec_DIV_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec_DIV_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_DIV_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -122122,7 +131009,8 @@ module dec_DIV(bigendian, sv_a_nz, DIV__insn_type, DIV__fn_unit, DIV__imm_data__ (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec_DIV_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -122199,13 +131087,15 @@ module dec_DIV(bigendian, sv_a_nz, DIV__insn_type, DIV__fn_unit, DIV__imm_data__ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec_DIV_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_DIV_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_DIV_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_DIV_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -122213,19 +131103,19 @@ module dec_DIV(bigendian, sv_a_nz, DIV__insn_type, DIV__fn_unit, DIV__imm_data__ (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec_DIV_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_DIV_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_DIV_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] dec_DIV_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:193" *) wire dec_ai_immz_out; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -122233,13 +131123,15 @@ module dec_DIV(bigendian, sv_a_nz, DIV__insn_type, DIV__fn_unit, DIV__imm_data__ (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:192" *) wire [2:0] dec_ai_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:194" *) wire dec_ai_sv_nz; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] dec_bi_imm_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_bi_imm_b_ok; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -122256,68 +131148,69 @@ module dec_DIV(bigendian, sv_a_nz, DIV__insn_type, DIV__fn_unit, DIV__imm_data__ (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" *) wire [3:0] dec_bi_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_oe_oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_oe_oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:527" *) wire [1:0] dec_oe_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] dec_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_rc_rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_rc_rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:490" *) wire [1:0] dec_rc_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:491" *) wire [31:0] insn_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:528" *) wire [31:0] \insn_in$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:884" *) wire is_mmu_spr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:883" *) wire is_spr_mv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:478" *) input [31:0] raw_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:878" *) wire [9:0] spr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:747" *) input sv_a_nz; - assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ; - assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ; - assign \$16 = dec_DIV_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31; - assign \$18 = dec_DIV_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e; - assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ; - assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12; - assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13; - assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ; - assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0; - assign \$2 = dec_DIV_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ; - assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30; - assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ; - assign \$36 = dec_DIV_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ; - assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$42 = dec_DIV_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; - assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ; - assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ; - assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ; - assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$8 = dec_DIV_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$8 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) is_mmu_spr; + assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$12 ; + assign \$16 = dec_DIV_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:885" *) 7'h31; + assign \$18 = dec_DIV_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) 7'h2e; + assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) \$18 ; + assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 5'h12; + assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 5'h13; + assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) \$24 ; + assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 10'h2d0; + assign \$2 = dec_DIV_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) 15'h0400; + assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) \$28 ; + assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) 6'h30; + assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) \$32 ; + assign \$36 = dec_DIV_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) 15'h0400; + assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) \$36 ; + assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) is_mmu_spr; + assign \$42 = dec_DIV_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) 15'h0800; + assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$42 ; + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) is_mmu_spr; + assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$46 ; + assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) \$2 ; + assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) is_mmu_spr; + assign \$8 = dec_DIV_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) 15'h0800; \dec$153 dec ( .DIV_BD(dec_DIV_BD), .DIV_DS(dec_DIV_DS), @@ -122381,14 +131274,14 @@ module dec_DIV(bigendian, sv_a_nz, DIV__insn_type, DIV__fn_unit, DIV__imm_data__ always @* begin if (\initial ) begin end DIV__write_cr0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:921" *) casez (dec_DIV_cr_out) /* \nmigen.decoding = "CR0/1|CR1/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:880" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:922" */ 3'h1, 3'h5: DIV__write_cr0 = dec_rc_rc; /* \nmigen.decoding = "BF/2|BT/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:924" */ 3'h2, 3'h3: DIV__write_cr0 = 1'h1; endcase @@ -122396,12 +131289,12 @@ module dec_DIV(bigendian, sv_a_nz, DIV__insn_type, DIV__fn_unit, DIV__imm_data__ always @* begin if (\initial ) begin end DIV__insn_type = dec_DIV_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) casez ({ \$14 , \$6 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" */ 2'b?1: DIV__insn_type = 7'h00; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" */ 2'b1?: DIV__insn_type = 7'h00; endcase @@ -122409,15 +131302,15 @@ module dec_DIV(bigendian, sv_a_nz, DIV__insn_type, DIV__fn_unit, DIV__imm_data__ always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) casez ({ \$48 , \$40 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" */ 2'b?1: - DIV__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + DIV__fn_unit = 15'h0000; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" */ 2'b1?: - DIV__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" */ + DIV__fn_unit = 15'h0000; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:900" */ default: DIV__fn_unit = dec_DIV_function_unit; endcase @@ -122448,83 +131341,84 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_LDST" *) (* generator = "nMigen" *) -module dec_LDST(bigendian, sv_a_nz, LDST__insn_type, LDST__fn_unit, LDST__imm_data__data, LDST__imm_data__ok, LDST__zero_a, LDST__rc__rc, LDST__rc__ok, LDST__oe__oe, LDST__oe__ok, LDST__is_32bit, LDST__is_signed, LDST__data_len, LDST__byte_reverse, LDST__sign_extend, LDST__ldst_mode, LDST__insn, raw_opcode_in); +module dec_LDST(raw_opcode_in, bigendian, sv_a_nz, LDST__insn_type, LDST__fn_unit, LDST__imm_data__data, LDST__imm_data__ok, LDST__zero_a, LDST__rc__rc, LDST__rc__ok, LDST__oe__oe, LDST__oe__ok, LDST__msr, LDST__is_32bit, LDST__is_signed, LDST__data_len, LDST__byte_reverse, LDST__sign_extend, LDST__ldst_mode, LDST__insn, core_msr); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:885" *) wire \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) wire \$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) wire \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) wire \$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) wire \$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$48 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output LDST__byte_reverse; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [3:0] LDST__data_len; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] LDST__fn_unit; - reg [13:0] LDST__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] LDST__fn_unit; + reg [14:0] LDST__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] LDST__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output LDST__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] LDST__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -122601,55 +131495,61 @@ module dec_LDST(bigendian, sv_a_nz, LDST__insn_type, LDST__fn_unit, LDST__imm_da (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] LDST__insn_type; reg [6:0] LDST__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output LDST__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output LDST__is_signed; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [1:0] LDST__ldst_mode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [63:0] LDST__msr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output LDST__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output LDST__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output LDST__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output LDST__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output LDST__sign_extend; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output LDST__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:479" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:17" *) + input [63:0] core_msr; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] dec_LDST_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] dec_LDST_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [23:0] dec_LDST_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire dec_LDST_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] dec_LDST_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire dec_LDST_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] dec_LDST_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] dec_LDST_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] dec_LDST_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] dec_LDST_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_LDST_br; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -122658,32 +131558,35 @@ module dec_LDST(bigendian, sv_a_nz, LDST__insn_type, LDST__fn_unit, LDST__imm_da (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_LDST_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec_LDST_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec_LDST_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_LDST_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -122700,7 +131603,8 @@ module dec_LDST(bigendian, sv_a_nz, LDST__insn_type, LDST__fn_unit, LDST__imm_da (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec_LDST_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -122777,9 +131681,11 @@ module dec_LDST(bigendian, sv_a_nz, LDST__insn_type, LDST__fn_unit, LDST__imm_da (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec_LDST_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_LDST_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -122787,28 +131693,28 @@ module dec_LDST(bigendian, sv_a_nz, LDST__insn_type, LDST__fn_unit, LDST__imm_da (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec_LDST_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_LDST_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_LDST_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_LDST_sgn_ext; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] dec_LDST_sh; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_LDST_upd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:193" *) wire dec_ai_immz_out; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -122816,13 +131722,15 @@ module dec_LDST(bigendian, sv_a_nz, LDST__insn_type, LDST__fn_unit, LDST__imm_da (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:192" *) wire [2:0] dec_ai_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:194" *) wire dec_ai_sv_nz; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] dec_bi_imm_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_bi_imm_b_ok; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -122839,68 +131747,69 @@ module dec_LDST(bigendian, sv_a_nz, LDST__insn_type, LDST__fn_unit, LDST__imm_da (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" *) wire [3:0] dec_bi_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_oe_oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_oe_oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:527" *) wire [1:0] dec_oe_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] dec_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_rc_rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_rc_rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:490" *) wire [1:0] dec_rc_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:491" *) wire [31:0] insn_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:528" *) wire [31:0] \insn_in$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:884" *) wire is_mmu_spr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:883" *) wire is_spr_mv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:478" *) input [31:0] raw_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:878" *) wire [9:0] spr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:747" *) input sv_a_nz; - assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ; - assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ; - assign \$16 = dec_LDST_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31; - assign \$18 = dec_LDST_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e; - assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ; - assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12; - assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13; - assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ; - assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0; - assign \$2 = dec_LDST_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ; - assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30; - assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ; - assign \$36 = dec_LDST_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ; - assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$42 = dec_LDST_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; - assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ; - assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ; - assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ; - assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$8 = dec_LDST_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$8 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) is_mmu_spr; + assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$12 ; + assign \$16 = dec_LDST_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:885" *) 7'h31; + assign \$18 = dec_LDST_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) 7'h2e; + assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) \$18 ; + assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 5'h12; + assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 5'h13; + assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) \$24 ; + assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 10'h2d0; + assign \$2 = dec_LDST_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) 15'h0400; + assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) \$28 ; + assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) 6'h30; + assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) \$32 ; + assign \$36 = dec_LDST_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) 15'h0400; + assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) \$36 ; + assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) is_mmu_spr; + assign \$42 = dec_LDST_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) 15'h0800; + assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$42 ; + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) is_mmu_spr; + assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$46 ; + assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) \$2 ; + assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) is_mmu_spr; + assign \$8 = dec_LDST_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) 15'h0800; \dec$166 dec ( .LDST_BD(dec_LDST_BD), .LDST_DS(dec_LDST_DS), @@ -122962,31 +131871,31 @@ module dec_LDST(bigendian, sv_a_nz, LDST__insn_type, LDST__fn_unit, LDST__imm_da ); always @* begin if (\initial ) begin end - LDST__insn_type = dec_LDST_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) - casez ({ \$14 , \$6 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) + casez ({ \$48 , \$40 }) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" */ 2'b?1: - LDST__insn_type = 7'h00; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + LDST__fn_unit = 15'h0000; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" */ 2'b1?: - LDST__insn_type = 7'h00; + LDST__fn_unit = 15'h0000; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:900" */ + default: + LDST__fn_unit = dec_LDST_function_unit; endcase end always @* begin if (\initial ) begin end - (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) - casez ({ \$48 , \$40 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + LDST__insn_type = dec_LDST_internal_op; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) + casez ({ \$14 , \$6 }) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" */ 2'b?1: - LDST__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + LDST__insn_type = 7'h00; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" */ 2'b1?: - LDST__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" */ - default: - LDST__fn_unit = dec_LDST_function_unit; + LDST__insn_type = 7'h00; endcase end assign LDST__ldst_mode = dec_LDST_upd; @@ -123005,6 +131914,7 @@ module dec_LDST(bigendian, sv_a_nz, LDST__insn_type, LDST__fn_unit, LDST__imm_da assign is_mmu_spr = \$34 ; assign is_spr_mv = \$20 ; assign spr = { dec_LDST_SPR[4:0], dec_LDST_SPR[9:5] }; + assign LDST__msr = core_msr; assign dec_oe_sel_in = dec_LDST_rc_sel; assign dec_rc_sel_in = dec_LDST_rc_sel; assign \insn_in$1 = dec_opcode_in; @@ -123016,85 +131926,86 @@ endmodule (* generator = "nMigen" *) module dec_LOGICAL(bigendian, sv_a_nz, LOGICAL__insn_type, LOGICAL__fn_unit, LOGICAL__imm_data__data, LOGICAL__imm_data__ok, LOGICAL__rc__rc, LOGICAL__rc__ok, LOGICAL__oe__oe, LOGICAL__oe__ok, LOGICAL__invert_in, LOGICAL__zero_a, LOGICAL__input_carry, LOGICAL__invert_out, LOGICAL__write_cr0, LOGICAL__output_carry, LOGICAL__is_32bit, LOGICAL__is_signed, LOGICAL__data_len, LOGICAL__insn, raw_opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:885" *) wire \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) wire \$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) wire \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) wire \$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) wire \$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$48 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [3:0] LOGICAL__data_len; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] LOGICAL__fn_unit; - reg [13:0] LOGICAL__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] LOGICAL__fn_unit; + reg [14:0] LOGICAL__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] LOGICAL__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output LOGICAL__imm_data__ok; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [1:0] LOGICAL__input_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] LOGICAL__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -123171,53 +132082,55 @@ module dec_LOGICAL(bigendian, sv_a_nz, LOGICAL__insn_type, LOGICAL__fn_unit, LOG (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] LOGICAL__insn_type; reg [6:0] LOGICAL__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output LOGICAL__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output LOGICAL__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output LOGICAL__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output LOGICAL__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output LOGICAL__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output LOGICAL__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output LOGICAL__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output LOGICAL__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output LOGICAL__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output LOGICAL__write_cr0; reg LOGICAL__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output LOGICAL__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:479" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] dec_LOGICAL_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] dec_LOGICAL_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [23:0] dec_LOGICAL_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire dec_LOGICAL_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] dec_LOGICAL_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire dec_LOGICAL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] dec_LOGICAL_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] dec_LOGICAL_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] dec_LOGICAL_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] dec_LOGICAL_UI; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -123226,40 +132139,43 @@ module dec_LOGICAL(bigendian, sv_a_nz, LOGICAL__insn_type, LOGICAL__fn_unit, LOG (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_LOGICAL_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_LOGICAL_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_LOGICAL_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec_LOGICAL_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec_LOGICAL_function_unit; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) (* enum_value_001 = "RA" *) (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_LOGICAL_in1_sel; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -123276,7 +132192,8 @@ module dec_LOGICAL(bigendian, sv_a_nz, LOGICAL__insn_type, LOGICAL__fn_unit, LOG (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec_LOGICAL_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -123353,13 +132270,15 @@ module dec_LOGICAL(bigendian, sv_a_nz, LOGICAL__insn_type, LOGICAL__fn_unit, LOG (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec_LOGICAL_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_LOGICAL_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_LOGICAL_inv_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_LOGICAL_is_32b; (* enum_base_type = "LdstLen" *) (* enum_value_0000 = "NONE" *) @@ -123367,19 +132286,19 @@ module dec_LOGICAL(bigendian, sv_a_nz, LOGICAL__insn_type, LOGICAL__fn_unit, LOG (* enum_value_0010 = "is2B" *) (* enum_value_0100 = "is4B" *) (* enum_value_1000 = "is8B" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec_LOGICAL_ldst_len; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_LOGICAL_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_LOGICAL_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] dec_LOGICAL_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:193" *) wire dec_ai_immz_out; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -123387,13 +132306,15 @@ module dec_LOGICAL(bigendian, sv_a_nz, LOGICAL__insn_type, LOGICAL__fn_unit, LOG (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:192" *) wire [2:0] dec_ai_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:194" *) wire dec_ai_sv_nz; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] dec_bi_imm_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_bi_imm_b_ok; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -123410,68 +132331,69 @@ module dec_LOGICAL(bigendian, sv_a_nz, LOGICAL__insn_type, LOGICAL__fn_unit, LOG (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" *) wire [3:0] dec_bi_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_oe_oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_oe_oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:527" *) wire [1:0] dec_oe_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] dec_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_rc_rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_rc_rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:490" *) wire [1:0] dec_rc_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:491" *) wire [31:0] insn_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:528" *) wire [31:0] \insn_in$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:884" *) wire is_mmu_spr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:883" *) wire is_spr_mv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:478" *) input [31:0] raw_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:878" *) wire [9:0] spr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:747" *) input sv_a_nz; - assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ; - assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ; - assign \$16 = dec_LOGICAL_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31; - assign \$18 = dec_LOGICAL_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e; - assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ; - assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12; - assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13; - assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ; - assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0; - assign \$2 = dec_LOGICAL_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ; - assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30; - assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ; - assign \$36 = dec_LOGICAL_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ; - assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$42 = dec_LOGICAL_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; - assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ; - assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ; - assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ; - assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$8 = dec_LOGICAL_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$8 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) is_mmu_spr; + assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$12 ; + assign \$16 = dec_LOGICAL_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:885" *) 7'h31; + assign \$18 = dec_LOGICAL_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) 7'h2e; + assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) \$18 ; + assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 5'h12; + assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 5'h13; + assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) \$24 ; + assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 10'h2d0; + assign \$2 = dec_LOGICAL_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) 15'h0400; + assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) \$28 ; + assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) 6'h30; + assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) \$32 ; + assign \$36 = dec_LOGICAL_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) 15'h0400; + assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) \$36 ; + assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) is_mmu_spr; + assign \$42 = dec_LOGICAL_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) 15'h0800; + assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$42 ; + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) is_mmu_spr; + assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$46 ; + assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) \$2 ; + assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) is_mmu_spr; + assign \$8 = dec_LOGICAL_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) 15'h0800; \dec$145 dec ( .LOGICAL_BD(dec_LOGICAL_BD), .LOGICAL_DS(dec_LOGICAL_DS), @@ -123535,14 +132457,14 @@ module dec_LOGICAL(bigendian, sv_a_nz, LOGICAL__insn_type, LOGICAL__fn_unit, LOG always @* begin if (\initial ) begin end LOGICAL__write_cr0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:921" *) casez (dec_LOGICAL_cr_out) /* \nmigen.decoding = "CR0/1|CR1/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:880" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:922" */ 3'h1, 3'h5: LOGICAL__write_cr0 = dec_rc_rc; /* \nmigen.decoding = "BF/2|BT/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:924" */ 3'h2, 3'h3: LOGICAL__write_cr0 = 1'h1; endcase @@ -123550,12 +132472,12 @@ module dec_LOGICAL(bigendian, sv_a_nz, LOGICAL__insn_type, LOGICAL__fn_unit, LOG always @* begin if (\initial ) begin end LOGICAL__insn_type = dec_LOGICAL_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) casez ({ \$14 , \$6 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" */ 2'b?1: LOGICAL__insn_type = 7'h00; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" */ 2'b1?: LOGICAL__insn_type = 7'h00; endcase @@ -123563,15 +132485,15 @@ module dec_LOGICAL(bigendian, sv_a_nz, LOGICAL__insn_type, LOGICAL__fn_unit, LOG always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) casez ({ \$48 , \$40 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" */ 2'b?1: - LOGICAL__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + LOGICAL__fn_unit = 15'h0000; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" */ 2'b1?: - LOGICAL__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" */ + LOGICAL__fn_unit = 15'h0000; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:900" */ default: LOGICAL__fn_unit = dec_LOGICAL_function_unit; endcase @@ -123604,77 +132526,78 @@ endmodule (* generator = "nMigen" *) module dec_MUL(bigendian, MUL__insn_type, MUL__fn_unit, MUL__imm_data__data, MUL__imm_data__ok, MUL__rc__rc, MUL__rc__ok, MUL__oe__oe, MUL__oe__ok, MUL__write_cr0, MUL__is_32bit, MUL__is_signed, MUL__insn, raw_opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:885" *) wire \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) wire \$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) wire \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) wire \$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) wire \$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$48 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$8 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] MUL__fn_unit; - reg [13:0] MUL__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] MUL__fn_unit; + reg [14:0] MUL__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] MUL__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output MUL__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] MUL__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -123751,43 +132674,45 @@ module dec_MUL(bigendian, MUL__insn_type, MUL__fn_unit, MUL__imm_data__data, MUL (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] MUL__insn_type; reg [6:0] MUL__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output MUL__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output MUL__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output MUL__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output MUL__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output MUL__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output MUL__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output MUL__write_cr0; reg MUL__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:479" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] dec_MUL_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] dec_MUL_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [23:0] dec_MUL_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire dec_MUL_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire dec_MUL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] dec_MUL_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] dec_MUL_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] dec_MUL_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] dec_MUL_UI; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -123796,25 +132721,26 @@ module dec_MUL(bigendian, MUL__insn_type, MUL__fn_unit, MUL__imm_data__data, MUL (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_MUL_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec_MUL_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec_MUL_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -123830,7 +132756,8 @@ module dec_MUL(bigendian, MUL__insn_type, MUL__fn_unit, MUL__imm_data__data, MUL (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec_MUL_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -123907,23 +132834,25 @@ module dec_MUL(bigendian, MUL__insn_type, MUL__fn_unit, MUL__imm_data__data, MUL (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec_MUL_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_MUL_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_MUL_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_MUL_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] dec_MUL_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] dec_bi_imm_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_bi_imm_b_ok; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -123940,66 +132869,67 @@ module dec_MUL(bigendian, MUL__insn_type, MUL__fn_unit, MUL__imm_data__data, MUL (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" *) wire [3:0] dec_bi_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_oe_oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_oe_oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:527" *) wire [1:0] dec_oe_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] dec_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_rc_rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_rc_rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:490" *) wire [1:0] dec_rc_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:491" *) wire [31:0] insn_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:528" *) wire [31:0] \insn_in$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:884" *) wire is_mmu_spr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:883" *) wire is_spr_mv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:478" *) input [31:0] raw_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:878" *) wire [9:0] spr; - assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ; - assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ; - assign \$16 = dec_MUL_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31; - assign \$18 = dec_MUL_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e; - assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ; - assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12; - assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13; - assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ; - assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0; - assign \$2 = dec_MUL_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ; - assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30; - assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ; - assign \$36 = dec_MUL_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ; - assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$42 = dec_MUL_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; - assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ; - assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ; - assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ; - assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$8 = dec_MUL_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$8 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) is_mmu_spr; + assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$12 ; + assign \$16 = dec_MUL_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:885" *) 7'h31; + assign \$18 = dec_MUL_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) 7'h2e; + assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) \$18 ; + assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 5'h12; + assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 5'h13; + assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) \$24 ; + assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 10'h2d0; + assign \$2 = dec_MUL_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) 15'h0400; + assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) \$28 ; + assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) 6'h30; + assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) \$32 ; + assign \$36 = dec_MUL_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) 15'h0400; + assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) \$36 ; + assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) is_mmu_spr; + assign \$42 = dec_MUL_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) 15'h0800; + assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$42 ; + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) is_mmu_spr; + assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$46 ; + assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) \$2 ; + assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) is_mmu_spr; + assign \$8 = dec_MUL_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) 15'h0800; \dec$158 dec ( .MUL_BD(dec_MUL_BD), .MUL_DS(dec_MUL_DS), @@ -124050,14 +132980,14 @@ module dec_MUL(bigendian, MUL__insn_type, MUL__fn_unit, MUL__imm_data__data, MUL always @* begin if (\initial ) begin end MUL__write_cr0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:921" *) casez (dec_MUL_cr_out) /* \nmigen.decoding = "CR0/1|CR1/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:880" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:922" */ 3'h1, 3'h5: MUL__write_cr0 = dec_rc_rc; /* \nmigen.decoding = "BF/2|BT/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:924" */ 3'h2, 3'h3: MUL__write_cr0 = 1'h1; endcase @@ -124065,12 +132995,12 @@ module dec_MUL(bigendian, MUL__insn_type, MUL__fn_unit, MUL__imm_data__data, MUL always @* begin if (\initial ) begin end MUL__insn_type = dec_MUL_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) casez ({ \$14 , \$6 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" */ 2'b?1: MUL__insn_type = 7'h00; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" */ 2'b1?: MUL__insn_type = 7'h00; endcase @@ -124078,15 +133008,15 @@ module dec_MUL(bigendian, MUL__insn_type, MUL__fn_unit, MUL__imm_data__data, MUL always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) casez ({ \$48 , \$40 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" */ 2'b?1: - MUL__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + MUL__fn_unit = 15'h0000; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" */ 2'b1?: - MUL__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" */ + MUL__fn_unit = 15'h0000; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:900" */ default: MUL__fn_unit = dec_MUL_function_unit; endcase @@ -124111,85 +133041,86 @@ endmodule (* generator = "nMigen" *) module dec_SHIFT_ROT(bigendian, SHIFT_ROT__insn_type, SHIFT_ROT__fn_unit, SHIFT_ROT__imm_data__data, SHIFT_ROT__imm_data__ok, SHIFT_ROT__rc__rc, SHIFT_ROT__rc__ok, SHIFT_ROT__oe__oe, SHIFT_ROT__oe__ok, SHIFT_ROT__write_cr0, SHIFT_ROT__invert_in, SHIFT_ROT__input_carry, SHIFT_ROT__output_carry, SHIFT_ROT__input_cr, SHIFT_ROT__output_cr, SHIFT_ROT__is_32bit, SHIFT_ROT__is_signed, SHIFT_ROT__insn, raw_opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:885" *) wire \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) wire \$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) wire \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) wire \$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) wire \$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$48 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$8 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] SHIFT_ROT__fn_unit; - reg [13:0] SHIFT_ROT__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] SHIFT_ROT__fn_unit; + reg [14:0] SHIFT_ROT__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] SHIFT_ROT__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output SHIFT_ROT__imm_data__ok; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [1:0] SHIFT_ROT__input_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output SHIFT_ROT__input_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] SHIFT_ROT__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -124266,49 +133197,51 @@ module dec_SHIFT_ROT(bigendian, SHIFT_ROT__insn_type, SHIFT_ROT__fn_unit, SHIFT_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] SHIFT_ROT__insn_type; reg [6:0] SHIFT_ROT__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output SHIFT_ROT__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output SHIFT_ROT__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output SHIFT_ROT__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output SHIFT_ROT__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output SHIFT_ROT__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output SHIFT_ROT__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output SHIFT_ROT__output_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output SHIFT_ROT__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output SHIFT_ROT__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output SHIFT_ROT__write_cr0; reg SHIFT_ROT__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:479" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] dec_SHIFT_ROT_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [13:0] dec_SHIFT_ROT_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [23:0] dec_SHIFT_ROT_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire dec_SHIFT_ROT_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire dec_SHIFT_ROT_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [4:0] dec_SHIFT_ROT_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] dec_SHIFT_ROT_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] dec_SHIFT_ROT_SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [15:0] dec_SHIFT_ROT_UI; (* enum_base_type = "CRInSel" *) (* enum_value_000 = "NONE" *) @@ -124319,7 +133252,7 @@ module dec_SHIFT_ROT(bigendian, SHIFT_ROT__insn_type, SHIFT_ROT__fn_unit, SHIFT_ (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_SHIFT_ROT_cr_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -124328,33 +133261,34 @@ module dec_SHIFT_ROT(bigendian, SHIFT_ROT__insn_type, SHIFT_ROT__fn_unit, SHIFT_ (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_SHIFT_ROT_cr_out; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_SHIFT_ROT_cry_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_SHIFT_ROT_cry_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec_SHIFT_ROT_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec_SHIFT_ROT_function_unit; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) (* enum_value_0001 = "RB" *) @@ -124370,7 +133304,8 @@ module dec_SHIFT_ROT(bigendian, SHIFT_ROT__insn_type, SHIFT_ROT__fn_unit, SHIFT_ (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [3:0] dec_SHIFT_ROT_in2_sel; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -124447,25 +133382,27 @@ module dec_SHIFT_ROT(bigendian, SHIFT_ROT__insn_type, SHIFT_ROT__fn_unit, SHIFT_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec_SHIFT_ROT_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_SHIFT_ROT_inv_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_SHIFT_ROT_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_SHIFT_ROT_rc_sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_SHIFT_ROT_sgn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [5:0] dec_SHIFT_ROT_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] dec_bi_imm_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_bi_imm_b_ok; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -124482,66 +133419,67 @@ module dec_SHIFT_ROT(bigendian, SHIFT_ROT__insn_type, SHIFT_ROT__fn_unit, SHIFT_ (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" *) wire [3:0] dec_bi_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_oe_oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_oe_oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:527" *) wire [1:0] dec_oe_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] dec_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_rc_rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec_rc_rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:490" *) wire [1:0] dec_rc_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:491" *) wire [31:0] insn_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:528" *) wire [31:0] \insn_in$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:884" *) wire is_mmu_spr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:883" *) wire is_spr_mv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:478" *) input [31:0] raw_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:878" *) wire [9:0] spr; - assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ; - assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ; - assign \$16 = dec_SHIFT_ROT_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31; - assign \$18 = dec_SHIFT_ROT_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e; - assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ; - assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12; - assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13; - assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ; - assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0; - assign \$2 = dec_SHIFT_ROT_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ; - assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30; - assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ; - assign \$36 = dec_SHIFT_ROT_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ; - assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$42 = dec_SHIFT_ROT_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; - assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ; - assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ; - assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ; - assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$8 = dec_SHIFT_ROT_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$8 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) is_mmu_spr; + assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$12 ; + assign \$16 = dec_SHIFT_ROT_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:885" *) 7'h31; + assign \$18 = dec_SHIFT_ROT_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) 7'h2e; + assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) \$18 ; + assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 5'h12; + assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 5'h13; + assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) \$24 ; + assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 10'h2d0; + assign \$2 = dec_SHIFT_ROT_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) 15'h0400; + assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) \$28 ; + assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) 6'h30; + assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) \$32 ; + assign \$36 = dec_SHIFT_ROT_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) 15'h0400; + assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) \$36 ; + assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) is_mmu_spr; + assign \$42 = dec_SHIFT_ROT_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) 15'h0800; + assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$42 ; + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) is_mmu_spr; + assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$46 ; + assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) \$2 ; + assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) is_mmu_spr; + assign \$8 = dec_SHIFT_ROT_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) 15'h0800; \dec$162 dec ( .SHIFT_ROT_BD(dec_SHIFT_ROT_BD), .SHIFT_ROT_DS(dec_SHIFT_ROT_DS), @@ -124596,14 +133534,14 @@ module dec_SHIFT_ROT(bigendian, SHIFT_ROT__insn_type, SHIFT_ROT__fn_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT__write_cr0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:921" *) casez (dec_SHIFT_ROT_cr_out) /* \nmigen.decoding = "CR0/1|CR1/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:880" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:922" */ 3'h1, 3'h5: SHIFT_ROT__write_cr0 = dec_rc_rc; /* \nmigen.decoding = "BF/2|BT/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:924" */ 3'h2, 3'h3: SHIFT_ROT__write_cr0 = 1'h1; endcase @@ -124611,12 +133549,12 @@ module dec_SHIFT_ROT(bigendian, SHIFT_ROT__insn_type, SHIFT_ROT__fn_unit, SHIFT_ always @* begin if (\initial ) begin end SHIFT_ROT__insn_type = dec_SHIFT_ROT_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) casez ({ \$14 , \$6 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" */ 2'b?1: SHIFT_ROT__insn_type = 7'h00; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" */ 2'b1?: SHIFT_ROT__insn_type = 7'h00; endcase @@ -124624,15 +133562,15 @@ module dec_SHIFT_ROT(bigendian, SHIFT_ROT__insn_type, SHIFT_ROT__fn_unit, SHIFT_ always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) casez ({ \$48 , \$40 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" */ 2'b?1: - SHIFT_ROT__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + SHIFT_ROT__fn_unit = 15'h0000; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" */ 2'b1?: - SHIFT_ROT__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" */ + SHIFT_ROT__fn_unit = 15'h0000; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:900" */ default: SHIFT_ROT__fn_unit = dec_SHIFT_ROT_function_unit; endcase @@ -124662,73 +133600,74 @@ endmodule (* generator = "nMigen" *) module dec_SPR(bigendian, SPR__insn_type, SPR__fn_unit, SPR__insn, SPR__is_32bit, raw_opcode_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:885" *) wire \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) wire \$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) wire \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) wire \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) wire \$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) wire \$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$48 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) wire \$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) wire \$8 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] SPR__fn_unit; - reg [13:0] SPR__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] SPR__fn_unit; + reg [14:0] SPR__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] SPR__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -124805,18 +133744,20 @@ module dec_SPR(bigendian, SPR__insn_type, SPR__fn_unit, SPR__insn, SPR__is_32bit (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] SPR__insn_type; reg [6:0] SPR__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output SPR__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:479" *) input bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire dec_SPR_OE; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire dec_SPR_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [9:0] dec_SPR_SPR; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -124825,25 +133766,26 @@ module dec_SPR(bigendian, SPR__insn_type, SPR__fn_unit, SPR__insn, SPR__is_32bit (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [2:0] dec_SPR_cr_out; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) - wire [13:0] dec_SPR_function_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) + wire [14:0] dec_SPR_function_unit; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -124919,66 +133861,68 @@ module dec_SPR(bigendian, SPR__insn_type, SPR__fn_unit, SPR__insn, SPR__is_32bit (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [6:0] dec_SPR_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:198" *) wire dec_SPR_is_32b; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) wire [1:0] dec_SPR_rc_sel; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:527" *) wire [1:0] dec_oe_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:311" *) wire [31:0] dec_opcode_in; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:490" *) wire [1:0] dec_rc_sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:491" *) wire [31:0] insn_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:528" *) wire [31:0] \insn_in$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:884" *) wire is_mmu_spr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:883" *) wire is_spr_mv; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:478" *) input [31:0] raw_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:878" *) wire [9:0] spr; - assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ; - assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ; - assign \$16 = dec_SPR_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31; - assign \$18 = dec_SPR_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e; - assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ; - assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12; - assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13; - assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ; - assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0; - assign \$2 = dec_SPR_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ; - assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30; - assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ; - assign \$36 = dec_SPR_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400; - assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ; - assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$42 = dec_SPR_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; - assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ; - assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr; - assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ; - assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ; - assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr; - assign \$8 = dec_SPR_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800; + assign \$10 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$8 ; + assign \$12 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) is_mmu_spr; + assign \$14 = \$10 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$12 ; + assign \$16 = dec_SPR_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:885" *) 7'h31; + assign \$18 = dec_SPR_internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) 7'h2e; + assign \$20 = \$16 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:886" *) \$18 ; + assign \$22 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 5'h12; + assign \$24 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 5'h13; + assign \$26 = \$22 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) \$24 ; + assign \$28 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) 10'h2d0; + assign \$2 = dec_SPR_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) 15'h0400; + assign \$30 = \$26 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:889" *) \$28 ; + assign \$32 = spr == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) 6'h30; + assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:890" *) \$32 ; + assign \$36 = dec_SPR_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) 15'h0400; + assign \$38 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) \$36 ; + assign \$40 = \$38 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) is_mmu_spr; + assign \$42 = dec_SPR_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) 15'h0800; + assign \$44 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$42 ; + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) is_mmu_spr; + assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) \$46 ; + assign \$4 = is_spr_mv & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) \$2 ; + assign \$6 = \$4 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) is_mmu_spr; + assign \$8 = dec_SPR_function_unit == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" *) 15'h0800; \dec$150 dec ( .SPR_OE(dec_SPR_OE), .SPR_Rc(dec_SPR_Rc), @@ -125004,12 +133948,12 @@ module dec_SPR(bigendian, SPR__insn_type, SPR__fn_unit, SPR__insn, SPR__is_32bit always @* begin if (\initial ) begin end SPR__insn_type = dec_SPR_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) casez ({ \$14 , \$6 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" */ 2'b?1: SPR__insn_type = 7'h00; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" */ 2'b1?: SPR__insn_type = 7'h00; endcase @@ -125017,15 +133961,15 @@ module dec_SPR(bigendian, SPR__insn_type, SPR__fn_unit, SPR__insn, SPR__is_32bit always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" *) casez ({ \$48 , \$40 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:892" */ 2'b?1: - SPR__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" */ + SPR__fn_unit = 15'h0000; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:896" */ 2'b1?: - SPR__fn_unit = 14'h0000; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" */ + SPR__fn_unit = 15'h0000; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:900" */ default: SPR__fn_unit = dec_SPR_function_unit; endcase @@ -125043,62 +133987,78 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.dec2.dec_a" *) (* generator = "nMigen" *) -module dec_a(SPR, sv_nz, sel_in, reg_a, reg_a_ok, spr_a, spr_a_ok, fast_a, fast_a_ok, RS, RA, BO, XL_XO, internal_op); +module dec_a(SPR, sv_nz, sel_in, reg_a, reg_a_ok, spr_a, spr_a_ok, fast_a, fast_a_ok, FRS, FRA, RS, RA, BO, XL_XO, internal_op); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:127" *) wire \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) wire \$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) wire \$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:137" *) wire \$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:144" *) wire \$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:151" *) wire \$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:127" *) wire \$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:128" *) wire \$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) wire \$25 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) wire \$27 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) wire \$29 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:128" *) wire \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) wire \$31 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) wire \$33 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:137" *) wire \$35 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:144" *) wire \$37 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:151" *) + wire \$39 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:160" *) + wire \$41 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:167" *) + wire \$43 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:167" *) + wire \$45 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) wire \$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) wire \$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [4:0] BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + input [4:0] FRA; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + input [4:0] FRS; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [4:0] RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [4:0] RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [9:0] SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) input [9:0] XL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [2:0] fast_a; reg [2:0] fast_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output fast_a_ok; reg fast_a_ok; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:142" *) + wire [4:0] fra; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:149" *) + wire [4:0] frs; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -125174,17 +134134,19 @@ module dec_a(SPR, sv_nz, sel_in, reg_a, reg_a_ok, spr_a, spr_a_ok, fast_a, fast_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [6:0] internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:125" *) wire [4:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [4:0] reg_a; reg [4:0] reg_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output reg_a_ok; reg reg_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:136" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:135" *) wire [4:0] rs; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -125192,9 +134154,11 @@ module dec_a(SPR, sv_nz, sel_in, reg_a, reg_a_ok, spr_a, spr_a_ok, fast_a, fast_ (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:110" *) input [2:0] sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:174" *) reg [9:0] spr; (* enum_base_type = "SPR" *) (* enum_value_0000000001 = "XER" *) @@ -125310,17 +134274,17 @@ module dec_a(SPR, sv_nz, sel_in, reg_a, reg_a_ok, spr_a, spr_a_ok, fast_a, fast_ (* enum_value_1110000000 = "PPR" *) (* enum_value_1110000010 = "PPR32" *) (* enum_value_1111111111 = "PIR" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [9:0] spr_a; reg [9:0] spr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output spr_a_ok; reg spr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [2:0] sprmap_fast_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire sprmap_fast_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:75" *) reg [9:0] sprmap_spr_i; (* enum_base_type = "SPR" *) (* enum_value_0000000001 = "XER" *) @@ -125436,31 +134400,35 @@ module dec_a(SPR, sv_nz, sel_in, reg_a, reg_a_ok, spr_a, spr_a_ok, fast_a, fast_ (* enum_value_1110000000 = "PPR" *) (* enum_value_1110000010 = "PPR32" *) (* enum_value_1111111111 = "PIR" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [9:0] sprmap_spr_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire sprmap_spr_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:115" *) input sv_nz; - assign \$9 = \$5 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) \$7 ; - assign \$11 = \$3 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) \$9 ; - assign \$13 = \$1 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) \$11 ; - assign \$15 = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" *) 3'h4; - assign \$17 = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128" *) 3'h1; - assign \$1 = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128" *) 3'h1; - assign \$19 = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" *) 3'h2; - assign \$21 = ra != (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) 5'h00; - assign \$23 = sv_nz != (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) 1'h0; - assign \$25 = \$21 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) \$23 ; - assign \$27 = \$19 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) \$25 ; - assign \$29 = \$17 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) \$27 ; - assign \$31 = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" *) 3'h4; - assign \$33 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" *) BO[2]; - assign \$35 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" *) XL_XO[5]; - assign \$37 = XL_XO[9] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" *) \$35 ; - assign \$3 = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" *) 3'h2; - assign \$5 = ra != (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) 5'h00; - assign \$7 = sv_nz != (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) 1'h0; + assign \$9 = \$5 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) \$7 ; + assign \$11 = \$3 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) \$9 ; + assign \$13 = \$1 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) \$11 ; + assign \$15 = sel_in == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:137" *) 3'h4; + assign \$17 = sel_in == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:144" *) 3'h5; + assign \$1 = sel_in == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:127" *) 3'h1; + assign \$19 = sel_in == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:151" *) 3'h6; + assign \$21 = sel_in == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:127" *) 3'h1; + assign \$23 = sel_in == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:128" *) 3'h2; + assign \$25 = ra != (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) 5'h00; + assign \$27 = sv_nz != (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) 1'h0; + assign \$29 = \$25 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) \$27 ; + assign \$31 = \$23 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) \$29 ; + assign \$33 = \$21 | (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) \$31 ; + assign \$35 = sel_in == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:137" *) 3'h4; + assign \$37 = sel_in == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:144" *) 3'h5; + assign \$3 = sel_in == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:128" *) 3'h2; + assign \$39 = sel_in == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:151" *) 3'h6; + assign \$41 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:160" *) BO[2]; + assign \$43 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:167" *) XL_XO[5]; + assign \$45 = XL_XO[9] & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:167" *) \$43 ; + assign \$5 = ra != (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) 5'h00; + assign \$7 = sv_nz != (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) 1'h0; sprmap sprmap ( .fast_o(sprmap_fast_o), .fast_o_ok(sprmap_fast_o_ok), @@ -125471,31 +134439,75 @@ module dec_a(SPR, sv_nz, sel_in, reg_a, reg_a_ok, spr_a, spr_a_ok, fast_a, fast_ always @* begin if (\initial ) begin end reg_a = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) casez (\$13 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" */ 1'h1: reg_a = ra; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:137" *) casez (\$15 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:137" */ 1'h1: reg_a = rs; endcase + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:144" *) + casez (\$17 ) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:144" */ + 1'h1: + reg_a = fra; + endcase + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:151" *) + casez (\$19 ) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:151" */ + 1'h1: + reg_a = frs; + endcase + end + always @* begin + if (\initial ) begin end + spr_a = 10'h000; + spr_a_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:156" *) + casez (internal_op) + /* \nmigen.decoding = "OP_BC/7" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:159" */ + 7'h07: + /* empty */; + /* \nmigen.decoding = "OP_BCREG/8" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:164" */ + 7'h08: + /* empty */; + /* \nmigen.decoding = "OP_MFSPR/46" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:173" */ + 7'h2e: + { spr_a_ok, spr_a } = { sprmap_spr_o_ok, sprmap_spr_o }; + endcase end always @* begin if (\initial ) begin end reg_a_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) - casez (\$29 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" */ + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" *) + casez (\$33 ) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:129" */ 1'h1: reg_a_ok = 1'h1; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" *) - casez (\$31 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" */ + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:137" *) + casez (\$35 ) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:137" */ + 1'h1: + reg_a_ok = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:144" *) + casez (\$37 ) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:144" */ + 1'h1: + reg_a_ok = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:151" *) + casez (\$39 ) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:151" */ 1'h1: reg_a_ok = 1'h1; endcase @@ -125504,14 +134516,14 @@ module dec_a(SPR, sv_nz, sel_in, reg_a, reg_a_ok, spr_a, spr_a_ok, fast_a, fast_ if (\initial ) begin end fast_a = 3'h0; fast_a_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:156" *) casez (internal_op) /* \nmigen.decoding = "OP_BC/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:159" */ 7'h07: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" *) - casez (\$33 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" */ + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:160" *) + casez (\$41 ) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:160" */ 1'h1: begin fast_a = 3'h0; @@ -125519,11 +134531,11 @@ module dec_a(SPR, sv_nz, sel_in, reg_a, reg_a_ok, spr_a, spr_a_ok, fast_a, fast_ end endcase /* \nmigen.decoding = "OP_BCREG/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:164" */ 7'h08: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" *) - casez (\$37 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" */ + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:167" *) + casez (\$45 ) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:167" */ 1'h1: begin fast_a = 3'h0; @@ -125531,7 +134543,7 @@ module dec_a(SPR, sv_nz, sel_in, reg_a, reg_a_ok, spr_a, spr_a_ok, fast_a, fast_ end endcase /* \nmigen.decoding = "OP_MFSPR/46" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:160" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:173" */ 7'h2e: { fast_a_ok, fast_a } = { sprmap_fast_o_ok, sprmap_fast_o }; endcase @@ -125539,18 +134551,18 @@ module dec_a(SPR, sv_nz, sel_in, reg_a, reg_a_ok, spr_a, spr_a_ok, fast_a, fast_ always @* begin if (\initial ) begin end spr = 10'h000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:156" *) casez (internal_op) /* \nmigen.decoding = "OP_BC/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:159" */ 7'h07: /* empty */; /* \nmigen.decoding = "OP_BCREG/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:164" */ 7'h08: /* empty */; /* \nmigen.decoding = "OP_MFSPR/46" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:160" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:173" */ 7'h2e: spr = { SPR[4:0], SPR[9:5] }; endcase @@ -125558,42 +134570,24 @@ module dec_a(SPR, sv_nz, sel_in, reg_a, reg_a_ok, spr_a, spr_a_ok, fast_a, fast_ always @* begin if (\initial ) begin end sprmap_spr_i = 10'h000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:156" *) casez (internal_op) /* \nmigen.decoding = "OP_BC/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:159" */ 7'h07: /* empty */; /* \nmigen.decoding = "OP_BCREG/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:164" */ 7'h08: /* empty */; /* \nmigen.decoding = "OP_MFSPR/46" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:160" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:173" */ 7'h2e: sprmap_spr_i = spr; endcase end - always @* begin - if (\initial ) begin end - spr_a = 10'h000; - spr_a_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143" *) - casez (internal_op) - /* \nmigen.decoding = "OP_BC/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146" */ - 7'h07: - /* empty */; - /* \nmigen.decoding = "OP_BCREG/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" */ - 7'h08: - /* empty */; - /* \nmigen.decoding = "OP_MFSPR/46" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:160" */ - 7'h2e: - { spr_a_ok, spr_a } = { sprmap_spr_o_ok, sprmap_spr_o }; - endcase - end + assign frs = FRS; + assign fra = FRA; assign rs = RS; assign ra = RA; endmodule @@ -125602,22 +134596,22 @@ endmodule (* generator = "nMigen" *) module dec_ai(sel_in, immz_out, ALU_RA, sv_nz); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:204" *) wire \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:204" *) wire \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:204" *) wire \$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:205" *) wire \$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:205" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [4:0] ALU_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:193" *) output immz_out; reg immz_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:201" *) wire [4:0] ra; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -125625,21 +134619,23 @@ module dec_ai(sel_in, immz_out, ALU_RA, sv_nz); (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:192" *) input [2:0] sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:194" *) input sv_nz; - assign \$9 = \$5 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) \$7 ; - assign \$1 = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) 3'h2; - assign \$3 = ra == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) 5'h00; - assign \$5 = \$1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) \$3 ; - assign \$7 = sv_nz == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) 1'h0; + assign \$9 = \$5 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:205" *) \$7 ; + assign \$1 = sel_in == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:204" *) 3'h2; + assign \$3 = ra == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:204" *) 5'h00; + assign \$5 = \$1 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:204" *) \$3 ; + assign \$7 = sv_nz == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:205" *) 1'h0; always @* begin if (\initial ) begin end immz_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:205" *) casez (\$9 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:205" */ 1'h1: immz_out = 1'h1; endcase @@ -125651,22 +134647,22 @@ endmodule (* generator = "nMigen" *) module \dec_ai$148 (sel_in, immz_out, LOGICAL_RA, sv_nz); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:204" *) wire \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:204" *) wire \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:204" *) wire \$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:205" *) wire \$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:205" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [4:0] LOGICAL_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:193" *) output immz_out; reg immz_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:201" *) wire [4:0] ra; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -125674,21 +134670,23 @@ module \dec_ai$148 (sel_in, immz_out, LOGICAL_RA, sv_nz); (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:192" *) input [2:0] sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:194" *) input sv_nz; - assign \$9 = \$5 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) \$7 ; - assign \$1 = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) 3'h2; - assign \$3 = ra == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) 5'h00; - assign \$5 = \$1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) \$3 ; - assign \$7 = sv_nz == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) 1'h0; + assign \$9 = \$5 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:205" *) \$7 ; + assign \$1 = sel_in == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:204" *) 3'h2; + assign \$3 = ra == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:204" *) 5'h00; + assign \$5 = \$1 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:204" *) \$3 ; + assign \$7 = sv_nz == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:205" *) 1'h0; always @* begin if (\initial ) begin end immz_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:205" *) casez (\$9 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:205" */ 1'h1: immz_out = 1'h1; endcase @@ -125700,22 +134698,22 @@ endmodule (* generator = "nMigen" *) module \dec_ai$156 (sel_in, immz_out, DIV_RA, sv_nz); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:204" *) wire \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:204" *) wire \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:204" *) wire \$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:205" *) wire \$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:205" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [4:0] DIV_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:193" *) output immz_out; reg immz_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:201" *) wire [4:0] ra; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -125723,21 +134721,23 @@ module \dec_ai$156 (sel_in, immz_out, DIV_RA, sv_nz); (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:192" *) input [2:0] sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:194" *) input sv_nz; - assign \$9 = \$5 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) \$7 ; - assign \$1 = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) 3'h2; - assign \$3 = ra == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) 5'h00; - assign \$5 = \$1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) \$3 ; - assign \$7 = sv_nz == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) 1'h0; + assign \$9 = \$5 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:205" *) \$7 ; + assign \$1 = sel_in == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:204" *) 3'h2; + assign \$3 = ra == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:204" *) 5'h00; + assign \$5 = \$1 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:204" *) \$3 ; + assign \$7 = sv_nz == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:205" *) 1'h0; always @* begin if (\initial ) begin end immz_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:205" *) casez (\$9 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:205" */ 1'h1: immz_out = 1'h1; endcase @@ -125749,22 +134749,22 @@ endmodule (* generator = "nMigen" *) module \dec_ai$169 (sel_in, immz_out, LDST_RA, sv_nz); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:204" *) wire \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:204" *) wire \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:204" *) wire \$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:205" *) wire \$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:205" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [4:0] LDST_RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:193" *) output immz_out; reg immz_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:201" *) wire [4:0] ra; (* enum_base_type = "In1Sel" *) (* enum_value_000 = "NONE" *) @@ -125772,21 +134772,23 @@ module \dec_ai$169 (sel_in, immz_out, LDST_RA, sv_nz); (* enum_value_010 = "RA_OR_ZERO" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" *) + (* enum_value_101 = "FRA" *) + (* enum_value_110 = "FRS" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:192" *) input [2:0] sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:194" *) input sv_nz; - assign \$9 = \$5 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) \$7 ; - assign \$1 = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) 3'h2; - assign \$3 = ra == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) 5'h00; - assign \$5 = \$1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) \$3 ; - assign \$7 = sv_nz == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) 1'h0; + assign \$9 = \$5 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:205" *) \$7 ; + assign \$1 = sel_in == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:204" *) 3'h2; + assign \$3 = ra == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:204" *) 5'h00; + assign \$5 = \$1 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:204" *) \$3 ; + assign \$7 = sv_nz == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:205" *) 1'h0; always @* begin if (\initial ) begin end immz_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:205" *) casez (\$9 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:205" */ 1'h1: immz_out = 1'h1; endcase @@ -125796,30 +134798,34 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.dec2.dec_b" *) (* generator = "nMigen" *) -module dec_b(sel_in, reg_b, reg_b_ok, fast_b, fast_b_ok, RS, RB, XL_XO, internal_op); +module dec_b(sel_in, reg_b, reg_b_ok, fast_b, fast_b_ok, FRB, RS, RB, XL_XO, internal_op); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:250" *) wire \$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:253" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [6:0] \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" *) - wire \$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + wire [6:0] \$5 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:250" *) wire \$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:253" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + input [4:0] FRB; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [4:0] RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [4:0] RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) input [9:0] XL_XO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [2:0] fast_b; reg [2:0] fast_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output fast_b_ok; reg fast_b_ok; (* enum_base_type = "MicrOp" *) @@ -125897,12 +134903,14 @@ module dec_b(sel_in, reg_b, reg_b_ok, fast_b, fast_b_ok, RS, RB, XL_XO, internal (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [6:0] internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [6:0] reg_b; reg [6:0] reg_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output reg_b_ok; reg reg_b_ok; (* enum_base_type = "In2Sel" *) @@ -125920,40 +134928,50 @@ module dec_b(sel_in, reg_b, reg_b_ok, fast_b, fast_b_ok, RS, RB, XL_XO, internal (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:222" *) input [3:0] sel_in; - assign \$9 = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" *) 7'h08; - assign \$11 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" *) XL_XO[9]; - assign \$1 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) RB; - assign \$3 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) RS; - assign \$5 = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" *) 7'h08; - assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" *) XL_XO[9]; + assign \$9 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:253" *) XL_XO[9]; + assign \$11 = internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:250" *) 7'h08; + assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:253" *) XL_XO[9]; + assign \$1 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) FRB; + assign \$3 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) RB; + assign \$5 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) RS; + assign \$7 = internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:250" *) 7'h08; always @* begin if (\initial ) begin end reg_b = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:235" *) casez (sel_in) + /* \nmigen.decoding = "FRB/14" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:236" */ + 4'he: + reg_b = \$1 ; /* \nmigen.decoding = "RB/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:223" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:239" */ 4'h1: - reg_b = \$1 ; + reg_b = \$3 ; /* \nmigen.decoding = "RS/13" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:242" */ 4'hd: - reg_b = \$3 ; + reg_b = \$5 ; endcase end always @* begin if (\initial ) begin end reg_b_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:235" *) casez (sel_in) + /* \nmigen.decoding = "FRB/14" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:236" */ + 4'he: + reg_b_ok = 1'h1; /* \nmigen.decoding = "RB/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:223" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:239" */ 4'h1: reg_b_ok = 1'h1; /* \nmigen.decoding = "RS/13" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:242" */ 4'hd: reg_b_ok = 1'h1; endcase @@ -125961,16 +134979,16 @@ module dec_b(sel_in, reg_b, reg_b_ok, fast_b, fast_b_ok, RS, RB, XL_XO, internal always @* begin if (\initial ) begin end fast_b = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" *) - casez (\$5 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" */ + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:250" *) + casez (\$7 ) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:250" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" *) - casez ({ XL_XO[5], \$7 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" */ + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:253" *) + casez ({ XL_XO[5], \$9 }) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:253" */ 2'b?1: fast_b = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:240" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:256" */ 2'b1?: fast_b = 3'h2; endcase @@ -125979,16 +134997,16 @@ module dec_b(sel_in, reg_b, reg_b_ok, fast_b, fast_b_ok, RS, RB, XL_XO, internal always @* begin if (\initial ) begin end fast_b_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" *) - casez (\$9 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" */ + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:250" *) + casez (\$11 ) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:250" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" *) - casez ({ XL_XO[5], \$11 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" */ + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:253" *) + casez ({ XL_XO[5], \$13 }) + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:253" */ 2'b?1: fast_b_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:240" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:256" */ 2'b1?: fast_b_ok = 1'h1; endcase @@ -126000,59 +135018,59 @@ endmodule (* generator = "nMigen" *) module dec_bi(imm_b, imm_b_ok, ALU_SI, ALU_UI, ALU_SH32, ALU_sh, ALU_LI, ALU_BD, ALU_DS, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [63:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [63:0] \$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:287" *) wire [46:0] \$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:287" *) wire [46:0] \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:297" *) wire [26:0] \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:297" *) wire [26:0] \$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:302" *) wire [16:0] \$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:302" *) wire [16:0] \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:307" *) wire [16:0] \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:307" *) wire [16:0] \$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" *) wire [63:0] \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" *) wire [46:0] \$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:311" *) wire [63:0] \$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [63:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [13:0] ALU_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [13:0] ALU_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [23:0] ALU_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [4:0] ALU_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [15:0] ALU_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [15:0] ALU_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [5:0] ALU_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:301" *) reg [15:0] bd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:306" *) reg [15:0] ds; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] imm_b; reg [63:0] imm_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output imm_b_ok; reg imm_b_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:296" *) reg [25:0] li; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -126069,67 +135087,68 @@ module dec_bi(imm_b, imm_b_ok, ALU_SI, ALU_UI, ALU_SH32, ALU_sh, ALU_LI, ALU_BD, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" *) input [3:0] sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:281" *) reg [15:0] si; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:286" *) reg [31:0] si_hi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:291" *) reg [15:0] ui; - assign \$9 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) ALU_sh; - assign \$11 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) ALU_SH32; - assign \$14 = ALU_SI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) 5'h10; - assign \$17 = ALU_LI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) 2'h2; - assign \$1 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) ALU_UI; - assign \$20 = ALU_BD <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) 2'h2; - assign \$23 = ALU_DS <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) 2'h2; - assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) 5'h10; - assign \$3 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) \$4 ; - assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) 64'h0000000000000000; + assign \$9 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) ALU_sh; + assign \$11 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) ALU_SH32; + assign \$14 = ALU_SI <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:287" *) 5'h10; + assign \$17 = ALU_LI <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:297" *) 2'h2; + assign \$1 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) ALU_UI; + assign \$20 = ALU_BD <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:302" *) 2'h2; + assign \$23 = ALU_DS <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:307" *) 2'h2; + assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" *) 5'h10; + assign \$3 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" *) \$4 ; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:311" *) 64'h0000000000000000; always @* begin if (\initial ) begin end imm_b = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: imm_b = \$1 ; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: imm_b = { si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si }; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: imm_b = { si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi }; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: imm_b = \$3 ; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: imm_b = { li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li }; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:300" */ 4'h7: imm_b = { bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd }; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:305" */ 4'h8: imm_b = { ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds }; /* \nmigen.decoding = "CONST_M1/9" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:310" */ 4'h9: imm_b = \$7 ; /* \nmigen.decoding = "CONST_SH/10" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:313" */ 4'ha: imm_b = \$9 ; /* \nmigen.decoding = "CONST_SH32/11" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:316" */ 4'hb: imm_b = \$11 ; endcase @@ -126137,46 +135156,46 @@ module dec_bi(imm_b, imm_b_ok, ALU_SI, ALU_UI, ALU_SH32, ALU_sh, ALU_LI, ALU_BD, always @* begin if (\initial ) begin end imm_b_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:300" */ 4'h7: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:305" */ 4'h8: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_M1/9" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:310" */ 4'h9: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SH/10" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:313" */ 4'ha: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SH32/11" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:316" */ 4'hb: imm_b_ok = 1'h1; endcase @@ -126184,14 +135203,14 @@ module dec_bi(imm_b, imm_b_ok, ALU_SI, ALU_UI, ALU_SH32, ALU_sh, ALU_LI, ALU_BD, always @* begin if (\initial ) begin end si = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: si = ALU_SI; endcase @@ -126199,18 +135218,18 @@ module dec_bi(imm_b, imm_b_ok, ALU_SI, ALU_UI, ALU_SH32, ALU_sh, ALU_LI, ALU_BD, always @* begin if (\initial ) begin end si_hi = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: si_hi = \$13 [31:0]; endcase @@ -126218,22 +135237,22 @@ module dec_bi(imm_b, imm_b_ok, ALU_SI, ALU_UI, ALU_SH32, ALU_sh, ALU_LI, ALU_BD, always @* begin if (\initial ) begin end ui = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: ui = ALU_UI; endcase @@ -126241,26 +135260,26 @@ module dec_bi(imm_b, imm_b_ok, ALU_SI, ALU_UI, ALU_SH32, ALU_sh, ALU_LI, ALU_BD, always @* begin if (\initial ) begin end li = 26'h0000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: li = \$16 [25:0]; endcase @@ -126268,30 +135287,30 @@ module dec_bi(imm_b, imm_b_ok, ALU_SI, ALU_UI, ALU_SH32, ALU_sh, ALU_LI, ALU_BD, always @* begin if (\initial ) begin end bd = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: /* empty */; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:300" */ 4'h7: bd = \$19 [15:0]; endcase @@ -126299,34 +135318,34 @@ module dec_bi(imm_b, imm_b_ok, ALU_SI, ALU_UI, ALU_SH32, ALU_sh, ALU_LI, ALU_BD, always @* begin if (\initial ) begin end ds = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: /* empty */; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:300" */ 4'h7: /* empty */; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:305" */ 4'h8: ds = \$22 [15:0]; endcase @@ -126341,59 +135360,59 @@ endmodule (* generator = "nMigen" *) module \dec_bi$144 (imm_b, imm_b_ok, BRANCH_SI, BRANCH_UI, BRANCH_SH32, BRANCH_sh, BRANCH_LI, BRANCH_BD, BRANCH_DS, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [63:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [63:0] \$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:287" *) wire [46:0] \$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:287" *) wire [46:0] \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:297" *) wire [26:0] \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:297" *) wire [26:0] \$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:302" *) wire [16:0] \$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:302" *) wire [16:0] \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:307" *) wire [16:0] \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:307" *) wire [16:0] \$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" *) wire [63:0] \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" *) wire [46:0] \$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:311" *) wire [63:0] \$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [63:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [13:0] BRANCH_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [13:0] BRANCH_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [23:0] BRANCH_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [4:0] BRANCH_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [15:0] BRANCH_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [15:0] BRANCH_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [5:0] BRANCH_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:301" *) reg [15:0] bd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:306" *) reg [15:0] ds; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] imm_b; reg [63:0] imm_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output imm_b_ok; reg imm_b_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:296" *) reg [25:0] li; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -126410,67 +135429,68 @@ module \dec_bi$144 (imm_b, imm_b_ok, BRANCH_SI, BRANCH_UI, BRANCH_SH32, BRANCH_s (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" *) input [3:0] sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:281" *) reg [15:0] si; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:286" *) reg [31:0] si_hi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:291" *) reg [15:0] ui; - assign \$9 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) BRANCH_sh; - assign \$11 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) BRANCH_SH32; - assign \$14 = BRANCH_SI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) 5'h10; - assign \$17 = BRANCH_LI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) 2'h2; - assign \$1 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) BRANCH_UI; - assign \$20 = BRANCH_BD <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) 2'h2; - assign \$23 = BRANCH_DS <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) 2'h2; - assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) 5'h10; - assign \$3 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) \$4 ; - assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) 64'h0000000000000000; + assign \$9 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) BRANCH_sh; + assign \$11 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) BRANCH_SH32; + assign \$14 = BRANCH_SI <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:287" *) 5'h10; + assign \$17 = BRANCH_LI <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:297" *) 2'h2; + assign \$1 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) BRANCH_UI; + assign \$20 = BRANCH_BD <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:302" *) 2'h2; + assign \$23 = BRANCH_DS <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:307" *) 2'h2; + assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" *) 5'h10; + assign \$3 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" *) \$4 ; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:311" *) 64'h0000000000000000; always @* begin if (\initial ) begin end imm_b = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: imm_b = \$1 ; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: imm_b = { si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si }; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: imm_b = { si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi }; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: imm_b = \$3 ; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: imm_b = { li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li }; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:300" */ 4'h7: imm_b = { bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd }; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:305" */ 4'h8: imm_b = { ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds }; /* \nmigen.decoding = "CONST_M1/9" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:310" */ 4'h9: imm_b = \$7 ; /* \nmigen.decoding = "CONST_SH/10" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:313" */ 4'ha: imm_b = \$9 ; /* \nmigen.decoding = "CONST_SH32/11" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:316" */ 4'hb: imm_b = \$11 ; endcase @@ -126478,46 +135498,46 @@ module \dec_bi$144 (imm_b, imm_b_ok, BRANCH_SI, BRANCH_UI, BRANCH_SH32, BRANCH_s always @* begin if (\initial ) begin end imm_b_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:300" */ 4'h7: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:305" */ 4'h8: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_M1/9" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:310" */ 4'h9: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SH/10" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:313" */ 4'ha: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SH32/11" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:316" */ 4'hb: imm_b_ok = 1'h1; endcase @@ -126525,14 +135545,14 @@ module \dec_bi$144 (imm_b, imm_b_ok, BRANCH_SI, BRANCH_UI, BRANCH_SH32, BRANCH_s always @* begin if (\initial ) begin end si = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: si = BRANCH_SI; endcase @@ -126540,18 +135560,18 @@ module \dec_bi$144 (imm_b, imm_b_ok, BRANCH_SI, BRANCH_UI, BRANCH_SH32, BRANCH_s always @* begin if (\initial ) begin end si_hi = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: si_hi = \$13 [31:0]; endcase @@ -126559,22 +135579,22 @@ module \dec_bi$144 (imm_b, imm_b_ok, BRANCH_SI, BRANCH_UI, BRANCH_SH32, BRANCH_s always @* begin if (\initial ) begin end ui = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: ui = BRANCH_UI; endcase @@ -126582,26 +135602,26 @@ module \dec_bi$144 (imm_b, imm_b_ok, BRANCH_SI, BRANCH_UI, BRANCH_SH32, BRANCH_s always @* begin if (\initial ) begin end li = 26'h0000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: li = \$16 [25:0]; endcase @@ -126609,30 +135629,30 @@ module \dec_bi$144 (imm_b, imm_b_ok, BRANCH_SI, BRANCH_UI, BRANCH_SH32, BRANCH_s always @* begin if (\initial ) begin end bd = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: /* empty */; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:300" */ 4'h7: bd = \$19 [15:0]; endcase @@ -126640,34 +135660,34 @@ module \dec_bi$144 (imm_b, imm_b_ok, BRANCH_SI, BRANCH_UI, BRANCH_SH32, BRANCH_s always @* begin if (\initial ) begin end ds = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: /* empty */; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:300" */ 4'h7: /* empty */; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:305" */ 4'h8: ds = \$22 [15:0]; endcase @@ -126682,59 +135702,59 @@ endmodule (* generator = "nMigen" *) module \dec_bi$149 (imm_b, imm_b_ok, LOGICAL_SI, LOGICAL_UI, LOGICAL_SH32, LOGICAL_sh, LOGICAL_LI, LOGICAL_BD, LOGICAL_DS, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [63:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [63:0] \$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:287" *) wire [46:0] \$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:287" *) wire [46:0] \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:297" *) wire [26:0] \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:297" *) wire [26:0] \$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:302" *) wire [16:0] \$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:302" *) wire [16:0] \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:307" *) wire [16:0] \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:307" *) wire [16:0] \$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" *) wire [63:0] \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" *) wire [46:0] \$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:311" *) wire [63:0] \$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [63:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [13:0] LOGICAL_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [13:0] LOGICAL_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [23:0] LOGICAL_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [4:0] LOGICAL_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [15:0] LOGICAL_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [15:0] LOGICAL_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [5:0] LOGICAL_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:301" *) reg [15:0] bd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:306" *) reg [15:0] ds; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] imm_b; reg [63:0] imm_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output imm_b_ok; reg imm_b_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:296" *) reg [25:0] li; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -126751,67 +135771,68 @@ module \dec_bi$149 (imm_b, imm_b_ok, LOGICAL_SI, LOGICAL_UI, LOGICAL_SH32, LOGIC (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" *) input [3:0] sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:281" *) reg [15:0] si; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:286" *) reg [31:0] si_hi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:291" *) reg [15:0] ui; - assign \$9 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) LOGICAL_sh; - assign \$11 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) LOGICAL_SH32; - assign \$14 = LOGICAL_SI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) 5'h10; - assign \$17 = LOGICAL_LI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) 2'h2; - assign \$1 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) LOGICAL_UI; - assign \$20 = LOGICAL_BD <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) 2'h2; - assign \$23 = LOGICAL_DS <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) 2'h2; - assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) 5'h10; - assign \$3 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) \$4 ; - assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) 64'h0000000000000000; + assign \$9 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) LOGICAL_sh; + assign \$11 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) LOGICAL_SH32; + assign \$14 = LOGICAL_SI <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:287" *) 5'h10; + assign \$17 = LOGICAL_LI <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:297" *) 2'h2; + assign \$1 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) LOGICAL_UI; + assign \$20 = LOGICAL_BD <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:302" *) 2'h2; + assign \$23 = LOGICAL_DS <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:307" *) 2'h2; + assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" *) 5'h10; + assign \$3 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" *) \$4 ; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:311" *) 64'h0000000000000000; always @* begin if (\initial ) begin end imm_b = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: imm_b = \$1 ; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: imm_b = { si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si }; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: imm_b = { si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi }; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: imm_b = \$3 ; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: imm_b = { li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li }; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:300" */ 4'h7: imm_b = { bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd }; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:305" */ 4'h8: imm_b = { ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds }; /* \nmigen.decoding = "CONST_M1/9" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:310" */ 4'h9: imm_b = \$7 ; /* \nmigen.decoding = "CONST_SH/10" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:313" */ 4'ha: imm_b = \$9 ; /* \nmigen.decoding = "CONST_SH32/11" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:316" */ 4'hb: imm_b = \$11 ; endcase @@ -126819,46 +135840,46 @@ module \dec_bi$149 (imm_b, imm_b_ok, LOGICAL_SI, LOGICAL_UI, LOGICAL_SH32, LOGIC always @* begin if (\initial ) begin end imm_b_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:300" */ 4'h7: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:305" */ 4'h8: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_M1/9" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:310" */ 4'h9: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SH/10" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:313" */ 4'ha: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SH32/11" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:316" */ 4'hb: imm_b_ok = 1'h1; endcase @@ -126866,14 +135887,14 @@ module \dec_bi$149 (imm_b, imm_b_ok, LOGICAL_SI, LOGICAL_UI, LOGICAL_SH32, LOGIC always @* begin if (\initial ) begin end si = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: si = LOGICAL_SI; endcase @@ -126881,18 +135902,18 @@ module \dec_bi$149 (imm_b, imm_b_ok, LOGICAL_SI, LOGICAL_UI, LOGICAL_SH32, LOGIC always @* begin if (\initial ) begin end si_hi = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: si_hi = \$13 [31:0]; endcase @@ -126900,22 +135921,22 @@ module \dec_bi$149 (imm_b, imm_b_ok, LOGICAL_SI, LOGICAL_UI, LOGICAL_SH32, LOGIC always @* begin if (\initial ) begin end ui = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: ui = LOGICAL_UI; endcase @@ -126923,26 +135944,26 @@ module \dec_bi$149 (imm_b, imm_b_ok, LOGICAL_SI, LOGICAL_UI, LOGICAL_SH32, LOGIC always @* begin if (\initial ) begin end li = 26'h0000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: li = \$16 [25:0]; endcase @@ -126950,30 +135971,30 @@ module \dec_bi$149 (imm_b, imm_b_ok, LOGICAL_SI, LOGICAL_UI, LOGICAL_SH32, LOGIC always @* begin if (\initial ) begin end bd = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: /* empty */; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:300" */ 4'h7: bd = \$19 [15:0]; endcase @@ -126981,34 +136002,34 @@ module \dec_bi$149 (imm_b, imm_b_ok, LOGICAL_SI, LOGICAL_UI, LOGICAL_SH32, LOGIC always @* begin if (\initial ) begin end ds = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: /* empty */; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:300" */ 4'h7: /* empty */; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:305" */ 4'h8: ds = \$22 [15:0]; endcase @@ -127023,59 +136044,59 @@ endmodule (* generator = "nMigen" *) module \dec_bi$157 (imm_b, imm_b_ok, DIV_SI, DIV_UI, DIV_SH32, DIV_sh, DIV_LI, DIV_BD, DIV_DS, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [63:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [63:0] \$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:287" *) wire [46:0] \$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:287" *) wire [46:0] \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:297" *) wire [26:0] \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:297" *) wire [26:0] \$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:302" *) wire [16:0] \$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:302" *) wire [16:0] \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:307" *) wire [16:0] \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:307" *) wire [16:0] \$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" *) wire [63:0] \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" *) wire [46:0] \$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:311" *) wire [63:0] \$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [63:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [13:0] DIV_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [13:0] DIV_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [23:0] DIV_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [4:0] DIV_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [15:0] DIV_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [15:0] DIV_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [5:0] DIV_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:301" *) reg [15:0] bd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:306" *) reg [15:0] ds; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] imm_b; reg [63:0] imm_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output imm_b_ok; reg imm_b_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:296" *) reg [25:0] li; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -127092,67 +136113,68 @@ module \dec_bi$157 (imm_b, imm_b_ok, DIV_SI, DIV_UI, DIV_SH32, DIV_sh, DIV_LI, D (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" *) input [3:0] sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:281" *) reg [15:0] si; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:286" *) reg [31:0] si_hi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:291" *) reg [15:0] ui; - assign \$9 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) DIV_sh; - assign \$11 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) DIV_SH32; - assign \$14 = DIV_SI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) 5'h10; - assign \$17 = DIV_LI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) 2'h2; - assign \$1 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) DIV_UI; - assign \$20 = DIV_BD <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) 2'h2; - assign \$23 = DIV_DS <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) 2'h2; - assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) 5'h10; - assign \$3 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) \$4 ; - assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) 64'h0000000000000000; + assign \$9 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) DIV_sh; + assign \$11 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) DIV_SH32; + assign \$14 = DIV_SI <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:287" *) 5'h10; + assign \$17 = DIV_LI <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:297" *) 2'h2; + assign \$1 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) DIV_UI; + assign \$20 = DIV_BD <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:302" *) 2'h2; + assign \$23 = DIV_DS <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:307" *) 2'h2; + assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" *) 5'h10; + assign \$3 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" *) \$4 ; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:311" *) 64'h0000000000000000; always @* begin if (\initial ) begin end imm_b = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: imm_b = \$1 ; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: imm_b = { si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si }; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: imm_b = { si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi }; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: imm_b = \$3 ; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: imm_b = { li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li }; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:300" */ 4'h7: imm_b = { bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd }; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:305" */ 4'h8: imm_b = { ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds }; /* \nmigen.decoding = "CONST_M1/9" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:310" */ 4'h9: imm_b = \$7 ; /* \nmigen.decoding = "CONST_SH/10" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:313" */ 4'ha: imm_b = \$9 ; /* \nmigen.decoding = "CONST_SH32/11" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:316" */ 4'hb: imm_b = \$11 ; endcase @@ -127160,46 +136182,46 @@ module \dec_bi$157 (imm_b, imm_b_ok, DIV_SI, DIV_UI, DIV_SH32, DIV_sh, DIV_LI, D always @* begin if (\initial ) begin end imm_b_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:300" */ 4'h7: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:305" */ 4'h8: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_M1/9" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:310" */ 4'h9: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SH/10" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:313" */ 4'ha: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SH32/11" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:316" */ 4'hb: imm_b_ok = 1'h1; endcase @@ -127207,14 +136229,14 @@ module \dec_bi$157 (imm_b, imm_b_ok, DIV_SI, DIV_UI, DIV_SH32, DIV_sh, DIV_LI, D always @* begin if (\initial ) begin end si = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: si = DIV_SI; endcase @@ -127222,18 +136244,18 @@ module \dec_bi$157 (imm_b, imm_b_ok, DIV_SI, DIV_UI, DIV_SH32, DIV_sh, DIV_LI, D always @* begin if (\initial ) begin end si_hi = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: si_hi = \$13 [31:0]; endcase @@ -127241,22 +136263,22 @@ module \dec_bi$157 (imm_b, imm_b_ok, DIV_SI, DIV_UI, DIV_SH32, DIV_sh, DIV_LI, D always @* begin if (\initial ) begin end ui = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: ui = DIV_UI; endcase @@ -127264,26 +136286,26 @@ module \dec_bi$157 (imm_b, imm_b_ok, DIV_SI, DIV_UI, DIV_SH32, DIV_sh, DIV_LI, D always @* begin if (\initial ) begin end li = 26'h0000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: li = \$16 [25:0]; endcase @@ -127291,30 +136313,30 @@ module \dec_bi$157 (imm_b, imm_b_ok, DIV_SI, DIV_UI, DIV_SH32, DIV_sh, DIV_LI, D always @* begin if (\initial ) begin end bd = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: /* empty */; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:300" */ 4'h7: bd = \$19 [15:0]; endcase @@ -127322,34 +136344,34 @@ module \dec_bi$157 (imm_b, imm_b_ok, DIV_SI, DIV_UI, DIV_SH32, DIV_sh, DIV_LI, D always @* begin if (\initial ) begin end ds = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: /* empty */; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:300" */ 4'h7: /* empty */; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:305" */ 4'h8: ds = \$22 [15:0]; endcase @@ -127364,59 +136386,59 @@ endmodule (* generator = "nMigen" *) module \dec_bi$161 (imm_b, imm_b_ok, MUL_SI, MUL_UI, MUL_SH32, MUL_sh, MUL_LI, MUL_BD, MUL_DS, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [63:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [63:0] \$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:287" *) wire [46:0] \$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:287" *) wire [46:0] \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:297" *) wire [26:0] \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:297" *) wire [26:0] \$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:302" *) wire [16:0] \$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:302" *) wire [16:0] \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:307" *) wire [16:0] \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:307" *) wire [16:0] \$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" *) wire [63:0] \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" *) wire [46:0] \$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:311" *) wire [63:0] \$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [63:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [13:0] MUL_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [13:0] MUL_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [23:0] MUL_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [4:0] MUL_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [15:0] MUL_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [15:0] MUL_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [5:0] MUL_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:301" *) reg [15:0] bd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:306" *) reg [15:0] ds; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] imm_b; reg [63:0] imm_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output imm_b_ok; reg imm_b_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:296" *) reg [25:0] li; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -127433,67 +136455,68 @@ module \dec_bi$161 (imm_b, imm_b_ok, MUL_SI, MUL_UI, MUL_SH32, MUL_sh, MUL_LI, M (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" *) input [3:0] sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:281" *) reg [15:0] si; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:286" *) reg [31:0] si_hi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:291" *) reg [15:0] ui; - assign \$9 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) MUL_sh; - assign \$11 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) MUL_SH32; - assign \$14 = MUL_SI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) 5'h10; - assign \$17 = MUL_LI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) 2'h2; - assign \$1 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) MUL_UI; - assign \$20 = MUL_BD <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) 2'h2; - assign \$23 = MUL_DS <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) 2'h2; - assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) 5'h10; - assign \$3 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) \$4 ; - assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) 64'h0000000000000000; + assign \$9 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) MUL_sh; + assign \$11 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) MUL_SH32; + assign \$14 = MUL_SI <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:287" *) 5'h10; + assign \$17 = MUL_LI <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:297" *) 2'h2; + assign \$1 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) MUL_UI; + assign \$20 = MUL_BD <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:302" *) 2'h2; + assign \$23 = MUL_DS <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:307" *) 2'h2; + assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" *) 5'h10; + assign \$3 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" *) \$4 ; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:311" *) 64'h0000000000000000; always @* begin if (\initial ) begin end imm_b = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: imm_b = \$1 ; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: imm_b = { si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si }; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: imm_b = { si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi }; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: imm_b = \$3 ; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: imm_b = { li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li }; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:300" */ 4'h7: imm_b = { bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd }; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:305" */ 4'h8: imm_b = { ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds }; /* \nmigen.decoding = "CONST_M1/9" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:310" */ 4'h9: imm_b = \$7 ; /* \nmigen.decoding = "CONST_SH/10" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:313" */ 4'ha: imm_b = \$9 ; /* \nmigen.decoding = "CONST_SH32/11" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:316" */ 4'hb: imm_b = \$11 ; endcase @@ -127501,46 +136524,46 @@ module \dec_bi$161 (imm_b, imm_b_ok, MUL_SI, MUL_UI, MUL_SH32, MUL_sh, MUL_LI, M always @* begin if (\initial ) begin end imm_b_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:300" */ 4'h7: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:305" */ 4'h8: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_M1/9" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:310" */ 4'h9: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SH/10" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:313" */ 4'ha: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SH32/11" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:316" */ 4'hb: imm_b_ok = 1'h1; endcase @@ -127548,14 +136571,14 @@ module \dec_bi$161 (imm_b, imm_b_ok, MUL_SI, MUL_UI, MUL_SH32, MUL_sh, MUL_LI, M always @* begin if (\initial ) begin end si = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: si = MUL_SI; endcase @@ -127563,18 +136586,18 @@ module \dec_bi$161 (imm_b, imm_b_ok, MUL_SI, MUL_UI, MUL_SH32, MUL_sh, MUL_LI, M always @* begin if (\initial ) begin end si_hi = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: si_hi = \$13 [31:0]; endcase @@ -127582,22 +136605,22 @@ module \dec_bi$161 (imm_b, imm_b_ok, MUL_SI, MUL_UI, MUL_SH32, MUL_sh, MUL_LI, M always @* begin if (\initial ) begin end ui = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: ui = MUL_UI; endcase @@ -127605,26 +136628,26 @@ module \dec_bi$161 (imm_b, imm_b_ok, MUL_SI, MUL_UI, MUL_SH32, MUL_sh, MUL_LI, M always @* begin if (\initial ) begin end li = 26'h0000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: li = \$16 [25:0]; endcase @@ -127632,30 +136655,30 @@ module \dec_bi$161 (imm_b, imm_b_ok, MUL_SI, MUL_UI, MUL_SH32, MUL_sh, MUL_LI, M always @* begin if (\initial ) begin end bd = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: /* empty */; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:300" */ 4'h7: bd = \$19 [15:0]; endcase @@ -127663,34 +136686,34 @@ module \dec_bi$161 (imm_b, imm_b_ok, MUL_SI, MUL_UI, MUL_SH32, MUL_sh, MUL_LI, M always @* begin if (\initial ) begin end ds = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: /* empty */; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:300" */ 4'h7: /* empty */; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:305" */ 4'h8: ds = \$22 [15:0]; endcase @@ -127705,59 +136728,59 @@ endmodule (* generator = "nMigen" *) module \dec_bi$165 (imm_b, imm_b_ok, SHIFT_ROT_SI, SHIFT_ROT_UI, SHIFT_ROT_SH32, SHIFT_ROT_sh, SHIFT_ROT_LI, SHIFT_ROT_BD, SHIFT_ROT_DS, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [63:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [63:0] \$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:287" *) wire [46:0] \$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:287" *) wire [46:0] \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:297" *) wire [26:0] \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:297" *) wire [26:0] \$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:302" *) wire [16:0] \$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:302" *) wire [16:0] \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:307" *) wire [16:0] \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:307" *) wire [16:0] \$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" *) wire [63:0] \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" *) wire [46:0] \$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:311" *) wire [63:0] \$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [63:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [13:0] SHIFT_ROT_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [13:0] SHIFT_ROT_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [23:0] SHIFT_ROT_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [4:0] SHIFT_ROT_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [15:0] SHIFT_ROT_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [15:0] SHIFT_ROT_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [5:0] SHIFT_ROT_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:301" *) reg [15:0] bd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:306" *) reg [15:0] ds; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] imm_b; reg [63:0] imm_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output imm_b_ok; reg imm_b_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:296" *) reg [25:0] li; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -127774,67 +136797,68 @@ module \dec_bi$165 (imm_b, imm_b_ok, SHIFT_ROT_SI, SHIFT_ROT_UI, SHIFT_ROT_SH32, (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" *) input [3:0] sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:281" *) reg [15:0] si; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:286" *) reg [31:0] si_hi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:291" *) reg [15:0] ui; - assign \$9 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) SHIFT_ROT_sh; - assign \$11 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) SHIFT_ROT_SH32; - assign \$14 = SHIFT_ROT_SI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) 5'h10; - assign \$17 = SHIFT_ROT_LI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) 2'h2; - assign \$1 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) SHIFT_ROT_UI; - assign \$20 = SHIFT_ROT_BD <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) 2'h2; - assign \$23 = SHIFT_ROT_DS <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) 2'h2; - assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) 5'h10; - assign \$3 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) \$4 ; - assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) 64'h0000000000000000; + assign \$9 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) SHIFT_ROT_sh; + assign \$11 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) SHIFT_ROT_SH32; + assign \$14 = SHIFT_ROT_SI <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:287" *) 5'h10; + assign \$17 = SHIFT_ROT_LI <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:297" *) 2'h2; + assign \$1 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) SHIFT_ROT_UI; + assign \$20 = SHIFT_ROT_BD <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:302" *) 2'h2; + assign \$23 = SHIFT_ROT_DS <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:307" *) 2'h2; + assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" *) 5'h10; + assign \$3 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" *) \$4 ; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:311" *) 64'h0000000000000000; always @* begin if (\initial ) begin end imm_b = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: imm_b = \$1 ; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: imm_b = { si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si }; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: imm_b = { si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi }; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: imm_b = \$3 ; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: imm_b = { li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li }; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:300" */ 4'h7: imm_b = { bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd }; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:305" */ 4'h8: imm_b = { ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds }; /* \nmigen.decoding = "CONST_M1/9" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:310" */ 4'h9: imm_b = \$7 ; /* \nmigen.decoding = "CONST_SH/10" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:313" */ 4'ha: imm_b = \$9 ; /* \nmigen.decoding = "CONST_SH32/11" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:316" */ 4'hb: imm_b = \$11 ; endcase @@ -127842,46 +136866,46 @@ module \dec_bi$165 (imm_b, imm_b_ok, SHIFT_ROT_SI, SHIFT_ROT_UI, SHIFT_ROT_SH32, always @* begin if (\initial ) begin end imm_b_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:300" */ 4'h7: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:305" */ 4'h8: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_M1/9" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:310" */ 4'h9: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SH/10" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:313" */ 4'ha: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SH32/11" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:316" */ 4'hb: imm_b_ok = 1'h1; endcase @@ -127889,14 +136913,14 @@ module \dec_bi$165 (imm_b, imm_b_ok, SHIFT_ROT_SI, SHIFT_ROT_UI, SHIFT_ROT_SH32, always @* begin if (\initial ) begin end si = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: si = SHIFT_ROT_SI; endcase @@ -127904,18 +136928,18 @@ module \dec_bi$165 (imm_b, imm_b_ok, SHIFT_ROT_SI, SHIFT_ROT_UI, SHIFT_ROT_SH32, always @* begin if (\initial ) begin end si_hi = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: si_hi = \$13 [31:0]; endcase @@ -127923,22 +136947,22 @@ module \dec_bi$165 (imm_b, imm_b_ok, SHIFT_ROT_SI, SHIFT_ROT_UI, SHIFT_ROT_SH32, always @* begin if (\initial ) begin end ui = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: ui = SHIFT_ROT_UI; endcase @@ -127946,26 +136970,26 @@ module \dec_bi$165 (imm_b, imm_b_ok, SHIFT_ROT_SI, SHIFT_ROT_UI, SHIFT_ROT_SH32, always @* begin if (\initial ) begin end li = 26'h0000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: li = \$16 [25:0]; endcase @@ -127973,30 +136997,30 @@ module \dec_bi$165 (imm_b, imm_b_ok, SHIFT_ROT_SI, SHIFT_ROT_UI, SHIFT_ROT_SH32, always @* begin if (\initial ) begin end bd = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: /* empty */; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:300" */ 4'h7: bd = \$19 [15:0]; endcase @@ -128004,34 +137028,34 @@ module \dec_bi$165 (imm_b, imm_b_ok, SHIFT_ROT_SI, SHIFT_ROT_UI, SHIFT_ROT_SH32, always @* begin if (\initial ) begin end ds = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: /* empty */; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:300" */ 4'h7: /* empty */; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:305" */ 4'h8: ds = \$22 [15:0]; endcase @@ -128046,59 +137070,59 @@ endmodule (* generator = "nMigen" *) module \dec_bi$170 (imm_b, imm_b_ok, LDST_SI, LDST_UI, LDST_SH32, LDST_sh, LDST_LI, LDST_BD, LDST_DS, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [63:0] \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [63:0] \$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:287" *) wire [46:0] \$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:287" *) wire [46:0] \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:297" *) wire [26:0] \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:297" *) wire [26:0] \$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:302" *) wire [16:0] \$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:302" *) wire [16:0] \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:307" *) wire [16:0] \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:307" *) wire [16:0] \$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" *) wire [63:0] \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" *) wire [46:0] \$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:311" *) wire [63:0] \$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) wire [63:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [13:0] LDST_BD; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [13:0] LDST_DS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [23:0] LDST_LI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [4:0] LDST_SH32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [15:0] LDST_SI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [15:0] LDST_UI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [5:0] LDST_sh; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:301" *) reg [15:0] bd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:306" *) reg [15:0] ds; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] imm_b; reg [63:0] imm_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output imm_b_ok; reg imm_b_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:296" *) reg [25:0] li; (* enum_base_type = "In2Sel" *) (* enum_value_0000 = "NONE" *) @@ -128115,67 +137139,68 @@ module \dec_bi$170 (imm_b, imm_b_ok, LDST_SI, LDST_UI, LDST_SH32, LDST_sh, LDST_ (* enum_value_1011 = "CONST_SH32" *) (* enum_value_1100 = "SPR" *) (* enum_value_1101 = "RS" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *) + (* enum_value_1110 = "FRB" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:268" *) input [3:0] sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:281" *) reg [15:0] si; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:286" *) reg [31:0] si_hi; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:291" *) reg [15:0] ui; - assign \$9 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) LDST_sh; - assign \$11 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) LDST_SH32; - assign \$14 = LDST_SI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) 5'h10; - assign \$17 = LDST_LI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) 2'h2; - assign \$1 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) LDST_UI; - assign \$20 = LDST_BD <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) 2'h2; - assign \$23 = LDST_DS <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) 2'h2; - assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) 5'h10; - assign \$3 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) \$4 ; - assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *) 64'h0000000000000000; + assign \$9 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) LDST_sh; + assign \$11 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) LDST_SH32; + assign \$14 = LDST_SI <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:287" *) 5'h10; + assign \$17 = LDST_LI <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:297" *) 2'h2; + assign \$1 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) LDST_UI; + assign \$20 = LDST_BD <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:302" *) 2'h2; + assign \$23 = LDST_DS <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:307" *) 2'h2; + assign \$4 = ui <<< (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" *) 5'h10; + assign \$3 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:293" *) \$4 ; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:311" *) 64'h0000000000000000; always @* begin if (\initial ) begin end imm_b = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: imm_b = \$1 ; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: imm_b = { si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si }; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: imm_b = { si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi }; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: imm_b = \$3 ; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: imm_b = { li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li }; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:300" */ 4'h7: imm_b = { bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd }; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:305" */ 4'h8: imm_b = { ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds }; /* \nmigen.decoding = "CONST_M1/9" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:310" */ 4'h9: imm_b = \$7 ; /* \nmigen.decoding = "CONST_SH/10" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:313" */ 4'ha: imm_b = \$9 ; /* \nmigen.decoding = "CONST_SH32/11" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:316" */ 4'hb: imm_b = \$11 ; endcase @@ -128183,46 +137208,46 @@ module \dec_bi$170 (imm_b, imm_b_ok, LDST_SI, LDST_UI, LDST_SH32, LDST_sh, LDST_ always @* begin if (\initial ) begin end imm_b_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:300" */ 4'h7: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:305" */ 4'h8: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_M1/9" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:310" */ 4'h9: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SH/10" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:313" */ 4'ha: imm_b_ok = 1'h1; /* \nmigen.decoding = "CONST_SH32/11" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:316" */ 4'hb: imm_b_ok = 1'h1; endcase @@ -128230,14 +137255,14 @@ module \dec_bi$170 (imm_b, imm_b_ok, LDST_SI, LDST_UI, LDST_SH32, LDST_sh, LDST_ always @* begin if (\initial ) begin end si = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: si = LDST_SI; endcase @@ -128245,18 +137270,18 @@ module \dec_bi$170 (imm_b, imm_b_ok, LDST_SI, LDST_UI, LDST_SH32, LDST_sh, LDST_ always @* begin if (\initial ) begin end si_hi = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: si_hi = \$13 [31:0]; endcase @@ -128264,22 +137289,22 @@ module \dec_bi$170 (imm_b, imm_b_ok, LDST_SI, LDST_UI, LDST_SH32, LDST_sh, LDST_ always @* begin if (\initial ) begin end ui = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: ui = LDST_UI; endcase @@ -128287,26 +137312,26 @@ module \dec_bi$170 (imm_b, imm_b_ok, LDST_SI, LDST_UI, LDST_SH32, LDST_sh, LDST_ always @* begin if (\initial ) begin end li = 26'h0000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: li = \$16 [25:0]; endcase @@ -128314,30 +137339,30 @@ module \dec_bi$170 (imm_b, imm_b_ok, LDST_SI, LDST_UI, LDST_SH32, LDST_sh, LDST_ always @* begin if (\initial ) begin end bd = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: /* empty */; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:300" */ 4'h7: bd = \$19 [15:0]; endcase @@ -128345,34 +137370,34 @@ module \dec_bi$170 (imm_b, imm_b_ok, LDST_SI, LDST_UI, LDST_SH32, LDST_sh, LDST_ always @* begin if (\initial ) begin end ds = 16'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:276" *) casez (sel_in) /* \nmigen.decoding = "CONST_UI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:277" */ 4'h2: /* empty */; /* \nmigen.decoding = "CONST_SI/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:280" */ 4'h3: /* empty */; /* \nmigen.decoding = "CONST_SI_HI/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:285" */ 4'h5: /* empty */; /* \nmigen.decoding = "CONST_UI_HI/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:290" */ 4'h4: /* empty */; /* \nmigen.decoding = "CONST_LI/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:295" */ 4'h6: /* empty */; /* \nmigen.decoding = "CONST_BD/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:300" */ 4'h7: /* empty */; /* \nmigen.decoding = "CONST_DS/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:305" */ 4'h8: ds = \$22 [15:0]; endcase @@ -128385,51 +137410,73 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.dec2.dec_c" *) (* generator = "nMigen" *) -module dec_c(reg_c, reg_c_ok, RS, RB, sel_in); +module dec_c(reg_c, reg_c_ok, FRS, FRC, RS, RB, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + input [4:0] FRC; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + input [4:0] FRS; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [4:0] RB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [4:0] RS; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [4:0] reg_c; reg [4:0] reg_c; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output reg_c_ok; reg reg_c_ok; (* enum_base_type = "In3Sel" *) - (* enum_value_00 = "NONE" *) - (* enum_value_01 = "RS" *) - (* enum_value_10 = "RB" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315" *) - input [1:0] sel_in; + (* enum_value_000 = "NONE" *) + (* enum_value_001 = "RS" *) + (* enum_value_010 = "RB" *) + (* enum_value_011 = "FRS" *) + (* enum_value_100 = "FRC" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:331" *) + input [2:0] sel_in; always @* begin if (\initial ) begin end reg_c = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:326" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:342" *) casez (sel_in) /* \nmigen.decoding = "RB/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:327" */ - 2'h2: + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:343" */ + 3'h2: reg_c = RB; + /* \nmigen.decoding = "FRS/3" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:347" */ + 3'h3: + reg_c = FRS; + /* \nmigen.decoding = "FRC/4" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:350" */ + 3'h4: + reg_c = FRC; /* \nmigen.decoding = "RS/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:331" */ - 2'h1: + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:353" */ + 3'h1: reg_c = RS; endcase end always @* begin if (\initial ) begin end reg_c_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:326" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:342" *) casez (sel_in) /* \nmigen.decoding = "RB/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:327" */ - 2'h2: + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:343" */ + 3'h2: + reg_c_ok = 1'h1; + /* \nmigen.decoding = "FRS/3" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:347" */ + 3'h3: + reg_c_ok = 1'h1; + /* \nmigen.decoding = "FRC/4" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:350" */ + 3'h4: reg_c_ok = 1'h1; /* \nmigen.decoding = "RS/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:331" */ - 2'h1: + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:353" */ + 3'h1: reg_c_ok = 1'h1; endcase end @@ -128439,53 +137486,53 @@ endmodule (* generator = "nMigen" *) module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok, cr_bitfield_b, cr_bitfield_b_ok, cr_bitfield_o, cr_bitfield_o_ok, BB, BA, BT, FXM, BI, BC, X_BFA, internal_op); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:624" *) wire \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:624" *) wire \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:624" *) wire \$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:624" *) wire \$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [4:0] BA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [4:0] BB; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [4:0] BC; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [4:0] BI; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [4:0] BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [7:0] FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) input [2:0] X_BFA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [2:0] cr_bitfield; reg [2:0] cr_bitfield; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [2:0] cr_bitfield_b; reg [2:0] cr_bitfield_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_bitfield_b_ok; reg cr_bitfield_b_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [2:0] cr_bitfield_o; reg [2:0] cr_bitfield_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_bitfield_o_ok; reg cr_bitfield_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_bitfield_ok; reg cr_bitfield_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [7:0] cr_fxm; reg [7:0] cr_fxm; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_fxm_ok; reg cr_fxm_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:571" *) input [31:0] insn_in; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -128562,9 +137609,11 @@ module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [6:0] internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:594" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:622" *) reg move_one; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) reg [7:0] ppick_i; @@ -128579,14 +137628,14 @@ module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok (* enum_value_101 = "BC" *) (* enum_value_110 = "WHOLE_REG" *) (* enum_value_111 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:542" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:570" *) input [2:0] sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:576" *) reg [1:0] sv_override; - assign \$1 = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) 7'h2d; - assign \$3 = \$1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) move_one; - assign \$5 = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) 7'h2d; - assign \$7 = \$5 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) move_one; + assign \$1 = internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:624" *) 7'h2d; + assign \$3 = \$1 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:624" *) move_one; + assign \$5 = internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:624" *) 7'h2d; + assign \$7 = \$5 & (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:624" *) move_one; ppick ppick ( .i(ppick_i), .o(ppick_o) @@ -128594,34 +137643,34 @@ module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok always @* begin if (\initial ) begin end cr_bitfield_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:593" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:594" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:596" */ 3'h1: cr_bitfield_ok = 1'h1; /* \nmigen.decoding = "CR1/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:600" */ 3'h7: cr_bitfield_ok = 1'h1; /* \nmigen.decoding = "BI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:576" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:604" */ 3'h2: cr_bitfield_ok = 1'h1; /* \nmigen.decoding = "BFA/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:607" */ 3'h3: cr_bitfield_ok = 1'h1; /* \nmigen.decoding = "BA_BB/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:582" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:610" */ 3'h4: cr_bitfield_ok = 1'h1; /* \nmigen.decoding = "BC/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:617" */ 3'h5: cr_bitfield_ok = 1'h1; endcase @@ -128629,30 +137678,30 @@ module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok always @* begin if (\initial ) begin end cr_bitfield_b_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:593" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:594" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:596" */ 3'h1: /* empty */; /* \nmigen.decoding = "CR1/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:600" */ 3'h7: /* empty */; /* \nmigen.decoding = "BI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:576" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:604" */ 3'h2: /* empty */; /* \nmigen.decoding = "BFA/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:607" */ 3'h3: /* empty */; /* \nmigen.decoding = "BA_BB/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:582" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:610" */ 3'h4: cr_bitfield_b_ok = 1'h1; endcase @@ -128661,46 +137710,46 @@ module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok if (\initial ) begin end cr_fxm = 8'h00; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:593" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:594" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:596" */ 3'h1: /* empty */; /* \nmigen.decoding = "CR1/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:600" */ 3'h7: /* empty */; /* \nmigen.decoding = "BI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:576" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:604" */ 3'h2: /* empty */; /* \nmigen.decoding = "BFA/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:607" */ 3'h3: /* empty */; /* \nmigen.decoding = "BA_BB/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:582" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:610" */ 3'h4: /* empty */; /* \nmigen.decoding = "BC/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:617" */ 3'h5: /* empty */; /* \nmigen.decoding = "WHOLE_REG/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:592" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:620" */ 3'h6: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:624" *) casez (\$7 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:624" */ 1'h1: cr_fxm = ppick_o; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:600" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:628" */ default: cr_fxm = 8'hff; endcase @@ -128709,30 +137758,30 @@ module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok always @* begin if (\initial ) begin end cr_bitfield_o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:593" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:594" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:596" */ 3'h1: /* empty */; /* \nmigen.decoding = "CR1/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:600" */ 3'h7: /* empty */; /* \nmigen.decoding = "BI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:576" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:604" */ 3'h2: /* empty */; /* \nmigen.decoding = "BFA/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:607" */ 3'h3: /* empty */; /* \nmigen.decoding = "BA_BB/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:582" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:610" */ 3'h4: cr_bitfield_o_ok = 1'h1; endcase @@ -128741,38 +137790,38 @@ module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok if (\initial ) begin end cr_fxm_ok = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:593" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:594" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:596" */ 3'h1: /* empty */; /* \nmigen.decoding = "CR1/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:600" */ 3'h7: /* empty */; /* \nmigen.decoding = "BI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:576" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:604" */ 3'h2: /* empty */; /* \nmigen.decoding = "BFA/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:607" */ 3'h3: /* empty */; /* \nmigen.decoding = "BA_BB/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:582" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:610" */ 3'h4: /* empty */; /* \nmigen.decoding = "BC/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:617" */ 3'h5: /* empty */; /* \nmigen.decoding = "WHOLE_REG/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:592" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:620" */ 3'h6: cr_fxm_ok = 1'h1; endcase @@ -128780,18 +137829,18 @@ module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok always @* begin if (\initial ) begin end sv_override = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:593" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:594" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:596" */ 3'h1: sv_override = 2'h1; /* \nmigen.decoding = "CR1/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:600" */ 3'h7: sv_override = 2'h2; endcase @@ -128799,34 +137848,34 @@ module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok always @* begin if (\initial ) begin end cr_bitfield = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:593" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:594" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:596" */ 3'h1: cr_bitfield = 3'h0; /* \nmigen.decoding = "CR1/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:600" */ 3'h7: cr_bitfield = 3'h1; /* \nmigen.decoding = "BI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:576" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:604" */ 3'h2: cr_bitfield = BI[4:2]; /* \nmigen.decoding = "BFA/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:607" */ 3'h3: cr_bitfield = X_BFA; /* \nmigen.decoding = "BA_BB/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:582" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:610" */ 3'h4: cr_bitfield = BA[4:2]; /* \nmigen.decoding = "BC/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:617" */ 3'h5: cr_bitfield = BC[4:2]; endcase @@ -128834,30 +137883,30 @@ module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok always @* begin if (\initial ) begin end cr_bitfield_b = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:593" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:594" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:596" */ 3'h1: /* empty */; /* \nmigen.decoding = "CR1/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:600" */ 3'h7: /* empty */; /* \nmigen.decoding = "BI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:576" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:604" */ 3'h2: /* empty */; /* \nmigen.decoding = "BFA/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:607" */ 3'h3: /* empty */; /* \nmigen.decoding = "BA_BB/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:582" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:610" */ 3'h4: cr_bitfield_b = BB[4:2]; endcase @@ -128865,30 +137914,30 @@ module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok always @* begin if (\initial ) begin end cr_bitfield_o = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:593" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:594" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:596" */ 3'h1: /* empty */; /* \nmigen.decoding = "CR1/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:600" */ 3'h7: /* empty */; /* \nmigen.decoding = "BI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:576" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:604" */ 3'h2: /* empty */; /* \nmigen.decoding = "BFA/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:607" */ 3'h3: /* empty */; /* \nmigen.decoding = "BA_BB/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:582" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:610" */ 3'h4: cr_bitfield_o = BT[4:2]; endcase @@ -128897,38 +137946,38 @@ module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok if (\initial ) begin end move_one = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:593" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:594" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:596" */ 3'h1: /* empty */; /* \nmigen.decoding = "CR1/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:600" */ 3'h7: /* empty */; /* \nmigen.decoding = "BI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:576" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:604" */ 3'h2: /* empty */; /* \nmigen.decoding = "BFA/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:607" */ 3'h3: /* empty */; /* \nmigen.decoding = "BA_BB/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:582" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:610" */ 3'h4: /* empty */; /* \nmigen.decoding = "BC/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:617" */ 3'h5: /* empty */; /* \nmigen.decoding = "WHOLE_REG/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:592" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:620" */ 3'h6: move_one = insn_in[20]; endcase @@ -128937,42 +137986,42 @@ module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok if (\initial ) begin end ppick_i = 8'h00; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:593" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:594" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:596" */ 3'h1: /* empty */; /* \nmigen.decoding = "CR1/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:600" */ 3'h7: /* empty */; /* \nmigen.decoding = "BI/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:576" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:604" */ 3'h2: /* empty */; /* \nmigen.decoding = "BFA/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:607" */ 3'h3: /* empty */; /* \nmigen.decoding = "BA_BB/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:582" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:610" */ 3'h4: /* empty */; /* \nmigen.decoding = "BC/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:617" */ 3'h5: /* empty */; /* \nmigen.decoding = "WHOLE_REG/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:592" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:620" */ 3'h6: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:624" *) casez (\$3 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:624" */ 1'h1: ppick_i = FXM; endcase @@ -128984,29 +138033,29 @@ endmodule (* generator = "nMigen" *) module dec_cr_out(insn_in, sel_in, rc_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok, FXM, X_BF, XL_BT, internal_op); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:689" *) wire \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:689" *) wire \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [7:0] FXM; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) input [4:0] XL_BT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:496" *) input [2:0] X_BF; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [2:0] cr_bitfield; reg [2:0] cr_bitfield; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_bitfield_ok; reg cr_bitfield_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [7:0] cr_fxm; reg [7:0] cr_fxm; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_fxm_ok; reg cr_fxm_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:646" *) input [31:0] insn_in; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -129083,9 +138132,11 @@ module dec_cr_out(insn_in, sel_in, rc_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bit (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [6:0] internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:659" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:687" *) reg move_one; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) wire ppick_en_o; @@ -129093,7 +138144,7 @@ module dec_cr_out(insn_in, sel_in, rc_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bit reg [7:0] ppick_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) wire [7:0] ppick_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:644" *) input rc_in; (* enum_base_type = "CROutSel" *) (* enum_value_000 = "NONE" *) @@ -129102,12 +138153,12 @@ module dec_cr_out(insn_in, sel_in, rc_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bit (* enum_value_011 = "BT" *) (* enum_value_100 = "WHOLE_REG" *) (* enum_value_101 = "CR1" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:617" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:645" *) input [2:0] sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:621" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:649" *) reg [1:0] sv_override; - assign \$1 = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" *) 7'h30; - assign \$3 = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" *) 7'h30; + assign \$1 = internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:689" *) 7'h30; + assign \$3 = internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:689" *) 7'h30; \ppick$175 ppick ( .en_o(ppick_en_o), .i(ppick_i), @@ -129116,26 +138167,26 @@ module dec_cr_out(insn_in, sel_in, rc_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bit always @* begin if (\initial ) begin end cr_bitfield_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:668" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:641" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:669" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:643" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:671" */ 3'h1: cr_bitfield_ok = rc_in; /* \nmigen.decoding = "CR1/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:647" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:675" */ 3'h5: cr_bitfield_ok = rc_in; /* \nmigen.decoding = "BF/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:679" */ 3'h2: cr_bitfield_ok = 1'h1; /* \nmigen.decoding = "BT/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:654" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:682" */ 3'h3: cr_bitfield_ok = 1'h1; endcase @@ -129143,30 +138194,30 @@ module dec_cr_out(insn_in, sel_in, rc_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bit always @* begin if (\initial ) begin end cr_fxm_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:668" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:641" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:669" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:643" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:671" */ 3'h1: /* empty */; /* \nmigen.decoding = "CR1/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:647" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:675" */ 3'h5: /* empty */; /* \nmigen.decoding = "BF/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:679" */ 3'h2: /* empty */; /* \nmigen.decoding = "BT/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:654" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:682" */ 3'h3: /* empty */; /* \nmigen.decoding = "WHOLE_REG/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:657" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:685" */ 3'h4: cr_fxm_ok = 1'h1; endcase @@ -129174,18 +138225,18 @@ module dec_cr_out(insn_in, sel_in, rc_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bit always @* begin if (\initial ) begin end sv_override = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:668" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:641" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:669" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:643" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:671" */ 3'h1: sv_override = 2'h1; /* \nmigen.decoding = "CR1/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:647" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:675" */ 3'h5: sv_override = 2'h2; endcase @@ -129193,26 +138244,26 @@ module dec_cr_out(insn_in, sel_in, rc_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bit always @* begin if (\initial ) begin end cr_bitfield = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:668" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:641" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:669" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:643" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:671" */ 3'h1: cr_bitfield = 3'h0; /* \nmigen.decoding = "CR1/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:647" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:675" */ 3'h5: cr_bitfield = 3'h1; /* \nmigen.decoding = "BF/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:679" */ 3'h2: cr_bitfield = X_BF; /* \nmigen.decoding = "BT/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:654" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:682" */ 3'h3: cr_bitfield = XL_BT[4:2]; endcase @@ -129220,30 +138271,30 @@ module dec_cr_out(insn_in, sel_in, rc_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bit always @* begin if (\initial ) begin end move_one = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:668" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:641" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:669" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:643" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:671" */ 3'h1: /* empty */; /* \nmigen.decoding = "CR1/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:647" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:675" */ 3'h5: /* empty */; /* \nmigen.decoding = "BF/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:679" */ 3'h2: /* empty */; /* \nmigen.decoding = "BT/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:654" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:682" */ 3'h3: /* empty */; /* \nmigen.decoding = "WHOLE_REG/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:657" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:685" */ 3'h4: move_one = insn_in[20]; endcase @@ -129251,38 +138302,38 @@ module dec_cr_out(insn_in, sel_in, rc_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bit always @* begin if (\initial ) begin end ppick_i = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:668" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:641" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:669" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:643" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:671" */ 3'h1: /* empty */; /* \nmigen.decoding = "CR1/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:647" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:675" */ 3'h5: /* empty */; /* \nmigen.decoding = "BF/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:679" */ 3'h2: /* empty */; /* \nmigen.decoding = "BT/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:654" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:682" */ 3'h3: /* empty */; /* \nmigen.decoding = "WHOLE_REG/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:657" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:685" */ 3'h4: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:689" *) casez (\$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:689" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:662" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:690" *) casez (move_one) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:662" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:690" */ 1'h1: ppick_i = FXM; endcase @@ -129292,56 +138343,56 @@ module dec_cr_out(insn_in, sel_in, rc_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bit always @* begin if (\initial ) begin end cr_fxm = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:668" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:641" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:669" */ 3'h0: /* empty */; /* \nmigen.decoding = "CR0/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:643" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:671" */ 3'h1: /* empty */; /* \nmigen.decoding = "CR1/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:647" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:675" */ 3'h5: /* empty */; /* \nmigen.decoding = "BF/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:679" */ 3'h2: /* empty */; /* \nmigen.decoding = "BT/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:654" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:682" */ 3'h3: /* empty */; /* \nmigen.decoding = "WHOLE_REG/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:657" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:685" */ 3'h4: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:689" *) casez (\$3 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:689" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:662" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:690" *) casez (move_one) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:662" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:690" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:665" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:693" *) casez (ppick_en_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:665" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:693" */ 1'h1: cr_fxm = ppick_o; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:667" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:695" */ default: cr_fxm = 8'h01; endcase - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:669" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:697" */ default: cr_fxm = FXM; endcase - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:699" */ default: cr_fxm = 8'hff; endcase @@ -129351,28 +138402,30 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.dec2.dec_o" *) (* generator = "nMigen" *) -module dec_o(SPR, sel_in, reg_o, reg_o_ok, spr_o, spr_o_ok, fast_o, fast_o_ok, RT, RA, BO, internal_op); +module dec_o(SPR, sel_in, reg_o, reg_o_ok, spr_o, spr_o_ok, fast_o, fast_o_ok, FRT, RT, RA, BO, internal_op); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:401" *) wire \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:401" *) wire \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:401" *) wire \$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:386" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:411" *) wire \$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [4:0] BO; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) + input [4:0] FRT; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [4:0] RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [4:0] RT; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [9:0] SPR; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [2:0] fast_o; reg [2:0] fast_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output fast_o_ok; reg fast_o_ok; (* enum_base_type = "MicrOp" *) @@ -129450,12 +138503,14 @@ module dec_o(SPR, sel_in, reg_o, reg_o_ok, spr_o, spr_o_ok, fast_o, fast_o_ok, R (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [6:0] internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [4:0] reg_o; reg [4:0] reg_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output reg_o_ok; reg reg_o_ok; (* enum_base_type = "OutSel" *) @@ -129464,9 +138519,10 @@ module dec_o(SPR, sel_in, reg_o, reg_o_ok, spr_o, spr_o_ok, fast_o, fast_o_ok, R (* enum_value_010 = "RA" *) (* enum_value_011 = "SPR" *) (* enum_value_100 = "RT_OR_ZERO" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:351" *) + (* enum_value_101 = "FRT" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:373" *) input [2:0] sel_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:398" *) reg [9:0] spr; (* enum_base_type = "SPR" *) (* enum_value_0000000001 = "XER" *) @@ -129582,17 +138638,17 @@ module dec_o(SPR, sel_in, reg_o, reg_o_ok, spr_o, spr_o_ok, fast_o, fast_o_ok, R (* enum_value_1110000000 = "PPR" *) (* enum_value_1110000010 = "PPR32" *) (* enum_value_1111111111 = "PIR" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [9:0] spr_o; reg [9:0] spr_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output spr_o_ok; reg spr_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [2:0] sprmap_fast_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire sprmap_fast_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:75" *) reg [9:0] sprmap_spr_i; (* enum_base_type = "SPR" *) (* enum_value_0000000001 = "XER" *) @@ -129708,14 +138764,14 @@ module dec_o(SPR, sel_in, reg_o, reg_o_ok, spr_o, spr_o_ok, fast_o, fast_o_ok, R (* enum_value_1110000000 = "PPR" *) (* enum_value_1110000010 = "PPR32" *) (* enum_value_1111111111 = "PIR" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [9:0] sprmap_spr_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire sprmap_spr_o_ok; - assign \$1 = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *) 7'h31; - assign \$3 = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *) 7'h31; - assign \$5 = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *) 7'h31; - assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:386" *) BO[2]; + assign \$1 = internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:401" *) 7'h31; + assign \$3 = internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:401" *) 7'h31; + assign \$5 = internal_op == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:401" *) 7'h31; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:411" *) BO[2]; \sprmap$174 sprmap ( .fast_o(sprmap_fast_o), .fast_o_ok(sprmap_fast_o_ok), @@ -129726,14 +138782,18 @@ module dec_o(SPR, sel_in, reg_o, reg_o_ok, spr_o, spr_o_ok, fast_o, fast_o_ok, R always @* begin if (\initial ) begin end reg_o = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:387" *) casez (sel_in) + /* \nmigen.decoding = "FRT/5" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:388" */ + 3'h5: + reg_o = FRT; /* \nmigen.decoding = "RT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:366" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:391" */ 3'h1: reg_o = RT; /* \nmigen.decoding = "RA/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:369" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:394" */ 3'h2: reg_o = RA; endcase @@ -129741,14 +138801,18 @@ module dec_o(SPR, sel_in, reg_o, reg_o_ok, spr_o, spr_o_ok, fast_o, fast_o_ok, R always @* begin if (\initial ) begin end reg_o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:387" *) casez (sel_in) + /* \nmigen.decoding = "FRT/5" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:388" */ + 3'h5: + reg_o_ok = 1'h1; /* \nmigen.decoding = "RT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:366" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:391" */ 3'h1: reg_o_ok = 1'h1; /* \nmigen.decoding = "RA/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:369" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:394" */ 3'h2: reg_o_ok = 1'h1; endcase @@ -129756,18 +138820,22 @@ module dec_o(SPR, sel_in, reg_o, reg_o_ok, spr_o, spr_o_ok, fast_o, fast_o_ok, R always @* begin if (\initial ) begin end spr = 10'h000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:387" *) casez (sel_in) + /* \nmigen.decoding = "FRT/5" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:388" */ + 3'h5: + /* empty */; /* \nmigen.decoding = "RT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:366" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:391" */ 3'h1: /* empty */; /* \nmigen.decoding = "RA/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:369" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:394" */ 3'h2: /* empty */; /* \nmigen.decoding = "SPR/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:372" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:397" */ 3'h3: spr = { SPR[4:0], SPR[9:5] }; endcase @@ -129775,22 +138843,26 @@ module dec_o(SPR, sel_in, reg_o, reg_o_ok, spr_o, spr_o_ok, fast_o, fast_o_ok, R always @* begin if (\initial ) begin end sprmap_spr_i = 10'h000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:387" *) casez (sel_in) + /* \nmigen.decoding = "FRT/5" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:388" */ + 3'h5: + /* empty */; /* \nmigen.decoding = "RT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:366" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:391" */ 3'h1: /* empty */; /* \nmigen.decoding = "RA/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:369" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:394" */ 3'h2: /* empty */; /* \nmigen.decoding = "SPR/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:372" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:397" */ 3'h3: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:401" *) casez (\$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:401" */ 1'h1: sprmap_spr_i = spr; endcase @@ -129800,22 +138872,26 @@ module dec_o(SPR, sel_in, reg_o, reg_o_ok, spr_o, spr_o_ok, fast_o, fast_o_ok, R if (\initial ) begin end spr_o = 10'h000; spr_o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:387" *) casez (sel_in) + /* \nmigen.decoding = "FRT/5" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:388" */ + 3'h5: + /* empty */; /* \nmigen.decoding = "RT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:366" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:391" */ 3'h1: /* empty */; /* \nmigen.decoding = "RA/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:369" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:394" */ 3'h2: /* empty */; /* \nmigen.decoding = "SPR/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:372" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:397" */ 3'h3: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:401" *) casez (\$3 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:401" */ 1'h1: { spr_o_ok, spr_o } = { sprmap_spr_o_ok, sprmap_spr_o }; endcase @@ -129825,34 +138901,38 @@ module dec_o(SPR, sel_in, reg_o, reg_o_ok, spr_o, spr_o_ok, fast_o, fast_o_ok, R if (\initial ) begin end fast_o = 3'h0; fast_o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:387" *) casez (sel_in) + /* \nmigen.decoding = "FRT/5" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:388" */ + 3'h5: + /* empty */; /* \nmigen.decoding = "RT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:366" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:391" */ 3'h1: /* empty */; /* \nmigen.decoding = "RA/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:369" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:394" */ 3'h2: /* empty */; /* \nmigen.decoding = "SPR/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:372" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:397" */ 3'h3: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:401" *) casez (\$5 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:401" */ 1'h1: { fast_o_ok, fast_o } = { sprmap_fast_o_ok, sprmap_fast_o }; endcase endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:382" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:407" *) casez (internal_op) /* \nmigen.decoding = "OP_BC/7|OP_BCREG/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:385" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:410" */ 7'h07, 7'h08: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:386" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:411" *) casez (\$7 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:386" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:411" */ 1'h1: begin fast_o = 3'h0; @@ -129860,7 +138940,7 @@ module dec_o(SPR, sel_in, reg_o, reg_o_ok, spr_o, spr_o_ok, fast_o, fast_o_ok, R end endcase /* \nmigen.decoding = "OP_RFID/70" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:392" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:417" */ 7'h46: begin fast_o = 3'h3; @@ -129872,20 +138952,26 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.dec2.dec_o2" *) (* generator = "nMigen" *) -module dec_o2(lk, reg_o2, reg_o2_ok, fast_o2, fast_o2_ok, upd, RA, internal_op); +module dec_o2(lk, reg_o2, reg_o2_ok, fast_o2, fast_o2_ok, fast_o3, fast_o3_ok, upd, RA, internal_op); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:458" *) wire \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:458" *) wire \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input [4:0] RA; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [2:0] fast_o2; reg [2:0] fast_o2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output fast_o2_ok; reg fast_o2_ok; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [2:0] fast_o3; + reg [2:0] fast_o3; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output fast_o3_ok; + reg fast_o3_ok; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -129961,14 +139047,16 @@ module dec_o2(lk, reg_o2, reg_o2_ok, fast_o2, fast_o2_ok, upd, RA, internal_op); (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [6:0] internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:441" *) input lk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [4:0] reg_o2; reg [4:0] reg_o2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output reg_o2_ok; reg reg_o2_ok; (* enum_base_type = "LDSTMode" *) @@ -129976,16 +139064,16 @@ module dec_o2(lk, reg_o2, reg_o2_ok, fast_o2, fast_o2_ok, upd, RA, internal_op); (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [1:0] upd; - assign \$1 = upd == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" *) 2'h1; - assign \$3 = upd == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" *) 2'h1; + assign \$1 = upd == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:458" *) 2'h1; + assign \$3 = upd == (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:458" *) 2'h1; always @* begin if (\initial ) begin end reg_o2 = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:458" *) casez (\$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:458" */ 1'h1: reg_o2 = RA; endcase @@ -129993,9 +139081,9 @@ module dec_o2(lk, reg_o2, reg_o2_ok, fast_o2, fast_o2_ok, upd, RA, internal_op); always @* begin if (\initial ) begin end reg_o2_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:458" *) casez (\$3 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:458" */ 1'h1: reg_o2_ok = 1'h1; endcase @@ -130003,19 +139091,19 @@ module dec_o2(lk, reg_o2, reg_o2_ok, fast_o2, fast_o2_ok, upd, RA, internal_op); always @* begin if (\initial ) begin end fast_o2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:438" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:464" *) casez (internal_op) /* \nmigen.decoding = "OP_BC/7|OP_B/6|OP_BCREG/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:467" */ 7'h07, 7'h06, 7'h08: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:468" *) casez (lk) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:468" */ 1'h1: fast_o2 = 3'h1; endcase /* \nmigen.decoding = "OP_RFID/70" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:447" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:473" */ 7'h46: fast_o2 = 3'h4; endcase @@ -130023,30 +139111,60 @@ module dec_o2(lk, reg_o2, reg_o2_ok, fast_o2, fast_o2_ok, upd, RA, internal_op); always @* begin if (\initial ) begin end fast_o2_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:438" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:464" *) casez (internal_op) /* \nmigen.decoding = "OP_BC/7|OP_B/6|OP_BCREG/8" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:467" */ 7'h07, 7'h06, 7'h08: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:468" *) casez (lk) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:468" */ 1'h1: fast_o2_ok = 1'h1; endcase /* \nmigen.decoding = "OP_RFID/70" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:447" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:473" */ 7'h46: fast_o2_ok = 1'h1; endcase end + always @* begin + if (\initial ) begin end + fast_o3 = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:464" *) + casez (internal_op) + /* \nmigen.decoding = "OP_BC/7|OP_B/6|OP_BCREG/8" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:467" */ + 7'h07, 7'h06, 7'h08: + /* empty */; + /* \nmigen.decoding = "OP_RFID/70" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:473" */ + 7'h46: + fast_o3 = 3'h0; + endcase + end + always @* begin + if (\initial ) begin end + fast_o3_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:464" *) + casez (internal_op) + /* \nmigen.decoding = "OP_BC/7|OP_B/6|OP_BCREG/8" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:467" */ + 7'h07, 7'h06, 7'h08: + /* empty */; + /* \nmigen.decoding = "OP_RFID/70" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:473" */ + 7'h46: + fast_o3_ok = 1'h1; + endcase + end endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.dec_ALU.dec_oe" *) (* generator = "nMigen" *) module dec_oe(ALU_internal_op, oe, oe_ok, ALU_OE, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input ALU_OE; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -130123,37 +139241,39 @@ module dec_oe(ALU_internal_op, oe, oe_ok, ALU_OE, sel_in); (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [6:0] ALU_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output oe; reg oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output oe_ok; reg oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:527" *) input [1:0] sel_in; always @* begin if (\initial ) begin end oe = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:536" *) casez (ALU_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:547" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:551" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:553" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:554" */ 2'h2: oe = ALU_OE; endcase @@ -130163,19 +139283,19 @@ module dec_oe(ALU_internal_op, oe, oe_ok, ALU_OE, sel_in); if (\initial ) begin end oe_ok = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:536" *) casez (ALU_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:547" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:551" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:553" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:554" */ 2'h2: oe_ok = 1'h1; endcase @@ -130187,7 +139307,7 @@ endmodule (* generator = "nMigen" *) module \dec_oe$140 (CR_internal_op, CR_OE, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input CR_OE; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -130264,35 +139384,37 @@ module \dec_oe$140 (CR_internal_op, CR_OE, sel_in); (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [6:0] CR_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:527" *) input [1:0] sel_in; always @* begin if (\initial ) begin end oe = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:536" *) casez (CR_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:547" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:551" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:553" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:554" */ 2'h2: oe = CR_OE; endcase @@ -130302,19 +139424,19 @@ module \dec_oe$140 (CR_internal_op, CR_OE, sel_in); if (\initial ) begin end oe_ok = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:536" *) casez (CR_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:547" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:551" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:553" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:554" */ 2'h2: oe_ok = 1'h1; endcase @@ -130326,7 +139448,7 @@ endmodule (* generator = "nMigen" *) module \dec_oe$143 (BRANCH_internal_op, BRANCH_OE, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input BRANCH_OE; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -130403,35 +139525,37 @@ module \dec_oe$143 (BRANCH_internal_op, BRANCH_OE, sel_in); (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [6:0] BRANCH_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:527" *) input [1:0] sel_in; always @* begin if (\initial ) begin end oe = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:536" *) casez (BRANCH_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:547" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:551" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:553" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:554" */ 2'h2: oe = BRANCH_OE; endcase @@ -130441,19 +139565,19 @@ module \dec_oe$143 (BRANCH_internal_op, BRANCH_OE, sel_in); if (\initial ) begin end oe_ok = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:536" *) casez (BRANCH_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:547" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:551" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:553" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:554" */ 2'h2: oe_ok = 1'h1; endcase @@ -130465,7 +139589,7 @@ endmodule (* generator = "nMigen" *) module \dec_oe$147 (LOGICAL_internal_op, oe, oe_ok, LOGICAL_OE, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input LOGICAL_OE; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -130542,37 +139666,39 @@ module \dec_oe$147 (LOGICAL_internal_op, oe, oe_ok, LOGICAL_OE, sel_in); (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [6:0] LOGICAL_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output oe; reg oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output oe_ok; reg oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:527" *) input [1:0] sel_in; always @* begin if (\initial ) begin end oe = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:536" *) casez (LOGICAL_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:547" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:551" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:553" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:554" */ 2'h2: oe = LOGICAL_OE; endcase @@ -130582,19 +139708,19 @@ module \dec_oe$147 (LOGICAL_internal_op, oe, oe_ok, LOGICAL_OE, sel_in); if (\initial ) begin end oe_ok = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:536" *) casez (LOGICAL_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:547" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:551" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:553" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:554" */ 2'h2: oe_ok = 1'h1; endcase @@ -130606,7 +139732,7 @@ endmodule (* generator = "nMigen" *) module \dec_oe$152 (SPR_internal_op, SPR_OE, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input SPR_OE; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -130683,35 +139809,37 @@ module \dec_oe$152 (SPR_internal_op, SPR_OE, sel_in); (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [6:0] SPR_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:527" *) input [1:0] sel_in; always @* begin if (\initial ) begin end oe = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:536" *) casez (SPR_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:547" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:551" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:553" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:554" */ 2'h2: oe = SPR_OE; endcase @@ -130721,19 +139849,19 @@ module \dec_oe$152 (SPR_internal_op, SPR_OE, sel_in); if (\initial ) begin end oe_ok = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:536" *) casez (SPR_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:547" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:551" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:553" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:554" */ 2'h2: oe_ok = 1'h1; endcase @@ -130745,7 +139873,7 @@ endmodule (* generator = "nMigen" *) module \dec_oe$155 (DIV_internal_op, oe, oe_ok, DIV_OE, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input DIV_OE; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -130822,37 +139950,39 @@ module \dec_oe$155 (DIV_internal_op, oe, oe_ok, DIV_OE, sel_in); (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [6:0] DIV_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output oe; reg oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output oe_ok; reg oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:527" *) input [1:0] sel_in; always @* begin if (\initial ) begin end oe = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:536" *) casez (DIV_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:547" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:551" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:553" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:554" */ 2'h2: oe = DIV_OE; endcase @@ -130862,19 +139992,19 @@ module \dec_oe$155 (DIV_internal_op, oe, oe_ok, DIV_OE, sel_in); if (\initial ) begin end oe_ok = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:536" *) casez (DIV_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:547" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:551" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:553" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:554" */ 2'h2: oe_ok = 1'h1; endcase @@ -130886,7 +140016,7 @@ endmodule (* generator = "nMigen" *) module \dec_oe$160 (MUL_internal_op, oe, oe_ok, MUL_OE, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input MUL_OE; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -130963,37 +140093,39 @@ module \dec_oe$160 (MUL_internal_op, oe, oe_ok, MUL_OE, sel_in); (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [6:0] MUL_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output oe; reg oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output oe_ok; reg oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:527" *) input [1:0] sel_in; always @* begin if (\initial ) begin end oe = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:536" *) casez (MUL_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:547" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:551" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:553" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:554" */ 2'h2: oe = MUL_OE; endcase @@ -131003,19 +140135,19 @@ module \dec_oe$160 (MUL_internal_op, oe, oe_ok, MUL_OE, sel_in); if (\initial ) begin end oe_ok = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:536" *) casez (MUL_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:547" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:551" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:553" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:554" */ 2'h2: oe_ok = 1'h1; endcase @@ -131027,7 +140159,7 @@ endmodule (* generator = "nMigen" *) module \dec_oe$164 (SHIFT_ROT_internal_op, oe, oe_ok, SHIFT_ROT_OE, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input SHIFT_ROT_OE; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -131104,37 +140236,39 @@ module \dec_oe$164 (SHIFT_ROT_internal_op, oe, oe_ok, SHIFT_ROT_OE, sel_in); (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [6:0] SHIFT_ROT_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output oe; reg oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output oe_ok; reg oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:527" *) input [1:0] sel_in; always @* begin if (\initial ) begin end oe = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:536" *) casez (SHIFT_ROT_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:547" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:551" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:553" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:554" */ 2'h2: oe = SHIFT_ROT_OE; endcase @@ -131144,19 +140278,19 @@ module \dec_oe$164 (SHIFT_ROT_internal_op, oe, oe_ok, SHIFT_ROT_OE, sel_in); if (\initial ) begin end oe_ok = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:536" *) casez (SHIFT_ROT_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:547" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:551" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:553" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:554" */ 2'h2: oe_ok = 1'h1; endcase @@ -131168,7 +140302,7 @@ endmodule (* generator = "nMigen" *) module \dec_oe$168 (LDST_internal_op, oe, oe_ok, LDST_OE, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input LDST_OE; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -131245,37 +140379,39 @@ module \dec_oe$168 (LDST_internal_op, oe, oe_ok, LDST_OE, sel_in); (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [6:0] LDST_internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output oe; reg oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output oe_ok; reg oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:527" *) input [1:0] sel_in; always @* begin if (\initial ) begin end oe = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:536" *) casez (LDST_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:547" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:551" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:553" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:554" */ 2'h2: oe = LDST_OE; endcase @@ -131285,19 +140421,19 @@ module \dec_oe$168 (LDST_internal_op, oe, oe_ok, LDST_OE, sel_in); if (\initial ) begin end oe_ok = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:536" *) casez (LDST_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:547" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:551" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:553" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:554" */ 2'h2: oe_ok = 1'h1; endcase @@ -131309,7 +140445,7 @@ endmodule (* generator = "nMigen" *) module \dec_oe$173 (internal_op, oe, oe_ok, OE, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input OE; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -131386,37 +140522,39 @@ module \dec_oe$173 (internal_op, oe, oe_ok, OE, sel_in); (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:189" *) input [6:0] internal_op; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output oe; reg oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output oe_ok; reg oe_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:527" *) input [1:0] sel_in; always @* begin if (\initial ) begin end oe = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:536" *) casez (internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:547" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:551" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:553" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:554" */ 2'h2: oe = OE; endcase @@ -131426,19 +140564,19 @@ module \dec_oe$173 (internal_op, oe, oe_ok, OE, sel_in); if (\initial ) begin end oe_ok = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:536" *) casez (internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:547" */ 7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20: /* empty */; /* \nmigen.decoding = {0{1'b0}} */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:551" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:553" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:554" */ 2'h2: oe_ok = 1'h1; endcase @@ -131450,35 +140588,35 @@ endmodule (* generator = "nMigen" *) module dec_rc(rc, rc_ok, ALU_Rc, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input ALU_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output rc; reg rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output rc_ok; reg rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:490" *) input [1:0] sel_in; always @* begin if (\initial ) begin end rc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:499" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:500" */ 2'h2: rc = ALU_Rc; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:503" */ 2'h1: rc = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:506" */ 2'h0: rc = 1'h0; endcase @@ -131486,18 +140624,18 @@ module dec_rc(rc, rc_ok, ALU_Rc, sel_in); always @* begin if (\initial ) begin end rc_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:499" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:500" */ 2'h2: rc_ok = 1'h1; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:503" */ 2'h1: rc_ok = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:506" */ 2'h0: rc_ok = 1'h1; endcase @@ -131508,33 +140646,33 @@ endmodule (* generator = "nMigen" *) module \dec_rc$139 (CR_Rc, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input CR_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:490" *) input [1:0] sel_in; always @* begin if (\initial ) begin end rc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:499" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:500" */ 2'h2: rc = CR_Rc; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:503" */ 2'h1: rc = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:506" */ 2'h0: rc = 1'h0; endcase @@ -131542,18 +140680,18 @@ module \dec_rc$139 (CR_Rc, sel_in); always @* begin if (\initial ) begin end rc_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:499" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:500" */ 2'h2: rc_ok = 1'h1; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:503" */ 2'h1: rc_ok = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:506" */ 2'h0: rc_ok = 1'h1; endcase @@ -131564,33 +140702,33 @@ endmodule (* generator = "nMigen" *) module \dec_rc$142 (BRANCH_Rc, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input BRANCH_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:490" *) input [1:0] sel_in; always @* begin if (\initial ) begin end rc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:499" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:500" */ 2'h2: rc = BRANCH_Rc; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:503" */ 2'h1: rc = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:506" */ 2'h0: rc = 1'h0; endcase @@ -131598,18 +140736,18 @@ module \dec_rc$142 (BRANCH_Rc, sel_in); always @* begin if (\initial ) begin end rc_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:499" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:500" */ 2'h2: rc_ok = 1'h1; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:503" */ 2'h1: rc_ok = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:506" */ 2'h0: rc_ok = 1'h1; endcase @@ -131620,35 +140758,35 @@ endmodule (* generator = "nMigen" *) module \dec_rc$146 (rc, rc_ok, LOGICAL_Rc, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input LOGICAL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output rc; reg rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output rc_ok; reg rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:490" *) input [1:0] sel_in; always @* begin if (\initial ) begin end rc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:499" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:500" */ 2'h2: rc = LOGICAL_Rc; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:503" */ 2'h1: rc = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:506" */ 2'h0: rc = 1'h0; endcase @@ -131656,18 +140794,18 @@ module \dec_rc$146 (rc, rc_ok, LOGICAL_Rc, sel_in); always @* begin if (\initial ) begin end rc_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:499" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:500" */ 2'h2: rc_ok = 1'h1; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:503" */ 2'h1: rc_ok = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:506" */ 2'h0: rc_ok = 1'h1; endcase @@ -131678,33 +140816,33 @@ endmodule (* generator = "nMigen" *) module \dec_rc$151 (SPR_Rc, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input SPR_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:490" *) input [1:0] sel_in; always @* begin if (\initial ) begin end rc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:499" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:500" */ 2'h2: rc = SPR_Rc; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:503" */ 2'h1: rc = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:506" */ 2'h0: rc = 1'h0; endcase @@ -131712,18 +140850,18 @@ module \dec_rc$151 (SPR_Rc, sel_in); always @* begin if (\initial ) begin end rc_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:499" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:500" */ 2'h2: rc_ok = 1'h1; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:503" */ 2'h1: rc_ok = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:506" */ 2'h0: rc_ok = 1'h1; endcase @@ -131734,35 +140872,35 @@ endmodule (* generator = "nMigen" *) module \dec_rc$154 (rc, rc_ok, DIV_Rc, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input DIV_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output rc; reg rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output rc_ok; reg rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:490" *) input [1:0] sel_in; always @* begin if (\initial ) begin end rc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:499" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:500" */ 2'h2: rc = DIV_Rc; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:503" */ 2'h1: rc = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:506" */ 2'h0: rc = 1'h0; endcase @@ -131770,18 +140908,18 @@ module \dec_rc$154 (rc, rc_ok, DIV_Rc, sel_in); always @* begin if (\initial ) begin end rc_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:499" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:500" */ 2'h2: rc_ok = 1'h1; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:503" */ 2'h1: rc_ok = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:506" */ 2'h0: rc_ok = 1'h1; endcase @@ -131792,35 +140930,35 @@ endmodule (* generator = "nMigen" *) module \dec_rc$159 (rc, rc_ok, MUL_Rc, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input MUL_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output rc; reg rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output rc_ok; reg rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:490" *) input [1:0] sel_in; always @* begin if (\initial ) begin end rc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:499" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:500" */ 2'h2: rc = MUL_Rc; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:503" */ 2'h1: rc = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:506" */ 2'h0: rc = 1'h0; endcase @@ -131828,18 +140966,18 @@ module \dec_rc$159 (rc, rc_ok, MUL_Rc, sel_in); always @* begin if (\initial ) begin end rc_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:499" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:500" */ 2'h2: rc_ok = 1'h1; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:503" */ 2'h1: rc_ok = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:506" */ 2'h0: rc_ok = 1'h1; endcase @@ -131850,35 +140988,35 @@ endmodule (* generator = "nMigen" *) module \dec_rc$163 (rc, rc_ok, SHIFT_ROT_Rc, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input SHIFT_ROT_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output rc; reg rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output rc_ok; reg rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:490" *) input [1:0] sel_in; always @* begin if (\initial ) begin end rc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:499" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:500" */ 2'h2: rc = SHIFT_ROT_Rc; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:503" */ 2'h1: rc = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:506" */ 2'h0: rc = 1'h0; endcase @@ -131886,18 +141024,18 @@ module \dec_rc$163 (rc, rc_ok, SHIFT_ROT_Rc, sel_in); always @* begin if (\initial ) begin end rc_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:499" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:500" */ 2'h2: rc_ok = 1'h1; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:503" */ 2'h1: rc_ok = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:506" */ 2'h0: rc_ok = 1'h1; endcase @@ -131908,35 +141046,35 @@ endmodule (* generator = "nMigen" *) module \dec_rc$167 (rc, rc_ok, LDST_Rc, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input LDST_Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output rc; reg rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output rc_ok; reg rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:490" *) input [1:0] sel_in; always @* begin if (\initial ) begin end rc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:499" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:500" */ 2'h2: rc = LDST_Rc; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:503" */ 2'h1: rc = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:506" */ 2'h0: rc = 1'h0; endcase @@ -131944,18 +141082,18 @@ module \dec_rc$167 (rc, rc_ok, LDST_Rc, sel_in); always @* begin if (\initial ) begin end rc_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:499" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:500" */ 2'h2: rc_ok = 1'h1; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:503" */ 2'h1: rc_ok = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:506" */ 2'h0: rc_ok = 1'h1; endcase @@ -131966,35 +141104,35 @@ endmodule (* generator = "nMigen" *) module \dec_rc$172 (rc, rc_ok, Rc, sel_in); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:483" *) input Rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output rc; reg rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output rc_ok; reg rc_ok; (* enum_base_type = "RC" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "RC" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:490" *) input [1:0] sel_in; always @* begin if (\initial ) begin end rc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:499" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:500" */ 2'h2: rc = Rc; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:503" */ 2'h1: rc = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:506" */ 2'h0: rc = 1'h0; endcase @@ -132002,18 +141140,18 @@ module \dec_rc$172 (rc, rc_ok, Rc, sel_in); always @* begin if (\initial ) begin end rc_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:499" *) casez (sel_in) /* \nmigen.decoding = "RC/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:500" */ 2'h2: rc_ok = 1'h1; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:503" */ 2'h1: rc_ok = 1'h1; /* \nmigen.decoding = "NONE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:506" */ 2'h0: rc_ok = 1'h1; endcase @@ -132022,7 +141160,7 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0" *) (* generator = "nMigen" *) -module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, oper_i_alu_div0__imm_data__data, oper_i_alu_div0__imm_data__ok, oper_i_alu_div0__rc__rc, oper_i_alu_div0__rc__ok, oper_i_alu_div0__oe__oe, oper_i_alu_div0__oe__ok, oper_i_alu_div0__invert_in, oper_i_alu_div0__zero_a, oper_i_alu_div0__input_carry, oper_i_alu_div0__invert_out, oper_i_alu_div0__write_cr0, oper_i_alu_div0__output_carry, oper_i_alu_div0__is_32bit, oper_i_alu_div0__is_signed, oper_i_alu_div0__data_len, oper_i_alu_div0__insn, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, cr_a_ok, dest2_o, xer_ov_ok, dest3_o, xer_so_ok, dest4_o, coresync_clk); +module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, oper_i_alu_div0__imm_data__data, oper_i_alu_div0__imm_data__ok, oper_i_alu_div0__rc__rc, oper_i_alu_div0__rc__ok, oper_i_alu_div0__oe__oe, oper_i_alu_div0__oe__ok, oper_i_alu_div0__invert_in, oper_i_alu_div0__zero_a, oper_i_alu_div0__input_carry, oper_i_alu_div0__invert_out, oper_i_alu_div0__write_cr0, oper_i_alu_div0__output_carry, oper_i_alu_div0__is_32bit, oper_i_alu_div0__is_signed, oper_i_alu_div0__data_len, oper_i_alu_div0__insn, oper_i_alu_div0__sv_pred_sz, oper_i_alu_div0__sv_pred_dz, oper_i_alu_div0__sv_saturate, oper_i_alu_div0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, cr_a_ok, dest2_o, xer_ov_ok, dest3_o, xer_so_ok, dest4_o, coresync_clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) wire \$10 ; @@ -132160,50 +141298,59 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, wire all_rd_pulse; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) wire all_rd_rise; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [3:0] alu_div0_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] alu_div0_logical_op__SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \alu_div0_logical_op__SV_Ptype$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [3:0] alu_div0_logical_op__data_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [3:0] \alu_div0_logical_op__data_len$next ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] alu_div0_logical_op__fn_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] \alu_div0_logical_op__fn_unit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] alu_div0_logical_op__fn_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] \alu_div0_logical_op__fn_unit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] alu_div0_logical_op__imm_data__data = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] \alu_div0_logical_op__imm_data__data$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_div0_logical_op__imm_data__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_div0_logical_op__imm_data__ok$next ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [1:0] alu_div0_logical_op__input_carry = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [1:0] \alu_div0_logical_op__input_carry$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] alu_div0_logical_op__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] \alu_div0_logical_op__insn$next ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -132280,73 +141427,91 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] alu_div0_logical_op__insn_type = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] \alu_div0_logical_op__insn_type$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_div0_logical_op__invert_in = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_div0_logical_op__invert_in$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_div0_logical_op__invert_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_div0_logical_op__invert_out$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_div0_logical_op__is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_div0_logical_op__is_32bit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_div0_logical_op__is_signed = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_div0_logical_op__is_signed$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_div0_logical_op__oe__oe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_div0_logical_op__oe__oe$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_div0_logical_op__oe__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_div0_logical_op__oe__ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_div0_logical_op__output_carry = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_div0_logical_op__output_carry$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_div0_logical_op__rc__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_div0_logical_op__rc__ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_div0_logical_op__rc__rc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_div0_logical_op__rc__rc$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg alu_div0_logical_op__sv_pred_dz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \alu_div0_logical_op__sv_pred_dz$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg alu_div0_logical_op__sv_pred_sz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \alu_div0_logical_op__sv_pred_sz$next ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] alu_div0_logical_op__sv_saturate = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \alu_div0_logical_op__sv_saturate$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_div0_logical_op__write_cr0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_div0_logical_op__write_cr0$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_div0_logical_op__zero_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_div0_logical_op__zero_a$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) wire alu_div0_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire alu_div0_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] alu_div0_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire alu_div0_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) wire alu_div0_p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] alu_div0_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] alu_div0_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [1:0] alu_div0_xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire alu_div0_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire \alu_div0_xer_so$1 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" *) wire alu_done; @@ -132376,11 +141541,11 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_a_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) output cu_busy_o; @@ -132448,7 +141613,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) output dest4_o; reg dest4_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire opc_l_q_opc; @@ -132460,36 +141625,43 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, reg opc_l_s_opc = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) reg \opc_l_s_opc$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_div0__SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [3:0] oper_i_alu_div0__data_len; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] oper_i_alu_div0__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] oper_i_alu_div0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] oper_i_alu_div0__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_div0__imm_data__ok; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] oper_i_alu_div0__input_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] oper_i_alu_div0__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -132566,29 +141738,41 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] oper_i_alu_div0__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_div0__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_div0__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_div0__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_div0__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_div0__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_div0__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_div0__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_div0__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_div0__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_div0__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_div0__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_div0__sv_saturate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_div0__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_div0__zero_a; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *) reg [3:0] prev_wr_go = 4'h0; @@ -132670,9 +141854,9 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, wire \src_sel$82 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" *) wire wr_any; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_so_ok; assign \$100 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *) alu_div0_logical_op__zero_a; assign \$102 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *) alu_div0_logical_op__imm_data__ok; @@ -132799,6 +141983,14 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, alu_div0_logical_op__data_len <= \alu_div0_logical_op__data_len$next ; always @(posedge coresync_clk) alu_div0_logical_op__insn <= \alu_div0_logical_op__insn$next ; + always @(posedge coresync_clk) + alu_div0_logical_op__sv_pred_sz <= \alu_div0_logical_op__sv_pred_sz$next ; + always @(posedge coresync_clk) + alu_div0_logical_op__sv_pred_dz <= \alu_div0_logical_op__sv_pred_dz$next ; + always @(posedge coresync_clk) + alu_div0_logical_op__sv_saturate <= \alu_div0_logical_op__sv_saturate$next ; + always @(posedge coresync_clk) + alu_div0_logical_op__SV_Ptype <= \alu_div0_logical_op__SV_Ptype$next ; always @(posedge coresync_clk) req_l_r_req <= \req_l_r_req$next ; always @(posedge coresync_clk) @@ -132830,6 +142022,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, .coresync_rst(coresync_rst), .cr_a(alu_div0_cr_a), .cr_a_ok(cr_a_ok), + .logical_op__SV_Ptype(alu_div0_logical_op__SV_Ptype), .logical_op__data_len(alu_div0_logical_op__data_len), .logical_op__fn_unit(alu_div0_logical_op__fn_unit), .logical_op__imm_data__data(alu_div0_logical_op__imm_data__data), @@ -132846,6 +142039,9 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, .logical_op__output_carry(alu_div0_logical_op__output_carry), .logical_op__rc__ok(alu_div0_logical_op__rc__ok), .logical_op__rc__rc(alu_div0_logical_op__rc__rc), + .logical_op__sv_pred_dz(alu_div0_logical_op__sv_pred_dz), + .logical_op__sv_pred_sz(alu_div0_logical_op__sv_pred_sz), + .logical_op__sv_saturate(alu_div0_logical_op__sv_saturate), .logical_op__write_cr0(alu_div0_logical_op__write_cr0), .logical_op__zero_a(alu_div0_logical_op__zero_a), .n_ready_i(alu_div0_n_ready_i), @@ -132923,7 +142119,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \rok_l_s_rdok$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_s_rdok$next = 1'h0; @@ -132932,7 +142128,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \rok_l_r_rdok$next = \$64 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_r_rdok$next = 1'h1; @@ -132941,7 +142137,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \rst_l_s_rst$next = all_rd; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_s_rst$next = 1'h0; @@ -132950,7 +142146,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \rst_l_r_rst$next = rst_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_r_rst$next = 1'h1; @@ -132959,7 +142155,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \opc_l_s_opc$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_s_opc$next = 1'h0; @@ -132968,7 +142164,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \opc_l_r_opc$next = req_done; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_r_opc$next = 1'h1; @@ -132977,7 +142173,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_s_src$next = 3'h0; @@ -132986,7 +142182,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \src_l_r_src$next = reset_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_r_src$next = 3'h7; @@ -132995,7 +142191,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \req_l_s_req$next = \$66 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_s_req$next = 4'h0; @@ -133004,7 +142200,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \req_l_r_req$next = \$68 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_r_req$next = 4'hf; @@ -133030,13 +142226,17 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, \alu_div0_logical_op__is_signed$next = alu_div0_logical_op__is_signed; \alu_div0_logical_op__data_len$next = alu_div0_logical_op__data_len; \alu_div0_logical_op__insn$next = alu_div0_logical_op__insn; + \alu_div0_logical_op__sv_pred_sz$next = alu_div0_logical_op__sv_pred_sz; + \alu_div0_logical_op__sv_pred_dz$next = alu_div0_logical_op__sv_pred_dz; + \alu_div0_logical_op__sv_saturate$next = alu_div0_logical_op__sv_saturate; + \alu_div0_logical_op__SV_Ptype$next = alu_div0_logical_op__SV_Ptype; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *) casez (cu_issue_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" */ 1'h1: - { \alu_div0_logical_op__insn$next , \alu_div0_logical_op__data_len$next , \alu_div0_logical_op__is_signed$next , \alu_div0_logical_op__is_32bit$next , \alu_div0_logical_op__output_carry$next , \alu_div0_logical_op__write_cr0$next , \alu_div0_logical_op__invert_out$next , \alu_div0_logical_op__input_carry$next , \alu_div0_logical_op__zero_a$next , \alu_div0_logical_op__invert_in$next , \alu_div0_logical_op__oe__ok$next , \alu_div0_logical_op__oe__oe$next , \alu_div0_logical_op__rc__ok$next , \alu_div0_logical_op__rc__rc$next , \alu_div0_logical_op__imm_data__ok$next , \alu_div0_logical_op__imm_data__data$next , \alu_div0_logical_op__fn_unit$next , \alu_div0_logical_op__insn_type$next } = { oper_i_alu_div0__insn, oper_i_alu_div0__data_len, oper_i_alu_div0__is_signed, oper_i_alu_div0__is_32bit, oper_i_alu_div0__output_carry, oper_i_alu_div0__write_cr0, oper_i_alu_div0__invert_out, oper_i_alu_div0__input_carry, oper_i_alu_div0__zero_a, oper_i_alu_div0__invert_in, oper_i_alu_div0__oe__ok, oper_i_alu_div0__oe__oe, oper_i_alu_div0__rc__ok, oper_i_alu_div0__rc__rc, oper_i_alu_div0__imm_data__ok, oper_i_alu_div0__imm_data__data, oper_i_alu_div0__fn_unit, oper_i_alu_div0__insn_type }; + { \alu_div0_logical_op__SV_Ptype$next , \alu_div0_logical_op__sv_saturate$next , \alu_div0_logical_op__sv_pred_dz$next , \alu_div0_logical_op__sv_pred_sz$next , \alu_div0_logical_op__insn$next , \alu_div0_logical_op__data_len$next , \alu_div0_logical_op__is_signed$next , \alu_div0_logical_op__is_32bit$next , \alu_div0_logical_op__output_carry$next , \alu_div0_logical_op__write_cr0$next , \alu_div0_logical_op__invert_out$next , \alu_div0_logical_op__input_carry$next , \alu_div0_logical_op__zero_a$next , \alu_div0_logical_op__invert_in$next , \alu_div0_logical_op__oe__ok$next , \alu_div0_logical_op__oe__oe$next , \alu_div0_logical_op__rc__ok$next , \alu_div0_logical_op__rc__rc$next , \alu_div0_logical_op__imm_data__ok$next , \alu_div0_logical_op__imm_data__data$next , \alu_div0_logical_op__fn_unit$next , \alu_div0_logical_op__insn_type$next } = { oper_i_alu_div0__SV_Ptype, oper_i_alu_div0__sv_saturate, oper_i_alu_div0__sv_pred_dz, oper_i_alu_div0__sv_pred_sz, oper_i_alu_div0__insn, oper_i_alu_div0__data_len, oper_i_alu_div0__is_signed, oper_i_alu_div0__is_32bit, oper_i_alu_div0__output_carry, oper_i_alu_div0__write_cr0, oper_i_alu_div0__invert_out, oper_i_alu_div0__input_carry, oper_i_alu_div0__zero_a, oper_i_alu_div0__invert_in, oper_i_alu_div0__oe__ok, oper_i_alu_div0__oe__oe, oper_i_alu_div0__rc__ok, oper_i_alu_div0__rc__rc, oper_i_alu_div0__imm_data__ok, oper_i_alu_div0__imm_data__data, oper_i_alu_div0__fn_unit, oper_i_alu_div0__insn_type }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -133065,7 +142265,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, 1'h1: { \data_r0__o_ok$next , \data_r0__o$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r0__o_ok$next = 1'h0; @@ -133087,7 +142287,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, 1'h1: { \data_r1__cr_a_ok$next , \data_r1__cr_a$next } = 5'h00; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r1__cr_a_ok$next = 1'h0; @@ -133109,7 +142309,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, 1'h1: { \data_r2__xer_ov_ok$next , \data_r2__xer_ov$next } = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r2__xer_ov_ok$next = 1'h0; @@ -133131,7 +142331,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, 1'h1: { \data_r3__xer_so_ok$next , \data_r3__xer_so$next } = 2'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r3__xer_so_ok$next = 1'h0; @@ -133170,7 +142370,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \alui_l_r_alui$next = \$94 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alui_l_r_alui$next = 1'h1; @@ -133179,7 +142379,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \alu_l_r_alu$next = \$96 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alu_l_r_alu$next = 1'h1; @@ -133228,7 +142428,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \prev_wr_go$next = \$20 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \prev_wr_go$next = 4'h0; @@ -133372,68 +142572,86 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.dummy" *) (* generator = "nMigen" *) -module dummy(trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, ra, rb, fast1, fast2, \muxid$1 , \trap_op__insn_type$2 , \trap_op__fn_unit$3 , \trap_op__insn$4 , \trap_op__msr$5 , \trap_op__cia$6 , \trap_op__is_32bit$7 , \trap_op__traptype$8 , \trap_op__trapaddr$9 , \trap_op__ldst_exc$10 , \ra$11 , \rb$12 , \fast1$13 , \fast2$14 , muxid); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) +module dummy(trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__svstate, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, trap_op__sv_pred_sz, trap_op__sv_pred_dz, trap_op__sv_saturate, trap_op__SV_Ptype, ra, rb, fast1, fast2, fast3, \muxid$1 , \trap_op__insn_type$2 , \trap_op__fn_unit$3 , \trap_op__insn$4 , \trap_op__msr$5 , \trap_op__cia$6 , \trap_op__svstate$7 , \trap_op__is_32bit$8 , \trap_op__traptype$9 , \trap_op__trapaddr$10 , \trap_op__ldst_exc$11 , \trap_op__sv_pred_sz$12 , \trap_op__sv_pred_dz$13 , \trap_op__sv_saturate$14 , \trap_op__SV_Ptype$15 , \ra$16 , \rb$17 , \fast1$18 , \fast2$19 , \fast3$20 , muxid); + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - output [63:0] \fast1$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + output [63:0] \fast1$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] fast2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - output [63:0] \fast2$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + output [63:0] \fast2$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + input [63:0] fast3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + output [63:0] \fast3$20 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] \muxid$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - output [63:0] \ra$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + output [63:0] \ra$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - output [63:0] \rb$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + output [63:0] \rb$17 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] trap_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \trap_op__SV_Ptype$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] trap_op__cia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \trap_op__cia$6 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] trap_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] trap_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \trap_op__fn_unit$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \trap_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] trap_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \trap_op__insn$4 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -133510,7 +142728,9 @@ module dummy(trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] trap_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -133587,33 +142807,60 @@ module dummy(trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] \trap_op__insn_type$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input trap_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output \trap_op__is_32bit$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \trap_op__is_32bit$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [7:0] trap_op__ldst_exc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [7:0] \trap_op__ldst_exc$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [7:0] \trap_op__ldst_exc$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] trap_op__msr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \trap_op__msr$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input trap_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \trap_op__sv_pred_dz$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input trap_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \trap_op__sv_pred_sz$12 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] trap_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \trap_op__sv_saturate$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [31:0] trap_op__svstate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [31:0] \trap_op__svstate$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [12:0] trap_op__trapaddr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [12:0] \trap_op__trapaddr$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [12:0] \trap_op__trapaddr$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [7:0] trap_op__traptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [7:0] \trap_op__traptype$8 ; - assign \fast2$14 = fast2; - assign \fast1$13 = fast1; - assign \rb$12 = rb; - assign \ra$11 = ra; - assign { \trap_op__ldst_exc$10 , \trap_op__trapaddr$9 , \trap_op__traptype$8 , \trap_op__is_32bit$7 , \trap_op__cia$6 , \trap_op__msr$5 , \trap_op__insn$4 , \trap_op__fn_unit$3 , \trap_op__insn_type$2 } = { trap_op__ldst_exc, trap_op__trapaddr, trap_op__traptype, trap_op__is_32bit, trap_op__cia, trap_op__msr, trap_op__insn, trap_op__fn_unit, trap_op__insn_type }; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [7:0] \trap_op__traptype$9 ; + assign \fast3$20 = fast3; + assign \fast2$19 = fast2; + assign \fast1$18 = fast1; + assign \rb$17 = rb; + assign \ra$16 = ra; + assign { \trap_op__SV_Ptype$15 , \trap_op__sv_saturate$14 , \trap_op__sv_pred_dz$13 , \trap_op__sv_pred_sz$12 , \trap_op__ldst_exc$11 , \trap_op__trapaddr$10 , \trap_op__traptype$9 , \trap_op__is_32bit$8 , \trap_op__svstate$7 , \trap_op__cia$6 , \trap_op__msr$5 , \trap_op__insn$4 , \trap_op__fn_unit$3 , \trap_op__insn_type$2 } = { trap_op__SV_Ptype, trap_op__sv_saturate, trap_op__sv_pred_dz, trap_op__sv_pred_sz, trap_op__ldst_exc, trap_op__trapaddr, trap_op__traptype, trap_op__is_32bit, trap_op__svstate, trap_op__cia, trap_op__msr, trap_op__insn, trap_op__fn_unit, trap_op__insn_type }; assign \muxid$1 = muxid; endmodule @@ -133621,20 +142868,20 @@ endmodule (* generator = "nMigen" *) module fast(coresync_rst, issue__addr, issue__ren, issue__data_o, \issue__addr$1 , issue__wen, issue__data_i, src1__data_o, src1__addr, src1__ren, dest1__data_i, dest1__addr, dest1__wen, coresync_clk); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) - input [2:0] dest1__addr; + input [3:0] dest1__addr; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [63:0] dest1__data_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input dest1__wen; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) - input [2:0] issue__addr; + input [3:0] issue__addr; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) - input [2:0] \issue__addr$1 ; + input [3:0] \issue__addr$1 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [63:0] issue__data_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) @@ -133644,42 +142891,42 @@ module fast(coresync_rst, issue__addr, issue__ren, issue__data_o, \issue__addr$1 input issue__ren; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input issue__wen; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *) - wire [2:0] memory_r_addr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *) - wire [2:0] \memory_r_addr$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:211" *) + wire [3:0] memory_r_addr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:211" *) + wire [3:0] \memory_r_addr$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:211" *) wire [63:0] memory_r_data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:211" *) wire [63:0] \memory_r_data$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) - wire [2:0] memory_w_addr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) - wire [2:0] \memory_w_addr$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:219" *) + wire [3:0] memory_w_addr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:219" *) + wire [3:0] \memory_w_addr$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:219" *) wire [63:0] memory_w_data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:219" *) wire [63:0] \memory_w_data$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:219" *) wire memory_w_en; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:219" *) wire \memory_w_en$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" *) reg ren_delay = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" *) reg \ren_delay$8 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" *) reg \ren_delay$8$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" *) reg \ren_delay$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) - input [2:0] src1__addr; + input [3:0] src1__addr; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) output [63:0] src1__data_o; reg [63:0] src1__data_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input src1__ren; - reg [63:0] memory [7:0]; + reg [63:0] memory [8:0]; initial begin memory[0] = 64'h0000000000000000; memory[1] = 64'h0000000000000000; @@ -133689,9 +142936,10 @@ module fast(coresync_rst, issue__addr, issue__ren, issue__data_o, \issue__addr$1 memory[5] = 64'h0000000000000000; memory[6] = 64'h0000000000000000; memory[7] = 64'h0000000000000000; + memory[8] = 64'h0000000000000000; end - reg [2:0] _0_; - reg [2:0] _1_; + reg [3:0] _0_; + reg [3:0] _1_; always @(posedge coresync_clk) begin _0_ <= memory_r_addr; _1_ <= \memory_r_addr$3 ; @@ -133707,7 +142955,7 @@ module fast(coresync_rst, issue__addr, issue__ren, issue__data_o, \issue__addr$1 always @* begin if (\initial ) begin end \ren_delay$next = src1__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \ren_delay$next = 1'h0; @@ -133716,9 +142964,9 @@ module fast(coresync_rst, issue__addr, issue__ren, issue__data_o, \issue__addr$1 always @* begin if (\initial ) begin end src1__data_o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:246" *) casez (ren_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:246" */ 1'h1: src1__data_o = memory_r_data; endcase @@ -133726,7 +142974,7 @@ module fast(coresync_rst, issue__addr, issue__ren, issue__data_o, \issue__addr$1 always @* begin if (\initial ) begin end \ren_delay$8$next = issue__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \ren_delay$8$next = 1'h0; @@ -133735,9 +142983,9 @@ module fast(coresync_rst, issue__addr, issue__ren, issue__data_o, \issue__addr$1 always @* begin if (\initial ) begin end issue__data_o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:246" *) casez (\ren_delay$8 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:246" */ 1'h1: issue__data_o = \memory_r_data$4 ; endcase @@ -134084,23 +143332,23 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus" *) (* generator = "nMigen" *) -module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, oper_i_alu_alu0__imm_data__data, oper_i_alu_alu0__imm_data__ok, oper_i_alu_alu0__rc__rc, oper_i_alu_alu0__rc__ok, oper_i_alu_alu0__oe__oe, oper_i_alu_alu0__oe__ok, oper_i_alu_alu0__invert_in, oper_i_alu_alu0__zero_a, oper_i_alu_alu0__invert_out, oper_i_alu_alu0__write_cr0, oper_i_alu_alu0__input_carry, oper_i_alu_alu0__output_carry, oper_i_alu_alu0__is_32bit, oper_i_alu_alu0__is_signed, oper_i_alu_alu0__data_len, oper_i_alu_alu0__insn, cu_issue_i, cu_busy_o, cu_rdmaskn_i, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, oper_i_alu_cr0__insn, \cu_issue_i$1 , \cu_busy_o$2 , \cu_rdmaskn_i$3 , oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_type, oper_i_alu_branch0__fn_unit, oper_i_alu_branch0__insn, oper_i_alu_branch0__imm_data__data, oper_i_alu_branch0__imm_data__ok, oper_i_alu_branch0__lk, oper_i_alu_branch0__is_32bit, \cu_issue_i$4 , \cu_busy_o$5 , \cu_rdmaskn_i$6 , oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_unit, oper_i_alu_trap0__insn, oper_i_alu_trap0__msr, oper_i_alu_trap0__cia, oper_i_alu_trap0__is_32bit, oper_i_alu_trap0__traptype, oper_i_alu_trap0__trapaddr, oper_i_alu_trap0__ldst_exc, \cu_issue_i$7 , \cu_busy_o$8 , \cu_rdmaskn_i$9 , oper_i_alu_logical0__insn_type, oper_i_alu_logical0__fn_unit, oper_i_alu_logical0__imm_data__data, oper_i_alu_logical0__imm_data__ok, oper_i_alu_logical0__rc__rc, oper_i_alu_logical0__rc__ok, oper_i_alu_logical0__oe__oe, oper_i_alu_logical0__oe__ok, oper_i_alu_logical0__invert_in, oper_i_alu_logical0__zero_a, oper_i_alu_logical0__input_carry, oper_i_alu_logical0__invert_out, oper_i_alu_logical0__write_cr0, oper_i_alu_logical0__output_carry, oper_i_alu_logical0__is_32bit, oper_i_alu_logical0__is_signed, oper_i_alu_logical0__data_len, oper_i_alu_logical0__insn, \cu_issue_i$10 , \cu_busy_o$11 , \cu_rdmaskn_i$12 , oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, oper_i_alu_spr0__insn, oper_i_alu_spr0__is_32bit, \cu_issue_i$13 , \cu_busy_o$14 , \cu_rdmaskn_i$15 , oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, oper_i_alu_div0__imm_data__data, oper_i_alu_div0__imm_data__ok, oper_i_alu_div0__rc__rc, oper_i_alu_div0__rc__ok, oper_i_alu_div0__oe__oe, oper_i_alu_div0__oe__ok, oper_i_alu_div0__invert_in, oper_i_alu_div0__zero_a, oper_i_alu_div0__input_carry, oper_i_alu_div0__invert_out, oper_i_alu_div0__write_cr0, oper_i_alu_div0__output_carry, oper_i_alu_div0__is_32bit, oper_i_alu_div0__is_signed, oper_i_alu_div0__data_len, oper_i_alu_div0__insn, \cu_issue_i$16 , \cu_busy_o$17 , \cu_rdmaskn_i$18 , oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, oper_i_alu_mul0__imm_data__data, oper_i_alu_mul0__imm_data__ok, oper_i_alu_mul0__rc__rc, oper_i_alu_mul0__rc__ok, oper_i_alu_mul0__oe__oe, oper_i_alu_mul0__oe__ok, oper_i_alu_mul0__write_cr0, oper_i_alu_mul0__is_32bit, oper_i_alu_mul0__is_signed, oper_i_alu_mul0__insn, \cu_issue_i$19 , \cu_busy_o$20 , \cu_rdmaskn_i$21 , oper_i_alu_shift_rot0__insn_type, oper_i_alu_shift_rot0__fn_unit, oper_i_alu_shift_rot0__imm_data__data, oper_i_alu_shift_rot0__imm_data__ok, oper_i_alu_shift_rot0__rc__rc, oper_i_alu_shift_rot0__rc__ok, oper_i_alu_shift_rot0__oe__oe, oper_i_alu_shift_rot0__oe__ok, oper_i_alu_shift_rot0__write_cr0, oper_i_alu_shift_rot0__invert_in, oper_i_alu_shift_rot0__input_carry, oper_i_alu_shift_rot0__output_carry, oper_i_alu_shift_rot0__input_cr, oper_i_alu_shift_rot0__output_cr, oper_i_alu_shift_rot0__is_32bit, oper_i_alu_shift_rot0__is_signed, oper_i_alu_shift_rot0__insn, \cu_issue_i$22 , \cu_busy_o$23 , \cu_rdmaskn_i$24 , oper_i_ldst_ldst0__insn_type, oper_i_ldst_ldst0__fn_unit, oper_i_ldst_ldst0__imm_data__data, oper_i_ldst_ldst0__imm_data__ok, oper_i_ldst_ldst0__zero_a, oper_i_ldst_ldst0__rc__rc, oper_i_ldst_ldst0__rc__ok, oper_i_ldst_ldst0__oe__oe, oper_i_ldst_ldst0__oe__ok, oper_i_ldst_ldst0__is_32bit, oper_i_ldst_ldst0__is_signed, oper_i_ldst_ldst0__data_len, oper_i_ldst_ldst0__byte_reverse, oper_i_ldst_ldst0__sign_extend, oper_i_ldst_ldst0__ldst_mode, oper_i_ldst_ldst0__insn, \cu_issue_i$25 , \cu_busy_o$26 , \cu_rdmaskn_i$27 , cu_rd__rel_o, cu_rd__go_i, src2_i, \cu_rd__rel_o$28 , \cu_rd__go_i$29 , \src2_i$30 , \cu_rd__rel_o$31 , \cu_rd__go_i$32 , \src2_i$33 , \cu_rd__rel_o$34 , \cu_rd__go_i$35 , \src2_i$36 , \cu_rd__rel_o$37 , \cu_rd__go_i$38 , \src2_i$39 , \cu_rd__rel_o$40 , \cu_rd__go_i$41 , \src2_i$42 , \cu_rd__rel_o$43 , \cu_rd__go_i$44 , \src2_i$45 , \cu_rd__rel_o$46 , \cu_rd__go_i$47 , \src2_i$48 , src3_i, \src3_i$49 , src1_i, \src1_i$50 , \src1_i$51 , \src1_i$52 , \cu_rd__rel_o$53 , \cu_rd__go_i$54 , \src1_i$55 , \src1_i$56 , \src1_i$57 , \src1_i$58 , \src1_i$59 , \src3_i$60 , \src3_i$61 , src4_i, \src3_i$62 , \src3_i$63 , \src4_i$64 , \src4_i$65 , src6_i, src5_i, \src5_i$66 , \src3_i$67 , \src4_i$68 , \cu_rd__rel_o$69 , \cu_rd__go_i$70 , \src3_i$71 , \src5_i$72 , \src6_i$73 , \src1_i$74 , \src3_i$75 , \src3_i$76 , \src2_i$77 , \src4_i$78 , \src2_i$79 , o_ok, cu_wr__rel_o, cu_wr__go_i, \o_ok$80 , \cu_wr__rel_o$81 , \cu_wr__go_i$82 , \o_ok$83 , \cu_wr__rel_o$84 , \cu_wr__go_i$85 , \o_ok$86 , \cu_wr__rel_o$87 , \cu_wr__go_i$88 , \o_ok$89 , \cu_wr__rel_o$90 , \cu_wr__go_i$91 , \o_ok$92 , \cu_wr__rel_o$93 , \cu_wr__go_i$94 , \o_ok$95 , \cu_wr__rel_o$96 , \cu_wr__go_i$97 , \o_ok$98 , \cu_wr__rel_o$99 , \cu_wr__go_i$100 , \cu_wr__rel_o$101 , \cu_wr__go_i$102 , dest1_o, \dest1_o$103 , \dest1_o$104 , \dest1_o$105 , \dest1_o$106 , \dest1_o$107 , \dest1_o$108 , \dest1_o$109 , o, ea, full_cr_ok, dest2_o, cr_a_ok, \cr_a_ok$110 , \cr_a_ok$111 , \cr_a_ok$112 , \cr_a_ok$113 , \cr_a_ok$114 , \dest2_o$115 , dest3_o, \dest2_o$116 , \dest2_o$117 , \dest2_o$118 , \dest2_o$119 , xer_ca_ok, \xer_ca_ok$120 , \xer_ca_ok$121 , \dest3_o$122 , dest6_o, \dest3_o$123 , xer_ov_ok, \xer_ov_ok$124 , \xer_ov_ok$125 , \xer_ov_ok$126 , dest4_o, dest5_o, \dest3_o$127 , \dest3_o$128 , xer_so_ok, \xer_so_ok$129 , \xer_so_ok$130 , \xer_so_ok$131 , \dest5_o$132 , \dest4_o$133 , \dest4_o$134 , \dest4_o$135 , fast1_ok, \cu_wr__rel_o$136 , \cu_wr__go_i$137 , \fast1_ok$138 , \fast1_ok$139 , fast2_ok, \fast2_ok$140 , \dest1_o$141 , \dest2_o$142 , \dest3_o$143 , \dest2_o$144 , \dest3_o$145 , nia_ok, \nia_ok$146 , \dest3_o$147 , \dest4_o$148 , msr_ok, \dest5_o$149 , spr1_ok, \dest2_o$150 , ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, \ldst_port0_exc_$signal , \ldst_port0_exc_$signal$151 , \ldst_port0_exc_$signal$152 , \ldst_port0_exc_$signal$153 , \ldst_port0_exc_$signal$154 , \ldst_port0_exc_$signal$155 , \ldst_port0_exc_$signal$156 , \ldst_port0_exc_$signal$157 , ldst_port0_addr_ok_o, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) +module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, \exc_o_$signal , oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, oper_i_alu_alu0__imm_data__data, oper_i_alu_alu0__imm_data__ok, oper_i_alu_alu0__rc__rc, oper_i_alu_alu0__rc__ok, oper_i_alu_alu0__oe__oe, oper_i_alu_alu0__oe__ok, oper_i_alu_alu0__invert_in, oper_i_alu_alu0__zero_a, oper_i_alu_alu0__invert_out, oper_i_alu_alu0__write_cr0, oper_i_alu_alu0__input_carry, oper_i_alu_alu0__output_carry, oper_i_alu_alu0__is_32bit, oper_i_alu_alu0__is_signed, oper_i_alu_alu0__data_len, oper_i_alu_alu0__insn, oper_i_alu_alu0__sv_pred_sz, oper_i_alu_alu0__sv_pred_dz, oper_i_alu_alu0__sv_saturate, oper_i_alu_alu0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, oper_i_alu_cr0__insn, oper_i_alu_cr0__sv_pred_sz, oper_i_alu_cr0__sv_pred_dz, oper_i_alu_cr0__sv_saturate, oper_i_alu_cr0__SV_Ptype, \cu_issue_i$1 , \cu_busy_o$2 , \cu_rdmaskn_i$3 , oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_type, oper_i_alu_branch0__fn_unit, oper_i_alu_branch0__insn, oper_i_alu_branch0__imm_data__data, oper_i_alu_branch0__imm_data__ok, oper_i_alu_branch0__lk, oper_i_alu_branch0__is_32bit, oper_i_alu_branch0__sv_pred_sz, oper_i_alu_branch0__sv_pred_dz, oper_i_alu_branch0__sv_saturate, oper_i_alu_branch0__SV_Ptype, \cu_issue_i$4 , \cu_busy_o$5 , \cu_rdmaskn_i$6 , oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_unit, oper_i_alu_trap0__insn, oper_i_alu_trap0__msr, oper_i_alu_trap0__cia, oper_i_alu_trap0__svstate, oper_i_alu_trap0__is_32bit, oper_i_alu_trap0__traptype, oper_i_alu_trap0__trapaddr, oper_i_alu_trap0__ldst_exc, oper_i_alu_trap0__sv_pred_sz, oper_i_alu_trap0__sv_pred_dz, oper_i_alu_trap0__sv_saturate, oper_i_alu_trap0__SV_Ptype, \cu_issue_i$7 , \cu_busy_o$8 , \cu_rdmaskn_i$9 , oper_i_alu_logical0__insn_type, oper_i_alu_logical0__fn_unit, oper_i_alu_logical0__imm_data__data, oper_i_alu_logical0__imm_data__ok, oper_i_alu_logical0__rc__rc, oper_i_alu_logical0__rc__ok, oper_i_alu_logical0__oe__oe, oper_i_alu_logical0__oe__ok, oper_i_alu_logical0__invert_in, oper_i_alu_logical0__zero_a, oper_i_alu_logical0__input_carry, oper_i_alu_logical0__invert_out, oper_i_alu_logical0__write_cr0, oper_i_alu_logical0__output_carry, oper_i_alu_logical0__is_32bit, oper_i_alu_logical0__is_signed, oper_i_alu_logical0__data_len, oper_i_alu_logical0__insn, oper_i_alu_logical0__sv_pred_sz, oper_i_alu_logical0__sv_pred_dz, oper_i_alu_logical0__sv_saturate, oper_i_alu_logical0__SV_Ptype, \cu_issue_i$10 , \cu_busy_o$11 , \cu_rdmaskn_i$12 , oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, oper_i_alu_spr0__insn, oper_i_alu_spr0__is_32bit, oper_i_alu_spr0__sv_pred_sz, oper_i_alu_spr0__sv_pred_dz, oper_i_alu_spr0__sv_saturate, oper_i_alu_spr0__SV_Ptype, \cu_issue_i$13 , \cu_busy_o$14 , \cu_rdmaskn_i$15 , oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, oper_i_alu_div0__imm_data__data, oper_i_alu_div0__imm_data__ok, oper_i_alu_div0__rc__rc, oper_i_alu_div0__rc__ok, oper_i_alu_div0__oe__oe, oper_i_alu_div0__oe__ok, oper_i_alu_div0__invert_in, oper_i_alu_div0__zero_a, oper_i_alu_div0__input_carry, oper_i_alu_div0__invert_out, oper_i_alu_div0__write_cr0, oper_i_alu_div0__output_carry, oper_i_alu_div0__is_32bit, oper_i_alu_div0__is_signed, oper_i_alu_div0__data_len, oper_i_alu_div0__insn, oper_i_alu_div0__sv_pred_sz, oper_i_alu_div0__sv_pred_dz, oper_i_alu_div0__sv_saturate, oper_i_alu_div0__SV_Ptype, \cu_issue_i$16 , \cu_busy_o$17 , \cu_rdmaskn_i$18 , oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, oper_i_alu_mul0__imm_data__data, oper_i_alu_mul0__imm_data__ok, oper_i_alu_mul0__rc__rc, oper_i_alu_mul0__rc__ok, oper_i_alu_mul0__oe__oe, oper_i_alu_mul0__oe__ok, oper_i_alu_mul0__write_cr0, oper_i_alu_mul0__is_32bit, oper_i_alu_mul0__is_signed, oper_i_alu_mul0__insn, oper_i_alu_mul0__sv_pred_sz, oper_i_alu_mul0__sv_pred_dz, oper_i_alu_mul0__sv_saturate, oper_i_alu_mul0__SV_Ptype, \cu_issue_i$19 , \cu_busy_o$20 , \cu_rdmaskn_i$21 , oper_i_alu_shift_rot0__insn_type, oper_i_alu_shift_rot0__fn_unit, oper_i_alu_shift_rot0__imm_data__data, oper_i_alu_shift_rot0__imm_data__ok, oper_i_alu_shift_rot0__rc__rc, oper_i_alu_shift_rot0__rc__ok, oper_i_alu_shift_rot0__oe__oe, oper_i_alu_shift_rot0__oe__ok, oper_i_alu_shift_rot0__write_cr0, oper_i_alu_shift_rot0__invert_in, oper_i_alu_shift_rot0__input_carry, oper_i_alu_shift_rot0__output_carry, oper_i_alu_shift_rot0__input_cr, oper_i_alu_shift_rot0__output_cr, oper_i_alu_shift_rot0__is_32bit, oper_i_alu_shift_rot0__is_signed, oper_i_alu_shift_rot0__insn, oper_i_alu_shift_rot0__sv_pred_sz, oper_i_alu_shift_rot0__sv_pred_dz, oper_i_alu_shift_rot0__sv_saturate, oper_i_alu_shift_rot0__SV_Ptype, \cu_issue_i$22 , \cu_busy_o$23 , \cu_rdmaskn_i$24 , oper_i_ldst_ldst0__insn_type, oper_i_ldst_ldst0__fn_unit, oper_i_ldst_ldst0__imm_data__data, oper_i_ldst_ldst0__imm_data__ok, oper_i_ldst_ldst0__zero_a, oper_i_ldst_ldst0__rc__rc, oper_i_ldst_ldst0__rc__ok, oper_i_ldst_ldst0__oe__oe, oper_i_ldst_ldst0__oe__ok, oper_i_ldst_ldst0__msr, oper_i_ldst_ldst0__is_32bit, oper_i_ldst_ldst0__is_signed, oper_i_ldst_ldst0__data_len, oper_i_ldst_ldst0__byte_reverse, oper_i_ldst_ldst0__sign_extend, oper_i_ldst_ldst0__ldst_mode, oper_i_ldst_ldst0__insn, oper_i_ldst_ldst0__sv_pred_sz, oper_i_ldst_ldst0__sv_pred_dz, oper_i_ldst_ldst0__sv_saturate, oper_i_ldst_ldst0__SV_Ptype, \cu_issue_i$25 , \cu_busy_o$26 , \cu_rdmaskn_i$27 , cu_rd__rel_o, cu_rd__go_i, src2_i, \cu_rd__rel_o$28 , \cu_rd__go_i$29 , \src2_i$30 , \cu_rd__rel_o$31 , \cu_rd__go_i$32 , \src2_i$33 , \cu_rd__rel_o$34 , \cu_rd__go_i$35 , \src2_i$36 , \cu_rd__rel_o$37 , \cu_rd__go_i$38 , \src2_i$39 , \cu_rd__rel_o$40 , \cu_rd__go_i$41 , \src2_i$42 , \cu_rd__rel_o$43 , \cu_rd__go_i$44 , \src2_i$45 , \cu_rd__rel_o$46 , \cu_rd__go_i$47 , \src2_i$48 , src3_i, \src3_i$49 , src1_i, \src1_i$50 , \src1_i$51 , \src1_i$52 , \cu_rd__rel_o$53 , \cu_rd__go_i$54 , \src1_i$55 , \src1_i$56 , \src1_i$57 , \src1_i$58 , \src1_i$59 , \src3_i$60 , \src3_i$61 , src4_i, \src3_i$62 , \src3_i$63 , \src4_i$64 , \src4_i$65 , src6_i, src5_i, \src5_i$66 , \src3_i$67 , \src4_i$68 , \cu_rd__rel_o$69 , \cu_rd__go_i$70 , \src3_i$71 , \src5_i$72 , \src6_i$73 , \src1_i$74 , \src3_i$75 , \src3_i$76 , \src2_i$77 , \src4_i$78 , \src5_i$79 , \src2_i$80 , o_ok, cu_wr__rel_o, cu_wr__go_i, \o_ok$81 , \cu_wr__rel_o$82 , \cu_wr__go_i$83 , \o_ok$84 , \cu_wr__rel_o$85 , \cu_wr__go_i$86 , \o_ok$87 , \cu_wr__rel_o$88 , \cu_wr__go_i$89 , \o_ok$90 , \cu_wr__rel_o$91 , \cu_wr__go_i$92 , \o_ok$93 , \cu_wr__rel_o$94 , \cu_wr__go_i$95 , \o_ok$96 , \cu_wr__rel_o$97 , \cu_wr__go_i$98 , \o_ok$99 , \cu_wr__rel_o$100 , \cu_wr__go_i$101 , \cu_wr__rel_o$102 , \cu_wr__go_i$103 , dest1_o, \dest1_o$104 , \dest1_o$105 , \dest1_o$106 , \dest1_o$107 , \dest1_o$108 , \dest1_o$109 , \dest1_o$110 , o, ea, full_cr_ok, dest2_o, cr_a_ok, \cr_a_ok$111 , \cr_a_ok$112 , \cr_a_ok$113 , \cr_a_ok$114 , \cr_a_ok$115 , \dest2_o$116 , dest3_o, \dest2_o$117 , \dest2_o$118 , \dest2_o$119 , \dest2_o$120 , xer_ca_ok, \xer_ca_ok$121 , \xer_ca_ok$122 , \dest3_o$123 , dest6_o, \dest3_o$124 , xer_ov_ok, \xer_ov_ok$125 , \xer_ov_ok$126 , \xer_ov_ok$127 , dest4_o, dest5_o, \dest3_o$128 , \dest3_o$129 , xer_so_ok, \xer_so_ok$130 , \xer_so_ok$131 , \xer_so_ok$132 , \dest5_o$133 , \dest4_o$134 , \dest4_o$135 , \dest4_o$136 , fast1_ok, \cu_wr__rel_o$137 , \cu_wr__go_i$138 , \fast1_ok$139 , \fast1_ok$140 , fast2_ok, \fast2_ok$141 , fast3_ok, \dest1_o$142 , \dest2_o$143 , \dest3_o$144 , \dest2_o$145 , \dest3_o$146 , \dest4_o$147 , nia_ok, \nia_ok$148 , \dest3_o$149 , \dest5_o$150 , msr_ok, \dest6_o$151 , svstate_ok, dest7_o, spr1_ok, \dest2_o$152 , ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, \ldst_port0_exc_$signal , \ldst_port0_exc_$signal$153 , \ldst_port0_exc_$signal$154 , \ldst_port0_exc_$signal$155 , \ldst_port0_exc_$signal$156 , \ldst_port0_exc_$signal$157 , \ldst_port0_exc_$signal$158 , \ldst_port0_exc_$signal$159 , ldst_port0_addr_ok_o, ldst_port0_msr_pr, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, coresync_clk); + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \cr_a_ok$110 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output \cr_a_ok$111 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output \cr_a_ok$112 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output \cr_a_ok$113 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output \cr_a_ok$114 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \cr_a_ok$115 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) input cu_ad__go_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) @@ -134150,7 +143398,7 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) input [5:0] \cu_rd__go_i$29 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - input [3:0] \cu_rd__go_i$32 ; + input [4:0] \cu_rd__go_i$32 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) input [2:0] \cu_rd__go_i$35 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) @@ -134170,7 +143418,7 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) output [5:0] \cu_rd__rel_o$28 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - output [3:0] \cu_rd__rel_o$31 ; + output [4:0] \cu_rd__rel_o$31 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) output [2:0] \cu_rd__rel_o$34 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) @@ -134204,7 +143452,7 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) input [2:0] \cu_rdmaskn_i$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) - input [3:0] \cu_rdmaskn_i$9 ; + input [4:0] \cu_rdmaskn_i$9 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) input cu_st__go_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) @@ -134212,48 +143460,46 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) input [4:0] cu_wr__go_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - input [2:0] \cu_wr__go_i$100 ; + input [2:0] \cu_wr__go_i$101 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - input [1:0] \cu_wr__go_i$102 ; + input [1:0] \cu_wr__go_i$103 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - input [2:0] \cu_wr__go_i$137 ; + input [2:0] \cu_wr__go_i$138 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - input [2:0] \cu_wr__go_i$82 ; + input [2:0] \cu_wr__go_i$83 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - input [4:0] \cu_wr__go_i$85 ; + input [6:0] \cu_wr__go_i$86 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - input [1:0] \cu_wr__go_i$88 ; + input [1:0] \cu_wr__go_i$89 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - input [5:0] \cu_wr__go_i$91 ; + input [5:0] \cu_wr__go_i$92 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - input [3:0] \cu_wr__go_i$94 ; + input [3:0] \cu_wr__go_i$95 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - input [3:0] \cu_wr__go_i$97 ; + input [3:0] \cu_wr__go_i$98 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) output [4:0] cu_wr__rel_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - output [1:0] \cu_wr__rel_o$101 ; + output [2:0] \cu_wr__rel_o$100 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - output [2:0] \cu_wr__rel_o$136 ; + output [1:0] \cu_wr__rel_o$102 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - output [2:0] \cu_wr__rel_o$81 ; + output [2:0] \cu_wr__rel_o$137 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - output [4:0] \cu_wr__rel_o$84 ; + output [2:0] \cu_wr__rel_o$82 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - output [1:0] \cu_wr__rel_o$87 ; + output [6:0] \cu_wr__rel_o$85 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - output [5:0] \cu_wr__rel_o$90 ; + output [1:0] \cu_wr__rel_o$88 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - output [3:0] \cu_wr__rel_o$93 ; + output [5:0] \cu_wr__rel_o$91 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - output [3:0] \cu_wr__rel_o$96 ; + output [3:0] \cu_wr__rel_o$94 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - output [2:0] \cu_wr__rel_o$99 ; + output [3:0] \cu_wr__rel_o$97 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) output [63:0] dest1_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - output [63:0] \dest1_o$103 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) output [63:0] \dest1_o$104 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) output [63:0] \dest1_o$105 ; @@ -134266,11 +143512,11 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) output [63:0] \dest1_o$109 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - output [63:0] \dest1_o$141 ; + output [63:0] \dest1_o$110 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - output [31:0] dest2_o; + output [63:0] \dest1_o$142 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - output [3:0] \dest2_o$115 ; + output [31:0] dest2_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) output [3:0] \dest2_o$116 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) @@ -134280,151 +143526,170 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) output [3:0] \dest2_o$119 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - output [63:0] \dest2_o$142 ; + output [3:0] \dest2_o$120 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - output [63:0] \dest2_o$144 ; + output [63:0] \dest2_o$143 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - output [63:0] \dest2_o$150 ; + output [63:0] \dest2_o$145 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - output [3:0] dest3_o; + output [63:0] \dest2_o$152 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - output [1:0] \dest3_o$122 ; + output [3:0] dest3_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) output [1:0] \dest3_o$123 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - output [1:0] \dest3_o$127 ; + output [1:0] \dest3_o$124 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) output [1:0] \dest3_o$128 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - output [63:0] \dest3_o$143 ; + output [1:0] \dest3_o$129 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - output [63:0] \dest3_o$145 ; + output [63:0] \dest3_o$144 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - output [63:0] \dest3_o$147 ; + output [63:0] \dest3_o$146 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - output [1:0] dest4_o; + output [63:0] \dest3_o$149 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - output \dest4_o$133 ; + output [1:0] dest4_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) output \dest4_o$134 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) output \dest4_o$135 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - output [63:0] \dest4_o$148 ; + output \dest4_o$136 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] \dest4_o$147 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) output [1:0] dest5_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - output \dest5_o$132 ; + output \dest5_o$133 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) - output [63:0] \dest5_o$149 ; + output [63:0] \dest5_o$150 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) output [1:0] dest6_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] \dest6_o$151 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [31:0] dest7_o; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] ea; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) + output \exc_o_$signal ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output fast1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \fast1_ok$138 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output \fast1_ok$139 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \fast1_ok$140 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output fast2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \fast2_ok$140 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \fast2_ok$141 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output fast3_ok; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output full_cr_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [95:0] ldst_port0_addr_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output ldst_port0_addr_i_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" *) input ldst_port0_addr_ok_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" *) input ldst_port0_busy_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103" *) output [3:0] ldst_port0_data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) input \ldst_port0_exc_$signal ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) - input \ldst_port0_exc_$signal$151 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) - input \ldst_port0_exc_$signal$152 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) input \ldst_port0_exc_$signal$153 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) input \ldst_port0_exc_$signal$154 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) input \ldst_port0_exc_$signal$155 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) input \ldst_port0_exc_$signal$156 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) input \ldst_port0_exc_$signal$157 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" *) - output ldst_port0_is_ld_i; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) + input \ldst_port0_exc_$signal$158 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) + input \ldst_port0_exc_$signal$159 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *) + output ldst_port0_is_ld_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:100" *) output ldst_port0_is_st_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [63:0] ldst_port0_ld_data_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input ldst_port0_ld_data_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:120" *) + output ldst_port0_msr_pr; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] ldst_port0_st_data_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output ldst_port0_st_data_i_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output msr_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output nia_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \nia_ok$146 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \nia_ok$148 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \o_ok$80 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \o_ok$83 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \o_ok$86 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \o_ok$89 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \o_ok$92 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \o_ok$95 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \o_ok$98 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \o_ok$81 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \o_ok$84 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \o_ok$87 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \o_ok$90 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \o_ok$93 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \o_ok$96 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \o_ok$99 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_alu0__SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [3:0] oper_i_alu_alu0__data_len; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] oper_i_alu_alu0__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] oper_i_alu_alu0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] oper_i_alu_alu0__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_alu0__imm_data__ok; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] oper_i_alu_alu0__input_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] oper_i_alu_alu0__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -134501,54 +143766,73 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] oper_i_alu_alu0__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_alu0__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_alu0__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_alu0__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_alu0__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_alu0__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_alu0__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_alu0__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_alu0__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_alu0__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_alu0__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_alu0__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_alu0__sv_saturate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_alu0__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_alu0__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_branch0__SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] oper_i_alu_branch0__cia; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] oper_i_alu_branch0__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] oper_i_alu_branch0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] oper_i_alu_branch0__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_branch0__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] oper_i_alu_branch0__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -134625,30 +143909,49 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] oper_i_alu_branch0__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_branch0__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_branch0__lk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_branch0__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_branch0__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_branch0__sv_saturate; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_cr0__SV_Ptype; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] oper_i_alu_cr0__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] oper_i_alu_cr0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] oper_i_alu_cr0__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -134725,38 +144028,57 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] oper_i_alu_cr0__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_cr0__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_cr0__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_cr0__sv_saturate; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_div0__SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [3:0] oper_i_alu_div0__data_len; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] oper_i_alu_div0__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] oper_i_alu_div0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] oper_i_alu_div0__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_div0__imm_data__ok; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] oper_i_alu_div0__input_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] oper_i_alu_div0__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -134833,60 +144155,79 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] oper_i_alu_div0__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_div0__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_div0__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_div0__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_div0__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_div0__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_div0__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_div0__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_div0__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_div0__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_div0__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_div0__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_div0__sv_saturate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_div0__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_div0__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_logical0__SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [3:0] oper_i_alu_logical0__data_len; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] oper_i_alu_logical0__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] oper_i_alu_logical0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] oper_i_alu_logical0__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_logical0__imm_data__ok; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] oper_i_alu_logical0__input_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] oper_i_alu_logical0__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -134963,52 +144304,71 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] oper_i_alu_logical0__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_logical0__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_logical0__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_logical0__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_logical0__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_logical0__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_logical0__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_logical0__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_logical0__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_logical0__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_logical0__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_logical0__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_logical0__sv_saturate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_logical0__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_logical0__zero_a; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_mul0__SV_Ptype; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] oper_i_alu_mul0__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] oper_i_alu_mul0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] oper_i_alu_mul0__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_mul0__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] oper_i_alu_mul0__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -135085,52 +144445,71 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] oper_i_alu_mul0__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_mul0__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_mul0__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_mul0__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_mul0__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_mul0__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_mul0__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_mul0__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_mul0__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_mul0__sv_saturate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_mul0__write_cr0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_shift_rot0__SV_Ptype; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] oper_i_alu_shift_rot0__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] oper_i_alu_shift_rot0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] oper_i_alu_shift_rot0__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_shift_rot0__imm_data__ok; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] oper_i_alu_shift_rot0__input_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_shift_rot0__input_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] oper_i_alu_shift_rot0__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -135207,46 +144586,65 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] oper_i_alu_shift_rot0__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_shift_rot0__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_shift_rot0__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_shift_rot0__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_shift_rot0__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_shift_rot0__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_shift_rot0__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_shift_rot0__output_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_shift_rot0__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_shift_rot0__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_shift_rot0__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_shift_rot0__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_shift_rot0__sv_saturate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_shift_rot0__write_cr0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_spr0__SV_Ptype; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] oper_i_alu_spr0__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] oper_i_alu_spr0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] oper_i_alu_spr0__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -135323,30 +144721,49 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] oper_i_alu_spr0__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_spr0__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_spr0__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_spr0__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_spr0__sv_saturate; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_trap0__SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] oper_i_alu_trap0__cia; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] oper_i_alu_trap0__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] oper_i_alu_trap0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] oper_i_alu_trap0__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -135423,44 +144840,65 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] oper_i_alu_trap0__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_trap0__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [7:0] oper_i_alu_trap0__ldst_exc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] oper_i_alu_trap0__msr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_trap0__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_trap0__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_trap0__sv_saturate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [31:0] oper_i_alu_trap0__svstate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [12:0] oper_i_alu_trap0__trapaddr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [7:0] oper_i_alu_trap0__traptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_ldst_ldst0__SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_ldst_ldst0__byte_reverse; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [3:0] oper_i_ldst_ldst0__data_len; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] oper_i_ldst_ldst0__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] oper_i_ldst_ldst0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] oper_i_ldst_ldst0__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_ldst_ldst0__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] oper_i_ldst_ldst0__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -135537,32 +144975,46 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] oper_i_ldst_ldst0__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_ldst_ldst0__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_ldst_ldst0__is_signed; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] oper_i_ldst_ldst0__ldst_mode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [63:0] oper_i_ldst_ldst0__msr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_ldst_ldst0__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_ldst_ldst0__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_ldst_ldst0__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_ldst_ldst0__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_ldst_ldst0__sign_extend; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_ldst_ldst0__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_ldst_ldst0__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_ldst_ldst0__sv_saturate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_ldst_ldst0__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output spr1_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) input [63:0] src1_i; @@ -135603,7 +145055,7 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) input [63:0] \src2_i$77 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) - input [63:0] \src2_i$79 ; + input [63:0] \src2_i$80 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) input [63:0] src3_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) @@ -135641,31 +145093,35 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) input [3:0] \src5_i$72 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] \src5_i$79 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) input [1:0] src6_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) input [3:0] \src6_i$73 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output svstate_ok; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \xer_ca_ok$120 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output \xer_ca_ok$121 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \xer_ca_ok$122 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \xer_ov_ok$124 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output \xer_ov_ok$125 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output \xer_ov_ok$126 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \xer_ov_ok$127 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_so_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \xer_so_ok$129 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output \xer_so_ok$130 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output \xer_so_ok$131 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \xer_so_ok$132 ; alu0 alu0 ( .coresync_clk(coresync_clk), .coresync_rst(coresync_rst), @@ -135678,11 +145134,12 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o .cu_wr__go_i(cu_wr__go_i), .cu_wr__rel_o(cu_wr__rel_o), .dest1_o(dest1_o), - .dest2_o(\dest2_o$115 ), - .dest3_o(\dest3_o$122 ), + .dest2_o(\dest2_o$116 ), + .dest3_o(\dest3_o$123 ), .dest4_o(dest4_o), - .dest5_o(\dest5_o$132 ), + .dest5_o(\dest5_o$133 ), .o_ok(o_ok), + .oper_i_alu_alu0__SV_Ptype(oper_i_alu_alu0__SV_Ptype), .oper_i_alu_alu0__data_len(oper_i_alu_alu0__data_len), .oper_i_alu_alu0__fn_unit(oper_i_alu_alu0__fn_unit), .oper_i_alu_alu0__imm_data__data(oper_i_alu_alu0__imm_data__data), @@ -135699,6 +145156,9 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o .oper_i_alu_alu0__output_carry(oper_i_alu_alu0__output_carry), .oper_i_alu_alu0__rc__ok(oper_i_alu_alu0__rc__ok), .oper_i_alu_alu0__rc__rc(oper_i_alu_alu0__rc__rc), + .oper_i_alu_alu0__sv_pred_dz(oper_i_alu_alu0__sv_pred_dz), + .oper_i_alu_alu0__sv_pred_sz(oper_i_alu_alu0__sv_pred_sz), + .oper_i_alu_alu0__sv_saturate(oper_i_alu_alu0__sv_saturate), .oper_i_alu_alu0__write_cr0(oper_i_alu_alu0__write_cr0), .oper_i_alu_alu0__zero_a(oper_i_alu_alu0__zero_a), .src1_i(src1_i), @@ -135717,14 +145177,15 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o .cu_rd__go_i(\cu_rd__go_i$70 ), .cu_rd__rel_o(\cu_rd__rel_o$69 ), .cu_rdmaskn_i(\cu_rdmaskn_i$6 ), - .cu_wr__go_i(\cu_wr__go_i$137 ), - .cu_wr__rel_o(\cu_wr__rel_o$136 ), - .dest1_o(\dest1_o$141 ), - .dest2_o(\dest2_o$144 ), - .dest3_o(\dest3_o$147 ), + .cu_wr__go_i(\cu_wr__go_i$138 ), + .cu_wr__rel_o(\cu_wr__rel_o$137 ), + .dest1_o(\dest1_o$142 ), + .dest2_o(\dest2_o$145 ), + .dest3_o(\dest3_o$149 ), .fast1_ok(fast1_ok), .fast2_ok(fast2_ok), .nia_ok(nia_ok), + .oper_i_alu_branch0__SV_Ptype(oper_i_alu_branch0__SV_Ptype), .oper_i_alu_branch0__cia(oper_i_alu_branch0__cia), .oper_i_alu_branch0__fn_unit(oper_i_alu_branch0__fn_unit), .oper_i_alu_branch0__imm_data__data(oper_i_alu_branch0__imm_data__data), @@ -135733,6 +145194,9 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o .oper_i_alu_branch0__insn_type(oper_i_alu_branch0__insn_type), .oper_i_alu_branch0__is_32bit(oper_i_alu_branch0__is_32bit), .oper_i_alu_branch0__lk(oper_i_alu_branch0__lk), + .oper_i_alu_branch0__sv_pred_dz(oper_i_alu_branch0__sv_pred_dz), + .oper_i_alu_branch0__sv_pred_sz(oper_i_alu_branch0__sv_pred_sz), + .oper_i_alu_branch0__sv_saturate(oper_i_alu_branch0__sv_saturate), .src1_i(\src1_i$74 ), .src2_i(\src2_i$77 ), .src3_i(\src3_i$71 ) @@ -135740,22 +145204,26 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o cr0 cr0 ( .coresync_clk(coresync_clk), .coresync_rst(coresync_rst), - .cr_a_ok(\cr_a_ok$110 ), + .cr_a_ok(\cr_a_ok$111 ), .cu_busy_o(\cu_busy_o$2 ), .cu_issue_i(\cu_issue_i$1 ), .cu_rd__go_i(\cu_rd__go_i$29 ), .cu_rd__rel_o(\cu_rd__rel_o$28 ), .cu_rdmaskn_i(\cu_rdmaskn_i$3 ), - .cu_wr__go_i(\cu_wr__go_i$82 ), - .cu_wr__rel_o(\cu_wr__rel_o$81 ), - .dest1_o(\dest1_o$103 ), + .cu_wr__go_i(\cu_wr__go_i$83 ), + .cu_wr__rel_o(\cu_wr__rel_o$82 ), + .dest1_o(\dest1_o$104 ), .dest2_o(dest2_o), .dest3_o(dest3_o), .full_cr_ok(full_cr_ok), - .o_ok(\o_ok$80 ), + .o_ok(\o_ok$81 ), + .oper_i_alu_cr0__SV_Ptype(oper_i_alu_cr0__SV_Ptype), .oper_i_alu_cr0__fn_unit(oper_i_alu_cr0__fn_unit), .oper_i_alu_cr0__insn(oper_i_alu_cr0__insn), .oper_i_alu_cr0__insn_type(oper_i_alu_cr0__insn_type), + .oper_i_alu_cr0__sv_pred_dz(oper_i_alu_cr0__sv_pred_dz), + .oper_i_alu_cr0__sv_pred_sz(oper_i_alu_cr0__sv_pred_sz), + .oper_i_alu_cr0__sv_saturate(oper_i_alu_cr0__sv_saturate), .src1_i(\src1_i$50 ), .src2_i(\src2_i$30 ), .src3_i(\src3_i$67 ), @@ -135766,19 +145234,20 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o div0 div0 ( .coresync_clk(coresync_clk), .coresync_rst(coresync_rst), - .cr_a_ok(\cr_a_ok$112 ), + .cr_a_ok(\cr_a_ok$113 ), .cu_busy_o(\cu_busy_o$17 ), .cu_issue_i(\cu_issue_i$16 ), .cu_rd__go_i(\cu_rd__go_i$38 ), .cu_rd__rel_o(\cu_rd__rel_o$37 ), .cu_rdmaskn_i(\cu_rdmaskn_i$18 ), - .cu_wr__go_i(\cu_wr__go_i$94 ), - .cu_wr__rel_o(\cu_wr__rel_o$93 ), - .dest1_o(\dest1_o$107 ), - .dest2_o(\dest2_o$117 ), - .dest3_o(\dest3_o$127 ), - .dest4_o(\dest4_o$134 ), - .o_ok(\o_ok$92 ), + .cu_wr__go_i(\cu_wr__go_i$95 ), + .cu_wr__rel_o(\cu_wr__rel_o$94 ), + .dest1_o(\dest1_o$108 ), + .dest2_o(\dest2_o$118 ), + .dest3_o(\dest3_o$128 ), + .dest4_o(\dest4_o$135 ), + .o_ok(\o_ok$93 ), + .oper_i_alu_div0__SV_Ptype(oper_i_alu_div0__SV_Ptype), .oper_i_alu_div0__data_len(oper_i_alu_div0__data_len), .oper_i_alu_div0__fn_unit(oper_i_alu_div0__fn_unit), .oper_i_alu_div0__imm_data__data(oper_i_alu_div0__imm_data__data), @@ -135795,13 +145264,16 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o .oper_i_alu_div0__output_carry(oper_i_alu_div0__output_carry), .oper_i_alu_div0__rc__ok(oper_i_alu_div0__rc__ok), .oper_i_alu_div0__rc__rc(oper_i_alu_div0__rc__rc), + .oper_i_alu_div0__sv_pred_dz(oper_i_alu_div0__sv_pred_dz), + .oper_i_alu_div0__sv_pred_sz(oper_i_alu_div0__sv_pred_sz), + .oper_i_alu_div0__sv_saturate(oper_i_alu_div0__sv_saturate), .oper_i_alu_div0__write_cr0(oper_i_alu_div0__write_cr0), .oper_i_alu_div0__zero_a(oper_i_alu_div0__zero_a), .src1_i(\src1_i$56 ), .src2_i(\src2_i$39 ), .src3_i(\src3_i$62 ), - .xer_ov_ok(\xer_ov_ok$125 ), - .xer_so_ok(\xer_so_ok$130 ) + .xer_ov_ok(\xer_ov_ok$126 ), + .xer_so_ok(\xer_so_ok$131 ) ); ldst0 ldst0 ( .coresync_clk(coresync_clk), @@ -135815,29 +145287,32 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o .cu_rdmaskn_i(\cu_rdmaskn_i$27 ), .cu_st__go_i(cu_st__go_i), .cu_st__rel_o(cu_st__rel_o), - .cu_wr__go_i(\cu_wr__go_i$102 ), - .cu_wr__rel_o(\cu_wr__rel_o$101 ), + .cu_wr__go_i(\cu_wr__go_i$103 ), + .cu_wr__rel_o(\cu_wr__rel_o$102 ), .ea(ea), + .\exc_o_$signal (\exc_o_$signal ), .ldst_port0_addr_i(ldst_port0_addr_i), .ldst_port0_addr_i_ok(ldst_port0_addr_i_ok), .ldst_port0_addr_ok_o(ldst_port0_addr_ok_o), .ldst_port0_busy_o(ldst_port0_busy_o), .ldst_port0_data_len(ldst_port0_data_len), .\ldst_port0_exc_$signal (\ldst_port0_exc_$signal ), - .\ldst_port0_exc_$signal$1 (\ldst_port0_exc_$signal$151 ), - .\ldst_port0_exc_$signal$2 (\ldst_port0_exc_$signal$152 ), - .\ldst_port0_exc_$signal$3 (\ldst_port0_exc_$signal$153 ), - .\ldst_port0_exc_$signal$4 (\ldst_port0_exc_$signal$154 ), - .\ldst_port0_exc_$signal$5 (\ldst_port0_exc_$signal$155 ), - .\ldst_port0_exc_$signal$6 (\ldst_port0_exc_$signal$156 ), - .\ldst_port0_exc_$signal$7 (\ldst_port0_exc_$signal$157 ), + .\ldst_port0_exc_$signal$1 (\ldst_port0_exc_$signal$153 ), + .\ldst_port0_exc_$signal$2 (\ldst_port0_exc_$signal$154 ), + .\ldst_port0_exc_$signal$3 (\ldst_port0_exc_$signal$155 ), + .\ldst_port0_exc_$signal$4 (\ldst_port0_exc_$signal$156 ), + .\ldst_port0_exc_$signal$5 (\ldst_port0_exc_$signal$157 ), + .\ldst_port0_exc_$signal$6 (\ldst_port0_exc_$signal$158 ), + .\ldst_port0_exc_$signal$7 (\ldst_port0_exc_$signal$159 ), .ldst_port0_is_ld_i(ldst_port0_is_ld_i), .ldst_port0_is_st_i(ldst_port0_is_st_i), .ldst_port0_ld_data_o(ldst_port0_ld_data_o), .ldst_port0_ld_data_o_ok(ldst_port0_ld_data_o_ok), + .ldst_port0_msr_pr(ldst_port0_msr_pr), .ldst_port0_st_data_i(ldst_port0_st_data_i), .ldst_port0_st_data_i_ok(ldst_port0_st_data_i_ok), .o(o), + .oper_i_ldst_ldst0__SV_Ptype(oper_i_ldst_ldst0__SV_Ptype), .oper_i_ldst_ldst0__byte_reverse(oper_i_ldst_ldst0__byte_reverse), .oper_i_ldst_ldst0__data_len(oper_i_ldst_ldst0__data_len), .oper_i_ldst_ldst0__fn_unit(oper_i_ldst_ldst0__fn_unit), @@ -135848,11 +145323,15 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o .oper_i_ldst_ldst0__is_32bit(oper_i_ldst_ldst0__is_32bit), .oper_i_ldst_ldst0__is_signed(oper_i_ldst_ldst0__is_signed), .oper_i_ldst_ldst0__ldst_mode(oper_i_ldst_ldst0__ldst_mode), + .oper_i_ldst_ldst0__msr(oper_i_ldst_ldst0__msr), .oper_i_ldst_ldst0__oe__oe(oper_i_ldst_ldst0__oe__oe), .oper_i_ldst_ldst0__oe__ok(oper_i_ldst_ldst0__oe__ok), .oper_i_ldst_ldst0__rc__ok(oper_i_ldst_ldst0__rc__ok), .oper_i_ldst_ldst0__rc__rc(oper_i_ldst_ldst0__rc__rc), .oper_i_ldst_ldst0__sign_extend(oper_i_ldst_ldst0__sign_extend), + .oper_i_ldst_ldst0__sv_pred_dz(oper_i_ldst_ldst0__sv_pred_dz), + .oper_i_ldst_ldst0__sv_pred_sz(oper_i_ldst_ldst0__sv_pred_sz), + .oper_i_ldst_ldst0__sv_saturate(oper_i_ldst_ldst0__sv_saturate), .oper_i_ldst_ldst0__zero_a(oper_i_ldst_ldst0__zero_a), .src1_i(\src1_i$59 ), .src2_i(\src2_i$48 ), @@ -135861,17 +145340,18 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o logical0 logical0 ( .coresync_clk(coresync_clk), .coresync_rst(coresync_rst), - .cr_a_ok(\cr_a_ok$111 ), + .cr_a_ok(\cr_a_ok$112 ), .cu_busy_o(\cu_busy_o$11 ), .cu_issue_i(\cu_issue_i$10 ), .cu_rd__go_i(\cu_rd__go_i$35 ), .cu_rd__rel_o(\cu_rd__rel_o$34 ), .cu_rdmaskn_i(\cu_rdmaskn_i$12 ), - .cu_wr__go_i(\cu_wr__go_i$88 ), - .cu_wr__rel_o(\cu_wr__rel_o$87 ), - .dest1_o(\dest1_o$105 ), - .dest2_o(\dest2_o$116 ), - .o_ok(\o_ok$86 ), + .cu_wr__go_i(\cu_wr__go_i$89 ), + .cu_wr__rel_o(\cu_wr__rel_o$88 ), + .dest1_o(\dest1_o$106 ), + .dest2_o(\dest2_o$117 ), + .o_ok(\o_ok$87 ), + .oper_i_alu_logical0__SV_Ptype(oper_i_alu_logical0__SV_Ptype), .oper_i_alu_logical0__data_len(oper_i_alu_logical0__data_len), .oper_i_alu_logical0__fn_unit(oper_i_alu_logical0__fn_unit), .oper_i_alu_logical0__imm_data__data(oper_i_alu_logical0__imm_data__data), @@ -135888,6 +145368,9 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o .oper_i_alu_logical0__output_carry(oper_i_alu_logical0__output_carry), .oper_i_alu_logical0__rc__ok(oper_i_alu_logical0__rc__ok), .oper_i_alu_logical0__rc__rc(oper_i_alu_logical0__rc__rc), + .oper_i_alu_logical0__sv_pred_dz(oper_i_alu_logical0__sv_pred_dz), + .oper_i_alu_logical0__sv_pred_sz(oper_i_alu_logical0__sv_pred_sz), + .oper_i_alu_logical0__sv_saturate(oper_i_alu_logical0__sv_saturate), .oper_i_alu_logical0__write_cr0(oper_i_alu_logical0__write_cr0), .oper_i_alu_logical0__zero_a(oper_i_alu_logical0__zero_a), .src1_i(\src1_i$52 ), @@ -135897,19 +145380,20 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o mul0 mul0 ( .coresync_clk(coresync_clk), .coresync_rst(coresync_rst), - .cr_a_ok(\cr_a_ok$113 ), + .cr_a_ok(\cr_a_ok$114 ), .cu_busy_o(\cu_busy_o$20 ), .cu_issue_i(\cu_issue_i$19 ), .cu_rd__go_i(\cu_rd__go_i$41 ), .cu_rd__rel_o(\cu_rd__rel_o$40 ), .cu_rdmaskn_i(\cu_rdmaskn_i$21 ), - .cu_wr__go_i(\cu_wr__go_i$97 ), - .cu_wr__rel_o(\cu_wr__rel_o$96 ), - .dest1_o(\dest1_o$108 ), - .dest2_o(\dest2_o$118 ), - .dest3_o(\dest3_o$128 ), - .dest4_o(\dest4_o$135 ), - .o_ok(\o_ok$95 ), + .cu_wr__go_i(\cu_wr__go_i$98 ), + .cu_wr__rel_o(\cu_wr__rel_o$97 ), + .dest1_o(\dest1_o$109 ), + .dest2_o(\dest2_o$119 ), + .dest3_o(\dest3_o$129 ), + .dest4_o(\dest4_o$136 ), + .o_ok(\o_ok$96 ), + .oper_i_alu_mul0__SV_Ptype(oper_i_alu_mul0__SV_Ptype), .oper_i_alu_mul0__fn_unit(oper_i_alu_mul0__fn_unit), .oper_i_alu_mul0__imm_data__data(oper_i_alu_mul0__imm_data__data), .oper_i_alu_mul0__imm_data__ok(oper_i_alu_mul0__imm_data__ok), @@ -135921,28 +145405,32 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o .oper_i_alu_mul0__oe__ok(oper_i_alu_mul0__oe__ok), .oper_i_alu_mul0__rc__ok(oper_i_alu_mul0__rc__ok), .oper_i_alu_mul0__rc__rc(oper_i_alu_mul0__rc__rc), + .oper_i_alu_mul0__sv_pred_dz(oper_i_alu_mul0__sv_pred_dz), + .oper_i_alu_mul0__sv_pred_sz(oper_i_alu_mul0__sv_pred_sz), + .oper_i_alu_mul0__sv_saturate(oper_i_alu_mul0__sv_saturate), .oper_i_alu_mul0__write_cr0(oper_i_alu_mul0__write_cr0), .src1_i(\src1_i$57 ), .src2_i(\src2_i$42 ), .src3_i(\src3_i$63 ), - .xer_ov_ok(\xer_ov_ok$126 ), - .xer_so_ok(\xer_so_ok$131 ) + .xer_ov_ok(\xer_ov_ok$127 ), + .xer_so_ok(\xer_so_ok$132 ) ); shiftrot0 shiftrot0 ( .coresync_clk(coresync_clk), .coresync_rst(coresync_rst), - .cr_a_ok(\cr_a_ok$114 ), + .cr_a_ok(\cr_a_ok$115 ), .cu_busy_o(\cu_busy_o$23 ), .cu_issue_i(\cu_issue_i$22 ), .cu_rd__go_i(\cu_rd__go_i$44 ), .cu_rd__rel_o(\cu_rd__rel_o$43 ), .cu_rdmaskn_i(\cu_rdmaskn_i$24 ), - .cu_wr__go_i(\cu_wr__go_i$100 ), - .cu_wr__rel_o(\cu_wr__rel_o$99 ), - .dest1_o(\dest1_o$109 ), - .dest2_o(\dest2_o$119 ), - .dest3_o(\dest3_o$123 ), - .o_ok(\o_ok$98 ), + .cu_wr__go_i(\cu_wr__go_i$101 ), + .cu_wr__rel_o(\cu_wr__rel_o$100 ), + .dest1_o(\dest1_o$110 ), + .dest2_o(\dest2_o$120 ), + .dest3_o(\dest3_o$124 ), + .o_ok(\o_ok$99 ), + .oper_i_alu_shift_rot0__SV_Ptype(oper_i_alu_shift_rot0__SV_Ptype), .oper_i_alu_shift_rot0__fn_unit(oper_i_alu_shift_rot0__fn_unit), .oper_i_alu_shift_rot0__imm_data__data(oper_i_alu_shift_rot0__imm_data__data), .oper_i_alu_shift_rot0__imm_data__ok(oper_i_alu_shift_rot0__imm_data__ok), @@ -135959,13 +145447,16 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o .oper_i_alu_shift_rot0__output_cr(oper_i_alu_shift_rot0__output_cr), .oper_i_alu_shift_rot0__rc__ok(oper_i_alu_shift_rot0__rc__ok), .oper_i_alu_shift_rot0__rc__rc(oper_i_alu_shift_rot0__rc__rc), + .oper_i_alu_shift_rot0__sv_pred_dz(oper_i_alu_shift_rot0__sv_pred_dz), + .oper_i_alu_shift_rot0__sv_pred_sz(oper_i_alu_shift_rot0__sv_pred_sz), + .oper_i_alu_shift_rot0__sv_saturate(oper_i_alu_shift_rot0__sv_saturate), .oper_i_alu_shift_rot0__write_cr0(oper_i_alu_shift_rot0__write_cr0), .src1_i(\src1_i$58 ), .src2_i(\src2_i$45 ), .src3_i(src3_i), .src4_i(\src4_i$64 ), .src5_i(src5_i), - .xer_ca_ok(\xer_ca_ok$121 ) + .xer_ca_ok(\xer_ca_ok$122 ) ); spr0 spr0 ( .coresync_clk(coresync_clk), @@ -135975,30 +145466,34 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o .cu_rd__go_i(\cu_rd__go_i$54 ), .cu_rd__rel_o(\cu_rd__rel_o$53 ), .cu_rdmaskn_i(\cu_rdmaskn_i$15 ), - .cu_wr__go_i(\cu_wr__go_i$91 ), - .cu_wr__rel_o(\cu_wr__rel_o$90 ), - .dest1_o(\dest1_o$106 ), - .dest2_o(\dest2_o$150 ), - .dest3_o(\dest3_o$143 ), - .dest4_o(\dest4_o$133 ), + .cu_wr__go_i(\cu_wr__go_i$92 ), + .cu_wr__rel_o(\cu_wr__rel_o$91 ), + .dest1_o(\dest1_o$107 ), + .dest2_o(\dest2_o$152 ), + .dest3_o(\dest3_o$144 ), + .dest4_o(\dest4_o$134 ), .dest5_o(dest5_o), .dest6_o(dest6_o), - .fast1_ok(\fast1_ok$139 ), - .o_ok(\o_ok$89 ), + .fast1_ok(\fast1_ok$140 ), + .o_ok(\o_ok$90 ), + .oper_i_alu_spr0__SV_Ptype(oper_i_alu_spr0__SV_Ptype), .oper_i_alu_spr0__fn_unit(oper_i_alu_spr0__fn_unit), .oper_i_alu_spr0__insn(oper_i_alu_spr0__insn), .oper_i_alu_spr0__insn_type(oper_i_alu_spr0__insn_type), .oper_i_alu_spr0__is_32bit(oper_i_alu_spr0__is_32bit), + .oper_i_alu_spr0__sv_pred_dz(oper_i_alu_spr0__sv_pred_dz), + .oper_i_alu_spr0__sv_pred_sz(oper_i_alu_spr0__sv_pred_sz), + .oper_i_alu_spr0__sv_saturate(oper_i_alu_spr0__sv_saturate), .spr1_ok(spr1_ok), .src1_i(\src1_i$55 ), - .src2_i(\src2_i$79 ), + .src2_i(\src2_i$80 ), .src3_i(\src3_i$76 ), .src4_i(src4_i), .src5_i(\src5_i$66 ), .src6_i(src6_i), - .xer_ca_ok(\xer_ca_ok$120 ), - .xer_ov_ok(\xer_ov_ok$124 ), - .xer_so_ok(\xer_so_ok$129 ) + .xer_ca_ok(\xer_ca_ok$121 ), + .xer_ov_ok(\xer_ov_ok$125 ), + .xer_so_ok(\xer_so_ok$130 ) ); trap0 trap0 ( .coresync_clk(coresync_clk), @@ -136008,18 +145503,22 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o .cu_rd__go_i(\cu_rd__go_i$32 ), .cu_rd__rel_o(\cu_rd__rel_o$31 ), .cu_rdmaskn_i(\cu_rdmaskn_i$9 ), - .cu_wr__go_i(\cu_wr__go_i$85 ), - .cu_wr__rel_o(\cu_wr__rel_o$84 ), - .dest1_o(\dest1_o$104 ), - .dest2_o(\dest2_o$142 ), - .dest3_o(\dest3_o$145 ), - .dest4_o(\dest4_o$148 ), - .dest5_o(\dest5_o$149 ), - .fast1_ok(\fast1_ok$138 ), - .fast2_ok(\fast2_ok$140 ), + .cu_wr__go_i(\cu_wr__go_i$86 ), + .cu_wr__rel_o(\cu_wr__rel_o$85 ), + .dest1_o(\dest1_o$105 ), + .dest2_o(\dest2_o$143 ), + .dest3_o(\dest3_o$146 ), + .dest4_o(\dest4_o$147 ), + .dest5_o(\dest5_o$150 ), + .dest6_o(\dest6_o$151 ), + .dest7_o(dest7_o), + .fast1_ok(\fast1_ok$139 ), + .fast2_ok(\fast2_ok$141 ), + .fast3_ok(fast3_ok), .msr_ok(msr_ok), - .nia_ok(\nia_ok$146 ), - .o_ok(\o_ok$83 ), + .nia_ok(\nia_ok$148 ), + .o_ok(\o_ok$84 ), + .oper_i_alu_trap0__SV_Ptype(oper_i_alu_trap0__SV_Ptype), .oper_i_alu_trap0__cia(oper_i_alu_trap0__cia), .oper_i_alu_trap0__fn_unit(oper_i_alu_trap0__fn_unit), .oper_i_alu_trap0__insn(oper_i_alu_trap0__insn), @@ -136027,12 +145526,18 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o .oper_i_alu_trap0__is_32bit(oper_i_alu_trap0__is_32bit), .oper_i_alu_trap0__ldst_exc(oper_i_alu_trap0__ldst_exc), .oper_i_alu_trap0__msr(oper_i_alu_trap0__msr), + .oper_i_alu_trap0__sv_pred_dz(oper_i_alu_trap0__sv_pred_dz), + .oper_i_alu_trap0__sv_pred_sz(oper_i_alu_trap0__sv_pred_sz), + .oper_i_alu_trap0__sv_saturate(oper_i_alu_trap0__sv_saturate), + .oper_i_alu_trap0__svstate(oper_i_alu_trap0__svstate), .oper_i_alu_trap0__trapaddr(oper_i_alu_trap0__trapaddr), .oper_i_alu_trap0__traptype(oper_i_alu_trap0__traptype), .src1_i(\src1_i$51 ), .src2_i(\src2_i$33 ), .src3_i(\src3_i$75 ), - .src4_i(\src4_i$78 ) + .src4_i(\src4_i$78 ), + .src5_i(\src5_i$79 ), + .svstate_ok(svstate_ok) ); endmodule @@ -136133,9 +145638,9 @@ module idx_l(coresync_rst, q_idx_l, s_idx_l, r_idx_l, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_idx_l; @@ -136164,7 +145669,7 @@ module idx_l(coresync_rst, q_idx_l, s_idx_l, r_idx_l, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -136239,7 +145744,7 @@ module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en wire a_stall_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" *) input a_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) input clk; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" *) reg [44:0] f_badaddr_o = 45'h000000000000; @@ -136289,7 +145794,7 @@ module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en reg [63:0] ibus_rdata = 64'h0000000000000000; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69" *) reg [63:0] \ibus_rdata$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) input rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" *) input wb_icache_en; @@ -136355,7 +145860,7 @@ module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en \ibus__cyc$next = 1'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \ibus__cyc$next = 1'h0; @@ -136383,7 +145888,7 @@ module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en \ibus__stb$next = 1'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \ibus__stb$next = 1'h0; @@ -136411,7 +145916,7 @@ module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en \ibus__sel$next = 8'hff; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \ibus__sel$next = 8'h00; @@ -136436,7 +145941,7 @@ module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \ibus_rdata$next = 64'h0000000000000000; @@ -136459,7 +145964,7 @@ module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en \ibus__adr$next = a_pc_i[47:3]; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \ibus__adr$next = 45'h000000000000; @@ -136482,7 +145987,7 @@ module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en \f_fetch_err_o$next = 1'h0; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \f_fetch_err_o$next = 1'h0; @@ -136502,7 +146007,7 @@ module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en \f_badaddr_o$next = ibus__adr; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \f_badaddr_o$next = 45'h000000000000; @@ -136562,73 +146067,91 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.input" *) (* generator = "nMigen" *) -module \input (alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, ra, rb, xer_so, xer_ca, \muxid$1 , \alu_op__insn_type$2 , \alu_op__fn_unit$3 , \alu_op__imm_data__data$4 , \alu_op__imm_data__ok$5 , \alu_op__rc__rc$6 , \alu_op__rc__ok$7 , \alu_op__oe__oe$8 , \alu_op__oe__ok$9 , \alu_op__invert_in$10 , \alu_op__zero_a$11 , \alu_op__invert_out$12 , \alu_op__write_cr0$13 , \alu_op__input_carry$14 , \alu_op__output_carry$15 , \alu_op__is_32bit$16 , \alu_op__is_signed$17 , \alu_op__data_len$18 , \alu_op__insn$19 , \ra$20 , \rb$21 , \xer_so$22 , \xer_ca$23 , muxid); +module \input (alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, alu_op__sv_pred_sz, alu_op__sv_pred_dz, alu_op__sv_saturate, alu_op__SV_Ptype, ra, rb, xer_so, xer_ca, \muxid$1 , \alu_op__insn_type$2 , \alu_op__fn_unit$3 , \alu_op__imm_data__data$4 , \alu_op__imm_data__ok$5 , \alu_op__rc__rc$6 , \alu_op__rc__ok$7 , \alu_op__oe__oe$8 , \alu_op__oe__ok$9 , \alu_op__invert_in$10 , \alu_op__zero_a$11 , \alu_op__invert_out$12 , \alu_op__write_cr0$13 , \alu_op__input_carry$14 , \alu_op__output_carry$15 , \alu_op__is_32bit$16 , \alu_op__is_signed$17 , \alu_op__data_len$18 , \alu_op__insn$19 , \alu_op__sv_pred_sz$20 , \alu_op__sv_pred_dz$21 , \alu_op__sv_saturate$22 , \alu_op__SV_Ptype$23 , \ra$24 , \rb$25 , \xer_so$26 , \xer_ca$27 , muxid); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" *) - wire [63:0] \$24 ; + wire [63:0] \$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *) + wire \$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:52" *) + wire \$32 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" *) reg [63:0] a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] alu_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \alu_op__SV_Ptype$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [3:0] alu_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [3:0] \alu_op__data_len$18 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] alu_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] alu_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \alu_op__fn_unit$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \alu_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] alu_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \alu_op__imm_data__data$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__imm_data__ok$5 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] alu_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [1:0] \alu_op__input_carry$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] alu_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \alu_op__insn$19 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -136705,7 +146228,9 @@ module \input (alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] alu_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -136782,76 +146307,102 @@ module \input (alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] \alu_op__insn_type$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__invert_in$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__invert_out$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__is_32bit$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__is_signed$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__oe__oe$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__oe__ok$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__output_carry$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__rc__ok$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__rc__rc$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input alu_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \alu_op__sv_pred_dz$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input alu_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \alu_op__sv_pred_sz$20 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] alu_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \alu_op__sv_saturate$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__write_cr0$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__zero_a$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:41" *) wire [63:0] b; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] \muxid$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - output [63:0] \ra$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + output [63:0] \ra$24 ; + reg [63:0] \ra$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - output [63:0] \rb$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + output [63:0] \rb$25 ; + reg [63:0] \rb$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [1:0] xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - output [1:0] \xer_ca$23 ; - reg [1:0] \xer_ca$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + output [1:0] \xer_ca$27 ; + reg [1:0] \xer_ca$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - output \xer_so$22 ; - assign \$24 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" *) ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + output \xer_so$26 ; + assign \$28 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" *) ra; + assign \$30 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *) alu_op__sv_pred_sz; + assign \$32 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:52" *) alu_op__sv_pred_sz; always @* begin if (\initial ) begin end (* full_case = 32'd1 *) @@ -136859,7 +146410,7 @@ module \input (alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_o casez (alu_op__invert_in) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" */ 1'h1: - a = \$24 ; + a = \$28 ; /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:29" */ default: a = ra; @@ -136867,118 +146418,150 @@ module \input (alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_o end always @* begin if (\initial ) begin end - \xer_ca$23 = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:55" *) + \ra$24 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *) + casez (\$30 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" */ + 1'h1: + \ra$24 = a; + endcase + end + always @* begin + if (\initial ) begin end + \rb$25 = rb; + end + always @* begin + if (\initial ) begin end + \xer_ca$27 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:59" *) casez (alu_op__input_carry) /* \nmigen.decoding = "ZERO/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:56" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:60" */ 2'h0: - \xer_ca$23 = 2'h0; + \xer_ca$27 = 2'h0; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:58" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:62" */ 2'h1: - \xer_ca$23 = 2'h3; + \xer_ca$27 = 2'h3; /* \nmigen.decoding = "CA/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:60" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:64" */ 2'h2: - \xer_ca$23 = xer_ca; + \xer_ca$27 = xer_ca; endcase end - assign { \alu_op__insn$19 , \alu_op__data_len$18 , \alu_op__is_signed$17 , \alu_op__is_32bit$16 , \alu_op__output_carry$15 , \alu_op__input_carry$14 , \alu_op__write_cr0$13 , \alu_op__invert_out$12 , \alu_op__zero_a$11 , \alu_op__invert_in$10 , \alu_op__oe__ok$9 , \alu_op__oe__oe$8 , \alu_op__rc__ok$7 , \alu_op__rc__rc$6 , \alu_op__imm_data__ok$5 , \alu_op__imm_data__data$4 , \alu_op__fn_unit$3 , \alu_op__insn_type$2 } = { alu_op__insn, alu_op__data_len, alu_op__is_signed, alu_op__is_32bit, alu_op__output_carry, alu_op__input_carry, alu_op__write_cr0, alu_op__invert_out, alu_op__zero_a, alu_op__invert_in, alu_op__oe__ok, alu_op__oe__oe, alu_op__rc__ok, alu_op__rc__rc, alu_op__imm_data__ok, alu_op__imm_data__data, alu_op__fn_unit, alu_op__insn_type }; + assign { \alu_op__SV_Ptype$23 , \alu_op__sv_saturate$22 , \alu_op__sv_pred_dz$21 , \alu_op__sv_pred_sz$20 , \alu_op__insn$19 , \alu_op__data_len$18 , \alu_op__is_signed$17 , \alu_op__is_32bit$16 , \alu_op__output_carry$15 , \alu_op__input_carry$14 , \alu_op__write_cr0$13 , \alu_op__invert_out$12 , \alu_op__zero_a$11 , \alu_op__invert_in$10 , \alu_op__oe__ok$9 , \alu_op__oe__oe$8 , \alu_op__rc__ok$7 , \alu_op__rc__rc$6 , \alu_op__imm_data__ok$5 , \alu_op__imm_data__data$4 , \alu_op__fn_unit$3 , \alu_op__insn_type$2 } = { alu_op__SV_Ptype, alu_op__sv_saturate, alu_op__sv_pred_dz, alu_op__sv_pred_sz, alu_op__insn, alu_op__data_len, alu_op__is_signed, alu_op__is_32bit, alu_op__output_carry, alu_op__input_carry, alu_op__write_cr0, alu_op__invert_out, alu_op__zero_a, alu_op__invert_in, alu_op__oe__ok, alu_op__oe__oe, alu_op__rc__ok, alu_op__rc__rc, alu_op__imm_data__ok, alu_op__imm_data__data, alu_op__fn_unit, alu_op__insn_type }; assign \muxid$1 = muxid; - assign \xer_so$22 = xer_so; - assign \rb$21 = rb; + assign \xer_so$26 = xer_so; assign b = rb; - assign \ra$20 = a; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.input" *) (* generator = "nMigen" *) -module \input$113 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, ra, rb, rc, xer_so, xer_ca, \muxid$1 , \sr_op__insn_type$2 , \sr_op__fn_unit$3 , \sr_op__imm_data__data$4 , \sr_op__imm_data__ok$5 , \sr_op__rc__rc$6 , \sr_op__rc__ok$7 , \sr_op__oe__oe$8 , \sr_op__oe__ok$9 , \sr_op__write_cr0$10 , \sr_op__invert_in$11 , \sr_op__input_carry$12 , \sr_op__output_carry$13 , \sr_op__input_cr$14 , \sr_op__output_cr$15 , \sr_op__is_32bit$16 , \sr_op__is_signed$17 , \sr_op__insn$18 , \ra$19 , \rb$20 , \rc$21 , \xer_so$22 , \xer_ca$23 , muxid); +module \input$113 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, sr_op__sv_pred_sz, sr_op__sv_pred_dz, sr_op__sv_saturate, sr_op__SV_Ptype, ra, rb, rc, xer_so, xer_ca, \muxid$1 , \sr_op__insn_type$2 , \sr_op__fn_unit$3 , \sr_op__imm_data__data$4 , \sr_op__imm_data__ok$5 , \sr_op__rc__rc$6 , \sr_op__rc__ok$7 , \sr_op__oe__oe$8 , \sr_op__oe__ok$9 , \sr_op__write_cr0$10 , \sr_op__invert_in$11 , \sr_op__input_carry$12 , \sr_op__output_carry$13 , \sr_op__input_cr$14 , \sr_op__output_cr$15 , \sr_op__is_32bit$16 , \sr_op__is_signed$17 , \sr_op__insn$18 , \sr_op__sv_pred_sz$19 , \sr_op__sv_pred_dz$20 , \sr_op__sv_saturate$21 , \sr_op__SV_Ptype$22 , \ra$23 , \rb$24 , \rc$25 , \xer_so$26 , \xer_ca$27 , muxid); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" *) - wire [63:0] \$24 ; + wire [63:0] \$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *) + wire \$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:52" *) + wire \$32 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" *) reg [63:0] a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:41" *) wire [63:0] b; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] \muxid$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - output [63:0] \ra$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + output [63:0] \ra$23 ; + reg [63:0] \ra$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - output [63:0] \rb$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + output [63:0] \rb$24 ; + reg [63:0] \rb$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - output [63:0] \rc$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + output [63:0] \rc$25 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] sr_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \sr_op__SV_Ptype$22 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] sr_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] sr_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \sr_op__fn_unit$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \sr_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] sr_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \sr_op__imm_data__data$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__imm_data__ok$5 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] sr_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [1:0] \sr_op__input_carry$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__input_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__input_cr$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] sr_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \sr_op__insn$18 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -137055,7 +146638,9 @@ module \input$113 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] sr_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -137132,58 +146717,82 @@ module \input$113 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] \sr_op__insn_type$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__invert_in$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__is_32bit$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__is_signed$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__oe__oe$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__oe__ok$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__output_carry$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__output_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__output_cr$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__rc__ok$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__rc__rc$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input sr_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \sr_op__sv_pred_dz$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input sr_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \sr_op__sv_pred_sz$19 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] sr_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \sr_op__sv_saturate$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__write_cr0$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [1:0] xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - output [1:0] \xer_ca$23 ; - reg [1:0] \xer_ca$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + output [1:0] \xer_ca$27 ; + reg [1:0] \xer_ca$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - output \xer_so$22 ; - assign \$24 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" *) ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + output \xer_so$26 ; + assign \$28 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" *) ra; + assign \$30 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *) sr_op__sv_pred_sz; + assign \$32 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:52" *) sr_op__sv_pred_sz; always @* begin if (\initial ) begin end (* full_case = 32'd1 *) @@ -137191,7 +146800,7 @@ module \input$113 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_o casez (sr_op__invert_in) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" */ 1'h1: - a = \$24 ; + a = \$28 ; /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:29" */ default: a = ra; @@ -137199,103 +146808,139 @@ module \input$113 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_o end always @* begin if (\initial ) begin end - \xer_ca$23 = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:55" *) + \ra$23 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *) + casez (\$30 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" */ + 1'h1: + \ra$23 = a; + endcase + end + always @* begin + if (\initial ) begin end + \rb$24 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:52" *) + casez (\$32 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:52" */ + 1'h1: + \rb$24 = b; + endcase + end + always @* begin + if (\initial ) begin end + \xer_ca$27 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:59" *) casez (sr_op__input_carry) /* \nmigen.decoding = "ZERO/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:56" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:60" */ 2'h0: - \xer_ca$23 = 2'h0; + \xer_ca$27 = 2'h0; /* \nmigen.decoding = "ONE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:58" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:62" */ 2'h1: - \xer_ca$23 = 2'h3; + \xer_ca$27 = 2'h3; /* \nmigen.decoding = "CA/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:60" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:64" */ 2'h2: - \xer_ca$23 = xer_ca; + \xer_ca$27 = xer_ca; endcase end - assign \rc$21 = rc; - assign { \sr_op__insn$18 , \sr_op__is_signed$17 , \sr_op__is_32bit$16 , \sr_op__output_cr$15 , \sr_op__input_cr$14 , \sr_op__output_carry$13 , \sr_op__input_carry$12 , \sr_op__invert_in$11 , \sr_op__write_cr0$10 , \sr_op__oe__ok$9 , \sr_op__oe__oe$8 , \sr_op__rc__ok$7 , \sr_op__rc__rc$6 , \sr_op__imm_data__ok$5 , \sr_op__imm_data__data$4 , \sr_op__fn_unit$3 , \sr_op__insn_type$2 } = { sr_op__insn, sr_op__is_signed, sr_op__is_32bit, sr_op__output_cr, sr_op__input_cr, sr_op__output_carry, sr_op__input_carry, sr_op__invert_in, sr_op__write_cr0, sr_op__oe__ok, sr_op__oe__oe, sr_op__rc__ok, sr_op__rc__rc, sr_op__imm_data__ok, sr_op__imm_data__data, sr_op__fn_unit, sr_op__insn_type }; + assign \rc$25 = rc; + assign { \sr_op__SV_Ptype$22 , \sr_op__sv_saturate$21 , \sr_op__sv_pred_dz$20 , \sr_op__sv_pred_sz$19 , \sr_op__insn$18 , \sr_op__is_signed$17 , \sr_op__is_32bit$16 , \sr_op__output_cr$15 , \sr_op__input_cr$14 , \sr_op__output_carry$13 , \sr_op__input_carry$12 , \sr_op__invert_in$11 , \sr_op__write_cr0$10 , \sr_op__oe__ok$9 , \sr_op__oe__oe$8 , \sr_op__rc__ok$7 , \sr_op__rc__rc$6 , \sr_op__imm_data__ok$5 , \sr_op__imm_data__data$4 , \sr_op__fn_unit$3 , \sr_op__insn_type$2 } = { sr_op__SV_Ptype, sr_op__sv_saturate, sr_op__sv_pred_dz, sr_op__sv_pred_sz, sr_op__insn, sr_op__is_signed, sr_op__is_32bit, sr_op__output_cr, sr_op__input_cr, sr_op__output_carry, sr_op__input_carry, sr_op__invert_in, sr_op__write_cr0, sr_op__oe__ok, sr_op__oe__oe, sr_op__rc__ok, sr_op__rc__rc, sr_op__imm_data__ok, sr_op__imm_data__data, sr_op__fn_unit, sr_op__insn_type }; assign \muxid$1 = muxid; - assign \xer_so$22 = xer_so; - assign \rb$20 = b; + assign \xer_so$26 = xer_so; assign b = rb; - assign \ra$19 = a; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.input" *) (* generator = "nMigen" *) -module \input$50 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, ra, rb, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \ra$20 , \rb$21 , \xer_so$22 , muxid); +module \input$50 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__SV_Ptype, ra, rb, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__SV_Ptype$23 , \ra$24 , \rb$25 , \xer_so$26 , muxid); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" *) - wire [63:0] \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *) + wire \$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:45" *) + wire [63:0] \$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:52" *) + wire \$31 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" *) wire [63:0] a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:41" *) reg [63:0] b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] logical_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \logical_op__SV_Ptype$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [3:0] logical_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [3:0] \logical_op__data_len$18 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] logical_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] logical_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \logical_op__fn_unit$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \logical_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] logical_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \logical_op__imm_data__data$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__imm_data__ok$5 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] logical_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [1:0] \logical_op__input_carry$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] logical_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \logical_op__insn$19 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -137372,7 +147017,9 @@ module \input$50 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_da (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] logical_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -137449,161 +147096,223 @@ module \input$50 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_da (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] \logical_op__insn_type$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__invert_in$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__invert_out$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__is_32bit$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__is_signed$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__oe__oe$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__oe__ok$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__output_carry$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__rc__ok$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__rc__rc$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input logical_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \logical_op__sv_pred_dz$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input logical_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \logical_op__sv_pred_sz$20 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] logical_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \logical_op__sv_saturate$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__write_cr0$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__zero_a$11 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] \muxid$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - output [63:0] \ra$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + output [63:0] \ra$24 ; + reg [63:0] \ra$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - output [63:0] \rb$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + output [63:0] \rb$25 ; + reg [63:0] \rb$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - output \xer_so$22 ; - assign \$23 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" *) rb; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + output \xer_so$26 ; + assign \$27 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *) logical_op__sv_pred_sz; + assign \$29 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:45" *) rb; + assign \$31 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:52" *) logical_op__sv_pred_sz; + always @* begin + if (\initial ) begin end + \ra$24 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *) + casez (\$27 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" */ + 1'h1: + \ra$24 = a; + endcase + end always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:42" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:44" *) casez (logical_op__invert_in) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:42" */ - 1'h1: - b = \$23 ; /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:44" */ + 1'h1: + b = \$29 ; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:46" */ default: b = rb; endcase end - assign { \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; + always @* begin + if (\initial ) begin end + \rb$25 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:52" *) + casez (\$31 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:52" */ + 1'h1: + \rb$25 = b; + endcase + end + assign { \logical_op__SV_Ptype$23 , \logical_op__sv_saturate$22 , \logical_op__sv_pred_dz$21 , \logical_op__sv_pred_sz$20 , \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__SV_Ptype, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; assign \muxid$1 = muxid; - assign \xer_so$22 = xer_so; - assign \rb$21 = b; - assign \ra$20 = a; + assign \xer_so$26 = xer_so; assign a = ra; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.input" *) (* generator = "nMigen" *) -module \input$78 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, ra, rb, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \ra$20 , \rb$21 , \xer_so$22 , muxid); +module \input$78 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__SV_Ptype, ra, rb, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__SV_Ptype$23 , \ra$24 , \rb$25 , \xer_so$26 , muxid); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" *) - wire [63:0] \$23 ; + wire [63:0] \$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *) + wire \$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:52" *) + wire \$31 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" *) reg [63:0] a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:41" *) wire [63:0] b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] logical_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \logical_op__SV_Ptype$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [3:0] logical_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [3:0] \logical_op__data_len$18 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] logical_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] logical_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \logical_op__fn_unit$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \logical_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] logical_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \logical_op__imm_data__data$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__imm_data__ok$5 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] logical_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [1:0] \logical_op__input_carry$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] logical_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \logical_op__insn$19 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -137680,7 +147389,9 @@ module \input$78 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_da (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] logical_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -137757,69 +147468,95 @@ module \input$78 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_da (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] \logical_op__insn_type$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__invert_in$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__invert_out$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__is_32bit$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__is_signed$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__oe__oe$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__oe__ok$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__output_carry$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__rc__ok$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__rc__rc$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input logical_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \logical_op__sv_pred_dz$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input logical_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \logical_op__sv_pred_sz$20 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] logical_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \logical_op__sv_saturate$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__write_cr0$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__zero_a$11 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] \muxid$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - output [63:0] \ra$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + output [63:0] \ra$24 ; + reg [63:0] \ra$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - output [63:0] \rb$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + output [63:0] \rb$25 ; + reg [63:0] \rb$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - output \xer_so$22 ; - assign \$23 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" *) ra; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + output \xer_so$26 ; + assign \$27 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" *) ra; + assign \$29 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *) logical_op__sv_pred_sz; + assign \$31 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:52" *) logical_op__sv_pred_sz; always @* begin if (\initial ) begin end (* full_case = 32'd1 *) @@ -137827,72 +147564,103 @@ module \input$78 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_da casez (logical_op__invert_in) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" */ 1'h1: - a = \$23 ; + a = \$27 ; /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:29" */ default: a = ra; endcase end - assign { \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; + always @* begin + if (\initial ) begin end + \ra$24 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *) + casez (\$29 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" */ + 1'h1: + \ra$24 = a; + endcase + end + always @* begin + if (\initial ) begin end + \rb$25 = rb; + end + assign { \logical_op__SV_Ptype$23 , \logical_op__sv_saturate$22 , \logical_op__sv_pred_dz$21 , \logical_op__sv_pred_sz$20 , \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__SV_Ptype, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; assign \muxid$1 = muxid; - assign \xer_so$22 = xer_so; - assign \rb$21 = rb; + assign \xer_so$26 = xer_so; assign b = rb; - assign \ra$20 = a; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.input" *) (* generator = "nMigen" *) -module \input$95 (mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, ra, rb, xer_so, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \ra$14 , \rb$15 , \xer_so$16 , muxid); +module \input$95 (mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, mul_op__sv_pred_sz, mul_op__sv_pred_dz, mul_op__sv_saturate, mul_op__SV_Ptype, ra, rb, xer_so, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \mul_op__sv_pred_sz$14 , \mul_op__sv_pred_dz$15 , \mul_op__sv_saturate$16 , \mul_op__SV_Ptype$17 , \ra$18 , \rb$19 , \xer_so$20 , muxid); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *) + wire \$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:52" *) + wire \$23 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" *) wire [63:0] a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:41" *) wire [63:0] b; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] mul_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \mul_op__SV_Ptype$17 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] mul_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] mul_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \mul_op__fn_unit$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \mul_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] mul_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \mul_op__imm_data__data$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__imm_data__ok$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] mul_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \mul_op__insn$13 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -137969,7 +147737,9 @@ module \input$95 (mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mu (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] mul_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -138046,58 +147816,96 @@ module \input$95 (mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mu (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] \mul_op__insn_type$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__is_32bit$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__is_signed$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__oe__oe$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__oe__ok$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__rc__ok$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__rc__rc$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input mul_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \mul_op__sv_pred_dz$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input mul_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \mul_op__sv_pred_sz$14 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] mul_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \mul_op__sv_saturate$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__write_cr0$10 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] \muxid$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - output [63:0] \ra$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + output [63:0] \ra$18 ; + reg [63:0] \ra$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - output [63:0] \rb$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + output [63:0] \rb$19 ; + reg [63:0] \rb$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - output \xer_so$16 ; - assign { \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2 } = { mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type }; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + output \xer_so$20 ; + assign \$21 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *) mul_op__sv_pred_sz; + assign \$23 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:52" *) mul_op__sv_pred_sz; + always @* begin + if (\initial ) begin end + \ra$18 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" *) + casez (\$21 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:35" */ + 1'h1: + \ra$18 = a; + endcase + end + always @* begin + if (\initial ) begin end + \rb$19 = rb; + end + assign { \mul_op__SV_Ptype$17 , \mul_op__sv_saturate$16 , \mul_op__sv_pred_dz$15 , \mul_op__sv_pred_sz$14 , \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2 } = { mul_op__SV_Ptype, mul_op__sv_saturate, mul_op__sv_pred_dz, mul_op__sv_pred_sz, mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type }; assign \muxid$1 = muxid; - assign \xer_so$16 = xer_so; - assign \rb$15 = rb; + assign \xer_so$20 = xer_so; assign b = rb; - assign \ra$14 = a; assign a = ra; endmodule @@ -138105,9 +147913,9 @@ endmodule (* generator = "nMigen" *) module \int (coresync_rst, dmi__addr, dmi__ren, dmi__data_o, src1__data_o, src1__addr, src1__ren, dest1__data_i, dest1__addr, dest1__wen, coresync_clk); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [4:0] dest1__addr; @@ -138122,27 +147930,27 @@ module \int (coresync_rst, dmi__addr, dmi__ren, dmi__data_o, src1__data_o, src1_ reg [63:0] dmi__data_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input dmi__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:211" *) wire [4:0] memory_r_addr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:211" *) wire [4:0] \memory_r_addr$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:211" *) wire [63:0] memory_r_data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:211" *) wire [63:0] \memory_r_data$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:219" *) wire [4:0] memory_w_addr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:219" *) wire [63:0] memory_w_data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:219" *) wire memory_w_en; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" *) reg ren_delay = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" *) reg \ren_delay$4 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" *) reg \ren_delay$4$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" *) reg \ren_delay$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [4:0] src1__addr; @@ -138202,7 +148010,7 @@ module \int (coresync_rst, dmi__addr, dmi__ren, dmi__data_o, src1__data_o, src1_ always @* begin if (\initial ) begin end \ren_delay$next = dmi__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \ren_delay$next = 1'h0; @@ -138211,9 +148019,9 @@ module \int (coresync_rst, dmi__addr, dmi__ren, dmi__data_o, src1__data_o, src1_ always @* begin if (\initial ) begin end dmi__data_o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:246" *) casez (ren_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:246" */ 1'h1: dmi__data_o = memory_r_data; endcase @@ -138221,7 +148029,7 @@ module \int (coresync_rst, dmi__addr, dmi__ren, dmi__data_o, src1__data_o, src1_ always @* begin if (\initial ) begin end \ren_delay$4$next = src1__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \ren_delay$4$next = 1'h0; @@ -138230,9 +148038,9 @@ module \int (coresync_rst, dmi__addr, dmi__ren, dmi__data_o, src1__data_o, src1_ always @* begin if (\initial ) begin end src1__data_o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:246" *) casez (\ren_delay$4 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:246" */ 1'h1: src1__data_o = \memory_r_data$3 ; endcase @@ -138323,7 +148131,7 @@ module irblock(capture, shift, update, TAP_bus__tdi, isir, tdo, posjtag_rst, pos 3'b1??: \ir$next = shift_ir; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (posjtag_rst) 1'h1: \ir$next = 4'h1; @@ -138334,7 +148142,7 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.jtag" *) (* generator = "nMigen" *) -module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0__dout, wb_sram_en, wb_dcache_en, wb_icache_en, mspi0_clk__core__o, mspi0_cs_n__core__o, mspi0_mosi__core__o, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dq_0__pad__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_1__pad__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_2__pad__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_3__pad__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_4__pad__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_5__pad__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_6__pad__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_7__pad__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_a_0__core__o, sdr_a_1__core__o, sdr_a_2__core__o, sdr_a_3__core__o, sdr_a_4__core__o, sdr_a_5__core__o, sdr_a_6__core__o, sdr_a_7__core__o, sdr_a_8__core__o, sdr_a_9__core__o, sdr_ba_0__core__o, sdr_ba_1__core__o, sdr_clock__core__o, sdr_cke__core__o, sdr_ras_n__core__o, sdr_cas_n__core__o, sdr_we_n__core__o, sdr_cs_n__core__o, sdr_a_10__core__o, sdr_a_11__core__o, sdr_a_12__core__o, sdr_dm_1__core__o, sdr_dq_8__pad__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_9__pad__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_10__pad__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_11__pad__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_12__pad__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_13__pad__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_14__pad__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_15__pad__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, gpio_e8__pad__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e9__pad__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e10__pad__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e11__pad__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e12__pad__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e13__pad__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e14__pad__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e15__pad__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_s0__pad__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s1__pad__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s2__pad__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s3__pad__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s4__pad__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s5__pad__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s6__pad__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s7__pad__i, gpio_s7__core__o, gpio_s7__core__oe, mtwi_sda__pad__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_scl__core__o, eint_0__pad__i, eint_1__pad__i, eint_2__pad__i, TAP_bus__tdi, mspi0_clk__pad__o, mspi0_cs_n__pad__o, mspi0_mosi__pad__o, mspi0_miso__core__i, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__pad__o, sdr_a_1__pad__o, sdr_a_2__pad__o, sdr_a_3__pad__o, sdr_a_4__pad__o, sdr_a_5__pad__o, sdr_a_6__pad__o, sdr_a_7__pad__o, sdr_a_8__pad__o, sdr_a_9__pad__o, sdr_ba_0__pad__o, sdr_ba_1__pad__o, sdr_clock__pad__o, sdr_cke__pad__o, sdr_ras_n__pad__o, sdr_cas_n__pad__o, sdr_we_n__pad__o, sdr_cs_n__pad__o, sdr_a_10__pad__o, sdr_a_11__pad__o, sdr_a_12__pad__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__pad__o, eint_0__core__i, eint_1__core__i, eint_2__core__i, TAP_bus__tdo, jtag_wb__adr, jtag_wb__sel, jtag_wb__stb, jtag_wb__we, jtag_wb__cyc, jtag_wb__dat_w, jtag_wb__ack, jtag_wb__dat_r, TAP_bus__tck, TAP_bus__tms, clk); +module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0__dout, wb_dcache_en, wb_icache_en, mspi0_clk__core__o, mspi0_cs_n__core__o, mspi0_mosi__core__o, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dq_0__pad__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_1__pad__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_2__pad__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_3__pad__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_4__pad__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_5__pad__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_6__pad__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_7__pad__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_a_0__core__o, sdr_a_1__core__o, sdr_a_2__core__o, sdr_a_3__core__o, sdr_a_4__core__o, sdr_a_5__core__o, sdr_a_6__core__o, sdr_a_7__core__o, sdr_a_8__core__o, sdr_a_9__core__o, sdr_ba_0__core__o, sdr_ba_1__core__o, sdr_clock__core__o, sdr_cke__core__o, sdr_ras_n__core__o, sdr_cas_n__core__o, sdr_we_n__core__o, sdr_cs_n__core__o, sdr_a_10__core__o, sdr_a_11__core__o, sdr_a_12__core__o, sdr_dm_1__core__o, sdr_dq_8__pad__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_9__pad__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_10__pad__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_11__pad__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_12__pad__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_13__pad__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_14__pad__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_15__pad__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, gpio_e8__pad__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e9__pad__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e10__pad__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e11__pad__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e12__pad__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e13__pad__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e14__pad__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e15__pad__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_s0__pad__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s1__pad__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s2__pad__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s3__pad__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s4__pad__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s5__pad__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s6__pad__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s7__pad__i, gpio_s7__core__o, gpio_s7__core__oe, mtwi_sda__pad__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_scl__core__o, eint_0__pad__i, eint_1__pad__i, eint_2__pad__i, TAP_bus__tdi, mspi0_clk__pad__o, mspi0_cs_n__pad__o, mspi0_mosi__pad__o, mspi0_miso__core__i, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__pad__o, sdr_a_1__pad__o, sdr_a_2__pad__o, sdr_a_3__pad__o, sdr_a_4__pad__o, sdr_a_5__pad__o, sdr_a_6__pad__o, sdr_a_7__pad__o, sdr_a_8__pad__o, sdr_a_9__pad__o, sdr_ba_0__pad__o, sdr_ba_1__pad__o, sdr_clock__pad__o, sdr_cke__pad__o, sdr_ras_n__pad__o, sdr_cas_n__pad__o, sdr_we_n__pad__o, sdr_cs_n__pad__o, sdr_a_10__pad__o, sdr_a_11__pad__o, sdr_a_12__pad__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__pad__o, eint_0__core__i, eint_1__core__i, eint_2__core__i, TAP_bus__tdo, jtag_wb__adr, jtag_wb__sel, jtag_wb__stb, jtag_wb__we, jtag_wb__cyc, jtag_wb__dat_w, jtag_wb__ack, jtag_wb__dat_r, TAP_bus__tck, TAP_bus__tms, clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" *) wire \$1 ; @@ -138831,7 +148639,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, input TAP_bus__tms; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:420" *) reg TAP_tdo; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) input clk; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) input dmi0__ack_o; @@ -139279,7 +149087,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, wire posjtag_clk; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" *) wire posjtag_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) input rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) input sdr_a_0__core__o; @@ -139634,7 +149442,6 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" *) reg \wb_icache_en$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:96" *) - output wb_sram_en; reg wb_sram_en = 1'h1; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:96" *) reg \wb_sram_en$next ; @@ -140004,7 +149811,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, always @* begin if (\initial ) begin end \sr0_update_core$next = sr0_update; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \sr0_update_core$next = 1'h0; @@ -140013,7 +149820,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, always @* begin if (\initial ) begin end \sr0_update_core_prev$next = sr0_update_core; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \sr0_update_core_prev$next = 1'h0; @@ -140031,7 +149838,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, default: \sr0__oe$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \sr0__oe$next = 1'h0; @@ -140052,7 +149859,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, 1'h1: \sr0_reg$next = sr0__i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (posjtag_rst) 1'h1: \sr0_reg$next = 3'h0; @@ -140061,7 +149868,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, always @* begin if (\initial ) begin end \jtag_wb_addrsr_update_core$next = jtag_wb_addrsr_update; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \jtag_wb_addrsr_update_core$next = 1'h0; @@ -140070,7 +149877,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, always @* begin if (\initial ) begin end \jtag_wb_addrsr_update_core_prev$next = jtag_wb_addrsr_update_core; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \jtag_wb_addrsr_update_core_prev$next = 1'h0; @@ -140088,7 +149895,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, default: \jtag_wb_addrsr__oe$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \jtag_wb_addrsr__oe$next = 1'h0; @@ -140109,7 +149916,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, 1'h1: \jtag_wb_addrsr_reg$next = jtag_wb_addrsr__i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (posjtag_rst) 1'h1: \jtag_wb_addrsr_reg$next = 30'h00000000; @@ -140118,7 +149925,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, always @* begin if (\initial ) begin end \jtag_wb_datasr_update_core$next = jtag_wb_datasr_update; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \jtag_wb_datasr_update_core$next = 1'h0; @@ -140127,7 +149934,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, always @* begin if (\initial ) begin end \jtag_wb_datasr_update_core_prev$next = jtag_wb_datasr_update_core; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \jtag_wb_datasr_update_core_prev$next = 1'h0; @@ -140145,7 +149952,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, default: \jtag_wb_datasr__oe$next = 2'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \jtag_wb_datasr__oe$next = 2'h0; @@ -140166,7 +149973,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, 1'h1: \jtag_wb_datasr_reg$next = jtag_wb_datasr__i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (posjtag_rst) 1'h1: \jtag_wb_datasr_reg$next = 32'd0; @@ -140175,7 +149982,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, always @* begin if (\initial ) begin end \dmi0_addrsr_update_core$next = dmi0_addrsr_update; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \dmi0_addrsr_update_core$next = 1'h0; @@ -140184,7 +149991,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, always @* begin if (\initial ) begin end \dmi0_addrsr_update_core_prev$next = dmi0_addrsr_update_core; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \dmi0_addrsr_update_core_prev$next = 1'h0; @@ -140202,7 +150009,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, default: \dmi0_addrsr__oe$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \dmi0_addrsr__oe$next = 1'h0; @@ -140223,7 +150030,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, 1'h1: \dmi0_addrsr_reg$next = dmi0_addrsr__i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (posjtag_rst) 1'h1: \dmi0_addrsr_reg$next = 8'h00; @@ -140232,7 +150039,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, always @* begin if (\initial ) begin end \dmi0_datasr_update_core$next = dmi0_datasr_update; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \dmi0_datasr_update_core$next = 1'h0; @@ -140241,7 +150048,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, always @* begin if (\initial ) begin end \dmi0_datasr_update_core_prev$next = dmi0_datasr_update_core; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \dmi0_datasr_update_core_prev$next = 1'h0; @@ -140259,7 +150066,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, default: \dmi0_datasr__oe$next = 2'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \dmi0_datasr__oe$next = 2'h0; @@ -140280,7 +150087,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, 1'h1: \dmi0_datasr_reg$next = dmi0_datasr__i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (posjtag_rst) 1'h1: \dmi0_datasr_reg$next = 64'h0000000000000000; @@ -140289,7 +150096,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, always @* begin if (\initial ) begin end \sr5_update_core$next = sr5_update; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \sr5_update_core$next = 1'h0; @@ -140298,7 +150105,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, always @* begin if (\initial ) begin end \sr5_update_core_prev$next = sr5_update_core; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \sr5_update_core_prev$next = 1'h0; @@ -140316,7 +150123,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, default: \sr5__oe$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \sr5__oe$next = 1'h0; @@ -140337,7 +150144,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, 1'h1: \sr5_reg$next = sr5__i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (posjtag_rst) 1'h1: \sr5_reg$next = 3'h0; @@ -140410,7 +150217,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, \jtag_wb__adr$next = \$462 [29:0]; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \jtag_wb__adr$next = 30'h00000000; @@ -140463,7 +150270,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, \fsm_state$next = 3'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \fsm_state$next = 3'h0; @@ -140490,7 +150297,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, \jtag_wb__dat_w$next = jtag_wb_datasr__o; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \jtag_wb__dat_w$next = 32'd0; @@ -140519,7 +150326,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, \jtag_wb_datasr__i$next = jtag_wb__dat_r; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \jtag_wb_datasr__i$next = 32'd0; @@ -140564,7 +150371,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, \dmi0__addr_i$next = \$479 [3:0]; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \dmi0__addr_i$next = 4'h0; @@ -140617,7 +150424,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, \fsm_state$467$next = 3'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \fsm_state$467$next = 3'h0; @@ -140644,7 +150451,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, \dmi0__din$next = dmi0_datasr__o; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \dmi0__din$next = 64'h0000000000000000; @@ -140673,7 +150480,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, \dmi0_datasr__i$next = dmi0__dout; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \dmi0_datasr__i$next = 64'h0000000000000000; @@ -140690,7 +150497,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, 1'h1: { \wb_sram_en$next , \wb_dcache_en$next , \wb_icache_en$next } = sr5__o; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: begin @@ -140722,7 +150529,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, 3'b?1?: \io_sr$next = { io_sr[128:0], TAP_bus__tdi }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (posjtag_rst) 1'h1: \io_sr$next = 130'h000000000000000000000000000000000; @@ -140743,7 +150550,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, 3'b1??: \io_bd$next = io_sr; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (negjtag_rst) 1'h1: \io_bd$next = 130'h000000000000000000000000000000000; @@ -140937,10 +150744,10 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.l0" *) (* generator = "nMigen" *) -module l0(coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, \ldst_port0_exc_$signal , \ldst_port0_exc_$signal$1 , \ldst_port0_exc_$signal$2 , \ldst_port0_exc_$signal$3 , \ldst_port0_exc_$signal$4 , \ldst_port0_exc_$signal$5 , \ldst_port0_exc_$signal$6 , \ldst_port0_exc_$signal$7 , ldst_port0_addr_ok_o, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, wb_dcache_en, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) +module l0(coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, \ldst_port0_exc_$signal , \ldst_port0_exc_$signal$1 , \ldst_port0_exc_$signal$2 , \ldst_port0_exc_$signal$3 , \ldst_port0_exc_$signal$4 , \ldst_port0_exc_$signal$5 , \ldst_port0_exc_$signal$6 , \ldst_port0_exc_$signal$7 , ldst_port0_addr_ok_o, ldst_port0_msr_pr, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, wb_dcache_en, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, coresync_clk); + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) input dbus__ack; @@ -140960,67 +150767,69 @@ module l0(coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_ output dbus__stb; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) output dbus__we; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [95:0] ldst_port0_addr_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input ldst_port0_addr_i_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" *) output ldst_port0_addr_ok_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" *) output ldst_port0_busy_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103" *) input [3:0] ldst_port0_data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) output \ldst_port0_exc_$signal ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) output \ldst_port0_exc_$signal$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) output \ldst_port0_exc_$signal$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) output \ldst_port0_exc_$signal$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) output \ldst_port0_exc_$signal$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) output \ldst_port0_exc_$signal$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) output \ldst_port0_exc_$signal$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) output \ldst_port0_exc_$signal$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" *) - input ldst_port0_is_ld_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *) + input ldst_port0_is_ld_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:100" *) input ldst_port0_is_st_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] ldst_port0_ld_data_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output ldst_port0_ld_data_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:120" *) + input ldst_port0_msr_pr; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [63:0] ldst_port0_st_data_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input ldst_port0_st_data_i_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [47:0] pimem_ldst_port0_addr_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pimem_ldst_port0_addr_i_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" *) wire pimem_ldst_port0_addr_ok_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" *) wire pimem_ldst_port0_busy_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103" *) wire [3:0] pimem_ldst_port0_data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \pimem_ldst_port0_exc_$signal ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" *) - wire pimem_ldst_port0_is_ld_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *) + wire pimem_ldst_port0_is_ld_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:100" *) wire pimem_ldst_port0_is_st_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] pimem_ldst_port0_ld_data_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pimem_ldst_port0_ld_data_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] pimem_ldst_port0_st_data_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire pimem_ldst_port0_st_data_i_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:69" *) wire [63:0] pimem_m_ld_data_o; @@ -141072,6 +150881,7 @@ module l0(coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_ .\ldst_port0_ld_data_o$15 (pimem_ldst_port0_ld_data_o), .ldst_port0_ld_data_o_ok(ldst_port0_ld_data_o_ok), .\ldst_port0_ld_data_o_ok$16 (pimem_ldst_port0_ld_data_o_ok), + .ldst_port0_msr_pr(ldst_port0_msr_pr), .ldst_port0_st_data_i(ldst_port0_st_data_i), .\ldst_port0_st_data_i$18 (pimem_ldst_port0_st_data_i), .ldst_port0_st_data_i_ok(ldst_port0_st_data_i_ok), @@ -141130,7 +150940,7 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.l0.l0" *) (* generator = "nMigen" *) -module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, \ldst_port0_exc_$signal , \ldst_port0_exc_$signal$1 , \ldst_port0_exc_$signal$2 , \ldst_port0_exc_$signal$3 , \ldst_port0_exc_$signal$4 , \ldst_port0_exc_$signal$5 , \ldst_port0_exc_$signal$6 , \ldst_port0_exc_$signal$7 , ldst_port0_addr_ok_o, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, \ldst_port0_is_ld_i$8 , \ldst_port0_is_st_i$9 , \ldst_port0_busy_o$10 , \ldst_port0_data_len$11 , \ldst_port0_addr_i$12 , \ldst_port0_addr_i_ok$13 , \ldst_port0_addr_ok_o$14 , \ldst_port0_ld_data_o$15 , \ldst_port0_ld_data_o_ok$16 , \ldst_port0_st_data_i_ok$17 , \ldst_port0_st_data_i$18 , \ldst_port0_exc_$signal$19 , coresync_clk); +module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, \ldst_port0_exc_$signal , \ldst_port0_exc_$signal$1 , \ldst_port0_exc_$signal$2 , \ldst_port0_exc_$signal$3 , \ldst_port0_exc_$signal$4 , \ldst_port0_exc_$signal$5 , \ldst_port0_exc_$signal$6 , \ldst_port0_exc_$signal$7 , ldst_port0_addr_ok_o, ldst_port0_msr_pr, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, \ldst_port0_is_ld_i$8 , \ldst_port0_is_st_i$9 , \ldst_port0_busy_o$10 , \ldst_port0_data_len$11 , \ldst_port0_addr_i$12 , \ldst_port0_addr_i_ok$13 , \ldst_port0_addr_ok_o$14 , \ldst_port0_ld_data_o$15 , \ldst_port0_ld_data_o_ok$16 , \ldst_port0_st_data_i_ok$17 , \ldst_port0_st_data_i$18 , \ldst_port0_exc_$signal$19 , coresync_clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" *) wire \$20 ; @@ -141142,13 +150952,13 @@ module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_ wire \$26 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" *) wire \$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136" *) - wire [95:0] \$31 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136" *) - wire [95:0] \$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:138" *) + wire [95:0] \$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:138" *) + wire [95:0] \$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) reg \idx_l$23 = 1'h0; @@ -141160,115 +150970,127 @@ module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_ reg idx_l_r_idx_l; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) reg idx_l_s_idx_l; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [95:0] ldst_port0_addr_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [47:0] \ldst_port0_addr_i$12 ; reg [47:0] \ldst_port0_addr_i$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input ldst_port0_addr_i_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output \ldst_port0_addr_i_ok$13 ; reg \ldst_port0_addr_i_ok$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" *) output ldst_port0_addr_ok_o; reg ldst_port0_addr_ok_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" *) input \ldst_port0_addr_ok_o$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" *) output ldst_port0_busy_o; reg ldst_port0_busy_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" *) input \ldst_port0_busy_o$10 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:128" *) reg ldst_port0_cache_paradox; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:128" *) - wire \ldst_port0_cache_paradox$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" *) + wire \ldst_port0_cache_paradox$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103" *) input [3:0] ldst_port0_data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103" *) output [3:0] \ldst_port0_data_len$11 ; reg [3:0] \ldst_port0_data_len$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) output \ldst_port0_exc_$signal ; reg \ldst_port0_exc_$signal ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) output \ldst_port0_exc_$signal$1 ; reg \ldst_port0_exc_$signal$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) input \ldst_port0_exc_$signal$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) output \ldst_port0_exc_$signal$2 ; reg \ldst_port0_exc_$signal$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) output \ldst_port0_exc_$signal$3 ; reg \ldst_port0_exc_$signal$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) - wire \ldst_port0_exc_$signal$33 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) - wire \ldst_port0_exc_$signal$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) - wire \ldst_port0_exc_$signal$35 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \ldst_port0_exc_$signal$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \ldst_port0_exc_$signal$37 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \ldst_port0_exc_$signal$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \ldst_port0_exc_$signal$39 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) output \ldst_port0_exc_$signal$4 ; reg \ldst_port0_exc_$signal$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) + wire \ldst_port0_exc_$signal$40 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) + wire \ldst_port0_exc_$signal$41 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) + wire \ldst_port0_exc_$signal$42 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) output \ldst_port0_exc_$signal$5 ; reg \ldst_port0_exc_$signal$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) output \ldst_port0_exc_$signal$6 ; reg \ldst_port0_exc_$signal$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) output \ldst_port0_exc_$signal$7 ; reg \ldst_port0_exc_$signal$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107" *) reg ldst_port0_go_die_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" *) - wire \ldst_port0_go_die_i$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107" *) + wire \ldst_port0_go_die_i$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:118" *) + reg ldst_port0_is_dcbz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:118" *) + wire \ldst_port0_is_dcbz$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *) input ldst_port0_is_ld_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *) output \ldst_port0_is_ld_i$8 ; reg \ldst_port0_is_ld_i$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:119" *) + reg ldst_port0_is_nc; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:119" *) + wire \ldst_port0_is_nc$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:100" *) input ldst_port0_is_st_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:100" *) output \ldst_port0_is_st_i$9 ; reg \ldst_port0_is_st_i$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] ldst_port0_ld_data_o; reg [63:0] ldst_port0_ld_data_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [63:0] \ldst_port0_ld_data_o$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output ldst_port0_ld_data_o_ok; reg ldst_port0_ld_data_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input \ldst_port0_ld_data_o_ok$16 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:126" *) reg ldst_port0_ldst_error; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:126" *) - wire \ldst_port0_ldst_error$41 ; + wire \ldst_port0_ldst_error$44 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123" *) reg ldst_port0_mmu_done; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123" *) - wire \ldst_port0_mmu_done$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire \ldst_port0_mmu_done$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:120" *) + input ldst_port0_msr_pr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:120" *) + reg \ldst_port0_msr_pr$35 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [63:0] ldst_port0_st_data_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] \ldst_port0_st_data_i$18 ; reg [63:0] \ldst_port0_st_data_i$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input ldst_port0_st_data_i_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output \ldst_port0_st_data_i_ok$17 ; reg \ldst_port0_st_data_i_ok$17 ; (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" *) @@ -141314,6 +151136,26 @@ module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_ .r_reset(reset_l_r_reset), .s_reset(reset_l_s_reset) ); + always @* begin + if (\initial ) begin end + \ldst_port0_data_len$11 = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *) + casez (idx_l_q_idx_l) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */ + 1'h1: + \ldst_port0_data_len$11 = ldst_port0_data_len; + endcase + end + always @* begin + if (\initial ) begin end + ldst_port0_go_die_i = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *) + casez (idx_l_q_idx_l) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */ + 1'h1: + ldst_port0_go_die_i = \ldst_port0_go_die_i$32 ; + endcase + end always @* begin if (\initial ) begin end \ldst_port0_addr_i$12 = 48'h000000000000; @@ -141321,7 +151163,7 @@ module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_ casez (idx_l_q_idx_l) /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */ 1'h1: - \ldst_port0_addr_i$12 = \$32 [47:0]; + \ldst_port0_addr_i$12 = \$34 [47:0]; endcase end always @* begin @@ -141345,6 +151187,16 @@ module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_ { \ldst_port0_st_data_i_ok$17 , \ldst_port0_st_data_i$18 } = { ldst_port0_st_data_i_ok, ldst_port0_st_data_i }; endcase end + always @* begin + if (\initial ) begin end + \ldst_port0_msr_pr$35 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *) + casez (idx_l_q_idx_l) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */ + 1'h1: + \ldst_port0_msr_pr$35 = ldst_port0_msr_pr; + endcase + end always @* begin if (\initial ) begin end ldst_port0_ld_data_o = 64'h0000000000000000; @@ -141366,6 +151218,21 @@ module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_ ldst_port0_busy_o = \ldst_port0_busy_o$10 ; endcase end + always @* begin + if (\initial ) begin end + \idx_l$23$next = \idx_l$23 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (idx_l_q_idx_l) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \idx_l$23$next = pick_o; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + casez (coresync_rst) + 1'h1: + \idx_l$23$next = 1'h0; + endcase + end always @* begin if (\initial ) begin end ldst_port0_addr_ok_o = 1'h0; @@ -141390,32 +151257,27 @@ module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_ casez (idx_l_q_idx_l) /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */ 1'h1: - { \ldst_port0_exc_$signal$7 , \ldst_port0_exc_$signal$6 , \ldst_port0_exc_$signal$5 , \ldst_port0_exc_$signal$4 , \ldst_port0_exc_$signal$3 , \ldst_port0_exc_$signal$2 , \ldst_port0_exc_$signal$1 , \ldst_port0_exc_$signal } = { \ldst_port0_exc_$signal$39 , \ldst_port0_exc_$signal$38 , \ldst_port0_exc_$signal$37 , \ldst_port0_exc_$signal$36 , \ldst_port0_exc_$signal$35 , \ldst_port0_exc_$signal$34 , \ldst_port0_exc_$signal$33 , \ldst_port0_exc_$signal$19 }; + { \ldst_port0_exc_$signal$7 , \ldst_port0_exc_$signal$6 , \ldst_port0_exc_$signal$5 , \ldst_port0_exc_$signal$4 , \ldst_port0_exc_$signal$3 , \ldst_port0_exc_$signal$2 , \ldst_port0_exc_$signal$1 , \ldst_port0_exc_$signal } = { \ldst_port0_exc_$signal$19 , \ldst_port0_exc_$signal$42 , \ldst_port0_exc_$signal$41 , \ldst_port0_exc_$signal$40 , \ldst_port0_exc_$signal$39 , \ldst_port0_exc_$signal$38 , \ldst_port0_exc_$signal$37 , \ldst_port0_exc_$signal$36 }; endcase end always @* begin if (\initial ) begin end - \idx_l$23$next = \idx_l$23 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + ldst_port0_mmu_done = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *) casez (idx_l_q_idx_l) - /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ - 1'h1: - \idx_l$23$next = pick_o; - endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) - casez (coresync_rst) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */ 1'h1: - \idx_l$23$next = 1'h0; + ldst_port0_mmu_done = \ldst_port0_mmu_done$43 ; endcase end always @* begin if (\initial ) begin end - ldst_port0_mmu_done = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *) - casez (idx_l_q_idx_l) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */ + idx_l_s_idx_l = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" *) + casez (\$26 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" */ 1'h1: - ldst_port0_mmu_done = \ldst_port0_mmu_done$40 ; + idx_l_s_idx_l = 1'h1; endcase end always @* begin @@ -141425,7 +151287,7 @@ module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_ casez (idx_l_q_idx_l) /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */ 1'h1: - ldst_port0_ldst_error = \ldst_port0_ldst_error$41 ; + ldst_port0_ldst_error = \ldst_port0_ldst_error$44 ; endcase end always @* begin @@ -141435,17 +151297,7 @@ module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_ casez (idx_l_q_idx_l) /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */ 1'h1: - ldst_port0_cache_paradox = \ldst_port0_cache_paradox$42 ; - endcase - end - always @* begin - if (\initial ) begin end - idx_l_s_idx_l = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" *) - casez (\$26 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" */ - 1'h1: - idx_l_s_idx_l = 1'h1; + ldst_port0_cache_paradox = \ldst_port0_cache_paradox$45 ; endcase end always @* begin @@ -141505,37 +151357,39 @@ module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_ end always @* begin if (\initial ) begin end - \ldst_port0_data_len$11 = 4'h0; + ldst_port0_is_nc = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *) casez (idx_l_q_idx_l) /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */ 1'h1: - \ldst_port0_data_len$11 = ldst_port0_data_len; + ldst_port0_is_nc = \ldst_port0_is_nc$30 ; endcase end always @* begin if (\initial ) begin end - ldst_port0_go_die_i = 1'h0; + ldst_port0_is_dcbz = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *) casez (idx_l_q_idx_l) /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" */ 1'h1: - ldst_port0_go_die_i = \ldst_port0_go_die_i$30 ; + ldst_port0_is_dcbz = \ldst_port0_is_dcbz$31 ; endcase end assign \$22 = \$24 ; - assign \$32 = ldst_port0_addr_i; - assign \ldst_port0_go_die_i$30 = 1'h0; - assign \ldst_port0_exc_$signal$33 = 1'h0; - assign \ldst_port0_exc_$signal$34 = 1'h0; - assign \ldst_port0_exc_$signal$35 = 1'h0; + assign \$34 = ldst_port0_addr_i; + assign \ldst_port0_is_nc$30 = 1'h0; + assign \ldst_port0_is_dcbz$31 = 1'h0; + assign \ldst_port0_go_die_i$32 = 1'h0; assign \ldst_port0_exc_$signal$36 = 1'h0; assign \ldst_port0_exc_$signal$37 = 1'h0; assign \ldst_port0_exc_$signal$38 = 1'h0; assign \ldst_port0_exc_$signal$39 = 1'h0; - assign \ldst_port0_mmu_done$40 = 1'h0; - assign \ldst_port0_ldst_error$41 = 1'h0; - assign \ldst_port0_cache_paradox$42 = 1'h0; + assign \ldst_port0_exc_$signal$40 = 1'h0; + assign \ldst_port0_exc_$signal$41 = 1'h0; + assign \ldst_port0_exc_$signal$42 = 1'h0; + assign \ldst_port0_mmu_done$43 = 1'h0; + assign \ldst_port0_ldst_error$44 = 1'h0; + assign \ldst_port0_cache_paradox$45 = 1'h0; assign \reset_delay$next = reset_l_q_reset; assign pick_i = \$20 ; endmodule @@ -141560,9 +151414,9 @@ module ld_active(coresync_rst, r_ld_active, s_ld_active, q_ld_active, coresync_c wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -141591,7 +151445,7 @@ module ld_active(coresync_rst, r_ld_active, s_ld_active, q_ld_active, coresync_c always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -141604,199 +151458,201 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.ldst0" *) (* generator = "nMigen" *) -module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, oper_i_ldst_ldst0__insn_type, oper_i_ldst_ldst0__fn_unit, oper_i_ldst_ldst0__imm_data__data, oper_i_ldst_ldst0__imm_data__ok, oper_i_ldst_ldst0__zero_a, oper_i_ldst_ldst0__rc__rc, oper_i_ldst_ldst0__rc__ok, oper_i_ldst_ldst0__oe__oe, oper_i_ldst_ldst0__oe__ok, oper_i_ldst_ldst0__is_32bit, oper_i_ldst_ldst0__is_signed, oper_i_ldst_ldst0__data_len, oper_i_ldst_ldst0__byte_reverse, oper_i_ldst_ldst0__sign_extend, oper_i_ldst_ldst0__ldst_mode, oper_i_ldst_ldst0__insn, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src3_i, src1_i, cu_wr__rel_o, cu_wr__go_i, o, ea, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, \ldst_port0_exc_$signal , \ldst_port0_exc_$signal$1 , \ldst_port0_exc_$signal$2 , \ldst_port0_exc_$signal$3 , \ldst_port0_exc_$signal$4 , \ldst_port0_exc_$signal$5 , \ldst_port0_exc_$signal$6 , \ldst_port0_exc_$signal$7 , ldst_port0_addr_ok_o, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, coresync_clk); +module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, \exc_o_$signal , oper_i_ldst_ldst0__insn_type, oper_i_ldst_ldst0__fn_unit, oper_i_ldst_ldst0__imm_data__data, oper_i_ldst_ldst0__imm_data__ok, oper_i_ldst_ldst0__zero_a, oper_i_ldst_ldst0__rc__rc, oper_i_ldst_ldst0__rc__ok, oper_i_ldst_ldst0__oe__oe, oper_i_ldst_ldst0__oe__ok, oper_i_ldst_ldst0__msr, oper_i_ldst_ldst0__is_32bit, oper_i_ldst_ldst0__is_signed, oper_i_ldst_ldst0__data_len, oper_i_ldst_ldst0__byte_reverse, oper_i_ldst_ldst0__sign_extend, oper_i_ldst_ldst0__ldst_mode, oper_i_ldst_ldst0__insn, oper_i_ldst_ldst0__sv_pred_sz, oper_i_ldst_ldst0__sv_pred_dz, oper_i_ldst_ldst0__sv_saturate, oper_i_ldst_ldst0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src3_i, src1_i, cu_wr__rel_o, cu_wr__go_i, o, ea, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, \ldst_port0_exc_$signal , \ldst_port0_exc_$signal$1 , \ldst_port0_exc_$signal$2 , \ldst_port0_exc_$signal$3 , \ldst_port0_exc_$signal$4 , \ldst_port0_exc_$signal$5 , \ldst_port0_exc_$signal$6 , \ldst_port0_exc_$signal$7 , ldst_port0_addr_ok_o, ldst_port0_msr_pr, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, coresync_clk); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:302" *) wire \$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" *) wire \$100 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:449" *) wire \$102 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:449" *) wire \$104 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:453" *) wire \$106 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:456" *) wire \$108 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:456" *) wire \$110 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:456" *) wire \$112 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:457" *) wire \$114 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" *) wire \$116 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" *) wire \$118 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:303" *) wire \$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" *) wire \$120 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" *) wire \$122 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" *) wire \$124 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *) wire \$126 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:316" *) wire \$128 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *) wire \$130 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *) wire \$132 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *) wire \$134 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469" *) wire \$136 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469" *) wire \$138 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:304" *) wire \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469" *) wire \$140 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" *) wire \$142 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" *) wire \$144 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *) - wire \$145 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" *) + wire \$146 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" *) wire \$147 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *) - wire \$150 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" *) + wire \$149 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" *) wire \$152 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:473" *) wire \$154 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:473" *) wire \$156 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:475" *) wire \$158 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:305" *) wire \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:475" *) wire \$160 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:475" *) wire \$162 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:316" *) wire \$164 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:482" *) - wire [2:0] \$166 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" *) - wire \$167 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:482" *) - wire [2:0] \$169 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489" *) - wire \$171 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:490" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:487" *) + wire \$166 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:492" *) + wire [2:0] \$168 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:316" *) + wire \$169 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:492" *) + wire [2:0] \$171 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499" *) wire \$173 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" *) - wire [95:0] \$175 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:494" *) - wire \$177 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:500" *) + wire \$175 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406" *) + wire [95:0] \$177 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:504" *) + wire \$179 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:306" *) wire [2:0] \$18 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) - wire [63:0] \$186 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) wire [63:0] \$188 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) wire [63:0] \$190 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" *) - wire \$192 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) - wire [63:0] \$194 ; + wire [63:0] \$192 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" *) + wire \$194 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) wire [63:0] \$196 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) wire [63:0] \$198 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:307" *) wire \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:308" *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) + wire [63:0] \$200 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:314" *) wire \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:315" *) wire \$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:312" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:318" *) wire \$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:313" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:319" *) wire \$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:350" *) wire \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:350" *) wire \$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:350" *) wire \$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:350" *) wire \$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:360" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:366" *) wire [1:0] \$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:363" *) wire \$39 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:316" *) wire \$41 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:363" *) wire \$43 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:363" *) wire \$45 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:363" *) wire \$47 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:316" *) wire \$49 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:363" *) wire \$51 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:363" *) wire \$53 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:360" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:366" *) wire [1:0] \$55 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:367" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:373" *) wire \$57 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:368" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:374" *) wire \$59 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:378" *) wire \$61 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:378" *) wire \$63 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) wire [63:0] \$65 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) wire [63:0] \$67 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:412" *) wire [63:0] \$69 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:417" *) wire [63:0] \$71 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:420" *) wire [64:0] \$73 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:414" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:420" *) wire [64:0] \$74 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) wire [2:0] \$76 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) wire [1:0] \$78 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301" *) wire \$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) wire [2:0] \$80 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) wire [2:0] \$82 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) wire [2:0] \$84 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" *) wire \$86 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" *) wire \$88 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" *) wire \$90 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" *) wire \$92 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" *) wire \$93 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) - wire \$96 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" *) + wire \$96 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" *) wire \$98 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:272" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:278" *) wire addr_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406" *) wire [63:0] addr_r; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire adr_l_q_adr; @@ -141812,17 +151668,19 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, wire alu_l_r_alu; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alu_l_s_alu; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:280" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:286" *) wire [63:0] alu_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:271" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:277" *) reg alu_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:271" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:277" *) wire \alu_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:276" *) wire alu_valid; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:452" *) + wire cancel; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) input cu_ad__go_i; @@ -141858,35 +151716,35 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, reg [63:0] dest1_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) reg [63:0] dest2_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] ea; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) reg [63:0] ea_r = 64'h0000000000000000; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) reg [63:0] \ea_r$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) - wire \exc_$signal ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) - wire \exc_$signal$179 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) - wire \exc_$signal$180 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) - wire \exc_$signal$181 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) - wire \exc_$signal$182 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) - wire \exc_$signal$183 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) - wire \exc_$signal$184 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) - wire \exc_$signal$185 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:110" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) + output \exc_o_$signal ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) + wire \exc_o_$signal$181 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) + wire \exc_o_$signal$182 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) + wire \exc_o_$signal$183 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) + wire \exc_o_$signal$184 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) + wire \exc_o_$signal$185 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) + wire \exc_o_$signal$186 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) + wire \exc_o_$signal$187 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:116" *) wire ld_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:273" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:279" *) wire ld_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:281" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:287" *) reg [63:0] ldd_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:385" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" *) wire [63:0] ldd_r; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:17" *) reg [63:0] lddata_r; @@ -141894,52 +151752,54 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, reg [63:0] ldo_r = 64'h0000000000000000; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) reg [63:0] \ldo_r$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [95:0] ldst_port0_addr_i; reg [95:0] ldst_port0_addr_i = 96'h000000000000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [95:0] \ldst_port0_addr_i$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output ldst_port0_addr_i_ok; reg ldst_port0_addr_i_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \ldst_port0_addr_i_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" *) input ldst_port0_addr_ok_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" *) input ldst_port0_busy_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103" *) output [3:0] ldst_port0_data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) input \ldst_port0_exc_$signal ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) input \ldst_port0_exc_$signal$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) input \ldst_port0_exc_$signal$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) input \ldst_port0_exc_$signal$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) input \ldst_port0_exc_$signal$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) input \ldst_port0_exc_$signal$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) input \ldst_port0_exc_$signal$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) input \ldst_port0_exc_$signal$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" *) - output ldst_port0_is_ld_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *) + output ldst_port0_is_ld_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:100" *) output ldst_port0_is_st_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [63:0] ldst_port0_ld_data_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input ldst_port0_ld_data_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:120" *) + output ldst_port0_msr_pr; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] ldst_port0_st_data_i; reg [63:0] ldst_port0_st_data_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output ldst_port0_st_data_i_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:114" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:120" *) wire load_mem_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) wire lod_l_qn_lod; @@ -141955,11 +151815,11 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, reg \lsd_l_r_lsd$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire lsd_l_s_lsd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:266" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:272" *) wire op_is_ld; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:267" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:273" *) wire op_is_st; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire opc_l_q_opc; @@ -141971,32 +151831,39 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, reg opc_l_s_opc = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) reg \opc_l_s_opc$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_ldst_ldst0__SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_ldst_ldst0__byte_reverse; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [3:0] oper_i_ldst_ldst0__data_len; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] oper_i_ldst_ldst0__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] oper_i_ldst_ldst0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] oper_i_ldst_ldst0__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_ldst_ldst0__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] oper_i_ldst_ldst0__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -142073,69 +151940,92 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] oper_i_ldst_ldst0__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_ldst_ldst0__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_ldst_ldst0__is_signed; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] oper_i_ldst_ldst0__ldst_mode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [63:0] oper_i_ldst_ldst0__msr; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_ldst_ldst0__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_ldst_ldst0__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_ldst_ldst0__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_ldst_ldst0__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_ldst_ldst0__sign_extend; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_ldst_ldst0__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_ldst_ldst0__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_ldst_ldst0__sv_saturate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_ldst_ldst0__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] oper_r__SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \oper_r__SV_Ptype$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg oper_r__byte_reverse = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \oper_r__byte_reverse$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [3:0] oper_r__data_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [3:0] \oper_r__data_len$next ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] oper_r__fn_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] \oper_r__fn_unit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] oper_r__fn_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] \oper_r__fn_unit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] oper_r__imm_data__data = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] \oper_r__imm_data__data$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg oper_r__imm_data__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \oper_r__imm_data__ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] oper_r__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] \oper_r__insn$next ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -142212,74 +152102,96 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] oper_r__insn_type = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] \oper_r__insn_type$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg oper_r__is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \oper_r__is_32bit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg oper_r__is_signed = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \oper_r__is_signed$next ; (* enum_base_type = "LDSTMode" *) (* enum_value_00 = "NONE" *) (* enum_value_01 = "update" *) (* enum_value_10 = "cix" *) (* enum_value_11 = "cx" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [1:0] oper_r__ldst_mode = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [1:0] \oper_r__ldst_mode$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [63:0] oper_r__msr = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [63:0] \oper_r__msr$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg oper_r__oe__oe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \oper_r__oe__oe$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg oper_r__oe__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \oper_r__oe__ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg oper_r__rc__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \oper_r__rc__ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg oper_r__rc__rc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \oper_r__rc__rc$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg oper_r__sign_extend = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \oper_r__sign_extend$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg oper_r__sv_pred_dz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \oper_r__sv_pred_dz$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg oper_r__sv_pred_sz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \oper_r__sv_pred_sz$next ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] oper_r__sv_saturate = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \oper_r__sv_saturate$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg oper_r__zero_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \oper_r__zero_a$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:303" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" *) reg p_st_go = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:303" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" *) wire \p_st_go$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:276" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:282" *) wire rd_done; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:275" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:281" *) wire rda_any; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" *) wire reset_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297" *) wire reset_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:287" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:293" *) wire reset_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298" *) wire [2:0] reset_r; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:293" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299" *) wire reset_s; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:289" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" *) wire reset_u; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:288" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:294" *) wire reset_w; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" *) reg [63:0] revnorev; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire rst_l_q_rst; @@ -142289,11 +152201,11 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, wire rst_l_s_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) input [63:0] src1_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:405" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411" *) wire [63:0] src1_or_z; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) input [63:0] src2_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416" *) wire [63:0] src2_or_imm; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) input [63:0] src3_i; @@ -142307,19 +152219,19 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, reg [2:0] src_l_s_src = 3'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) reg [2:0] \src_l_s_src$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:398" *) reg [63:0] src_r0 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:398" *) reg [63:0] \src_r0$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:398" *) reg [63:0] src_r1 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:398" *) reg [63:0] \src_r1$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:398" *) reg [63:0] src_r2 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:398" *) reg [63:0] \src_r2$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:111" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:117" *) wire st_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:17" *) reg [63:0] stdata_r; @@ -142331,7 +152243,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, reg \sto_l_r_sto$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire sto_l_s_sto; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:115" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:121" *) wire stwd_mem_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire upd_l_q_upd; @@ -142343,9 +152255,9 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, reg upd_l_s_upd = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) reg \upd_l_s_upd$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:274" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:280" *) wire wr_any; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:277" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:283" *) wire wr_reset; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire wri_l_q_wri; @@ -142355,101 +152267,102 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, reg \wri_l_r_wri$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire wri_l_s_wri; - assign \$100 = alu_valid & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" *) \$98 ; - assign \$102 = alu_valid & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" *) adr_l_q_adr; - assign \$104 = \$102 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" *) cu_busy_o; - assign \$106 = sto_l_q_sto & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" *) cu_busy_o; - assign \$108 = \$106 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" *) rd_done; - assign \$10 = cu_done_o | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" *) cu_go_die_i; - assign \$110 = \$108 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" *) op_is_st; - assign \$112 = \$110 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447" *) cu_shadown_i; - assign \$114 = rd_done & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" *) wri_l_q_wri; - assign \$116 = \$114 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" *) cu_busy_o; - assign \$118 = \$116 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" *) lod_l_qn_lod; - assign \$120 = \$118 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" *) op_is_ld; - assign \$122 = \$120 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" *) cu_shadown_i; - assign \$124 = upd_l_q_upd & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" *) cu_busy_o; - assign \$126 = oper_r__ldst_mode == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" *) 2'h1; - assign \$128 = \$124 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" *) \$126 ; - assign \$12 = cu_wr__go_i[0] | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297" *) cu_go_die_i; - assign \$130 = \$128 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" *) alu_valid; - assign \$132 = \$130 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" *) cu_shadown_i; - assign \$134 = cu_st__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" *) p_st_go; - assign \$136 = \$134 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" *) cu_wr__go_i[0]; - assign \$138 = \$136 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" *) cu_wr__go_i[1]; - assign \$140 = rst_l_q_rst & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *) cu_busy_o; - assign \$142 = \$140 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *) cu_shadown_i; - assign \$145 = cu_st__rel_o | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *) cu_wr__rel_o[0]; - assign \$147 = \$145 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *) cu_wr__rel_o[1]; - assign \$144 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *) \$147 ; - assign \$14 = cu_wr__go_i[1] | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298" *) cu_go_die_i; - assign \$150 = \$142 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *) \$144 ; - assign \$152 = lod_l_qn_lod | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" *) op_is_st; - assign \$154 = \$150 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" *) \$152 ; - assign \$156 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *) ldst_port0_busy_o; - assign \$158 = \$156 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *) op_is_ld; - assign \$160 = wr_reset & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *) \$158 ; - assign \$162 = oper_r__ldst_mode == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" *) 2'h1; - assign \$164 = \$162 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" *) cu_wr__go_i[1]; - assign \$167 = oper_r__ldst_mode == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" *) 2'h1; - assign \$16 = cu_st__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299" *) cu_go_die_i; - assign \$169 = { cu_busy_o, cu_busy_o, cu_busy_o } & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:482" *) { \$167 , op_is_ld }; - assign \$171 = op_is_ld & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489" *) cu_busy_o; - assign \$173 = op_is_st & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:490" *) cu_busy_o; - assign \$175 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" *) addr_r; - assign \$177 = alu_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:494" *) lsd_l_q_lsd; - assign \$186 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) ldst_port0_ld_data_o[7:0]; - assign \$188 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) { ldst_port0_ld_data_o[7:0], ldst_port0_ld_data_o[15:8] }; - assign \$18 = cu_rd__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i }; - assign \$190 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) { ldst_port0_ld_data_o[7:0], ldst_port0_ld_data_o[15:8], ldst_port0_ld_data_o[23:16], ldst_port0_ld_data_o[31:24] }; - assign \$192 = oper_r__data_len == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" *) 2'h2; - assign \$194 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) src_r2[7:0]; - assign \$196 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) { src_r2[7:0], src_r2[15:8] }; - assign \$198 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) { src_r2[7:0], src_r2[15:8], src_r2[23:16], src_r2[31:24] }; - assign \$20 = cu_ad__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301" *) cu_go_die_i; - assign \$22 = oper_r__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:308" *) 7'h26; - assign \$24 = oper_r__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" *) 7'h25; - assign \$26 = op_is_ld & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:312" *) cu_ad__go_i; - assign \$28 = op_is_st & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:313" *) cu_st__go_i; - assign \$30 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" *) alu_valid; - assign \$32 = alu_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" *) \$30 ; - assign \$34 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" *) rda_any; - assign \$36 = \$32 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" *) \$34 ; - assign \$39 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *) ldst_port0_busy_o; - assign \$41 = oper_r__ldst_mode == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" *) 2'h1; - assign \$43 = \$39 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *) \$41 ; - assign \$45 = wr_reset | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *) \$43 ; - assign \$47 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *) ldst_port0_busy_o; - assign \$49 = oper_r__ldst_mode == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" *) 2'h1; - assign \$51 = \$47 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *) \$49 ; - assign \$53 = wr_reset | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *) \$51 ; - assign \$55 = reset_w | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:360" *) { \$45 , \$53 }; - assign \$57 = addr_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:367" *) op_is_st; - assign \$59 = reset_s | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:368" *) p_st_go; - assign \$61 = reset_s | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" *) p_st_go; - assign \$63 = \$61 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" *) ld_ok; + assign \$100 = alu_valid & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" *) \$98 ; + assign \$102 = alu_valid & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:449" *) adr_l_q_adr; + assign \$104 = \$102 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:449" *) cu_busy_o; + assign \$106 = \exc_o_$signal | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:453" *) cu_shadown_i; + assign \$108 = sto_l_q_sto & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:456" *) cu_busy_o; + assign \$10 = cu_done_o | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:302" *) cu_go_die_i; + assign \$110 = \$108 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:456" *) rd_done; + assign \$112 = \$110 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:456" *) op_is_st; + assign \$114 = \$112 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:457" *) cancel; + assign \$116 = rd_done & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" *) wri_l_q_wri; + assign \$118 = \$116 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" *) cu_busy_o; + assign \$120 = \$118 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" *) lod_l_qn_lod; + assign \$122 = \$120 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" *) op_is_ld; + assign \$124 = \$122 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" *) cancel; + assign \$126 = upd_l_q_upd & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *) cu_busy_o; + assign \$128 = oper_r__ldst_mode == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:316" *) 2'h1; + assign \$12 = cu_wr__go_i[0] | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:303" *) cu_go_die_i; + assign \$130 = \$126 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *) \$128 ; + assign \$132 = \$130 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *) alu_valid; + assign \$134 = \$132 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *) cancel; + assign \$136 = cu_st__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469" *) p_st_go; + assign \$138 = \$136 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469" *) cu_wr__go_i[0]; + assign \$140 = \$138 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469" *) cu_wr__go_i[1]; + assign \$142 = rst_l_q_rst & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" *) cu_busy_o; + assign \$144 = \$142 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" *) cancel; + assign \$147 = cu_st__rel_o | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" *) cu_wr__rel_o[0]; + assign \$14 = cu_wr__go_i[1] | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:304" *) cu_go_die_i; + assign \$149 = \$147 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" *) cu_wr__rel_o[1]; + assign \$146 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" *) \$149 ; + assign \$152 = \$144 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" *) \$146 ; + assign \$154 = lod_l_qn_lod | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:473" *) op_is_st; + assign \$156 = \$152 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:473" *) \$154 ; + assign \$158 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:475" *) ldst_port0_busy_o; + assign \$160 = \$158 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:475" *) op_is_ld; + assign \$162 = wr_reset & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:475" *) \$160 ; + assign \$164 = oper_r__ldst_mode == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:316" *) 2'h1; + assign \$166 = \$164 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:487" *) cu_wr__go_i[1]; + assign \$16 = cu_st__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:305" *) cu_go_die_i; + assign \$169 = oper_r__ldst_mode == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:316" *) 2'h1; + assign \$171 = { cu_busy_o, cu_busy_o, cu_busy_o } & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:492" *) { \$169 , op_is_ld }; + assign \$173 = op_is_ld & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499" *) cu_busy_o; + assign \$175 = op_is_st & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:500" *) cu_busy_o; + assign \$177 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406" *) addr_r; + assign \$179 = alu_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:504" *) lsd_l_q_lsd; + assign \$188 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) ldst_port0_ld_data_o[7:0]; + assign \$18 = cu_rd__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:306" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i }; + assign \$190 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) { ldst_port0_ld_data_o[7:0], ldst_port0_ld_data_o[15:8] }; + assign \$192 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) { ldst_port0_ld_data_o[7:0], ldst_port0_ld_data_o[15:8], ldst_port0_ld_data_o[23:16], ldst_port0_ld_data_o[31:24] }; + assign \$194 = oper_r__data_len == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" *) 2'h2; + assign \$196 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) src_r2[7:0]; + assign \$198 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) { src_r2[7:0], src_r2[15:8] }; + assign \$200 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) { src_r2[7:0], src_r2[15:8], src_r2[23:16], src_r2[31:24] }; + assign \$20 = cu_ad__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:307" *) cu_go_die_i; + assign \$22 = oper_r__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:314" *) 7'h26; + assign \$24 = oper_r__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:315" *) 7'h25; + assign \$26 = op_is_ld & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:318" *) cu_ad__go_i; + assign \$28 = op_is_st & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:319" *) cu_st__go_i; + assign \$30 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:350" *) alu_valid; + assign \$32 = alu_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:350" *) \$30 ; + assign \$34 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:350" *) rda_any; + assign \$36 = \$32 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:350" *) \$34 ; + assign \$39 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:363" *) ldst_port0_busy_o; + assign \$41 = oper_r__ldst_mode == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:316" *) 2'h1; + assign \$43 = \$39 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:363" *) \$41 ; + assign \$45 = wr_reset | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:363" *) \$43 ; + assign \$47 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:363" *) ldst_port0_busy_o; + assign \$49 = oper_r__ldst_mode == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:316" *) 2'h1; + assign \$51 = \$47 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:363" *) \$49 ; + assign \$53 = wr_reset | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:363" *) \$51 ; + assign \$55 = reset_w | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:366" *) { \$45 , \$53 }; + assign \$57 = addr_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:373" *) op_is_st; + assign \$59 = reset_s | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:374" *) p_st_go; + assign \$61 = reset_s | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:378" *) p_st_go; + assign \$63 = \$61 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:378" *) ld_ok; assign \$65 = ld_ok ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) ldd_o : ldo_r; assign \$67 = alu_l_q_alu ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) alu_o : ea_r; - assign \$69 = oper_r__zero_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406" *) 64'h0000000000000000 : src_r0; - assign \$71 = oper_r__imm_data__ok ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411" *) oper_r__imm_data__data : src_r1; - assign \$74 = src1_or_z + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:414" *) src2_or_imm; - assign \$76 = src_l_q_src & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" *) { cu_busy_o, cu_busy_o, cu_busy_o }; - assign \$78 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" *) { oper_r__imm_data__ok, oper_r__zero_a }; - assign \$80 = \$76 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" *) \$78 ; - assign \$82 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" *) cu_rdmaskn_i; - assign \$84 = \$80 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" *) \$82 ; - assign \$86 = src_l_q_src[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" *) cu_busy_o; - assign \$88 = \$86 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" *) op_is_st; - assign \$8 = cu_issue_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" *) cu_go_die_i; - assign \$90 = cu_rd__go_i[0] | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431" *) cu_rd__go_i[1]; - assign \$93 = cu_rd__rel_o[0] | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) cu_rd__rel_o[1]; - assign \$92 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) \$93 ; - assign \$96 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) \$92 ; - assign \$98 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" *) cu_rd__rel_o[2]; + assign \$69 = oper_r__zero_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:412" *) 64'h0000000000000000 : src_r0; + assign \$71 = oper_r__imm_data__ok ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:417" *) oper_r__imm_data__data : src_r1; + assign \$74 = src1_or_z + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:420" *) src2_or_imm; + assign \$76 = src_l_q_src & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) { cu_busy_o, cu_busy_o, cu_busy_o }; + assign \$78 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) { oper_r__imm_data__ok, oper_r__zero_a }; + assign \$80 = \$76 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) \$78 ; + assign \$82 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) cu_rdmaskn_i; + assign \$84 = \$80 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) \$82 ; + assign \$86 = src_l_q_src[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" *) cu_busy_o; + assign \$88 = \$86 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" *) op_is_st; + assign \$8 = cu_issue_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301" *) cu_go_die_i; + assign \$90 = cu_rd__go_i[0] | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" *) cu_rd__go_i[1]; + assign \$93 = cu_rd__rel_o[0] | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" *) cu_rd__rel_o[1]; + assign \$92 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" *) \$93 ; + assign \$96 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" *) \$92 ; + assign \$98 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" *) cu_rd__rel_o[2]; always @(posedge coresync_clk) ldst_port0_addr_i_ok <= \ldst_port0_addr_i_ok$next ; always @(posedge coresync_clk) - ldst_port0_addr_i <= \$175 ; + ldst_port0_addr_i <= \$177 ; always @(posedge coresync_clk) alu_ok <= \$96 ; always @(posedge coresync_clk) @@ -142480,6 +152393,8 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, oper_r__oe__oe <= \oper_r__oe__oe$next ; always @(posedge coresync_clk) oper_r__oe__ok <= \oper_r__oe__ok$next ; + always @(posedge coresync_clk) + oper_r__msr <= \oper_r__msr$next ; always @(posedge coresync_clk) oper_r__is_32bit <= \oper_r__is_32bit$next ; always @(posedge coresync_clk) @@ -142494,6 +152409,14 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, oper_r__ldst_mode <= \oper_r__ldst_mode$next ; always @(posedge coresync_clk) oper_r__insn <= \oper_r__insn$next ; + always @(posedge coresync_clk) + oper_r__sv_pred_sz <= \oper_r__sv_pred_sz$next ; + always @(posedge coresync_clk) + oper_r__sv_pred_dz <= \oper_r__sv_pred_dz$next ; + always @(posedge coresync_clk) + oper_r__sv_saturate <= \oper_r__sv_saturate$next ; + always @(posedge coresync_clk) + oper_r__SV_Ptype <= \oper_r__SV_Ptype$next ; always @(posedge coresync_clk) lsd_l_r_lsd <= \lsd_l_r_lsd$next ; always @(posedge coresync_clk) @@ -142586,10 +152509,69 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, .r_wri(wri_l_r_wri), .s_wri(wri_l_s_wri) ); + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:521" *) + casez (oper_r__sign_extend) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:521" */ + 1'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" *) + casez (\$194 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" */ + 1'h1: + ldd_o = { revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15:0] }; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:525" */ + default: + ldd_o = { revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31:0] }; + endcase + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:527" */ + default: + ldd_o = revnorev; + endcase + end + always @* begin + if (\initial ) begin end + stdata_r = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:535" *) + casez (oper_r__byte_reverse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:535" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:30" *) + casez (oper_r__data_len) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:32" */ + 4'h1: + stdata_r = \$196 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:32" */ + 4'h2: + stdata_r = \$198 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:32" */ + 4'h4: + stdata_r = \$200 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:32" */ + 4'h8: + stdata_r = { src_r2[7:0], src_r2[15:8], src_r2[23:16], src_r2[31:24], src_r2[39:32], src_r2[47:40], src_r2[55:48], src_r2[63:56] }; + endcase + endcase + end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:535" *) + casez (oper_r__byte_reverse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:535" */ + 1'h1: + ldst_port0_st_data_i = stdata_r; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:540" */ + default: + ldst_port0_st_data_i = src_r2; + endcase + end always @* begin if (\initial ) begin end \opc_l_s_opc$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_s_opc$next = 1'h0; @@ -142598,7 +152580,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \opc_l_r_opc$next = reset_o; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_r_opc$next = 1'h1; @@ -142607,7 +152589,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_s_src$next = 3'h0; @@ -142616,7 +152598,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \src_l_r_src$next = reset_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_r_src$next = 3'h7; @@ -142625,7 +152607,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \adr_l_r_adr$next = reset_a; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \adr_l_r_adr$next = 1'h1; @@ -142634,7 +152616,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \wri_l_r_wri$next = \$38 [0]; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \wri_l_r_wri$next = 1'h1; @@ -142643,7 +152625,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \upd_l_s_upd$next = reset_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \upd_l_s_upd$next = 1'h0; @@ -142652,7 +152634,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \upd_l_r_upd$next = reset_u; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \upd_l_r_upd$next = 1'h1; @@ -142661,7 +152643,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \sto_l_r_sto$next = \$59 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \sto_l_r_sto$next = 1'h1; @@ -142670,7 +152652,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \lsd_l_r_lsd$next = \$63 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \lsd_l_r_lsd$next = 1'h1; @@ -142687,6 +152669,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, \oper_r__rc__ok$next = oper_r__rc__ok; \oper_r__oe__oe$next = oper_r__oe__oe; \oper_r__oe__ok$next = oper_r__oe__ok; + \oper_r__msr$next = oper_r__msr; \oper_r__is_32bit$next = oper_r__is_32bit; \oper_r__is_signed$next = oper_r__is_signed; \oper_r__data_len$next = oper_r__data_len; @@ -142694,19 +152677,23 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, \oper_r__sign_extend$next = oper_r__sign_extend; \oper_r__ldst_mode$next = oper_r__ldst_mode; \oper_r__insn$next = oper_r__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:379" *) + \oper_r__sv_pred_sz$next = oper_r__sv_pred_sz; + \oper_r__sv_pred_dz$next = oper_r__sv_pred_dz; + \oper_r__sv_saturate$next = oper_r__sv_saturate; + \oper_r__SV_Ptype$next = oper_r__SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:385" *) casez (cu_issue_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:379" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:385" */ 1'h1: - { \oper_r__insn$next , \oper_r__ldst_mode$next , \oper_r__sign_extend$next , \oper_r__byte_reverse$next , \oper_r__data_len$next , \oper_r__is_signed$next , \oper_r__is_32bit$next , \oper_r__oe__ok$next , \oper_r__oe__oe$next , \oper_r__rc__ok$next , \oper_r__rc__rc$next , \oper_r__zero_a$next , \oper_r__imm_data__ok$next , \oper_r__imm_data__data$next , \oper_r__fn_unit$next , \oper_r__insn_type$next } = { oper_i_ldst_ldst0__insn, oper_i_ldst_ldst0__ldst_mode, oper_i_ldst_ldst0__sign_extend, oper_i_ldst_ldst0__byte_reverse, oper_i_ldst_ldst0__data_len, oper_i_ldst_ldst0__is_signed, oper_i_ldst_ldst0__is_32bit, oper_i_ldst_ldst0__oe__ok, oper_i_ldst_ldst0__oe__oe, oper_i_ldst_ldst0__rc__ok, oper_i_ldst_ldst0__rc__rc, oper_i_ldst_ldst0__zero_a, oper_i_ldst_ldst0__imm_data__ok, oper_i_ldst_ldst0__imm_data__data, oper_i_ldst_ldst0__fn_unit, oper_i_ldst_ldst0__insn_type }; + { \oper_r__SV_Ptype$next , \oper_r__sv_saturate$next , \oper_r__sv_pred_dz$next , \oper_r__sv_pred_sz$next , \oper_r__insn$next , \oper_r__ldst_mode$next , \oper_r__sign_extend$next , \oper_r__byte_reverse$next , \oper_r__data_len$next , \oper_r__is_signed$next , \oper_r__is_32bit$next , \oper_r__msr$next , \oper_r__oe__ok$next , \oper_r__oe__oe$next , \oper_r__rc__ok$next , \oper_r__rc__rc$next , \oper_r__zero_a$next , \oper_r__imm_data__ok$next , \oper_r__imm_data__data$next , \oper_r__fn_unit$next , \oper_r__insn_type$next } = { oper_i_ldst_ldst0__SV_Ptype, oper_i_ldst_ldst0__sv_saturate, oper_i_ldst_ldst0__sv_pred_dz, oper_i_ldst_ldst0__sv_pred_sz, oper_i_ldst_ldst0__insn, oper_i_ldst_ldst0__ldst_mode, oper_i_ldst_ldst0__sign_extend, oper_i_ldst_ldst0__byte_reverse, oper_i_ldst_ldst0__data_len, oper_i_ldst_ldst0__is_signed, oper_i_ldst_ldst0__is_32bit, oper_i_ldst_ldst0__msr, oper_i_ldst_ldst0__oe__ok, oper_i_ldst_ldst0__oe__oe, oper_i_ldst_ldst0__rc__ok, oper_i_ldst_ldst0__rc__rc, oper_i_ldst_ldst0__zero_a, oper_i_ldst_ldst0__imm_data__ok, oper_i_ldst_ldst0__imm_data__data, oper_i_ldst_ldst0__fn_unit, oper_i_ldst_ldst0__insn_type }; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:381" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:387" *) casez (cu_done_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:381" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:387" */ 1'h1: - { \oper_r__insn$next , \oper_r__ldst_mode$next , \oper_r__sign_extend$next , \oper_r__byte_reverse$next , \oper_r__data_len$next , \oper_r__is_signed$next , \oper_r__is_32bit$next , \oper_r__oe__ok$next , \oper_r__oe__oe$next , \oper_r__rc__ok$next , \oper_r__rc__rc$next , \oper_r__zero_a$next , \oper_r__imm_data__ok$next , \oper_r__imm_data__data$next , \oper_r__fn_unit$next , \oper_r__insn_type$next } = 133'h0000000000000000000000000000000000; + { \oper_r__SV_Ptype$next , \oper_r__sv_saturate$next , \oper_r__sv_pred_dz$next , \oper_r__sv_pred_sz$next , \oper_r__insn$next , \oper_r__ldst_mode$next , \oper_r__sign_extend$next , \oper_r__byte_reverse$next , \oper_r__data_len$next , \oper_r__is_signed$next , \oper_r__is_32bit$next , \oper_r__msr$next , \oper_r__oe__ok$next , \oper_r__oe__oe$next , \oper_r__rc__ok$next , \oper_r__rc__rc$next , \oper_r__zero_a$next , \oper_r__imm_data__ok$next , \oper_r__imm_data__data$next , \oper_r__fn_unit$next , \oper_r__insn_type$next } = 204'h000000000000000000000000000000000000000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -142732,15 +152719,15 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \src_r0$next = src_r0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:399" *) casez (cu_rd__go_i[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:399" */ 1'h1: \src_r0$next = src1_i; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:401" *) casez (cu_issue_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:401" */ 1'h1: \src_r0$next = 64'h0000000000000000; endcase @@ -142748,15 +152735,15 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \src_r1$next = src_r1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:399" *) casez (cu_rd__go_i[1]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:399" */ 1'h1: \src_r1$next = src2_i; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:401" *) casez (cu_issue_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:401" */ 1'h1: \src_r1$next = 64'h0000000000000000; endcase @@ -142764,15 +152751,15 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \src_r2$next = src_r2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:399" *) casez (cu_rd__go_i[2]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:399" */ 1'h1: \src_r2$next = src3_i; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:401" *) casez (cu_issue_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:401" */ 1'h1: \src_r2$next = 64'h0000000000000000; endcase @@ -142790,9 +152777,9 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end dest1_o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:482" *) casez (cu_wr__go_i[0]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:482" */ 1'h1: dest1_o = ldd_r; endcase @@ -142800,17 +152787,17 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end dest2_o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" *) - casez (\$164 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:487" *) + casez (\$166 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:487" */ 1'h1: dest2_o = addr_r; endcase end always @* begin if (\initial ) begin end - \ldst_port0_addr_i_ok$next = \$177 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \ldst_port0_addr_i_ok$next = \$179 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \ldst_port0_addr_i_ok$next = 1'h0; @@ -142819,21 +152806,21 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end lddata_r = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:500" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:512" *) casez (oper_r__byte_reverse) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:500" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:512" */ 1'h1: (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:30" *) casez (oper_r__data_len) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:32" */ 4'h1: - lddata_r = \$186 ; + lddata_r = \$188 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:32" */ 4'h2: - lddata_r = \$188 ; + lddata_r = \$190 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:32" */ 4'h4: - lddata_r = \$190 ; + lddata_r = \$192 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:32" */ 4'h8: lddata_r = { ldst_port0_ld_data_o[7:0], ldst_port0_ld_data_o[15:8], ldst_port0_ld_data_o[23:16], ldst_port0_ld_data_o[31:24], ldst_port0_ld_data_o[39:32], ldst_port0_ld_data_o[47:40], ldst_port0_ld_data_o[55:48], ldst_port0_ld_data_o[63:56] }; @@ -142843,97 +152830,40 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:500" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:512" *) casez (oper_r__byte_reverse) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:500" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:512" */ 1'h1: revnorev = lddata_r; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:505" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:517" */ default: revnorev = ldst_port0_ld_data_o; endcase end - always @* begin - if (\initial ) begin end - (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:509" *) - casez (oper_r__sign_extend) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:509" */ - 1'h1: - (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" *) - casez (\$192 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" */ - 1'h1: - ldd_o = { revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15:0] }; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:513" */ - default: - ldd_o = { revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31:0] }; - endcase - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:515" */ - default: - ldd_o = revnorev; - endcase - end - always @* begin - if (\initial ) begin end - stdata_r = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" *) - casez (oper_r__byte_reverse) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" */ - 1'h1: - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:30" *) - casez (oper_r__data_len) - /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:32" */ - 4'h1: - stdata_r = \$194 ; - /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:32" */ - 4'h2: - stdata_r = \$196 ; - /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:32" */ - 4'h4: - stdata_r = \$198 ; - /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:32" */ - 4'h8: - stdata_r = { src_r2[7:0], src_r2[15:8], src_r2[23:16], src_r2[31:24], src_r2[39:32], src_r2[47:40], src_r2[55:48], src_r2[63:56] }; - endcase - endcase - end - always @* begin - if (\initial ) begin end - (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" *) - casez (oper_r__byte_reverse) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" */ - 1'h1: - ldst_port0_st_data_i = stdata_r; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:528" */ - default: - ldst_port0_st_data_i = src_r2; - endcase - end assign \$38 = \$55 ; assign \$73 = \$74 ; - assign \$166 = \$169 ; + assign \$168 = \$171 ; assign cu_go_die_i = 1'h0; assign cu_shadown_i = 1'h1; assign ldst_port0_st_data_i_ok = cu_st__go_i; assign ld_ok = ldst_port0_ld_data_o_ok; + assign ldst_port0_msr_pr = oper_r__msr[14]; assign addr_ok = ldst_port0_addr_ok_o; - assign { \exc_$signal$185 , \exc_$signal$184 , \exc_$signal$183 , \exc_$signal$182 , \exc_$signal$181 , \exc_$signal$180 , \exc_$signal$179 , \exc_$signal } = { \ldst_port0_exc_$signal$7 , \ldst_port0_exc_$signal$6 , \ldst_port0_exc_$signal$5 , \ldst_port0_exc_$signal$4 , \ldst_port0_exc_$signal$3 , \ldst_port0_exc_$signal$2 , \ldst_port0_exc_$signal$1 , \ldst_port0_exc_$signal }; - assign \ldst_port0_addr_i$next = \$175 ; + assign { \exc_o_$signal , \exc_o_$signal$187 , \exc_o_$signal$186 , \exc_o_$signal$185 , \exc_o_$signal$184 , \exc_o_$signal$183 , \exc_o_$signal$182 , \exc_o_$signal$181 } = { \ldst_port0_exc_$signal$7 , \ldst_port0_exc_$signal$6 , \ldst_port0_exc_$signal$5 , \ldst_port0_exc_$signal$4 , \ldst_port0_exc_$signal$3 , \ldst_port0_exc_$signal$2 , \ldst_port0_exc_$signal$1 , \ldst_port0_exc_$signal }; + assign \ldst_port0_addr_i$next = \$177 ; assign ldst_port0_data_len = oper_r__data_len; - assign ldst_port0_is_st_i = \$173 ; - assign ldst_port0_is_ld_i = \$171 ; - assign cu_wrmask_o = \$169 [1:0]; + assign ldst_port0_is_st_i = \$175 ; + assign ldst_port0_is_ld_i = \$173 ; + assign cu_wrmask_o = \$171 [1:0]; assign ea = dest2_o; assign o = dest1_o; - assign cu_done_o = \$160 ; - assign wr_reset = \$154 ; - assign wr_any = \$138 ; - assign cu_wr__rel_o[1] = \$132 ; - assign cu_wr__rel_o[0] = \$122 ; - assign cu_st__rel_o = \$112 ; + assign cu_done_o = \$162 ; + assign wr_reset = \$156 ; + assign wr_any = \$140 ; + assign cu_wr__rel_o[1] = \$134 ; + assign cu_wr__rel_o[0] = \$124 ; + assign cu_st__rel_o = \$114 ; + assign cancel = \$106 ; assign cu_ad__rel_o = \$104 ; assign rd_done = \$100 ; assign alu_valid = \$96 ; @@ -143566,7 +153496,7 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.l0.pimem.lenexp" *) (* generator = "nMigen" *) -module lenexp(addr_i, lexp_o, rexp_o, len_i); +module lenexp(len_i, addr_i, rexp_o, lexp_o); (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" *) wire [20:0] \$1 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" *) @@ -143617,9 +153547,9 @@ module lod_l(coresync_rst, s_lod, r_lod, qn_lod, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -143648,7 +153578,7 @@ module lod_l(coresync_rst, s_lod, r_lod, qn_lod, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -143661,7 +153591,7 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0" *) (* generator = "nMigen" *) -module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical0__fn_unit, oper_i_alu_logical0__imm_data__data, oper_i_alu_logical0__imm_data__ok, oper_i_alu_logical0__rc__rc, oper_i_alu_logical0__rc__ok, oper_i_alu_logical0__oe__oe, oper_i_alu_logical0__oe__ok, oper_i_alu_logical0__invert_in, oper_i_alu_logical0__zero_a, oper_i_alu_logical0__input_carry, oper_i_alu_logical0__invert_out, oper_i_alu_logical0__write_cr0, oper_i_alu_logical0__output_carry, oper_i_alu_logical0__is_32bit, oper_i_alu_logical0__is_signed, oper_i_alu_logical0__data_len, oper_i_alu_logical0__insn, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, cr_a_ok, dest2_o, coresync_clk); +module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical0__fn_unit, oper_i_alu_logical0__imm_data__data, oper_i_alu_logical0__imm_data__ok, oper_i_alu_logical0__rc__rc, oper_i_alu_logical0__rc__ok, oper_i_alu_logical0__oe__oe, oper_i_alu_logical0__oe__ok, oper_i_alu_logical0__invert_in, oper_i_alu_logical0__zero_a, oper_i_alu_logical0__input_carry, oper_i_alu_logical0__invert_out, oper_i_alu_logical0__write_cr0, oper_i_alu_logical0__output_carry, oper_i_alu_logical0__is_32bit, oper_i_alu_logical0__is_signed, oper_i_alu_logical0__data_len, oper_i_alu_logical0__insn, oper_i_alu_logical0__sv_pred_sz, oper_i_alu_logical0__sv_pred_dz, oper_i_alu_logical0__sv_saturate, oper_i_alu_logical0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, cr_a_ok, dest2_o, coresync_clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *) wire \$1 ; @@ -143803,50 +153733,59 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical reg \alu_l_r_alu$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alu_l_s_alu; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [3:0] alu_logical0_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] alu_logical0_logical_op__SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \alu_logical0_logical_op__SV_Ptype$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [3:0] alu_logical0_logical_op__data_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [3:0] \alu_logical0_logical_op__data_len$next ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] alu_logical0_logical_op__fn_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] \alu_logical0_logical_op__fn_unit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] alu_logical0_logical_op__fn_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] \alu_logical0_logical_op__fn_unit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] alu_logical0_logical_op__imm_data__data = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] \alu_logical0_logical_op__imm_data__data$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_logical0_logical_op__imm_data__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_logical0_logical_op__imm_data__ok$next ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [1:0] alu_logical0_logical_op__input_carry = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [1:0] \alu_logical0_logical_op__input_carry$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] alu_logical0_logical_op__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] \alu_logical0_logical_op__insn$next ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -143923,69 +153862,87 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] alu_logical0_logical_op__insn_type = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] \alu_logical0_logical_op__insn_type$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_logical0_logical_op__invert_in = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_logical0_logical_op__invert_in$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_logical0_logical_op__invert_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_logical0_logical_op__invert_out$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_logical0_logical_op__is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_logical0_logical_op__is_32bit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_logical0_logical_op__is_signed = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_logical0_logical_op__is_signed$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_logical0_logical_op__oe__oe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_logical0_logical_op__oe__oe$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_logical0_logical_op__oe__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_logical0_logical_op__oe__ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_logical0_logical_op__output_carry = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_logical0_logical_op__output_carry$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_logical0_logical_op__rc__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_logical0_logical_op__rc__ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_logical0_logical_op__rc__rc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_logical0_logical_op__rc__rc$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg alu_logical0_logical_op__sv_pred_dz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \alu_logical0_logical_op__sv_pred_dz$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg alu_logical0_logical_op__sv_pred_sz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \alu_logical0_logical_op__sv_pred_sz$next ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] alu_logical0_logical_op__sv_saturate = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \alu_logical0_logical_op__sv_saturate$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_logical0_logical_op__write_cr0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_logical0_logical_op__write_cr0$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_logical0_logical_op__zero_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_logical0_logical_op__zero_a$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) wire alu_logical0_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire alu_logical0_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] alu_logical0_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire alu_logical0_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) wire alu_logical0_p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] alu_logical0_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] alu_logical0_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire alu_logical0_xer_so; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" *) wire alu_pulse; @@ -143999,11 +153956,11 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_a_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) output cu_busy_o; @@ -144049,7 +154006,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) output [3:0] dest2_o; reg [3:0] dest2_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire opc_l_q_opc; @@ -144061,36 +154018,43 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical reg opc_l_s_opc = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) reg \opc_l_s_opc$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_logical0__SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [3:0] oper_i_alu_logical0__data_len; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] oper_i_alu_logical0__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] oper_i_alu_logical0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] oper_i_alu_logical0__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_logical0__imm_data__ok; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] oper_i_alu_logical0__input_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] oper_i_alu_logical0__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -144167,29 +154131,41 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] oper_i_alu_logical0__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_logical0__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_logical0__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_logical0__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_logical0__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_logical0__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_logical0__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_logical0__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_logical0__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_logical0__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_logical0__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_logical0__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_logical0__sv_saturate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_logical0__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_logical0__zero_a; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *) reg [1:0] prev_wr_go = 2'h0; @@ -144382,6 +154358,14 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical alu_logical0_logical_op__data_len <= \alu_logical0_logical_op__data_len$next ; always @(posedge coresync_clk) alu_logical0_logical_op__insn <= \alu_logical0_logical_op__insn$next ; + always @(posedge coresync_clk) + alu_logical0_logical_op__sv_pred_sz <= \alu_logical0_logical_op__sv_pred_sz$next ; + always @(posedge coresync_clk) + alu_logical0_logical_op__sv_pred_dz <= \alu_logical0_logical_op__sv_pred_dz$next ; + always @(posedge coresync_clk) + alu_logical0_logical_op__sv_saturate <= \alu_logical0_logical_op__sv_saturate$next ; + always @(posedge coresync_clk) + alu_logical0_logical_op__SV_Ptype <= \alu_logical0_logical_op__SV_Ptype$next ; always @(posedge coresync_clk) req_l_r_req <= \req_l_r_req$next ; always @(posedge coresync_clk) @@ -144420,6 +154404,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical .coresync_rst(coresync_rst), .cr_a(alu_logical0_cr_a), .cr_a_ok(cr_a_ok), + .logical_op__SV_Ptype(alu_logical0_logical_op__SV_Ptype), .logical_op__data_len(alu_logical0_logical_op__data_len), .logical_op__fn_unit(alu_logical0_logical_op__fn_unit), .logical_op__imm_data__data(alu_logical0_logical_op__imm_data__data), @@ -144436,6 +154421,9 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical .logical_op__output_carry(alu_logical0_logical_op__output_carry), .logical_op__rc__ok(alu_logical0_logical_op__rc__ok), .logical_op__rc__rc(alu_logical0_logical_op__rc__rc), + .logical_op__sv_pred_dz(alu_logical0_logical_op__sv_pred_dz), + .logical_op__sv_pred_sz(alu_logical0_logical_op__sv_pred_sz), + .logical_op__sv_saturate(alu_logical0_logical_op__sv_saturate), .logical_op__write_cr0(alu_logical0_logical_op__write_cr0), .logical_op__zero_a(alu_logical0_logical_op__zero_a), .n_ready_i(alu_logical0_n_ready_i), @@ -144502,7 +154490,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \rok_l_s_rdok$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_s_rdok$next = 1'h0; @@ -144511,7 +154499,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \rok_l_r_rdok$next = \$63 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_r_rdok$next = 1'h1; @@ -144520,7 +154508,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \rst_l_s_rst$next = all_rd; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_s_rst$next = 1'h0; @@ -144529,7 +154517,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \rst_l_r_rst$next = rst_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_r_rst$next = 1'h1; @@ -144538,7 +154526,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \opc_l_s_opc$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_s_opc$next = 1'h0; @@ -144547,7 +154535,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \opc_l_r_opc$next = req_done; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_r_opc$next = 1'h1; @@ -144556,7 +154544,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_s_src$next = 3'h0; @@ -144565,7 +154553,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \src_l_r_src$next = reset_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_r_src$next = 3'h7; @@ -144574,7 +154562,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \req_l_s_req$next = \$65 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_s_req$next = 2'h0; @@ -144583,7 +154571,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \req_l_r_req$next = \$67 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_r_req$next = 2'h3; @@ -144609,13 +154597,17 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical \alu_logical0_logical_op__is_signed$next = alu_logical0_logical_op__is_signed; \alu_logical0_logical_op__data_len$next = alu_logical0_logical_op__data_len; \alu_logical0_logical_op__insn$next = alu_logical0_logical_op__insn; + \alu_logical0_logical_op__sv_pred_sz$next = alu_logical0_logical_op__sv_pred_sz; + \alu_logical0_logical_op__sv_pred_dz$next = alu_logical0_logical_op__sv_pred_dz; + \alu_logical0_logical_op__sv_saturate$next = alu_logical0_logical_op__sv_saturate; + \alu_logical0_logical_op__SV_Ptype$next = alu_logical0_logical_op__SV_Ptype; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *) casez (cu_issue_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" */ 1'h1: - { \alu_logical0_logical_op__insn$next , \alu_logical0_logical_op__data_len$next , \alu_logical0_logical_op__is_signed$next , \alu_logical0_logical_op__is_32bit$next , \alu_logical0_logical_op__output_carry$next , \alu_logical0_logical_op__write_cr0$next , \alu_logical0_logical_op__invert_out$next , \alu_logical0_logical_op__input_carry$next , \alu_logical0_logical_op__zero_a$next , \alu_logical0_logical_op__invert_in$next , \alu_logical0_logical_op__oe__ok$next , \alu_logical0_logical_op__oe__oe$next , \alu_logical0_logical_op__rc__ok$next , \alu_logical0_logical_op__rc__rc$next , \alu_logical0_logical_op__imm_data__ok$next , \alu_logical0_logical_op__imm_data__data$next , \alu_logical0_logical_op__fn_unit$next , \alu_logical0_logical_op__insn_type$next } = { oper_i_alu_logical0__insn, oper_i_alu_logical0__data_len, oper_i_alu_logical0__is_signed, oper_i_alu_logical0__is_32bit, oper_i_alu_logical0__output_carry, oper_i_alu_logical0__write_cr0, oper_i_alu_logical0__invert_out, oper_i_alu_logical0__input_carry, oper_i_alu_logical0__zero_a, oper_i_alu_logical0__invert_in, oper_i_alu_logical0__oe__ok, oper_i_alu_logical0__oe__oe, oper_i_alu_logical0__rc__ok, oper_i_alu_logical0__rc__rc, oper_i_alu_logical0__imm_data__ok, oper_i_alu_logical0__imm_data__data, oper_i_alu_logical0__fn_unit, oper_i_alu_logical0__insn_type }; + { \alu_logical0_logical_op__SV_Ptype$next , \alu_logical0_logical_op__sv_saturate$next , \alu_logical0_logical_op__sv_pred_dz$next , \alu_logical0_logical_op__sv_pred_sz$next , \alu_logical0_logical_op__insn$next , \alu_logical0_logical_op__data_len$next , \alu_logical0_logical_op__is_signed$next , \alu_logical0_logical_op__is_32bit$next , \alu_logical0_logical_op__output_carry$next , \alu_logical0_logical_op__write_cr0$next , \alu_logical0_logical_op__invert_out$next , \alu_logical0_logical_op__input_carry$next , \alu_logical0_logical_op__zero_a$next , \alu_logical0_logical_op__invert_in$next , \alu_logical0_logical_op__oe__ok$next , \alu_logical0_logical_op__oe__oe$next , \alu_logical0_logical_op__rc__ok$next , \alu_logical0_logical_op__rc__rc$next , \alu_logical0_logical_op__imm_data__ok$next , \alu_logical0_logical_op__imm_data__data$next , \alu_logical0_logical_op__fn_unit$next , \alu_logical0_logical_op__insn_type$next } = { oper_i_alu_logical0__SV_Ptype, oper_i_alu_logical0__sv_saturate, oper_i_alu_logical0__sv_pred_dz, oper_i_alu_logical0__sv_pred_sz, oper_i_alu_logical0__insn, oper_i_alu_logical0__data_len, oper_i_alu_logical0__is_signed, oper_i_alu_logical0__is_32bit, oper_i_alu_logical0__output_carry, oper_i_alu_logical0__write_cr0, oper_i_alu_logical0__invert_out, oper_i_alu_logical0__input_carry, oper_i_alu_logical0__zero_a, oper_i_alu_logical0__invert_in, oper_i_alu_logical0__oe__ok, oper_i_alu_logical0__oe__oe, oper_i_alu_logical0__rc__ok, oper_i_alu_logical0__rc__rc, oper_i_alu_logical0__imm_data__ok, oper_i_alu_logical0__imm_data__data, oper_i_alu_logical0__fn_unit, oper_i_alu_logical0__insn_type }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -144644,7 +154636,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical 1'h1: { \data_r0__o_ok$next , \data_r0__o$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r0__o_ok$next = 1'h0; @@ -144666,7 +154658,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical 1'h1: { \data_r1__cr_a_ok$next , \data_r1__cr_a$next } = 5'h00; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r1__cr_a_ok$next = 1'h0; @@ -144705,7 +154697,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \alui_l_r_alui$next = \$89 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alui_l_r_alui$next = 1'h1; @@ -144714,7 +154706,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \alu_l_r_alu$next = \$91 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alu_l_r_alu$next = 1'h1; @@ -144743,7 +154735,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \prev_wr_go$next = \$19 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \prev_wr_go$next = 2'h0; @@ -144785,94 +154777,108 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1" *) (* generator = "nMigen" *) -module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, o, o_ok, cr_a, cr_a_ok, xer_so, xer_so_ok, p_valid_i, p_ready_o, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , ra, rb, \xer_so$20 , coresync_clk); +module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__SV_Ptype, o, o_ok, cr_a, cr_a_ok, xer_so, xer_so_ok, p_valid_i, p_ready_o, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__SV_Ptype$23 , ra, rb, \xer_so$24 , coresync_clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) - wire \$64 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + wire \$76 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [3:0] cr_a; reg [3:0] cr_a = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [3:0] \cr_a$87 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [3:0] \cr_a$89 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [3:0] \cr_a$103 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [3:0] \cr_a$105 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [3:0] \cr_a$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_a_ok; reg cr_a_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \cr_a_ok$88 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \cr_a_ok$90 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \cr_a_ok$104 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \cr_a_ok$106 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \cr_a_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] input_logical_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \input_logical_op__SV_Ptype$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [3:0] input_logical_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [3:0] \input_logical_op__data_len$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [3:0] \input_logical_op__data_len$42 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] input_logical_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] input_logical_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \input_logical_op__fn_unit$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \input_logical_op__fn_unit$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] input_logical_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \input_logical_op__imm_data__data$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \input_logical_op__imm_data__data$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_logical_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_logical_op__imm_data__ok$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_logical_op__imm_data__ok$29 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [1:0] input_logical_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [1:0] \input_logical_op__input_carry$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \input_logical_op__input_carry$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] input_logical_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \input_logical_op__insn$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \input_logical_op__insn$43 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -144948,7 +154954,9 @@ module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] input_logical_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -145025,178 +155033,224 @@ module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \input_logical_op__insn_type$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \input_logical_op__insn_type$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_logical_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_logical_op__invert_in$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_logical_op__invert_in$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_logical_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_logical_op__invert_out$33 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_logical_op__invert_out$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_logical_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_logical_op__is_32bit$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_logical_op__is_32bit$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_logical_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_logical_op__is_signed$37 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_logical_op__is_signed$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_logical_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_logical_op__oe__oe$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_logical_op__oe__oe$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_logical_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_logical_op__oe__ok$29 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_logical_op__oe__ok$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_logical_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_logical_op__output_carry$35 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_logical_op__output_carry$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_logical_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_logical_op__rc__ok$27 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_logical_op__rc__ok$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_logical_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_logical_op__rc__rc$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_logical_op__rc__rc$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire input_logical_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_logical_op__sv_pred_dz$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire input_logical_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_logical_op__sv_pred_sz$44 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] input_logical_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \input_logical_op__sv_saturate$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_logical_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_logical_op__write_cr0$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_logical_op__write_cr0$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_logical_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_logical_op__zero_a$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_logical_op__zero_a$35 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] input_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \input_muxid$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [1:0] \input_muxid$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] input_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \input_ra$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \input_ra$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] input_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \input_rb$41 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \input_rb$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire input_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire \input_xer_so$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire \input_xer_so$50 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] logical_op__SV_Ptype; + reg [1:0] logical_op__SV_Ptype = 2'h0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \logical_op__SV_Ptype$100 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] \logical_op__SV_Ptype$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \logical_op__SV_Ptype$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [3:0] logical_op__data_len; reg [3:0] logical_op__data_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [3:0] \logical_op__data_len$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [3:0] \logical_op__data_len$83 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [3:0] \logical_op__data_len$95 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [3:0] \logical_op__data_len$next ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] logical_op__fn_unit; - reg [13:0] logical_op__fn_unit = 14'h0000; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] logical_op__fn_unit; + reg [14:0] logical_op__fn_unit = 15'h0000; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] \logical_op__fn_unit$3 ; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] \logical_op__fn_unit$3 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \logical_op__fn_unit$68 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] \logical_op__fn_unit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \logical_op__fn_unit$80 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] \logical_op__fn_unit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] logical_op__imm_data__data; reg [63:0] logical_op__imm_data__data = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] \logical_op__imm_data__data$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \logical_op__imm_data__data$69 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \logical_op__imm_data__data$81 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] \logical_op__imm_data__data$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output logical_op__imm_data__ok; reg logical_op__imm_data__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \logical_op__imm_data__ok$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__imm_data__ok$70 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__imm_data__ok$82 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__imm_data__ok$next ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [1:0] logical_op__input_carry; reg [1:0] logical_op__input_carry = 2'h0; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] \logical_op__input_carry$12 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [1:0] \logical_op__input_carry$77 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \logical_op__input_carry$89 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [1:0] \logical_op__input_carry$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] logical_op__insn; reg [31:0] logical_op__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] \logical_op__insn$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \logical_op__insn$84 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \logical_op__insn$96 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] \logical_op__insn$next ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -145273,7 +155327,9 @@ module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] logical_op__insn_type; reg [6:0] logical_op__insn_type = 7'h00; (* enum_base_type = "MicrOp" *) @@ -145351,7 +155407,9 @@ module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] \logical_op__insn_type$2 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -145428,171 +155486,226 @@ module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \logical_op__insn_type$67 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \logical_op__insn_type$79 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] \logical_op__insn_type$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output logical_op__invert_in; reg logical_op__invert_in = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \logical_op__invert_in$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__invert_in$75 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__invert_in$87 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__invert_in$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output logical_op__invert_out; reg logical_op__invert_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \logical_op__invert_out$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__invert_out$78 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__invert_out$90 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__invert_out$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output logical_op__is_32bit; reg logical_op__is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \logical_op__is_32bit$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__is_32bit$81 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__is_32bit$93 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__is_32bit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output logical_op__is_signed; reg logical_op__is_signed = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \logical_op__is_signed$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__is_signed$82 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__is_signed$94 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__is_signed$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output logical_op__oe__oe; reg logical_op__oe__oe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__oe__oe$73 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \logical_op__oe__oe$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__oe__oe$85 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__oe__oe$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output logical_op__oe__ok; reg logical_op__oe__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__oe__ok$74 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__oe__ok$86 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \logical_op__oe__ok$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__oe__ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output logical_op__output_carry; reg logical_op__output_carry = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \logical_op__output_carry$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__output_carry$80 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__output_carry$92 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__output_carry$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output logical_op__rc__ok; reg logical_op__rc__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \logical_op__rc__ok$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__rc__ok$72 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__rc__ok$84 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__rc__ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output logical_op__rc__rc; reg logical_op__rc__rc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \logical_op__rc__rc$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__rc__rc$71 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__rc__rc$83 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__rc__rc$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output logical_op__sv_pred_dz; + reg logical_op__sv_pred_dz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input \logical_op__sv_pred_dz$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__sv_pred_dz$98 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__sv_pred_dz$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output logical_op__sv_pred_sz; + reg logical_op__sv_pred_sz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input \logical_op__sv_pred_sz$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__sv_pred_sz$97 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__sv_pred_sz$next ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] logical_op__sv_saturate; + reg [1:0] logical_op__sv_saturate = 2'h0; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] \logical_op__sv_saturate$22 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \logical_op__sv_saturate$99 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \logical_op__sv_saturate$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output logical_op__write_cr0; reg logical_op__write_cr0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \logical_op__write_cr0$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__write_cr0$79 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__write_cr0$91 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__write_cr0$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output logical_op__zero_a; reg logical_op__zero_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \logical_op__zero_a$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__zero_a$76 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__zero_a$88 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__zero_a$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] main_logical_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \main_logical_op__SV_Ptype$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [3:0] main_logical_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [3:0] \main_logical_op__data_len$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [3:0] \main_logical_op__data_len$68 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] main_logical_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] main_logical_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \main_logical_op__fn_unit$45 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \main_logical_op__fn_unit$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] main_logical_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \main_logical_op__imm_data__data$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \main_logical_op__imm_data__data$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_logical_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_logical_op__imm_data__ok$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_logical_op__imm_data__ok$55 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [1:0] main_logical_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [1:0] \main_logical_op__input_carry$54 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \main_logical_op__input_carry$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] main_logical_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \main_logical_op__insn$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \main_logical_op__insn$69 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -145668,7 +155781,9 @@ module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] main_logical_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -145745,75 +155860,97 @@ module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \main_logical_op__insn_type$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \main_logical_op__insn_type$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_logical_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_logical_op__invert_in$52 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_logical_op__invert_in$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_logical_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_logical_op__invert_out$55 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_logical_op__invert_out$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_logical_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_logical_op__is_32bit$58 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_logical_op__is_32bit$66 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_logical_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_logical_op__is_signed$59 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_logical_op__is_signed$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_logical_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_logical_op__oe__oe$50 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_logical_op__oe__oe$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_logical_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_logical_op__oe__ok$51 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_logical_op__oe__ok$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_logical_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_logical_op__output_carry$57 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_logical_op__output_carry$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_logical_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_logical_op__rc__ok$49 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_logical_op__rc__ok$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_logical_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_logical_op__rc__rc$48 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_logical_op__rc__rc$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire main_logical_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_logical_op__sv_pred_dz$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire main_logical_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_logical_op__sv_pred_sz$70 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] main_logical_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \main_logical_op__sv_saturate$72 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_logical_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_logical_op__write_cr0$56 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_logical_op__write_cr0$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_logical_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_logical_op__zero_a$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_logical_op__zero_a$61 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] main_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \main_muxid$43 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \main_muxid$51 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] main_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire main_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] main_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] main_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire main_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \main_xer_so$62 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \main_xer_so$74 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] muxid; reg [1:0] muxid = 2'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] \muxid$1 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \muxid$66 ; + wire [1:0] \muxid$78 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) reg [1:0] \muxid$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *) @@ -145822,65 +155959,55 @@ module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] o; reg [63:0] o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \o$85 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \o$101 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [63:0] \o$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output o_ok; reg o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \o_ok$86 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \o_ok$102 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \o_ok$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) input p_valid_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *) - wire \p_valid_i$63 ; + wire \p_valid_i$75 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *) wire p_valid_i_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg r_busy = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg \r_busy$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_so; reg xer_so = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - input \xer_so$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_so$91 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_so$107 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + input \xer_so$24 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \xer_so$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_so_ok; reg xer_so_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_so_ok$92 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_so_ok$93 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_so_ok$108 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_so_ok$109 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \xer_so_ok$next ; - assign \$64 = \p_valid_i$63 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; - always @(posedge coresync_clk) - xer_so <= \xer_so$next ; - always @(posedge coresync_clk) - xer_so_ok <= \xer_so_ok$next ; - always @(posedge coresync_clk) - cr_a <= \cr_a$next ; - always @(posedge coresync_clk) - cr_a_ok <= \cr_a_ok$next ; - always @(posedge coresync_clk) - o <= \o$next ; + assign \$76 = \p_valid_i$75 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; always @(posedge coresync_clk) o_ok <= \o_ok$next ; always @(posedge coresync_clk) @@ -145919,101 +156046,135 @@ module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn logical_op__data_len <= \logical_op__data_len$next ; always @(posedge coresync_clk) logical_op__insn <= \logical_op__insn$next ; + always @(posedge coresync_clk) + logical_op__sv_pred_sz <= \logical_op__sv_pred_sz$next ; + always @(posedge coresync_clk) + logical_op__sv_pred_dz <= \logical_op__sv_pred_dz$next ; + always @(posedge coresync_clk) + logical_op__sv_saturate <= \logical_op__sv_saturate$next ; + always @(posedge coresync_clk) + logical_op__SV_Ptype <= \logical_op__SV_Ptype$next ; always @(posedge coresync_clk) muxid <= \muxid$next ; always @(posedge coresync_clk) r_busy <= \r_busy$next ; + always @(posedge coresync_clk) + xer_so <= \xer_so$next ; + always @(posedge coresync_clk) + xer_so_ok <= \xer_so_ok$next ; + always @(posedge coresync_clk) + cr_a <= \cr_a$next ; + always @(posedge coresync_clk) + cr_a_ok <= \cr_a_ok$next ; + always @(posedge coresync_clk) + o <= \o$next ; \input$50 \input ( + .logical_op__SV_Ptype(input_logical_op__SV_Ptype), + .\logical_op__SV_Ptype$23 (\input_logical_op__SV_Ptype$47 ), .logical_op__data_len(input_logical_op__data_len), - .\logical_op__data_len$18 (\input_logical_op__data_len$38 ), + .\logical_op__data_len$18 (\input_logical_op__data_len$42 ), .logical_op__fn_unit(input_logical_op__fn_unit), - .\logical_op__fn_unit$3 (\input_logical_op__fn_unit$23 ), + .\logical_op__fn_unit$3 (\input_logical_op__fn_unit$27 ), .logical_op__imm_data__data(input_logical_op__imm_data__data), - .\logical_op__imm_data__data$4 (\input_logical_op__imm_data__data$24 ), + .\logical_op__imm_data__data$4 (\input_logical_op__imm_data__data$28 ), .logical_op__imm_data__ok(input_logical_op__imm_data__ok), - .\logical_op__imm_data__ok$5 (\input_logical_op__imm_data__ok$25 ), + .\logical_op__imm_data__ok$5 (\input_logical_op__imm_data__ok$29 ), .logical_op__input_carry(input_logical_op__input_carry), - .\logical_op__input_carry$12 (\input_logical_op__input_carry$32 ), + .\logical_op__input_carry$12 (\input_logical_op__input_carry$36 ), .logical_op__insn(input_logical_op__insn), - .\logical_op__insn$19 (\input_logical_op__insn$39 ), + .\logical_op__insn$19 (\input_logical_op__insn$43 ), .logical_op__insn_type(input_logical_op__insn_type), - .\logical_op__insn_type$2 (\input_logical_op__insn_type$22 ), + .\logical_op__insn_type$2 (\input_logical_op__insn_type$26 ), .logical_op__invert_in(input_logical_op__invert_in), - .\logical_op__invert_in$10 (\input_logical_op__invert_in$30 ), + .\logical_op__invert_in$10 (\input_logical_op__invert_in$34 ), .logical_op__invert_out(input_logical_op__invert_out), - .\logical_op__invert_out$13 (\input_logical_op__invert_out$33 ), + .\logical_op__invert_out$13 (\input_logical_op__invert_out$37 ), .logical_op__is_32bit(input_logical_op__is_32bit), - .\logical_op__is_32bit$16 (\input_logical_op__is_32bit$36 ), + .\logical_op__is_32bit$16 (\input_logical_op__is_32bit$40 ), .logical_op__is_signed(input_logical_op__is_signed), - .\logical_op__is_signed$17 (\input_logical_op__is_signed$37 ), + .\logical_op__is_signed$17 (\input_logical_op__is_signed$41 ), .logical_op__oe__oe(input_logical_op__oe__oe), - .\logical_op__oe__oe$8 (\input_logical_op__oe__oe$28 ), + .\logical_op__oe__oe$8 (\input_logical_op__oe__oe$32 ), .logical_op__oe__ok(input_logical_op__oe__ok), - .\logical_op__oe__ok$9 (\input_logical_op__oe__ok$29 ), + .\logical_op__oe__ok$9 (\input_logical_op__oe__ok$33 ), .logical_op__output_carry(input_logical_op__output_carry), - .\logical_op__output_carry$15 (\input_logical_op__output_carry$35 ), + .\logical_op__output_carry$15 (\input_logical_op__output_carry$39 ), .logical_op__rc__ok(input_logical_op__rc__ok), - .\logical_op__rc__ok$7 (\input_logical_op__rc__ok$27 ), + .\logical_op__rc__ok$7 (\input_logical_op__rc__ok$31 ), .logical_op__rc__rc(input_logical_op__rc__rc), - .\logical_op__rc__rc$6 (\input_logical_op__rc__rc$26 ), + .\logical_op__rc__rc$6 (\input_logical_op__rc__rc$30 ), + .logical_op__sv_pred_dz(input_logical_op__sv_pred_dz), + .\logical_op__sv_pred_dz$21 (\input_logical_op__sv_pred_dz$45 ), + .logical_op__sv_pred_sz(input_logical_op__sv_pred_sz), + .\logical_op__sv_pred_sz$20 (\input_logical_op__sv_pred_sz$44 ), + .logical_op__sv_saturate(input_logical_op__sv_saturate), + .\logical_op__sv_saturate$22 (\input_logical_op__sv_saturate$46 ), .logical_op__write_cr0(input_logical_op__write_cr0), - .\logical_op__write_cr0$14 (\input_logical_op__write_cr0$34 ), + .\logical_op__write_cr0$14 (\input_logical_op__write_cr0$38 ), .logical_op__zero_a(input_logical_op__zero_a), - .\logical_op__zero_a$11 (\input_logical_op__zero_a$31 ), + .\logical_op__zero_a$11 (\input_logical_op__zero_a$35 ), .muxid(input_muxid), - .\muxid$1 (\input_muxid$21 ), + .\muxid$1 (\input_muxid$25 ), .ra(input_ra), - .\ra$20 (\input_ra$40 ), + .\ra$24 (\input_ra$48 ), .rb(input_rb), - .\rb$21 (\input_rb$41 ), + .\rb$25 (\input_rb$49 ), .xer_so(input_xer_so), - .\xer_so$22 (\input_xer_so$42 ) + .\xer_so$26 (\input_xer_so$50 ) ); \main$51 main ( + .logical_op__SV_Ptype(main_logical_op__SV_Ptype), + .\logical_op__SV_Ptype$23 (\main_logical_op__SV_Ptype$73 ), .logical_op__data_len(main_logical_op__data_len), - .\logical_op__data_len$18 (\main_logical_op__data_len$60 ), + .\logical_op__data_len$18 (\main_logical_op__data_len$68 ), .logical_op__fn_unit(main_logical_op__fn_unit), - .\logical_op__fn_unit$3 (\main_logical_op__fn_unit$45 ), + .\logical_op__fn_unit$3 (\main_logical_op__fn_unit$53 ), .logical_op__imm_data__data(main_logical_op__imm_data__data), - .\logical_op__imm_data__data$4 (\main_logical_op__imm_data__data$46 ), + .\logical_op__imm_data__data$4 (\main_logical_op__imm_data__data$54 ), .logical_op__imm_data__ok(main_logical_op__imm_data__ok), - .\logical_op__imm_data__ok$5 (\main_logical_op__imm_data__ok$47 ), + .\logical_op__imm_data__ok$5 (\main_logical_op__imm_data__ok$55 ), .logical_op__input_carry(main_logical_op__input_carry), - .\logical_op__input_carry$12 (\main_logical_op__input_carry$54 ), + .\logical_op__input_carry$12 (\main_logical_op__input_carry$62 ), .logical_op__insn(main_logical_op__insn), - .\logical_op__insn$19 (\main_logical_op__insn$61 ), + .\logical_op__insn$19 (\main_logical_op__insn$69 ), .logical_op__insn_type(main_logical_op__insn_type), - .\logical_op__insn_type$2 (\main_logical_op__insn_type$44 ), + .\logical_op__insn_type$2 (\main_logical_op__insn_type$52 ), .logical_op__invert_in(main_logical_op__invert_in), - .\logical_op__invert_in$10 (\main_logical_op__invert_in$52 ), + .\logical_op__invert_in$10 (\main_logical_op__invert_in$60 ), .logical_op__invert_out(main_logical_op__invert_out), - .\logical_op__invert_out$13 (\main_logical_op__invert_out$55 ), + .\logical_op__invert_out$13 (\main_logical_op__invert_out$63 ), .logical_op__is_32bit(main_logical_op__is_32bit), - .\logical_op__is_32bit$16 (\main_logical_op__is_32bit$58 ), + .\logical_op__is_32bit$16 (\main_logical_op__is_32bit$66 ), .logical_op__is_signed(main_logical_op__is_signed), - .\logical_op__is_signed$17 (\main_logical_op__is_signed$59 ), + .\logical_op__is_signed$17 (\main_logical_op__is_signed$67 ), .logical_op__oe__oe(main_logical_op__oe__oe), - .\logical_op__oe__oe$8 (\main_logical_op__oe__oe$50 ), + .\logical_op__oe__oe$8 (\main_logical_op__oe__oe$58 ), .logical_op__oe__ok(main_logical_op__oe__ok), - .\logical_op__oe__ok$9 (\main_logical_op__oe__ok$51 ), + .\logical_op__oe__ok$9 (\main_logical_op__oe__ok$59 ), .logical_op__output_carry(main_logical_op__output_carry), - .\logical_op__output_carry$15 (\main_logical_op__output_carry$57 ), + .\logical_op__output_carry$15 (\main_logical_op__output_carry$65 ), .logical_op__rc__ok(main_logical_op__rc__ok), - .\logical_op__rc__ok$7 (\main_logical_op__rc__ok$49 ), + .\logical_op__rc__ok$7 (\main_logical_op__rc__ok$57 ), .logical_op__rc__rc(main_logical_op__rc__rc), - .\logical_op__rc__rc$6 (\main_logical_op__rc__rc$48 ), + .\logical_op__rc__rc$6 (\main_logical_op__rc__rc$56 ), + .logical_op__sv_pred_dz(main_logical_op__sv_pred_dz), + .\logical_op__sv_pred_dz$21 (\main_logical_op__sv_pred_dz$71 ), + .logical_op__sv_pred_sz(main_logical_op__sv_pred_sz), + .\logical_op__sv_pred_sz$20 (\main_logical_op__sv_pred_sz$70 ), + .logical_op__sv_saturate(main_logical_op__sv_saturate), + .\logical_op__sv_saturate$22 (\main_logical_op__sv_saturate$72 ), .logical_op__write_cr0(main_logical_op__write_cr0), - .\logical_op__write_cr0$14 (\main_logical_op__write_cr0$56 ), + .\logical_op__write_cr0$14 (\main_logical_op__write_cr0$64 ), .logical_op__zero_a(main_logical_op__zero_a), - .\logical_op__zero_a$11 (\main_logical_op__zero_a$53 ), + .\logical_op__zero_a$11 (\main_logical_op__zero_a$61 ), .muxid(main_muxid), - .\muxid$1 (\main_muxid$43 ), + .\muxid$1 (\main_muxid$51 ), .o(main_o), .o_ok(main_o_ok), .ra(main_ra), .rb(main_rb), .xer_so(main_xer_so), - .\xer_so$20 (\main_xer_so$62 ) + .\xer_so$24 (\main_xer_so$74 ) ); \n$49 n ( .n_ready_i(n_ready_i), @@ -146025,300 +156186,328 @@ module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn ); always @* begin if (\initial ) begin end - \r_busy$next = r_busy; + \o$next = o; + \o_ok$next = o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \r_busy$next = 1'h1; + { \o_ok$next , \o$next } = { \o_ok$102 , \o$101 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \r_busy$next = 1'h0; + { \o_ok$next , \o$next } = { \o_ok$102 , \o$101 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \r_busy$next = 1'h0; + \o_ok$next = 1'h0; endcase end always @* begin if (\initial ) begin end - \muxid$next = muxid; + \cr_a$next = cr_a; + \cr_a_ok$next = cr_a_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \muxid$next = \muxid$66 ; + { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$104 , \cr_a$103 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \muxid$next = \muxid$66 ; + { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$104 , \cr_a$103 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + casez (coresync_rst) + 1'h1: + \cr_a_ok$next = 1'h0; endcase end always @* begin if (\initial ) begin end - \logical_op__insn_type$next = logical_op__insn_type; - \logical_op__fn_unit$next = logical_op__fn_unit; - \logical_op__imm_data__data$next = logical_op__imm_data__data; - \logical_op__imm_data__ok$next = logical_op__imm_data__ok; - \logical_op__rc__rc$next = logical_op__rc__rc; - \logical_op__rc__ok$next = logical_op__rc__ok; - \logical_op__oe__oe$next = logical_op__oe__oe; - \logical_op__oe__ok$next = logical_op__oe__ok; - \logical_op__invert_in$next = logical_op__invert_in; - \logical_op__zero_a$next = logical_op__zero_a; - \logical_op__input_carry$next = logical_op__input_carry; - \logical_op__invert_out$next = logical_op__invert_out; - \logical_op__write_cr0$next = logical_op__write_cr0; - \logical_op__output_carry$next = logical_op__output_carry; - \logical_op__is_32bit$next = logical_op__is_32bit; - \logical_op__is_signed$next = logical_op__is_signed; - \logical_op__data_len$next = logical_op__data_len; - \logical_op__insn$next = logical_op__insn; + \xer_so$next = xer_so; + \xer_so_ok$next = xer_so_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \logical_op__insn$next , \logical_op__data_len$next , \logical_op__is_signed$next , \logical_op__is_32bit$next , \logical_op__output_carry$next , \logical_op__write_cr0$next , \logical_op__invert_out$next , \logical_op__input_carry$next , \logical_op__zero_a$next , \logical_op__invert_in$next , \logical_op__oe__ok$next , \logical_op__oe__oe$next , \logical_op__rc__ok$next , \logical_op__rc__rc$next , \logical_op__imm_data__ok$next , \logical_op__imm_data__data$next , \logical_op__fn_unit$next , \logical_op__insn_type$next } = { \logical_op__insn$84 , \logical_op__data_len$83 , \logical_op__is_signed$82 , \logical_op__is_32bit$81 , \logical_op__output_carry$80 , \logical_op__write_cr0$79 , \logical_op__invert_out$78 , \logical_op__input_carry$77 , \logical_op__zero_a$76 , \logical_op__invert_in$75 , \logical_op__oe__ok$74 , \logical_op__oe__oe$73 , \logical_op__rc__ok$72 , \logical_op__rc__rc$71 , \logical_op__imm_data__ok$70 , \logical_op__imm_data__data$69 , \logical_op__fn_unit$68 , \logical_op__insn_type$67 }; + { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$108 , \xer_so$107 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \logical_op__insn$next , \logical_op__data_len$next , \logical_op__is_signed$next , \logical_op__is_32bit$next , \logical_op__output_carry$next , \logical_op__write_cr0$next , \logical_op__invert_out$next , \logical_op__input_carry$next , \logical_op__zero_a$next , \logical_op__invert_in$next , \logical_op__oe__ok$next , \logical_op__oe__oe$next , \logical_op__rc__ok$next , \logical_op__rc__rc$next , \logical_op__imm_data__ok$next , \logical_op__imm_data__data$next , \logical_op__fn_unit$next , \logical_op__insn_type$next } = { \logical_op__insn$84 , \logical_op__data_len$83 , \logical_op__is_signed$82 , \logical_op__is_32bit$81 , \logical_op__output_carry$80 , \logical_op__write_cr0$79 , \logical_op__invert_out$78 , \logical_op__input_carry$77 , \logical_op__zero_a$76 , \logical_op__invert_in$75 , \logical_op__oe__ok$74 , \logical_op__oe__oe$73 , \logical_op__rc__ok$72 , \logical_op__rc__rc$71 , \logical_op__imm_data__ok$70 , \logical_op__imm_data__data$69 , \logical_op__fn_unit$68 , \logical_op__insn_type$67 }; + { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$108 , \xer_so$107 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - begin - \logical_op__imm_data__data$next = 64'h0000000000000000; - \logical_op__imm_data__ok$next = 1'h0; - \logical_op__rc__rc$next = 1'h0; - \logical_op__rc__ok$next = 1'h0; - \logical_op__oe__oe$next = 1'h0; - \logical_op__oe__ok$next = 1'h0; - end + \xer_so_ok$next = 1'h0; endcase end always @* begin if (\initial ) begin end - \o$next = o; - \o_ok$next = o_ok; + \r_busy$next = r_busy; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \o_ok$next , \o$next } = { \o_ok$86 , \o$85 }; + \r_busy$next = 1'h1; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \o_ok$next , \o$next } = { \o_ok$86 , \o$85 }; + \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \o_ok$next = 1'h0; + \r_busy$next = 1'h0; endcase end always @* begin if (\initial ) begin end - \cr_a$next = cr_a; - \cr_a_ok$next = cr_a_ok; + \muxid$next = muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$88 , \cr_a$87 }; + \muxid$next = \muxid$78 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$88 , \cr_a$87 }; - endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) - casez (coresync_rst) - 1'h1: - \cr_a_ok$next = 1'h0; + \muxid$next = \muxid$78 ; endcase end always @* begin if (\initial ) begin end - \xer_so$next = xer_so; - \xer_so_ok$next = xer_so_ok; + \logical_op__insn_type$next = logical_op__insn_type; + \logical_op__fn_unit$next = logical_op__fn_unit; + \logical_op__imm_data__data$next = logical_op__imm_data__data; + \logical_op__imm_data__ok$next = logical_op__imm_data__ok; + \logical_op__rc__rc$next = logical_op__rc__rc; + \logical_op__rc__ok$next = logical_op__rc__ok; + \logical_op__oe__oe$next = logical_op__oe__oe; + \logical_op__oe__ok$next = logical_op__oe__ok; + \logical_op__invert_in$next = logical_op__invert_in; + \logical_op__zero_a$next = logical_op__zero_a; + \logical_op__input_carry$next = logical_op__input_carry; + \logical_op__invert_out$next = logical_op__invert_out; + \logical_op__write_cr0$next = logical_op__write_cr0; + \logical_op__output_carry$next = logical_op__output_carry; + \logical_op__is_32bit$next = logical_op__is_32bit; + \logical_op__is_signed$next = logical_op__is_signed; + \logical_op__data_len$next = logical_op__data_len; + \logical_op__insn$next = logical_op__insn; + \logical_op__sv_pred_sz$next = logical_op__sv_pred_sz; + \logical_op__sv_pred_dz$next = logical_op__sv_pred_dz; + \logical_op__sv_saturate$next = logical_op__sv_saturate; + \logical_op__SV_Ptype$next = logical_op__SV_Ptype; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$92 , \xer_so$91 }; + { \logical_op__SV_Ptype$next , \logical_op__sv_saturate$next , \logical_op__sv_pred_dz$next , \logical_op__sv_pred_sz$next , \logical_op__insn$next , \logical_op__data_len$next , \logical_op__is_signed$next , \logical_op__is_32bit$next , \logical_op__output_carry$next , \logical_op__write_cr0$next , \logical_op__invert_out$next , \logical_op__input_carry$next , \logical_op__zero_a$next , \logical_op__invert_in$next , \logical_op__oe__ok$next , \logical_op__oe__oe$next , \logical_op__rc__ok$next , \logical_op__rc__rc$next , \logical_op__imm_data__ok$next , \logical_op__imm_data__data$next , \logical_op__fn_unit$next , \logical_op__insn_type$next } = { \logical_op__SV_Ptype$100 , \logical_op__sv_saturate$99 , \logical_op__sv_pred_dz$98 , \logical_op__sv_pred_sz$97 , \logical_op__insn$96 , \logical_op__data_len$95 , \logical_op__is_signed$94 , \logical_op__is_32bit$93 , \logical_op__output_carry$92 , \logical_op__write_cr0$91 , \logical_op__invert_out$90 , \logical_op__input_carry$89 , \logical_op__zero_a$88 , \logical_op__invert_in$87 , \logical_op__oe__ok$86 , \logical_op__oe__oe$85 , \logical_op__rc__ok$84 , \logical_op__rc__rc$83 , \logical_op__imm_data__ok$82 , \logical_op__imm_data__data$81 , \logical_op__fn_unit$80 , \logical_op__insn_type$79 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$92 , \xer_so$91 }; + { \logical_op__SV_Ptype$next , \logical_op__sv_saturate$next , \logical_op__sv_pred_dz$next , \logical_op__sv_pred_sz$next , \logical_op__insn$next , \logical_op__data_len$next , \logical_op__is_signed$next , \logical_op__is_32bit$next , \logical_op__output_carry$next , \logical_op__write_cr0$next , \logical_op__invert_out$next , \logical_op__input_carry$next , \logical_op__zero_a$next , \logical_op__invert_in$next , \logical_op__oe__ok$next , \logical_op__oe__oe$next , \logical_op__rc__ok$next , \logical_op__rc__rc$next , \logical_op__imm_data__ok$next , \logical_op__imm_data__data$next , \logical_op__fn_unit$next , \logical_op__insn_type$next } = { \logical_op__SV_Ptype$100 , \logical_op__sv_saturate$99 , \logical_op__sv_pred_dz$98 , \logical_op__sv_pred_sz$97 , \logical_op__insn$96 , \logical_op__data_len$95 , \logical_op__is_signed$94 , \logical_op__is_32bit$93 , \logical_op__output_carry$92 , \logical_op__write_cr0$91 , \logical_op__invert_out$90 , \logical_op__input_carry$89 , \logical_op__zero_a$88 , \logical_op__invert_in$87 , \logical_op__oe__ok$86 , \logical_op__oe__oe$85 , \logical_op__rc__ok$84 , \logical_op__rc__rc$83 , \logical_op__imm_data__ok$82 , \logical_op__imm_data__data$81 , \logical_op__fn_unit$80 , \logical_op__insn_type$79 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \xer_so_ok$next = 1'h0; + begin + \logical_op__imm_data__data$next = 64'h0000000000000000; + \logical_op__imm_data__ok$next = 1'h0; + \logical_op__rc__rc$next = 1'h0; + \logical_op__rc__ok$next = 1'h0; + \logical_op__oe__oe$next = 1'h0; + \logical_op__oe__ok$next = 1'h0; + end endcase end - assign \cr_a$89 = 4'h0; - assign \cr_a_ok$90 = 1'h0; - assign \xer_so_ok$93 = 1'h0; + assign \cr_a$105 = 4'h0; + assign \cr_a_ok$106 = 1'h0; + assign \xer_so_ok$109 = 1'h0; assign p_ready_o = n_i_rdy_data; assign n_valid_o = r_busy; - assign { \xer_so_ok$92 , \xer_so$91 } = { 1'h0, \main_xer_so$62 }; - assign { \cr_a_ok$88 , \cr_a$87 } = 5'h00; - assign { \o_ok$86 , \o$85 } = { main_o_ok, main_o }; - assign { \logical_op__insn$84 , \logical_op__data_len$83 , \logical_op__is_signed$82 , \logical_op__is_32bit$81 , \logical_op__output_carry$80 , \logical_op__write_cr0$79 , \logical_op__invert_out$78 , \logical_op__input_carry$77 , \logical_op__zero_a$76 , \logical_op__invert_in$75 , \logical_op__oe__ok$74 , \logical_op__oe__oe$73 , \logical_op__rc__ok$72 , \logical_op__rc__rc$71 , \logical_op__imm_data__ok$70 , \logical_op__imm_data__data$69 , \logical_op__fn_unit$68 , \logical_op__insn_type$67 } = { \main_logical_op__insn$61 , \main_logical_op__data_len$60 , \main_logical_op__is_signed$59 , \main_logical_op__is_32bit$58 , \main_logical_op__output_carry$57 , \main_logical_op__write_cr0$56 , \main_logical_op__invert_out$55 , \main_logical_op__input_carry$54 , \main_logical_op__zero_a$53 , \main_logical_op__invert_in$52 , \main_logical_op__oe__ok$51 , \main_logical_op__oe__oe$50 , \main_logical_op__rc__ok$49 , \main_logical_op__rc__rc$48 , \main_logical_op__imm_data__ok$47 , \main_logical_op__imm_data__data$46 , \main_logical_op__fn_unit$45 , \main_logical_op__insn_type$44 }; - assign \muxid$66 = \main_muxid$43 ; - assign p_valid_i_p_ready_o = \$64 ; + assign { \xer_so_ok$108 , \xer_so$107 } = { 1'h0, \main_xer_so$74 }; + assign { \cr_a_ok$104 , \cr_a$103 } = 5'h00; + assign { \o_ok$102 , \o$101 } = { main_o_ok, main_o }; + assign { \logical_op__SV_Ptype$100 , \logical_op__sv_saturate$99 , \logical_op__sv_pred_dz$98 , \logical_op__sv_pred_sz$97 , \logical_op__insn$96 , \logical_op__data_len$95 , \logical_op__is_signed$94 , \logical_op__is_32bit$93 , \logical_op__output_carry$92 , \logical_op__write_cr0$91 , \logical_op__invert_out$90 , \logical_op__input_carry$89 , \logical_op__zero_a$88 , \logical_op__invert_in$87 , \logical_op__oe__ok$86 , \logical_op__oe__oe$85 , \logical_op__rc__ok$84 , \logical_op__rc__rc$83 , \logical_op__imm_data__ok$82 , \logical_op__imm_data__data$81 , \logical_op__fn_unit$80 , \logical_op__insn_type$79 } = { \main_logical_op__SV_Ptype$73 , \main_logical_op__sv_saturate$72 , \main_logical_op__sv_pred_dz$71 , \main_logical_op__sv_pred_sz$70 , \main_logical_op__insn$69 , \main_logical_op__data_len$68 , \main_logical_op__is_signed$67 , \main_logical_op__is_32bit$66 , \main_logical_op__output_carry$65 , \main_logical_op__write_cr0$64 , \main_logical_op__invert_out$63 , \main_logical_op__input_carry$62 , \main_logical_op__zero_a$61 , \main_logical_op__invert_in$60 , \main_logical_op__oe__ok$59 , \main_logical_op__oe__oe$58 , \main_logical_op__rc__ok$57 , \main_logical_op__rc__rc$56 , \main_logical_op__imm_data__ok$55 , \main_logical_op__imm_data__data$54 , \main_logical_op__fn_unit$53 , \main_logical_op__insn_type$52 }; + assign \muxid$78 = \main_muxid$51 ; + assign p_valid_i_p_ready_o = \$76 ; assign n_i_rdy_data = n_ready_i; - assign \p_valid_i$63 = p_valid_i; - assign main_xer_so = \input_xer_so$42 ; - assign main_rb = \input_rb$41 ; - assign main_ra = \input_ra$40 ; - assign { main_logical_op__insn, main_logical_op__data_len, main_logical_op__is_signed, main_logical_op__is_32bit, main_logical_op__output_carry, main_logical_op__write_cr0, main_logical_op__invert_out, main_logical_op__input_carry, main_logical_op__zero_a, main_logical_op__invert_in, main_logical_op__oe__ok, main_logical_op__oe__oe, main_logical_op__rc__ok, main_logical_op__rc__rc, main_logical_op__imm_data__ok, main_logical_op__imm_data__data, main_logical_op__fn_unit, main_logical_op__insn_type } = { \input_logical_op__insn$39 , \input_logical_op__data_len$38 , \input_logical_op__is_signed$37 , \input_logical_op__is_32bit$36 , \input_logical_op__output_carry$35 , \input_logical_op__write_cr0$34 , \input_logical_op__invert_out$33 , \input_logical_op__input_carry$32 , \input_logical_op__zero_a$31 , \input_logical_op__invert_in$30 , \input_logical_op__oe__ok$29 , \input_logical_op__oe__oe$28 , \input_logical_op__rc__ok$27 , \input_logical_op__rc__rc$26 , \input_logical_op__imm_data__ok$25 , \input_logical_op__imm_data__data$24 , \input_logical_op__fn_unit$23 , \input_logical_op__insn_type$22 }; - assign main_muxid = \input_muxid$21 ; - assign input_xer_so = \xer_so$20 ; + assign \p_valid_i$75 = p_valid_i; + assign main_xer_so = \input_xer_so$50 ; + assign main_rb = \input_rb$49 ; + assign main_ra = \input_ra$48 ; + assign { main_logical_op__SV_Ptype, main_logical_op__sv_saturate, main_logical_op__sv_pred_dz, main_logical_op__sv_pred_sz, main_logical_op__insn, main_logical_op__data_len, main_logical_op__is_signed, main_logical_op__is_32bit, main_logical_op__output_carry, main_logical_op__write_cr0, main_logical_op__invert_out, main_logical_op__input_carry, main_logical_op__zero_a, main_logical_op__invert_in, main_logical_op__oe__ok, main_logical_op__oe__oe, main_logical_op__rc__ok, main_logical_op__rc__rc, main_logical_op__imm_data__ok, main_logical_op__imm_data__data, main_logical_op__fn_unit, main_logical_op__insn_type } = { \input_logical_op__SV_Ptype$47 , \input_logical_op__sv_saturate$46 , \input_logical_op__sv_pred_dz$45 , \input_logical_op__sv_pred_sz$44 , \input_logical_op__insn$43 , \input_logical_op__data_len$42 , \input_logical_op__is_signed$41 , \input_logical_op__is_32bit$40 , \input_logical_op__output_carry$39 , \input_logical_op__write_cr0$38 , \input_logical_op__invert_out$37 , \input_logical_op__input_carry$36 , \input_logical_op__zero_a$35 , \input_logical_op__invert_in$34 , \input_logical_op__oe__ok$33 , \input_logical_op__oe__oe$32 , \input_logical_op__rc__ok$31 , \input_logical_op__rc__rc$30 , \input_logical_op__imm_data__ok$29 , \input_logical_op__imm_data__data$28 , \input_logical_op__fn_unit$27 , \input_logical_op__insn_type$26 }; + assign main_muxid = \input_muxid$25 ; + assign input_xer_so = \xer_so$24 ; assign input_rb = rb; assign input_ra = ra; - assign { input_logical_op__insn, input_logical_op__data_len, input_logical_op__is_signed, input_logical_op__is_32bit, input_logical_op__output_carry, input_logical_op__write_cr0, input_logical_op__invert_out, input_logical_op__input_carry, input_logical_op__zero_a, input_logical_op__invert_in, input_logical_op__oe__ok, input_logical_op__oe__oe, input_logical_op__rc__ok, input_logical_op__rc__rc, input_logical_op__imm_data__ok, input_logical_op__imm_data__data, input_logical_op__fn_unit, input_logical_op__insn_type } = { \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 }; + assign { input_logical_op__SV_Ptype, input_logical_op__sv_saturate, input_logical_op__sv_pred_dz, input_logical_op__sv_pred_sz, input_logical_op__insn, input_logical_op__data_len, input_logical_op__is_signed, input_logical_op__is_32bit, input_logical_op__output_carry, input_logical_op__write_cr0, input_logical_op__invert_out, input_logical_op__input_carry, input_logical_op__zero_a, input_logical_op__invert_in, input_logical_op__oe__ok, input_logical_op__oe__oe, input_logical_op__rc__ok, input_logical_op__rc__rc, input_logical_op__imm_data__ok, input_logical_op__imm_data__data, input_logical_op__fn_unit, input_logical_op__insn_type } = { \logical_op__SV_Ptype$23 , \logical_op__sv_saturate$22 , \logical_op__sv_pred_dz$21 , \logical_op__sv_pred_sz$20 , \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 }; assign input_muxid = \muxid$1 ; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2" *) (* generator = "nMigen" *) -module logical_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, o, o_ok, cr_a, cr_a_ok, xer_so, xer_so_ok, n_valid_o, n_ready_i, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \o$20 , \o_ok$21 , \cr_a$22 , \cr_a_ok$23 , coresync_clk); +module logical_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__SV_Ptype, o, o_ok, cr_a, cr_a_ok, xer_so, xer_so_ok, n_valid_o, n_ready_i, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__SV_Ptype$23 , \o$24 , \o_ok$25 , \cr_a$26 , \cr_a_ok$27 , coresync_clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) - wire \$49 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + wire \$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [3:0] \cr_a$22 ; - reg [3:0] \cr_a$22 = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg [3:0] \cr_a$22$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [3:0] \cr_a$72 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [3:0] \cr_a$26 ; + reg [3:0] \cr_a$26 = 4'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg [3:0] \cr_a$26$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [3:0] \cr_a$84 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input cr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \cr_a_ok$23 ; - reg \cr_a_ok$23 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg \cr_a_ok$23$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \cr_a_ok$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \cr_a_ok$73 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \cr_a_ok$27 ; + reg \cr_a_ok$27 = 1'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg \cr_a_ok$27$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \cr_a_ok$54 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \cr_a_ok$85 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] logical_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \logical_op__SV_Ptype$23 ; + reg [1:0] \logical_op__SV_Ptype$23 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \logical_op__SV_Ptype$23$next ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \logical_op__SV_Ptype$81 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [3:0] logical_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [3:0] \logical_op__data_len$18 ; reg [3:0] \logical_op__data_len$18 = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [3:0] \logical_op__data_len$18$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [3:0] \logical_op__data_len$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [3:0] \logical_op__data_len$76 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] logical_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] logical_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \logical_op__fn_unit$3 ; - reg [13:0] \logical_op__fn_unit$3 = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] \logical_op__fn_unit$3$next ; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \logical_op__fn_unit$3 ; + reg [14:0] \logical_op__fn_unit$3 = 15'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] \logical_op__fn_unit$3$next ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \logical_op__fn_unit$53 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \logical_op__fn_unit$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] logical_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \logical_op__imm_data__data$4 ; reg [63:0] \logical_op__imm_data__data$4 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] \logical_op__imm_data__data$4$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \logical_op__imm_data__data$54 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \logical_op__imm_data__data$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__imm_data__ok$5 ; reg \logical_op__imm_data__ok$5 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__imm_data__ok$5$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__imm_data__ok$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__imm_data__ok$63 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] logical_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [1:0] \logical_op__input_carry$12 ; reg [1:0] \logical_op__input_carry$12 = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [1:0] \logical_op__input_carry$12$next ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [1:0] \logical_op__input_carry$62 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \logical_op__input_carry$70 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] logical_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \logical_op__insn$19 ; reg [31:0] \logical_op__insn$19 = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] \logical_op__insn$19$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \logical_op__insn$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \logical_op__insn$77 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -146394,7 +156583,9 @@ module logical_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] logical_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -146471,10 +156662,12 @@ module logical_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] \logical_op__insn_type$2 ; reg [6:0] \logical_op__insn_type$2 = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] \logical_op__insn_type$2$next ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -146551,107 +156744,148 @@ module logical_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \logical_op__insn_type$52 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \logical_op__insn_type$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__invert_in$10 ; reg \logical_op__invert_in$10 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__invert_in$10$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__invert_in$60 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__invert_in$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__invert_out$13 ; reg \logical_op__invert_out$13 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__invert_out$13$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__invert_out$63 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__invert_out$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__is_32bit$16 ; reg \logical_op__is_32bit$16 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__is_32bit$16$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__is_32bit$66 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__is_32bit$74 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__is_signed$17 ; reg \logical_op__is_signed$17 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__is_signed$17$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__is_signed$67 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__is_signed$75 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__oe__oe$58 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__oe__oe$66 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__oe__oe$8 ; reg \logical_op__oe__oe$8 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__oe__oe$8$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__oe__ok$59 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__oe__ok$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__oe__ok$9 ; reg \logical_op__oe__ok$9 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__oe__ok$9$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__output_carry$15 ; reg \logical_op__output_carry$15 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__output_carry$15$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__output_carry$65 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__output_carry$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__rc__ok$57 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__rc__ok$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__rc__ok$7 ; reg \logical_op__rc__ok$7 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__rc__ok$7$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__rc__rc$56 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__rc__rc$6 ; reg \logical_op__rc__rc$6 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__rc__rc$6$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__rc__rc$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input logical_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \logical_op__sv_pred_dz$21 ; + reg \logical_op__sv_pred_dz$21 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__sv_pred_dz$21$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__sv_pred_dz$79 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input logical_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \logical_op__sv_pred_sz$20 ; + reg \logical_op__sv_pred_sz$20 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__sv_pred_sz$20$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__sv_pred_sz$78 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] logical_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \logical_op__sv_saturate$22 ; + reg [1:0] \logical_op__sv_saturate$22 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \logical_op__sv_saturate$22$next ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \logical_op__sv_saturate$80 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__write_cr0$14 ; reg \logical_op__write_cr0$14 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__write_cr0$14$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__write_cr0$64 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__write_cr0$72 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__zero_a$11 ; reg \logical_op__zero_a$11 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__zero_a$11$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__zero_a$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__zero_a$69 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) @@ -146660,99 +156894,113 @@ module logical_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) reg [1:0] \muxid$1$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \muxid$51 ; + wire [1:0] \muxid$59 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *) wire n_i_rdy_data; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [63:0] \o$20 ; - reg [63:0] \o$20 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg [63:0] \o$20$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \o$70 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [63:0] \o$24 ; + reg [63:0] \o$24 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg [63:0] \o$24$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \o$82 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \o_ok$21 ; - reg \o_ok$21 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg \o_ok$21$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \o_ok$71 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \o_ok$25 ; + reg \o_ok$25 = 1'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg \o_ok$25$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \o_ok$83 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [3:0] output_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [3:0] \output_cr_a$45 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [3:0] \output_cr_a$53 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire output_cr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] output_logical_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \output_logical_op__SV_Ptype$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [3:0] output_logical_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [3:0] \output_logical_op__data_len$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [3:0] \output_logical_op__data_len$45 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] output_logical_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] output_logical_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \output_logical_op__fn_unit$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \output_logical_op__fn_unit$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] output_logical_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \output_logical_op__imm_data__data$27 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \output_logical_op__imm_data__data$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_logical_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_logical_op__imm_data__ok$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_logical_op__imm_data__ok$32 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [1:0] output_logical_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [1:0] \output_logical_op__input_carry$35 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \output_logical_op__input_carry$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] output_logical_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \output_logical_op__insn$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \output_logical_op__insn$46 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -146828,7 +157076,9 @@ module logical_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] output_logical_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -146905,93 +157155,115 @@ module logical_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \output_logical_op__insn_type$25 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \output_logical_op__insn_type$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_logical_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_logical_op__invert_in$33 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_logical_op__invert_in$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_logical_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_logical_op__invert_out$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_logical_op__invert_out$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_logical_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_logical_op__is_32bit$39 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_logical_op__is_32bit$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_logical_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_logical_op__is_signed$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_logical_op__is_signed$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_logical_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_logical_op__oe__oe$31 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_logical_op__oe__oe$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_logical_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_logical_op__oe__ok$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_logical_op__oe__ok$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_logical_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_logical_op__output_carry$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_logical_op__output_carry$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_logical_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_logical_op__rc__ok$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_logical_op__rc__ok$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_logical_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_logical_op__rc__rc$29 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_logical_op__rc__rc$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire output_logical_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_logical_op__sv_pred_dz$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire output_logical_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_logical_op__sv_pred_sz$47 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] output_logical_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \output_logical_op__sv_saturate$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_logical_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_logical_op__write_cr0$37 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_logical_op__write_cr0$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_logical_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_logical_op__zero_a$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_logical_op__zero_a$38 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] output_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \output_muxid$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \output_muxid$28 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] output_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \output_o$43 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \output_o$51 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire output_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \output_o_ok$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \output_o_ok$52 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire output_xer_so; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) input p_valid_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *) - wire \p_valid_i$48 ; + wire \p_valid_i$56 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *) wire p_valid_i_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg r_busy = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg \r_busy$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input xer_so_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_so_ok$47 ; - assign \$49 = \p_valid_i$48 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_so_ok$55 ; + assign \$57 = \p_valid_i$56 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; always @(posedge coresync_clk) - \cr_a$22 <= \cr_a$22$next ; + \cr_a$26 <= \cr_a$26$next ; always @(posedge coresync_clk) - \cr_a_ok$23 <= \cr_a_ok$23$next ; + \cr_a_ok$27 <= \cr_a_ok$27$next ; always @(posedge coresync_clk) - \o$20 <= \o$20$next ; + \o$24 <= \o$24$next ; always @(posedge coresync_clk) - \o_ok$21 <= \o_ok$21$next ; + \o_ok$25 <= \o_ok$25$next ; always @(posedge coresync_clk) \logical_op__insn_type$2 <= \logical_op__insn_type$2$next ; always @(posedge coresync_clk) @@ -147028,6 +157300,14 @@ module logical_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn \logical_op__data_len$18 <= \logical_op__data_len$18$next ; always @(posedge coresync_clk) \logical_op__insn$19 <= \logical_op__insn$19$next ; + always @(posedge coresync_clk) + \logical_op__sv_pred_sz$20 <= \logical_op__sv_pred_sz$20$next ; + always @(posedge coresync_clk) + \logical_op__sv_pred_dz$21 <= \logical_op__sv_pred_dz$21$next ; + always @(posedge coresync_clk) + \logical_op__sv_saturate$22 <= \logical_op__sv_saturate$22$next ; + always @(posedge coresync_clk) + \logical_op__SV_Ptype$23 <= \logical_op__SV_Ptype$23$next ; always @(posedge coresync_clk) \muxid$1 <= \muxid$1$next ; always @(posedge coresync_clk) @@ -147038,50 +157318,58 @@ module logical_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn ); \output$54 \output ( .cr_a(output_cr_a), - .\cr_a$22 (\output_cr_a$45 ), + .\cr_a$26 (\output_cr_a$53 ), .cr_a_ok(output_cr_a_ok), + .logical_op__SV_Ptype(output_logical_op__SV_Ptype), + .\logical_op__SV_Ptype$23 (\output_logical_op__SV_Ptype$50 ), .logical_op__data_len(output_logical_op__data_len), - .\logical_op__data_len$18 (\output_logical_op__data_len$41 ), + .\logical_op__data_len$18 (\output_logical_op__data_len$45 ), .logical_op__fn_unit(output_logical_op__fn_unit), - .\logical_op__fn_unit$3 (\output_logical_op__fn_unit$26 ), + .\logical_op__fn_unit$3 (\output_logical_op__fn_unit$30 ), .logical_op__imm_data__data(output_logical_op__imm_data__data), - .\logical_op__imm_data__data$4 (\output_logical_op__imm_data__data$27 ), + .\logical_op__imm_data__data$4 (\output_logical_op__imm_data__data$31 ), .logical_op__imm_data__ok(output_logical_op__imm_data__ok), - .\logical_op__imm_data__ok$5 (\output_logical_op__imm_data__ok$28 ), + .\logical_op__imm_data__ok$5 (\output_logical_op__imm_data__ok$32 ), .logical_op__input_carry(output_logical_op__input_carry), - .\logical_op__input_carry$12 (\output_logical_op__input_carry$35 ), + .\logical_op__input_carry$12 (\output_logical_op__input_carry$39 ), .logical_op__insn(output_logical_op__insn), - .\logical_op__insn$19 (\output_logical_op__insn$42 ), + .\logical_op__insn$19 (\output_logical_op__insn$46 ), .logical_op__insn_type(output_logical_op__insn_type), - .\logical_op__insn_type$2 (\output_logical_op__insn_type$25 ), + .\logical_op__insn_type$2 (\output_logical_op__insn_type$29 ), .logical_op__invert_in(output_logical_op__invert_in), - .\logical_op__invert_in$10 (\output_logical_op__invert_in$33 ), + .\logical_op__invert_in$10 (\output_logical_op__invert_in$37 ), .logical_op__invert_out(output_logical_op__invert_out), - .\logical_op__invert_out$13 (\output_logical_op__invert_out$36 ), + .\logical_op__invert_out$13 (\output_logical_op__invert_out$40 ), .logical_op__is_32bit(output_logical_op__is_32bit), - .\logical_op__is_32bit$16 (\output_logical_op__is_32bit$39 ), + .\logical_op__is_32bit$16 (\output_logical_op__is_32bit$43 ), .logical_op__is_signed(output_logical_op__is_signed), - .\logical_op__is_signed$17 (\output_logical_op__is_signed$40 ), + .\logical_op__is_signed$17 (\output_logical_op__is_signed$44 ), .logical_op__oe__oe(output_logical_op__oe__oe), - .\logical_op__oe__oe$8 (\output_logical_op__oe__oe$31 ), + .\logical_op__oe__oe$8 (\output_logical_op__oe__oe$35 ), .logical_op__oe__ok(output_logical_op__oe__ok), - .\logical_op__oe__ok$9 (\output_logical_op__oe__ok$32 ), + .\logical_op__oe__ok$9 (\output_logical_op__oe__ok$36 ), .logical_op__output_carry(output_logical_op__output_carry), - .\logical_op__output_carry$15 (\output_logical_op__output_carry$38 ), + .\logical_op__output_carry$15 (\output_logical_op__output_carry$42 ), .logical_op__rc__ok(output_logical_op__rc__ok), - .\logical_op__rc__ok$7 (\output_logical_op__rc__ok$30 ), + .\logical_op__rc__ok$7 (\output_logical_op__rc__ok$34 ), .logical_op__rc__rc(output_logical_op__rc__rc), - .\logical_op__rc__rc$6 (\output_logical_op__rc__rc$29 ), + .\logical_op__rc__rc$6 (\output_logical_op__rc__rc$33 ), + .logical_op__sv_pred_dz(output_logical_op__sv_pred_dz), + .\logical_op__sv_pred_dz$21 (\output_logical_op__sv_pred_dz$48 ), + .logical_op__sv_pred_sz(output_logical_op__sv_pred_sz), + .\logical_op__sv_pred_sz$20 (\output_logical_op__sv_pred_sz$47 ), + .logical_op__sv_saturate(output_logical_op__sv_saturate), + .\logical_op__sv_saturate$22 (\output_logical_op__sv_saturate$49 ), .logical_op__write_cr0(output_logical_op__write_cr0), - .\logical_op__write_cr0$14 (\output_logical_op__write_cr0$37 ), + .\logical_op__write_cr0$14 (\output_logical_op__write_cr0$41 ), .logical_op__zero_a(output_logical_op__zero_a), - .\logical_op__zero_a$11 (\output_logical_op__zero_a$34 ), + .\logical_op__zero_a$11 (\output_logical_op__zero_a$38 ), .muxid(output_muxid), - .\muxid$1 (\output_muxid$24 ), + .\muxid$1 (\output_muxid$28 ), .o(output_o), - .\o$20 (\output_o$43 ), + .\o$24 (\output_o$51 ), .o_ok(output_o_ok), - .\o_ok$21 (\output_o_ok$44 ), + .\o_ok$25 (\output_o_ok$52 ), .xer_so(output_xer_so) ); \p$52 p ( @@ -147100,7 +157388,7 @@ module logical_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -147113,10 +157401,10 @@ module logical_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \muxid$1$next = \muxid$51 ; + \muxid$1$next = \muxid$59 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \muxid$1$next = \muxid$51 ; + \muxid$1$next = \muxid$59 ; endcase end always @* begin @@ -147139,16 +157427,20 @@ module logical_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn \logical_op__is_signed$17$next = \logical_op__is_signed$17 ; \logical_op__data_len$18$next = \logical_op__data_len$18 ; \logical_op__insn$19$next = \logical_op__insn$19 ; + \logical_op__sv_pred_sz$20$next = \logical_op__sv_pred_sz$20 ; + \logical_op__sv_pred_dz$21$next = \logical_op__sv_pred_dz$21 ; + \logical_op__sv_saturate$22$next = \logical_op__sv_saturate$22 ; + \logical_op__SV_Ptype$23$next = \logical_op__SV_Ptype$23 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \logical_op__insn$19$next , \logical_op__data_len$18$next , \logical_op__is_signed$17$next , \logical_op__is_32bit$16$next , \logical_op__output_carry$15$next , \logical_op__write_cr0$14$next , \logical_op__invert_out$13$next , \logical_op__input_carry$12$next , \logical_op__zero_a$11$next , \logical_op__invert_in$10$next , \logical_op__oe__ok$9$next , \logical_op__oe__oe$8$next , \logical_op__rc__ok$7$next , \logical_op__rc__rc$6$next , \logical_op__imm_data__ok$5$next , \logical_op__imm_data__data$4$next , \logical_op__fn_unit$3$next , \logical_op__insn_type$2$next } = { \logical_op__insn$69 , \logical_op__data_len$68 , \logical_op__is_signed$67 , \logical_op__is_32bit$66 , \logical_op__output_carry$65 , \logical_op__write_cr0$64 , \logical_op__invert_out$63 , \logical_op__input_carry$62 , \logical_op__zero_a$61 , \logical_op__invert_in$60 , \logical_op__oe__ok$59 , \logical_op__oe__oe$58 , \logical_op__rc__ok$57 , \logical_op__rc__rc$56 , \logical_op__imm_data__ok$55 , \logical_op__imm_data__data$54 , \logical_op__fn_unit$53 , \logical_op__insn_type$52 }; + { \logical_op__SV_Ptype$23$next , \logical_op__sv_saturate$22$next , \logical_op__sv_pred_dz$21$next , \logical_op__sv_pred_sz$20$next , \logical_op__insn$19$next , \logical_op__data_len$18$next , \logical_op__is_signed$17$next , \logical_op__is_32bit$16$next , \logical_op__output_carry$15$next , \logical_op__write_cr0$14$next , \logical_op__invert_out$13$next , \logical_op__input_carry$12$next , \logical_op__zero_a$11$next , \logical_op__invert_in$10$next , \logical_op__oe__ok$9$next , \logical_op__oe__oe$8$next , \logical_op__rc__ok$7$next , \logical_op__rc__rc$6$next , \logical_op__imm_data__ok$5$next , \logical_op__imm_data__data$4$next , \logical_op__fn_unit$3$next , \logical_op__insn_type$2$next } = { \logical_op__SV_Ptype$81 , \logical_op__sv_saturate$80 , \logical_op__sv_pred_dz$79 , \logical_op__sv_pred_sz$78 , \logical_op__insn$77 , \logical_op__data_len$76 , \logical_op__is_signed$75 , \logical_op__is_32bit$74 , \logical_op__output_carry$73 , \logical_op__write_cr0$72 , \logical_op__invert_out$71 , \logical_op__input_carry$70 , \logical_op__zero_a$69 , \logical_op__invert_in$68 , \logical_op__oe__ok$67 , \logical_op__oe__oe$66 , \logical_op__rc__ok$65 , \logical_op__rc__rc$64 , \logical_op__imm_data__ok$63 , \logical_op__imm_data__data$62 , \logical_op__fn_unit$61 , \logical_op__insn_type$60 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \logical_op__insn$19$next , \logical_op__data_len$18$next , \logical_op__is_signed$17$next , \logical_op__is_32bit$16$next , \logical_op__output_carry$15$next , \logical_op__write_cr0$14$next , \logical_op__invert_out$13$next , \logical_op__input_carry$12$next , \logical_op__zero_a$11$next , \logical_op__invert_in$10$next , \logical_op__oe__ok$9$next , \logical_op__oe__oe$8$next , \logical_op__rc__ok$7$next , \logical_op__rc__rc$6$next , \logical_op__imm_data__ok$5$next , \logical_op__imm_data__data$4$next , \logical_op__fn_unit$3$next , \logical_op__insn_type$2$next } = { \logical_op__insn$69 , \logical_op__data_len$68 , \logical_op__is_signed$67 , \logical_op__is_32bit$66 , \logical_op__output_carry$65 , \logical_op__write_cr0$64 , \logical_op__invert_out$63 , \logical_op__input_carry$62 , \logical_op__zero_a$61 , \logical_op__invert_in$60 , \logical_op__oe__ok$59 , \logical_op__oe__oe$58 , \logical_op__rc__ok$57 , \logical_op__rc__rc$56 , \logical_op__imm_data__ok$55 , \logical_op__imm_data__data$54 , \logical_op__fn_unit$53 , \logical_op__insn_type$52 }; + { \logical_op__SV_Ptype$23$next , \logical_op__sv_saturate$22$next , \logical_op__sv_pred_dz$21$next , \logical_op__sv_pred_sz$20$next , \logical_op__insn$19$next , \logical_op__data_len$18$next , \logical_op__is_signed$17$next , \logical_op__is_32bit$16$next , \logical_op__output_carry$15$next , \logical_op__write_cr0$14$next , \logical_op__invert_out$13$next , \logical_op__input_carry$12$next , \logical_op__zero_a$11$next , \logical_op__invert_in$10$next , \logical_op__oe__ok$9$next , \logical_op__oe__oe$8$next , \logical_op__rc__ok$7$next , \logical_op__rc__rc$6$next , \logical_op__imm_data__ok$5$next , \logical_op__imm_data__data$4$next , \logical_op__fn_unit$3$next , \logical_op__insn_type$2$next } = { \logical_op__SV_Ptype$81 , \logical_op__sv_saturate$80 , \logical_op__sv_pred_dz$79 , \logical_op__sv_pred_sz$78 , \logical_op__insn$77 , \logical_op__data_len$76 , \logical_op__is_signed$75 , \logical_op__is_32bit$74 , \logical_op__output_carry$73 , \logical_op__write_cr0$72 , \logical_op__invert_out$71 , \logical_op__input_carry$70 , \logical_op__zero_a$69 , \logical_op__invert_in$68 , \logical_op__oe__ok$67 , \logical_op__oe__oe$66 , \logical_op__rc__ok$65 , \logical_op__rc__rc$64 , \logical_op__imm_data__ok$63 , \logical_op__imm_data__data$62 , \logical_op__fn_unit$61 , \logical_op__insn_type$60 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -147163,55 +157455,55 @@ module logical_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn end always @* begin if (\initial ) begin end - \o$20$next = \o$20 ; - \o_ok$21$next = \o_ok$21 ; + \o$24$next = \o$24 ; + \o_ok$25$next = \o_ok$25 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \o_ok$21$next , \o$20$next } = { \o_ok$71 , \o$70 }; + { \o_ok$25$next , \o$24$next } = { \o_ok$83 , \o$82 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \o_ok$21$next , \o$20$next } = { \o_ok$71 , \o$70 }; + { \o_ok$25$next , \o$24$next } = { \o_ok$83 , \o$82 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \o_ok$21$next = 1'h0; + \o_ok$25$next = 1'h0; endcase end always @* begin if (\initial ) begin end - \cr_a$22$next = \cr_a$22 ; - \cr_a_ok$23$next = \cr_a_ok$23 ; + \cr_a$26$next = \cr_a$26 ; + \cr_a_ok$27$next = \cr_a_ok$27 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \cr_a_ok$23$next , \cr_a$22$next } = { \cr_a_ok$73 , \cr_a$72 }; + { \cr_a_ok$27$next , \cr_a$26$next } = { \cr_a_ok$85 , \cr_a$84 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \cr_a_ok$23$next , \cr_a$22$next } = { \cr_a_ok$73 , \cr_a$72 }; + { \cr_a_ok$27$next , \cr_a$26$next } = { \cr_a_ok$85 , \cr_a$84 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \cr_a_ok$23$next = 1'h0; + \cr_a_ok$27$next = 1'h0; endcase end assign p_ready_o = n_i_rdy_data; assign n_valid_o = r_busy; - assign { \cr_a_ok$73 , \cr_a$72 } = { output_cr_a_ok, \output_cr_a$45 }; - assign { \o_ok$71 , \o$70 } = { \output_o_ok$44 , \output_o$43 }; - assign { \logical_op__insn$69 , \logical_op__data_len$68 , \logical_op__is_signed$67 , \logical_op__is_32bit$66 , \logical_op__output_carry$65 , \logical_op__write_cr0$64 , \logical_op__invert_out$63 , \logical_op__input_carry$62 , \logical_op__zero_a$61 , \logical_op__invert_in$60 , \logical_op__oe__ok$59 , \logical_op__oe__oe$58 , \logical_op__rc__ok$57 , \logical_op__rc__rc$56 , \logical_op__imm_data__ok$55 , \logical_op__imm_data__data$54 , \logical_op__fn_unit$53 , \logical_op__insn_type$52 } = { \output_logical_op__insn$42 , \output_logical_op__data_len$41 , \output_logical_op__is_signed$40 , \output_logical_op__is_32bit$39 , \output_logical_op__output_carry$38 , \output_logical_op__write_cr0$37 , \output_logical_op__invert_out$36 , \output_logical_op__input_carry$35 , \output_logical_op__zero_a$34 , \output_logical_op__invert_in$33 , \output_logical_op__oe__ok$32 , \output_logical_op__oe__oe$31 , \output_logical_op__rc__ok$30 , \output_logical_op__rc__rc$29 , \output_logical_op__imm_data__ok$28 , \output_logical_op__imm_data__data$27 , \output_logical_op__fn_unit$26 , \output_logical_op__insn_type$25 }; - assign \muxid$51 = \output_muxid$24 ; - assign p_valid_i_p_ready_o = \$49 ; + assign { \cr_a_ok$85 , \cr_a$84 } = { output_cr_a_ok, \output_cr_a$53 }; + assign { \o_ok$83 , \o$82 } = { \output_o_ok$52 , \output_o$51 }; + assign { \logical_op__SV_Ptype$81 , \logical_op__sv_saturate$80 , \logical_op__sv_pred_dz$79 , \logical_op__sv_pred_sz$78 , \logical_op__insn$77 , \logical_op__data_len$76 , \logical_op__is_signed$75 , \logical_op__is_32bit$74 , \logical_op__output_carry$73 , \logical_op__write_cr0$72 , \logical_op__invert_out$71 , \logical_op__input_carry$70 , \logical_op__zero_a$69 , \logical_op__invert_in$68 , \logical_op__oe__ok$67 , \logical_op__oe__oe$66 , \logical_op__rc__ok$65 , \logical_op__rc__rc$64 , \logical_op__imm_data__ok$63 , \logical_op__imm_data__data$62 , \logical_op__fn_unit$61 , \logical_op__insn_type$60 } = { \output_logical_op__SV_Ptype$50 , \output_logical_op__sv_saturate$49 , \output_logical_op__sv_pred_dz$48 , \output_logical_op__sv_pred_sz$47 , \output_logical_op__insn$46 , \output_logical_op__data_len$45 , \output_logical_op__is_signed$44 , \output_logical_op__is_32bit$43 , \output_logical_op__output_carry$42 , \output_logical_op__write_cr0$41 , \output_logical_op__invert_out$40 , \output_logical_op__input_carry$39 , \output_logical_op__zero_a$38 , \output_logical_op__invert_in$37 , \output_logical_op__oe__ok$36 , \output_logical_op__oe__oe$35 , \output_logical_op__rc__ok$34 , \output_logical_op__rc__rc$33 , \output_logical_op__imm_data__ok$32 , \output_logical_op__imm_data__data$31 , \output_logical_op__fn_unit$30 , \output_logical_op__insn_type$29 }; + assign \muxid$59 = \output_muxid$28 ; + assign p_valid_i_p_ready_o = \$57 ; assign n_i_rdy_data = n_ready_i; - assign \p_valid_i$48 = p_valid_i; - assign { \xer_so_ok$47 , output_xer_so } = { xer_so_ok, xer_so }; - assign { \cr_a_ok$46 , output_cr_a } = { cr_a_ok, cr_a }; + assign \p_valid_i$56 = p_valid_i; + assign { \xer_so_ok$55 , output_xer_so } = { xer_so_ok, xer_so }; + assign { \cr_a_ok$54 , output_cr_a } = { cr_a_ok, cr_a }; assign { output_o_ok, output_o } = { o_ok, o }; - assign { output_logical_op__insn, output_logical_op__data_len, output_logical_op__is_signed, output_logical_op__is_32bit, output_logical_op__output_carry, output_logical_op__write_cr0, output_logical_op__invert_out, output_logical_op__input_carry, output_logical_op__zero_a, output_logical_op__invert_in, output_logical_op__oe__ok, output_logical_op__oe__oe, output_logical_op__rc__ok, output_logical_op__rc__rc, output_logical_op__imm_data__ok, output_logical_op__imm_data__data, output_logical_op__fn_unit, output_logical_op__insn_type } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; + assign { output_logical_op__SV_Ptype, output_logical_op__sv_saturate, output_logical_op__sv_pred_dz, output_logical_op__sv_pred_sz, output_logical_op__insn, output_logical_op__data_len, output_logical_op__is_signed, output_logical_op__is_32bit, output_logical_op__output_carry, output_logical_op__write_cr0, output_logical_op__invert_out, output_logical_op__input_carry, output_logical_op__zero_a, output_logical_op__invert_in, output_logical_op__oe__ok, output_logical_op__oe__oe, output_logical_op__rc__ok, output_logical_op__rc__rc, output_logical_op__imm_data__ok, output_logical_op__imm_data__data, output_logical_op__fn_unit, output_logical_op__insn_type } = { logical_op__SV_Ptype, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; assign output_muxid = muxid; endmodule @@ -147235,9 +157527,9 @@ module lsd_l(coresync_rst, s_lsd, r_lsd, q_lsd, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -147266,7 +157558,7 @@ module lsd_l(coresync_rst, s_lsd, r_lsd, q_lsd, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -147377,9 +157669,9 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ wire \$93 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" *) wire \$95 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) input dbus__ack; @@ -147549,7 +157841,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ \dbus__cyc$next = 1'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dbus__cyc$next = 1'h0; @@ -147577,7 +157869,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ \dbus__stb$next = 1'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dbus__stb$next = 1'h0; @@ -147638,7 +157930,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ \dbus__sel$next = 8'h00; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dbus__sel$next = 8'h00; @@ -147663,7 +157955,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \m_ld_data_o$next = 64'h0000000000000000; @@ -147690,7 +157982,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ \dbus__adr$next = 45'h000000000000; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dbus__adr$next = 45'h000000000000; @@ -147717,7 +158009,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ \dbus__we$next = 1'h0; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dbus__we$next = 1'h0; @@ -147744,7 +158036,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ \dbus__dat_w$next = 64'h0000000000000000; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \dbus__dat_w$next = 64'h0000000000000000; @@ -147767,7 +158059,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ \m_load_err_o$next = 1'h0; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \m_load_err_o$next = 1'h0; @@ -147790,7 +158082,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ \m_store_err_o$next = 1'h0; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \m_store_err_o$next = 1'h0; @@ -147810,7 +158102,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ \m_badaddr_o$next = dbus__adr; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \m_badaddr_o$next = 45'h000000000000; @@ -147822,39 +158114,39 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.main" *) (* generator = "nMigen" *) -module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, ra, rb, xer_so, xer_ca, \muxid$1 , \alu_op__insn_type$2 , \alu_op__fn_unit$3 , \alu_op__imm_data__data$4 , \alu_op__imm_data__ok$5 , \alu_op__rc__rc$6 , \alu_op__rc__ok$7 , \alu_op__oe__oe$8 , \alu_op__oe__ok$9 , \alu_op__invert_in$10 , \alu_op__zero_a$11 , \alu_op__invert_out$12 , \alu_op__write_cr0$13 , \alu_op__input_carry$14 , \alu_op__output_carry$15 , \alu_op__is_32bit$16 , \alu_op__is_signed$17 , \alu_op__data_len$18 , \alu_op__insn$19 , o, o_ok, cr_a, cr_a_ok, \xer_ca$20 , xer_ca_ok, xer_ov, xer_ov_ok, \xer_so$21 , muxid); +module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, alu_op__sv_pred_sz, alu_op__sv_pred_dz, alu_op__sv_saturate, alu_op__SV_Ptype, ra, rb, xer_so, xer_ca, \muxid$1 , \alu_op__insn_type$2 , \alu_op__fn_unit$3 , \alu_op__imm_data__data$4 , \alu_op__imm_data__ok$5 , \alu_op__rc__rc$6 , \alu_op__rc__ok$7 , \alu_op__oe__oe$8 , \alu_op__oe__ok$9 , \alu_op__invert_in$10 , \alu_op__zero_a$11 , \alu_op__invert_out$12 , \alu_op__write_cr0$13 , \alu_op__input_carry$14 , \alu_op__output_carry$15 , \alu_op__is_32bit$16 , \alu_op__is_signed$17 , \alu_op__data_len$18 , \alu_op__insn$19 , \alu_op__sv_pred_sz$20 , \alu_op__sv_pred_dz$21 , \alu_op__sv_saturate$22 , \alu_op__SV_Ptype$23 , o, o_ok, cr_a, cr_a_ok, \xer_ca$24 , xer_ca_ok, xer_ov, xer_ov_ok, \xer_so$25 , muxid); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:131" *) wire \$101 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:185" *) wire \$103 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" *) wire \$105 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:183" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" *) wire \$107 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" *) wire \$109 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:183" *) wire \$111 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" *) wire \$113 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" *) wire \$115 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) - wire \$116 ; + wire \$117 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) wire \$119 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) - wire \$121 ; + wire \$120 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) wire \$123 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) - wire \$124 ; + wire \$125 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) wire \$127 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) - wire \$129 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) + wire \$128 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) wire \$131 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) wire \$133 ; @@ -147868,85 +158160,85 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ wire \$141 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) wire \$143 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) + wire \$145 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) + wire \$147 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" *) - wire \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57" *) - wire \$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" *) wire \$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57" *) wire \$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" *) wire \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" *) wire \$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) - wire \$34 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" *) + wire \$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) wire \$36 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) wire \$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) - wire \$40 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" *) + wire \$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) wire \$42 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) wire \$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" *) wire \$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) + wire \$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) + wire \$50 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" *) - wire [66:0] \$48 ; + wire [66:0] \$52 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" *) - wire [66:0] \$49 ; + wire [66:0] \$53 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" *) - wire [63:0] \$51 ; + wire [63:0] \$55 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" *) - wire \$53 ; + wire \$57 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" *) - wire \$55 ; + wire \$59 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" *) - wire \$57 ; + wire \$61 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" *) - wire \$58 ; + wire \$62 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" *) - wire [31:0] \$59 ; + wire [31:0] \$63 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" *) - wire \$63 ; + wire \$67 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" *) - wire \$64 ; + wire \$68 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" *) - wire [31:0] \$65 ; + wire [31:0] \$69 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) - wire \$69 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) - wire \$71 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" *) wire \$73 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) wire \$75 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" *) wire \$77 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" *) wire \$79 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" *) wire \$81 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:120" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) wire \$83 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) wire \$85 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:120" *) wire \$87 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) wire \$89 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) wire \$91 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" *) wire \$93 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) wire \$95 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:131" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) wire \$97 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:185" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" *) wire \$99 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:65" *) reg [63:0] a_i; @@ -147960,67 +158252,81 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ reg [65:0] add_b; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" *) reg [65:0] add_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] alu_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \alu_op__SV_Ptype$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [3:0] alu_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [3:0] \alu_op__data_len$18 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] alu_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] alu_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \alu_op__fn_unit$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \alu_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] alu_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \alu_op__imm_data__data$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__imm_data__ok$5 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] alu_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [1:0] \alu_op__input_carry$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] alu_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \alu_op__insn$19 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -148097,7 +158403,9 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] alu_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -148174,51 +158482,73 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] \alu_op__insn_type$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__invert_in$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__invert_out$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__is_32bit$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__is_signed$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__oe__oe$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__oe__ok$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__output_carry$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__rc__ok$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__rc__rc$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input alu_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \alu_op__sv_pred_dz$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input alu_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \alu_op__sv_pred_sz$20 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] alu_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \alu_op__sv_saturate$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__write_cr0$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__zero_a$11 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:66" *) reg [63:0] b_i; @@ -148228,10 +158558,10 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ reg carry_32; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:101" *) reg carry_64; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [3:0] cr_a; reg [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_a_ok; reg cr_a_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" *) @@ -148246,120 +158576,120 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] \muxid$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] o; reg [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output o_ok; reg o_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:156" *) reg [1:0] ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] rb; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:179" *) reg [7:0] src1; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:98" *) reg [4:0] tval; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [1:0] xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [1:0] \xer_ca$20 ; - reg [1:0] \xer_ca$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [1:0] \xer_ca$24 ; + reg [1:0] \xer_ca$24 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ca_ok; reg xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [1:0] xer_ov; reg [1:0] xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ov_ok; reg xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \xer_so$21 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \xer_so$25 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:103" *) reg zerohi; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:102" *) reg zerolo; - assign \$99 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:185" *) eqs; - assign \$101 = alu_op__data_len == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" *) 1'h1; - assign \$103 = alu_op__data_len == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" *) 2'h2; - assign \$105 = alu_op__data_len == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" *) 3'h4; - assign \$107 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:183" *) eqs; - assign \$109 = a_i[32] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" *) b_i[32]; - assign \$111 = add_o[33] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" *) \$109 ; - assign \$113 = ca[0] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) add_o[64]; - assign \$116 = a_i[63] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) b_i[63]; - assign \$115 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) \$116 ; - assign \$119 = \$113 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) \$115 ; - assign \$121 = ca[1] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) add_o[32]; - assign \$124 = a_i[31] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) b_i[31]; - assign \$123 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) \$124 ; - assign \$127 = \$121 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) \$123 ; - assign \$129 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[7:0]; - assign \$131 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[15:8]; - assign \$133 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[23:16]; - assign \$135 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[31:24]; - assign \$137 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[39:32]; - assign \$139 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[47:40]; - assign \$141 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[55:48]; - assign \$143 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[63:56]; - assign \$22 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" *) 7'h0a; - assign \$24 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57" *) alu_op__insn[21]; - assign \$26 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" *) 7'h0a; - assign \$28 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" *) 7'h0a; - assign \$30 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" *) 7'h02; - assign \$32 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) 7'h0a; - assign \$34 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) \$32 ; - assign \$36 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" *) 7'h02; - assign \$38 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) 7'h0a; - assign \$40 = \$36 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) \$38 ; - assign \$42 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" *) 7'h02; - assign \$44 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) 7'h0a; - assign \$46 = \$42 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) \$44 ; - assign \$49 = add_a + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" *) add_b; - assign \$51 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" *) ra; - assign \$53 = add_o[33] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" *) ra[32]; - assign \$55 = \$53 ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" *) rb[32]; - assign \$59 = a_n[31:0] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" *) rb[31:0]; - assign \$58 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" *) \$59 ; - assign \$57 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" *) \$58 ; - assign \$65 = a_n[63:32] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" *) rb[63:32]; - assign \$64 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" *) \$65 ; - assign \$63 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" *) \$64 ; - assign \$69 = is_32bit | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) zerohi; - assign \$71 = zerolo & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) \$69 ; - assign \$73 = msb_a != (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" *) msb_b; - assign \$75 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" *) a_lt; - assign \$77 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" *) a_lt; - assign \$79 = is_32bit | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) zerohi; - assign \$81 = zerolo & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) \$79 ; - assign \$83 = is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:120" *) a_n[31] : a_n[63]; - assign \$85 = is_32bit | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) zerohi; - assign \$87 = zerolo & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) \$85 ; - assign \$89 = is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" *) rb[31] : rb[63]; - assign \$91 = is_32bit | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) zerohi; - assign \$93 = zerolo & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) \$91 ; - assign \$95 = msb_a != (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" *) msb_b; - assign \$97 = is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:131" *) carry_32 : carry_64; + assign \$99 = msb_a != (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" *) msb_b; + assign \$101 = is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:131" *) carry_32 : carry_64; + assign \$103 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:185" *) eqs; + assign \$105 = alu_op__data_len == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" *) 1'h1; + assign \$107 = alu_op__data_len == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" *) 2'h2; + assign \$109 = alu_op__data_len == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" *) 3'h4; + assign \$111 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:183" *) eqs; + assign \$113 = a_i[32] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" *) b_i[32]; + assign \$115 = add_o[33] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" *) \$113 ; + assign \$117 = ca[0] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) add_o[64]; + assign \$120 = a_i[63] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) b_i[63]; + assign \$119 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) \$120 ; + assign \$123 = \$117 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) \$119 ; + assign \$125 = ca[1] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) add_o[32]; + assign \$128 = a_i[31] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) b_i[31]; + assign \$127 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) \$128 ; + assign \$131 = \$125 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) \$127 ; + assign \$133 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[7:0]; + assign \$135 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[15:8]; + assign \$137 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[23:16]; + assign \$139 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[31:24]; + assign \$141 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[39:32]; + assign \$143 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[47:40]; + assign \$145 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[55:48]; + assign \$147 = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[63:56]; + assign \$26 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" *) 7'h0a; + assign \$28 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57" *) alu_op__insn[21]; + assign \$30 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" *) 7'h0a; + assign \$32 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" *) 7'h0a; + assign \$34 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" *) 7'h02; + assign \$36 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) 7'h0a; + assign \$38 = \$34 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) \$36 ; + assign \$40 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" *) 7'h02; + assign \$42 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) 7'h0a; + assign \$44 = \$40 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) \$42 ; + assign \$46 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" *) 7'h02; + assign \$48 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) 7'h0a; + assign \$50 = \$46 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) \$48 ; + assign \$53 = add_a + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" *) add_b; + assign \$55 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" *) ra; + assign \$57 = add_o[33] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" *) ra[32]; + assign \$59 = \$57 ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" *) rb[32]; + assign \$63 = a_n[31:0] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" *) rb[31:0]; + assign \$62 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" *) \$63 ; + assign \$61 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" *) \$62 ; + assign \$69 = a_n[63:32] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" *) rb[63:32]; + assign \$68 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" *) \$69 ; + assign \$67 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" *) \$68 ; + assign \$73 = is_32bit | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) zerohi; + assign \$75 = zerolo & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) \$73 ; + assign \$77 = msb_a != (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" *) msb_b; + assign \$79 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" *) a_lt; + assign \$81 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" *) a_lt; + assign \$83 = is_32bit | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) zerohi; + assign \$85 = zerolo & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) \$83 ; + assign \$87 = is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:120" *) a_n[31] : a_n[63]; + assign \$89 = is_32bit | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) zerohi; + assign \$91 = zerolo & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) \$89 ; + assign \$93 = is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" *) rb[31] : rb[63]; + assign \$95 = is_32bit | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) zerohi; + assign \$97 = zerolo & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) \$95 ; always @* begin if (\initial ) begin end is_32bit = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" *) - casez (\$22 ) + casez (\$26 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" */ 1'h1: - is_32bit = \$24 ; + is_32bit = \$28 ; endcase end always @* begin if (\initial ) begin end (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" *) - casez ({ is_32bit, \$26 }) + casez ({ is_32bit, \$30 }) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" */ 2'b?1: a_i = ra; @@ -148388,7 +158718,7 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ /* \nmigen.decoding = "OP_CMP/10" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" */ 7'h0a: - zerohi = \$63 ; + zerohi = \$67 ; endcase end always @* begin @@ -148401,7 +158731,7 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ 7'h0a: (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) - casez (\$71 ) + casez (\$75 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" */ 1'h1: tval[2] = 1'h1; @@ -148409,13 +158739,13 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ default: (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" *) - casez (\$73 ) + casez (\$77 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" */ 1'h1: tval = { msb_a, msb_b, 1'h0, msb_b, msb_a }; /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:128" */ default: - tval = { a_lt, \$77 , 1'h0, a_lt, \$75 }; + tval = { a_lt, \$81 , 1'h0, a_lt, \$79 }; endcase endcase endcase @@ -148430,13 +158760,13 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ 7'h0a: (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) - casez (\$81 ) + casez (\$85 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" */ 1'h1: /* empty */; /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" */ default: - msb_a = \$83 ; + msb_a = \$87 ; endcase endcase end @@ -148450,13 +158780,13 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ 7'h0a: (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) - casez (\$87 ) + casez (\$91 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" */ 1'h1: /* empty */; /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" */ default: - msb_b = \$89 ; + msb_b = \$93 ; endcase endcase end @@ -148470,7 +158800,7 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ 7'h0a: (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) - casez (\$93 ) + casez (\$97 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" */ 1'h1: /* empty */; @@ -148478,13 +158808,13 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ default: (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" *) - casez (\$95 ) + casez (\$99 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" */ 1'h1: /* empty */; /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:128" */ default: - a_lt = \$97 ; + a_lt = \$101 ; endcase endcase endcase @@ -148521,7 +158851,7 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ /* \nmigen.decoding = "OP_CMPEQB/12" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:177" */ 7'h0c: - cr_a = { 1'h0, \$99 , 2'h0 }; + cr_a = { 1'h0, \$103 , 2'h0 }; endcase end always @* begin @@ -148565,19 +158895,19 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ 7'h1f: begin (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" *) - casez (\$101 ) + casez (\$105 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" */ 1'h1: o = { ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7:0] }; endcase (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" *) - casez (\$103 ) + casez (\$107 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" */ 1'h1: o = { ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15:0] }; endcase (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" *) - casez (\$105 ) + casez (\$109 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" */ 1'h1: o = { ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31:0] }; @@ -148586,7 +158916,7 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ /* \nmigen.decoding = "OP_CMPEQB/12" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:177" */ 7'h0c: - o[0] = \$107 ; + o[0] = \$111 ; endcase end always @* begin @@ -148626,7 +158956,7 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ 7'h02: begin ca[0] = add_o[65]; - ca[1] = \$111 ; + ca[1] = \$115 ; end endcase end @@ -148634,7 +158964,7 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ if (\initial ) begin end (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" *) - casez ({ is_32bit, \$28 }) + casez ({ is_32bit, \$32 }) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" */ 2'b?1: b_i = rb; @@ -148657,7 +158987,7 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ end always @* begin if (\initial ) begin end - \xer_ca$20 = 2'h0; + \xer_ca$24 = 2'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *) casez (alu_op__insn_type) /* \nmigen.decoding = "OP_CMP/10" */ @@ -148667,7 +158997,7 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ /* \nmigen.decoding = "OP_ADD/2" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:143" */ 7'h02: - \xer_ca$20 = ca; + \xer_ca$24 = ca; endcase end always @* begin @@ -148698,8 +159028,8 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:143" */ 7'h02: begin - ov[0] = \$119 ; - ov[1] = \$127 ; + ov[0] = \$123 ; + ov[1] = \$131 ; end endcase end @@ -148777,14 +159107,14 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:177" */ 7'h0c: begin - eqs[0] = \$129 ; - eqs[1] = \$131 ; - eqs[2] = \$133 ; - eqs[3] = \$135 ; - eqs[4] = \$137 ; - eqs[5] = \$139 ; - eqs[6] = \$141 ; - eqs[7] = \$143 ; + eqs[0] = \$133 ; + eqs[1] = \$135 ; + eqs[2] = \$137 ; + eqs[3] = \$139 ; + eqs[4] = \$141 ; + eqs[5] = \$143 ; + eqs[6] = \$145 ; + eqs[7] = \$147 ; end endcase end @@ -148792,7 +159122,7 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ if (\initial ) begin end add_a = 66'h00000000000000000; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) - casez (\$34 ) + casez (\$38 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" */ 1'h1: add_a = { 1'h0, a_i, xer_ca[0] }; @@ -148802,7 +159132,7 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ if (\initial ) begin end add_b = 66'h00000000000000000; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) - casez (\$40 ) + casez (\$44 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" */ 1'h1: add_b = { 1'h0, b_i, 1'h1 }; @@ -148812,10 +159142,10 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ if (\initial ) begin end add_o = 66'h00000000000000000; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) - casez (\$46 ) + casez (\$50 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" */ 1'h1: - add_o = \$48 [65:0]; + add_o = \$52 [65:0]; endcase end always @* begin @@ -148826,7 +159156,7 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ /* \nmigen.decoding = "OP_CMP/10" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" */ 7'h0a: - a_n = \$51 ; + a_n = \$55 ; endcase end always @* begin @@ -148837,7 +159167,7 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ /* \nmigen.decoding = "OP_CMP/10" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" */ 7'h0a: - carry_32 = \$55 ; + carry_32 = \$59 ; endcase end always @* begin @@ -148859,18 +159189,18 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ /* \nmigen.decoding = "OP_CMP/10" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" */ 7'h0a: - zerolo = \$57 ; + zerolo = \$61 ; endcase end - assign \$48 = \$49 ; - assign { \alu_op__insn$19 , \alu_op__data_len$18 , \alu_op__is_signed$17 , \alu_op__is_32bit$16 , \alu_op__output_carry$15 , \alu_op__input_carry$14 , \alu_op__write_cr0$13 , \alu_op__invert_out$12 , \alu_op__zero_a$11 , \alu_op__invert_in$10 , \alu_op__oe__ok$9 , \alu_op__oe__oe$8 , \alu_op__rc__ok$7 , \alu_op__rc__rc$6 , \alu_op__imm_data__ok$5 , \alu_op__imm_data__data$4 , \alu_op__fn_unit$3 , \alu_op__insn_type$2 } = { alu_op__insn, alu_op__data_len, alu_op__is_signed, alu_op__is_32bit, alu_op__output_carry, alu_op__input_carry, alu_op__write_cr0, alu_op__invert_out, alu_op__zero_a, alu_op__invert_in, alu_op__oe__ok, alu_op__oe__oe, alu_op__rc__ok, alu_op__rc__rc, alu_op__imm_data__ok, alu_op__imm_data__data, alu_op__fn_unit, alu_op__insn_type }; + assign \$52 = \$53 ; + assign { \alu_op__SV_Ptype$23 , \alu_op__sv_saturate$22 , \alu_op__sv_pred_dz$21 , \alu_op__sv_pred_sz$20 , \alu_op__insn$19 , \alu_op__data_len$18 , \alu_op__is_signed$17 , \alu_op__is_32bit$16 , \alu_op__output_carry$15 , \alu_op__input_carry$14 , \alu_op__write_cr0$13 , \alu_op__invert_out$12 , \alu_op__zero_a$11 , \alu_op__invert_in$10 , \alu_op__oe__ok$9 , \alu_op__oe__oe$8 , \alu_op__rc__ok$7 , \alu_op__rc__rc$6 , \alu_op__imm_data__ok$5 , \alu_op__imm_data__data$4 , \alu_op__fn_unit$3 , \alu_op__insn_type$2 } = { alu_op__SV_Ptype, alu_op__sv_saturate, alu_op__sv_pred_dz, alu_op__sv_pred_sz, alu_op__insn, alu_op__data_len, alu_op__is_signed, alu_op__is_32bit, alu_op__output_carry, alu_op__input_carry, alu_op__write_cr0, alu_op__invert_out, alu_op__zero_a, alu_op__invert_in, alu_op__oe__ok, alu_op__oe__oe, alu_op__rc__ok, alu_op__rc__rc, alu_op__imm_data__ok, alu_op__imm_data__data, alu_op__fn_unit, alu_op__insn_type }; assign \muxid$1 = muxid; - assign \xer_so$21 = xer_so; + assign \xer_so$25 = xer_so; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main" *) (* generator = "nMigen" *) -module \main$114 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, ra, rb, rc, xer_so, \muxid$1 , \sr_op__insn_type$2 , \sr_op__fn_unit$3 , \sr_op__imm_data__data$4 , \sr_op__imm_data__ok$5 , \sr_op__rc__rc$6 , \sr_op__rc__ok$7 , \sr_op__oe__oe$8 , \sr_op__oe__ok$9 , \sr_op__write_cr0$10 , \sr_op__invert_in$11 , \sr_op__input_carry$12 , \sr_op__output_carry$13 , \sr_op__input_cr$14 , \sr_op__output_cr$15 , \sr_op__is_32bit$16 , \sr_op__is_signed$17 , \sr_op__insn$18 , o, o_ok, \xer_so$19 , xer_ca, muxid); +module \main$114 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, sr_op__sv_pred_sz, sr_op__sv_pred_dz, sr_op__sv_saturate, sr_op__SV_Ptype, ra, rb, rc, xer_so, \muxid$1 , \sr_op__insn_type$2 , \sr_op__fn_unit$3 , \sr_op__imm_data__data$4 , \sr_op__imm_data__ok$5 , \sr_op__rc__rc$6 , \sr_op__rc__ok$7 , \sr_op__oe__oe$8 , \sr_op__oe__ok$9 , \sr_op__write_cr0$10 , \sr_op__invert_in$11 , \sr_op__input_carry$12 , \sr_op__output_carry$13 , \sr_op__input_cr$14 , \sr_op__output_cr$15 , \sr_op__is_32bit$16 , \sr_op__is_signed$17 , \sr_op__insn$18 , \sr_op__sv_pred_sz$19 , \sr_op__sv_pred_dz$20 , \sr_op__sv_saturate$21 , \sr_op__SV_Ptype$22 , o, o_ok, \xer_so$23 , xer_ca, muxid); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:46" *) wire [4:0] mb; @@ -148884,16 +159214,16 @@ module \main$114 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] \muxid$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output o_ok; reg o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] rc; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:59" *) wire rotator_arith; @@ -148923,67 +159253,81 @@ module \main$114 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op wire [6:0] rotator_shift; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62" *) wire rotator_sign_ext_rs; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] sr_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \sr_op__SV_Ptype$22 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] sr_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] sr_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \sr_op__fn_unit$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \sr_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] sr_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \sr_op__imm_data__data$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__imm_data__ok$5 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] sr_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [1:0] \sr_op__input_carry$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__input_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__input_cr$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] sr_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \sr_op__insn$18 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -149060,7 +159404,9 @@ module \main$114 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] sr_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -149137,54 +159483,76 @@ module \main$114 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] \sr_op__insn_type$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__invert_in$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__is_32bit$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__is_signed$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__oe__oe$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__oe__ok$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__output_carry$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__output_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__output_cr$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__rc__ok$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__rc__rc$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input sr_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \sr_op__sv_pred_dz$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input sr_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \sr_op__sv_pred_sz$19 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] sr_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \sr_op__sv_saturate$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__write_cr0$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [1:0] xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \xer_so$19 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \xer_so$23 ; rotator rotator ( .arith(rotator_arith), .carry_out_o(rotator_carry_out_o), @@ -149268,9 +159636,9 @@ module \main$114 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op mode = 4'h8; endcase end - assign { \sr_op__insn$18 , \sr_op__is_signed$17 , \sr_op__is_32bit$16 , \sr_op__output_cr$15 , \sr_op__input_cr$14 , \sr_op__output_carry$13 , \sr_op__input_carry$12 , \sr_op__invert_in$11 , \sr_op__write_cr0$10 , \sr_op__oe__ok$9 , \sr_op__oe__oe$8 , \sr_op__rc__ok$7 , \sr_op__rc__rc$6 , \sr_op__imm_data__ok$5 , \sr_op__imm_data__data$4 , \sr_op__fn_unit$3 , \sr_op__insn_type$2 } = { sr_op__insn, sr_op__is_signed, sr_op__is_32bit, sr_op__output_cr, sr_op__input_cr, sr_op__output_carry, sr_op__input_carry, sr_op__invert_in, sr_op__write_cr0, sr_op__oe__ok, sr_op__oe__oe, sr_op__rc__ok, sr_op__rc__rc, sr_op__imm_data__ok, sr_op__imm_data__data, sr_op__fn_unit, sr_op__insn_type }; + assign { \sr_op__SV_Ptype$22 , \sr_op__sv_saturate$21 , \sr_op__sv_pred_dz$20 , \sr_op__sv_pred_sz$19 , \sr_op__insn$18 , \sr_op__is_signed$17 , \sr_op__is_32bit$16 , \sr_op__output_cr$15 , \sr_op__input_cr$14 , \sr_op__output_carry$13 , \sr_op__input_carry$12 , \sr_op__invert_in$11 , \sr_op__write_cr0$10 , \sr_op__oe__ok$9 , \sr_op__oe__oe$8 , \sr_op__rc__ok$7 , \sr_op__rc__rc$6 , \sr_op__imm_data__ok$5 , \sr_op__imm_data__data$4 , \sr_op__fn_unit$3 , \sr_op__insn_type$2 } = { sr_op__SV_Ptype, sr_op__sv_saturate, sr_op__sv_pred_dz, sr_op__sv_pred_sz, sr_op__insn, sr_op__is_signed, sr_op__is_32bit, sr_op__output_cr, sr_op__input_cr, sr_op__output_carry, sr_op__input_carry, sr_op__invert_in, sr_op__write_cr0, sr_op__oe__ok, sr_op__oe__oe, sr_op__rc__ok, sr_op__rc__rc, sr_op__imm_data__ok, sr_op__imm_data__data, sr_op__fn_unit, sr_op__insn_type }; assign \muxid$1 = muxid; - assign \xer_so$19 = xer_so; + assign \xer_so$23 = xer_so; assign xer_ca = { rotator_carry_out_o, rotator_carry_out_o }; assign o = rotator_result_o; assign { rotator_sign_ext_rs, rotator_clear_right, rotator_clear_left, rotator_right_shift } = mode; @@ -149289,50 +159657,50 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.main" *) (* generator = "nMigen" *) -module \main$22 (br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_op__imm_data__data, br_op__imm_data__ok, br_op__lk, br_op__is_32bit, fast1, fast2, cr_a, \muxid$1 , \br_op__cia$2 , \br_op__insn_type$3 , \br_op__fn_unit$4 , \br_op__insn$5 , \br_op__imm_data__data$6 , \br_op__imm_data__ok$7 , \br_op__lk$8 , \br_op__is_32bit$9 , \fast1$10 , fast1_ok, \fast2$11 , fast2_ok, nia, nia_ok, muxid); +module \main$22 (br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_op__imm_data__data, br_op__imm_data__ok, br_op__lk, br_op__is_32bit, br_op__sv_pred_sz, br_op__sv_pred_dz, br_op__sv_saturate, br_op__SV_Ptype, fast1, fast2, cr_a, \muxid$1 , \br_op__cia$2 , \br_op__insn_type$3 , \br_op__fn_unit$4 , \br_op__insn$5 , \br_op__imm_data__data$6 , \br_op__imm_data__ok$7 , \br_op__lk$8 , \br_op__is_32bit$9 , \br_op__sv_pred_sz$10 , \br_op__sv_pred_dz$11 , \br_op__sv_saturate$12 , \br_op__SV_Ptype$13 , \fast1$14 , fast1_ok, \fast2$15 , fast2_ok, nia, nia_ok, muxid); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" *) - wire \$12 ; + wire \$16 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" *) - wire \$14 ; + wire \$18 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" *) - wire [64:0] \$16 ; + wire [64:0] \$20 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" *) - wire [64:0] \$17 ; + wire [64:0] \$21 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" *) - wire \$19 ; + wire \$23 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" *) - wire \$21 ; + wire \$25 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" *) - wire \$23 ; + wire \$27 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" *) - wire \$25 ; + wire \$29 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" *) - wire \$27 ; + wire \$31 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" *) - wire \$29 ; + wire \$33 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" *) - wire \$31 ; + wire \$35 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" *) - wire \$33 ; + wire \$37 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" *) - wire [64:0] \$35 ; + wire [64:0] \$39 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" *) - wire [64:0] \$36 ; + wire [64:0] \$40 ; (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) - wire [63:0] \$38 ; + wire [63:0] \$42 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" *) - wire \$40 ; + wire \$44 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" *) - wire \$42 ; + wire \$46 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" *) - wire \$44 ; + wire \$48 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" *) - wire \$46 ; + wire \$50 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" *) - wire [64:0] \$48 ; + wire [64:0] \$52 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" *) - wire [64:0] \$49 ; + wire [64:0] \$53 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:119" *) reg bc_taken; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:109" *) @@ -149343,55 +159711,69 @@ module \main$22 (br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_o reg [63:0] br_addr; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:87" *) reg [63:0] br_imm_addr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] br_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \br_op__SV_Ptype$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] br_op__cia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \br_op__cia$2 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] br_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] br_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \br_op__fn_unit$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \br_op__fn_unit$4 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] br_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \br_op__imm_data__data$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input br_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \br_op__imm_data__ok$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] br_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \br_op__insn$5 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -149468,7 +159850,9 @@ module \main$22 (br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] br_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -149545,19 +159929,41 @@ module \main$22 (br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] \br_op__insn_type$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input br_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \br_op__is_32bit$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input br_op__lk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \br_op__lk$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input br_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \br_op__sv_pred_dz$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input br_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \br_op__sv_pred_sz$10 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] br_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \br_op__sv_saturate$12 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:89" *) reg br_taken; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [3:0] cr_a; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:110" *) reg cr_bit; @@ -149569,59 +159975,59 @@ module \main$22 (br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_o reg ctr_write; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:135" *) reg ctr_zero_bo1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [63:0] \fast1$10 ; - reg [63:0] \fast1$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [63:0] \fast1$14 ; + reg [63:0] \fast1$14 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output fast1_ok; reg fast1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] fast2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [63:0] \fast2$11 ; - reg [63:0] \fast2$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [63:0] \fast2$15 ; + reg [63:0] \fast2$15 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output fast2_ok; reg fast2_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] \muxid$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] nia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output nia_ok; - assign \$12 = br_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" *) 7'h08; - assign \$14 = br_op__insn[1] | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" *) \$12 ; - assign \$17 = br_imm_addr + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" *) br_op__cia; - assign \$19 = cr_bit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" *) bo[3]; - assign \$21 = \$19 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" *) bo[4]; - assign \$23 = bo[4:3] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" *) 1'h0; - assign \$25 = bo[4:3] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" *) 1'h1; - assign \$27 = bo[4] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" *) 1'h1; - assign \$29 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" *) cr_bit; - assign \$31 = ctr_zero_bo1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" *) \$29 ; - assign \$33 = ctr_zero_bo1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" *) cr_bit; - assign \$36 = fast1 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" *) 1'h1; - assign \$38 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) fast1[31:0]; - assign \$40 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" *) ctr_n; - assign \$42 = bo[1] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" *) \$40 ; - assign \$44 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" *) br_op__insn[6]; - assign \$46 = br_op__insn[10] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" *) \$44 ; - assign \$49 = br_op__cia + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" *) 3'h4; + assign \$16 = br_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" *) 7'h08; + assign \$18 = br_op__insn[1] | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" *) \$16 ; + assign \$21 = br_imm_addr + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" *) br_op__cia; + assign \$23 = cr_bit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" *) bo[3]; + assign \$25 = \$23 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" *) bo[4]; + assign \$27 = bo[4:3] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" *) 1'h0; + assign \$29 = bo[4:3] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" *) 1'h1; + assign \$31 = bo[4] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" *) 1'h1; + assign \$33 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" *) cr_bit; + assign \$35 = ctr_zero_bo1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" *) \$33 ; + assign \$37 = ctr_zero_bo1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" *) cr_bit; + assign \$40 = fast1 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" *) 1'h1; + assign \$42 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) fast1[31:0]; + assign \$44 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" *) ctr_n; + assign \$46 = bo[1] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" *) \$44 ; + assign \$48 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" *) br_op__insn[6]; + assign \$50 = br_op__insn[10] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" *) \$48 ; + assign \$53 = br_op__cia + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" *) 3'h4; always @* begin if (\initial ) begin end (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" *) - casez (\$14 ) + casez (\$18 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" */ 1'h1: br_addr = br_imm_addr; /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:94" */ default: - br_addr = \$16 [63:0]; + br_addr = \$20 [63:0]; endcase end always @* begin @@ -149642,7 +160048,7 @@ module \main$22 (br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_o 7'h08: (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" *) - casez (\$46 ) + casez (\$50 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" */ 1'h1: br_imm_addr = { fast1[63:2], 2'h0 }; @@ -149692,12 +160098,12 @@ module \main$22 (br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_o end always @* begin if (\initial ) begin end - \fast2$11 = 64'h0000000000000000; + \fast2$15 = 64'h0000000000000000; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" *) casez (br_op__lk) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" */ 1'h1: - \fast2$11 = \$48 [63:0]; + \fast2$15 = \$52 [63:0]; endcase end always @* begin @@ -149747,17 +160153,17 @@ module \main$22 (br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_o casez (bo[2]) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" */ 1'h1: - bc_taken = \$21 ; + bc_taken = \$25 ; /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122" */ default: (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" *) - casez ({ \$27 , \$25 , \$23 }) + casez ({ \$31 , \$29 , \$27 }) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" */ 3'b??1: - bc_taken = \$31 ; + bc_taken = \$35 ; /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" */ 3'b?1?: - bc_taken = \$33 ; + bc_taken = \$37 ; /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" */ 3'b1??: bc_taken = ctr_zero_bo1; @@ -149775,12 +160181,12 @@ module \main$22 (br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_o /* empty */; /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122" */ default: - ctr_n = \$35 [63:0]; + ctr_n = \$39 [63:0]; endcase end always @* begin if (\initial ) begin end - \fast1$10 = 64'h0000000000000000; + \fast1$14 = 64'h0000000000000000; (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" *) casez (bo[2]) @@ -149789,7 +160195,7 @@ module \main$22 (br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_o /* empty */; /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122" */ default: - \fast1$10 = ctr_n; + \fast1$14 = ctr_n; endcase end always @* begin @@ -149808,7 +160214,7 @@ module \main$22 (br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_o casez (br_op__is_32bit) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:130" */ 1'h1: - ctr_m = \$38 ; + ctr_m = \$42 ; /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:132" */ default: ctr_m = fast1; @@ -149826,13 +160232,13 @@ module \main$22 (br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_o /* empty */; /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122" */ default: - ctr_zero_bo1 = \$42 ; + ctr_zero_bo1 = \$46 ; endcase end - assign \$16 = \$17 ; - assign \$35 = \$36 ; - assign \$48 = \$49 ; - assign { \br_op__is_32bit$9 , \br_op__lk$8 , \br_op__imm_data__ok$7 , \br_op__imm_data__data$6 , \br_op__insn$5 , \br_op__fn_unit$4 , \br_op__insn_type$3 , \br_op__cia$2 } = { br_op__is_32bit, br_op__lk, br_op__imm_data__ok, br_op__imm_data__data, br_op__insn, br_op__fn_unit, br_op__insn_type, br_op__cia }; + assign \$20 = \$21 ; + assign \$39 = \$40 ; + assign \$52 = \$53 ; + assign { \br_op__SV_Ptype$13 , \br_op__sv_saturate$12 , \br_op__sv_pred_dz$11 , \br_op__sv_pred_sz$10 , \br_op__is_32bit$9 , \br_op__lk$8 , \br_op__imm_data__ok$7 , \br_op__imm_data__data$6 , \br_op__insn$5 , \br_op__fn_unit$4 , \br_op__insn_type$3 , \br_op__cia$2 } = { br_op__SV_Ptype, br_op__sv_saturate, br_op__sv_pred_dz, br_op__sv_pred_sz, br_op__is_32bit, br_op__lk, br_op__imm_data__ok, br_op__imm_data__data, br_op__insn, br_op__fn_unit, br_op__insn_type, br_op__cia }; assign \muxid$1 = muxid; assign nia_ok = br_taken; assign nia = br_addr; @@ -149842,191 +160248,223 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.main" *) (* generator = "nMigen" *) -module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, ra, rb, fast1, fast2, \muxid$1 , \trap_op__insn_type$2 , \trap_op__fn_unit$3 , \trap_op__insn$4 , \trap_op__msr$5 , \trap_op__cia$6 , \trap_op__is_32bit$7 , \trap_op__traptype$8 , \trap_op__trapaddr$9 , \trap_op__ldst_exc$10 , o, o_ok, \fast1$11 , fast1_ok, \fast2$12 , fast2_ok, nia, nia_ok, msr, msr_ok, muxid); +module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__svstate, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, trap_op__sv_pred_sz, trap_op__sv_pred_dz, trap_op__sv_saturate, trap_op__SV_Ptype, ra, rb, fast1, fast2, \muxid$1 , \trap_op__insn_type$2 , \trap_op__fn_unit$3 , \trap_op__insn$4 , \trap_op__msr$5 , \trap_op__cia$6 , \trap_op__svstate$7 , \trap_op__is_32bit$8 , \trap_op__traptype$9 , \trap_op__trapaddr$10 , \trap_op__ldst_exc$11 , \trap_op__sv_pred_sz$12 , \trap_op__sv_pred_dz$13 , \trap_op__sv_saturate$14 , \trap_op__SV_Ptype$15 , o, o_ok, \fast1$16 , fast1_ok, \fast2$17 , fast2_ok, fast3, fast3_ok, nia, nia_ok, msr, msr_ok, svstate, svstate_ok, muxid); reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:311" *) + wire \$100 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:312" *) + wire \$102 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:312" *) + wire \$104 ; (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) - wire [63:0] \$13 ; + wire [63:0] \$18 ; (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) - wire [63:0] \$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" *) - wire \$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" *) - wire \$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" *) - wire \$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" *) - wire \$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" *) - wire \$25 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" *) - wire \$27 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" *) - wire [4:0] \$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" *) - wire \$31 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" *) - wire \$33 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" *) - wire [63:0] \$35 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" *) - wire [19:0] \$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:315" *) - wire [64:0] \$39 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:315" *) - wire [64:0] \$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" *) - wire \$42 ; + wire [63:0] \$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171" *) + wire \$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:172" *) + wire \$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173" *) + wire \$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:174" *) + wire \$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175" *) + wire \$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" *) + wire \$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" *) + wire [4:0] \$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" *) + wire \$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" *) + wire \$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" *) + wire [63:0] \$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" *) + wire [19:0] \$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:331" *) + wire [64:0] \$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:331" *) + wire [64:0] \$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:198" *) + wire \$47 ; (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) - wire \$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" *) - wire [7:0] \$45 ; + wire \$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:201" *) + wire [7:0] \$50 ; (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) - wire \$48 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" *) - wire [7:0] \$49 ; + wire \$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:203" *) + wire [7:0] \$54 ; (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) - wire \$52 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" *) - wire [7:0] \$53 ; + wire \$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:205" *) + wire [7:0] \$58 ; (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) - wire \$56 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" *) - wire [7:0] \$57 ; + wire \$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:207" *) + wire [7:0] \$62 ; (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) - wire \$63 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" *) - wire [7:0] \$64 ; + wire \$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:221" *) + wire [7:0] \$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \$72 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \$74 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \$76 ; (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) - wire \$71 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" *) - wire [7:0] \$72 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [64:0] \$75 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" *) - wire \$77 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:240" *) - wire \$79 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" *) - wire \$81 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" *) - wire \$83 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" *) - wire \$85 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" *) - wire \$87 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" *) - wire \$89 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" *) - wire \$91 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" *) - wire \$93 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:141" *) + wire \$82 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:207" *) + wire [7:0] \$83 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [64:0] \$86 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:246" *) + wire \$88 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:252" *) + wire \$90 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:253" *) + wire \$92 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:253" *) + wire \$94 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:268" *) + wire \$96 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:298" *) + wire \$98 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149" *) reg [63:0] a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:138" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:146" *) reg [63:0] a_s; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:142" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:150" *) reg [63:0] b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:139" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:147" *) reg [63:0] b_s; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:161" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:169" *) wire equal; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [63:0] \fast1$11 ; - reg [63:0] \fast1$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [63:0] \fast1$16 ; + reg [63:0] \fast1$16 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output fast1_ok; reg fast1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] fast2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [63:0] \fast2$12 ; - reg [63:0] \fast2$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [63:0] \fast2$17 ; + reg [63:0] \fast2$17 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output fast2_ok; reg fast2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:158" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [63:0] fast3; + reg [63:0] fast3; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output fast3_ok; + reg fast3_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" *) wire gt_s; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:160" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:168" *) wire gt_u; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" *) wire lt_s; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:159" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" *) wire lt_u; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] msr; reg [63:0] msr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output msr_ok; reg msr_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] \muxid$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] nia; reg [63:0] nia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output nia_ok; reg nia_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] o; reg [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output o_ok; reg o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184" *) wire should_trap; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:134" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [31:0] svstate; + reg [31:0] svstate; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output svstate_ok; + reg svstate_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:142" *) wire [4:0] to; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" *) wire [4:0] trap_bits; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] trap_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \trap_op__SV_Ptype$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] trap_op__cia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \trap_op__cia$6 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] trap_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] trap_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \trap_op__fn_unit$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \trap_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] trap_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \trap_op__insn$4 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -150103,7 +160541,9 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] trap_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -150180,90 +160620,119 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] \trap_op__insn_type$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input trap_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output \trap_op__is_32bit$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \trap_op__is_32bit$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [7:0] trap_op__ldst_exc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [7:0] \trap_op__ldst_exc$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [7:0] \trap_op__ldst_exc$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] trap_op__msr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \trap_op__msr$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input trap_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \trap_op__sv_pred_dz$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input trap_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \trap_op__sv_pred_sz$12 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] trap_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \trap_op__sv_saturate$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [31:0] trap_op__svstate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [31:0] \trap_op__svstate$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [12:0] trap_op__trapaddr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [12:0] \trap_op__trapaddr$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [12:0] \trap_op__trapaddr$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [7:0] trap_op__traptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [7:0] \trap_op__traptype$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [7:0] \trap_op__traptype$9 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) reg \trapexc_$signal ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) - reg \trapexc_$signal$60 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) - reg \trapexc_$signal$61 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) - reg \trapexc_$signal$62 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) + reg \trapexc_$signal$65 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) + reg \trapexc_$signal$66 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) reg \trapexc_$signal$67 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) - reg \trapexc_$signal$68 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) - reg \trapexc_$signal$69 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) - reg \trapexc_$signal$70 ; - assign \$13 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) ra[31:0]; - assign \$15 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) rb[31:0]; - assign \$17 = $signed(a_s) < (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" *) $signed(b_s); - assign \$19 = $signed(a_s) > (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" *) $signed(b_s); - assign \$21 = a < (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" *) b; - assign \$23 = a > (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" *) b; - assign \$25 = a == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" *) b; - assign \$28 = trap_bits & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" *) to; - assign \$27 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" *) \$28 ; - assign \$31 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" *) trap_op__traptype; - assign \$33 = \$27 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" *) \$31 ; - assign \$36 = trap_op__trapaddr <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" *) 3'h4; - assign \$35 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" *) \$36 ; - assign \$40 = trap_op__cia + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:315" *) 3'h4; - assign \$42 = trap_op__traptype == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" *) 1'h0; - assign \$45 = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" *) 2'h2; - assign \$44 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$45 ; - assign \$49 = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" *) 1'h1; - assign \$48 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$49 ; - assign \$53 = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" *) 4'h8; - assign \$52 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$53 ; - assign \$57 = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" *) 7'h40; - assign \$56 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$57 ; - assign \$64 = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" *) 8'h80; - assign \$63 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$64 ; - assign \$72 = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" *) 7'h40; - assign \$71 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$72 ; - assign \$75 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) trap_op__msr; - assign \$77 = trap_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" *) 7'h48; - assign \$79 = trap_op__msr[34:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:240" *) 3'h2; - assign \$81 = ra[34:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" *) 3'h0; - assign \$83 = \$79 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" *) \$81 ; - assign \$85 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" *) trap_op__msr[60]; - assign \$87 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" *) trap_op__insn[9]; - assign \$89 = trap_op__msr[34:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" *) 3'h2; - assign \$91 = fast2[34:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" *) 3'h0; - assign \$93 = \$89 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" *) \$91 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) + reg \trapexc_$signal$78 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) + reg \trapexc_$signal$79 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) + reg \trapexc_$signal$80 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) + reg \trapexc_$signal$81 ; + assign \$100 = trap_op__msr[34:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:311" *) 3'h2; + assign \$102 = fast2[34:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:312" *) 3'h0; + assign \$104 = \$100 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:312" *) \$102 ; + assign \$18 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) ra[31:0]; + assign \$20 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) rb[31:0]; + assign \$22 = $signed(a_s) < (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171" *) $signed(b_s); + assign \$24 = $signed(a_s) > (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:172" *) $signed(b_s); + assign \$26 = a < (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173" *) b; + assign \$28 = a > (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:174" *) b; + assign \$30 = a == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175" *) b; + assign \$33 = trap_bits & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" *) to; + assign \$32 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" *) \$33 ; + assign \$36 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" *) trap_op__traptype; + assign \$38 = \$32 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" *) \$36 ; + assign \$41 = trap_op__trapaddr <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" *) 3'h4; + assign \$40 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" *) \$41 ; + assign \$45 = trap_op__cia + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:331" *) 3'h4; + assign \$47 = trap_op__traptype == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:198" *) 1'h0; + assign \$50 = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:201" *) 2'h2; + assign \$49 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$50 ; + assign \$54 = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:203" *) 1'h1; + assign \$53 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$54 ; + assign \$58 = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:205" *) 4'h8; + assign \$57 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$58 ; + assign \$62 = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:207" *) 7'h40; + assign \$61 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$62 ; + assign \$69 = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:221" *) 8'h80; + assign \$68 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$69 ; + assign \$72 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) trap_op__svstate; + assign \$74 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) trap_op__svstate; + assign \$76 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) trap_op__svstate; + assign \$83 = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:207" *) 7'h40; + assign \$82 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$83 ; + assign \$86 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) trap_op__msr; + assign \$88 = trap_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:246" *) 7'h48; + assign \$90 = trap_op__msr[34:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:252" *) 3'h2; + assign \$92 = ra[34:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:253" *) 3'h0; + assign \$94 = \$90 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:253" *) \$92 ; + assign \$96 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:268" *) trap_op__msr[60]; + assign \$98 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:298" *) trap_op__insn[9]; always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:153" *) casez (trap_op__is_32bit) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:153" */ 1'h1: a_s = { ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31:0] }; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:150" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:158" */ default: a_s = ra; endcase @@ -150271,31 +160740,31 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m always @* begin if (\initial ) begin end nia = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" *) casez (trap_op__insn_type) /* \nmigen.decoding = "OP_TRAP/63" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" */ 7'h3f: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" *) casez (should_trap) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" */ 1'h1: - nia = \$35 ; + nia = \$40 ; endcase /* \nmigen.decoding = "OP_MTMSRD/72|OP_MTMSR/74" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:223" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:235" */ 7'h48, 7'h4a: /* empty */; /* \nmigen.decoding = "OP_MFMSR/71" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:265" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:277" */ 7'h47: /* empty */; /* \nmigen.decoding = "OP_RFID/70" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:273" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:285" */ 7'h46: nia = { fast1[63:2], 2'h0 }; /* \nmigen.decoding = "OP_SC/73" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:304" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:320" */ 7'h49: nia = 64'h0000000000000c00; endcase @@ -150303,267 +160772,331 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m always @* begin if (\initial ) begin end nia_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" *) casez (trap_op__insn_type) /* \nmigen.decoding = "OP_TRAP/63" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" */ 7'h3f: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" *) casez (should_trap) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" */ 1'h1: nia_ok = 1'h1; endcase /* \nmigen.decoding = "OP_MTMSRD/72|OP_MTMSR/74" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:223" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:235" */ 7'h48, 7'h4a: /* empty */; /* \nmigen.decoding = "OP_MFMSR/71" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:265" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:277" */ 7'h47: /* empty */; /* \nmigen.decoding = "OP_RFID/70" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:273" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:285" */ 7'h46: nia_ok = 1'h1; /* \nmigen.decoding = "OP_SC/73" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:304" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:320" */ 7'h49: nia_ok = 1'h1; endcase end always @* begin if (\initial ) begin end - \fast1$11 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" *) + \fast1$16 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" *) casez (trap_op__insn_type) /* \nmigen.decoding = "OP_TRAP/63" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" */ 7'h3f: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" *) casez (should_trap) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" */ 1'h1: - \fast1$11 = trap_op__cia; + \fast1$16 = trap_op__cia; endcase /* \nmigen.decoding = "OP_MTMSRD/72|OP_MTMSR/74" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:223" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:235" */ 7'h48, 7'h4a: /* empty */; /* \nmigen.decoding = "OP_MFMSR/71" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:265" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:277" */ 7'h47: /* empty */; /* \nmigen.decoding = "OP_RFID/70" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:273" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:285" */ 7'h46: /* empty */; /* \nmigen.decoding = "OP_SC/73" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:304" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:320" */ 7'h49: - \fast1$11 = \$39 [63:0]; + \fast1$16 = \$44 [63:0]; endcase end always @* begin if (\initial ) begin end fast1_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" *) casez (trap_op__insn_type) /* \nmigen.decoding = "OP_TRAP/63" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" */ 7'h3f: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" *) casez (should_trap) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" */ 1'h1: fast1_ok = 1'h1; endcase /* \nmigen.decoding = "OP_MTMSRD/72|OP_MTMSR/74" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:223" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:235" */ 7'h48, 7'h4a: /* empty */; /* \nmigen.decoding = "OP_MFMSR/71" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:265" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:277" */ 7'h47: /* empty */; /* \nmigen.decoding = "OP_RFID/70" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:273" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:285" */ 7'h46: /* empty */; /* \nmigen.decoding = "OP_SC/73" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:304" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:320" */ 7'h49: fast1_ok = 1'h1; endcase end always @* begin if (\initial ) begin end - \fast2$12 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" *) + \fast2$17 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" *) casez (trap_op__insn_type) /* \nmigen.decoding = "OP_TRAP/63" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" */ 7'h3f: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" *) casez (should_trap) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" */ 1'h1: begin - \fast2$12 = 64'h0000000000000000; - \fast2$12 [15:0] = trap_op__msr[15:0]; - \fast2$12 [26:22] = trap_op__msr[26:22]; - \fast2$12 [63:31] = trap_op__msr[63:31]; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" *) - casez (\$42 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" */ + \fast2$17 = 64'h0000000000000000; + \fast2$17 [15:0] = trap_op__msr[15:0]; + \fast2$17 [26:22] = trap_op__msr[26:22]; + \fast2$17 [63:31] = trap_op__msr[63:31]; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:198" *) + casez (\$47 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:198" */ 1'h1: - \fast2$12 [17] = 1'h1; + \fast2$17 [17] = 1'h1; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" *) - casez (\$44 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:201" *) + casez (\$49 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:201" */ 1'h1: - \fast2$12 [18] = 1'h1; + \fast2$17 [18] = 1'h1; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" *) - casez (\$48 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:203" *) + casez (\$53 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:203" */ 1'h1: - \fast2$12 [20] = 1'h1; + \fast2$17 [20] = 1'h1; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" *) - casez (\$52 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:205" *) + casez (\$57 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:205" */ 1'h1: - \fast2$12 [16] = 1'h1; + \fast2$17 [16] = 1'h1; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" *) - casez (\$56 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:207" *) + casez (\$61 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:207" */ 1'h1: begin - \fast2$12 [30] = \trapexc_$signal ; - \fast2$12 [28] = \trapexc_$signal$60 ; - \fast2$12 [19] = \trapexc_$signal$61 ; - \fast2$12 [18] = \trapexc_$signal$62 ; + \fast2$17 [30] = \trapexc_$signal ; + \fast2$17 [28] = \trapexc_$signal$65 ; + \fast2$17 [19] = \trapexc_$signal$66 ; + \fast2$17 [18] = \trapexc_$signal$67 ; end endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" *) - casez (\$63 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:221" *) + casez (\$68 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:221" */ 1'h1: - \fast2$12 [19] = 1'h1; + \fast2$17 [19] = 1'h1; endcase end endcase /* \nmigen.decoding = "OP_MTMSRD/72|OP_MTMSR/74" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:223" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:235" */ 7'h48, 7'h4a: /* empty */; /* \nmigen.decoding = "OP_MFMSR/71" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:265" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:277" */ 7'h47: /* empty */; /* \nmigen.decoding = "OP_RFID/70" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:273" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:285" */ 7'h46: /* empty */; /* \nmigen.decoding = "OP_SC/73" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:304" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:320" */ 7'h49: begin - \fast2$12 = 64'h0000000000000000; - \fast2$12 [15:0] = trap_op__msr[15:0]; - \fast2$12 [26:22] = trap_op__msr[26:22]; - \fast2$12 [63:31] = trap_op__msr[63:31]; + \fast2$17 = 64'h0000000000000000; + \fast2$17 [15:0] = trap_op__msr[15:0]; + \fast2$17 [26:22] = trap_op__msr[26:22]; + \fast2$17 [63:31] = trap_op__msr[63:31]; end endcase end always @* begin if (\initial ) begin end fast2_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" *) casez (trap_op__insn_type) /* \nmigen.decoding = "OP_TRAP/63" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" */ 7'h3f: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" *) casez (should_trap) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" */ 1'h1: fast2_ok = 1'h1; endcase /* \nmigen.decoding = "OP_MTMSRD/72|OP_MTMSR/74" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:223" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:235" */ 7'h48, 7'h4a: /* empty */; /* \nmigen.decoding = "OP_MFMSR/71" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:265" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:277" */ 7'h47: /* empty */; /* \nmigen.decoding = "OP_RFID/70" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:273" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:285" */ 7'h46: /* empty */; /* \nmigen.decoding = "OP_SC/73" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:304" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:320" */ 7'h49: fast2_ok = 1'h1; endcase end always @* begin if (\initial ) begin end - \trapexc_$signal$67 = 1'h0; - \trapexc_$signal$68 = 1'h0; - \trapexc_$signal$69 = 1'h0; - \trapexc_$signal = 1'h0; - \trapexc_$signal$61 = 1'h0; - \trapexc_$signal$60 = 1'h0; - \trapexc_$signal$62 = 1'h0; - \trapexc_$signal$70 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" *) + fast3 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" *) casez (trap_op__insn_type) /* \nmigen.decoding = "OP_TRAP/63" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" */ 7'h3f: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" *) casez (should_trap) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" *) - casez (\$71 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" */ - 1'h1: - { \trapexc_$signal$70 , \trapexc_$signal$62 , \trapexc_$signal$60 , \trapexc_$signal$61 , \trapexc_$signal , \trapexc_$signal$69 , \trapexc_$signal$68 , \trapexc_$signal$67 } = trap_op__ldst_exc; - endcase + fast3 = \$74 ; + endcase + /* \nmigen.decoding = "OP_MTMSRD/72|OP_MTMSR/74" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:235" */ + 7'h48, 7'h4a: + /* empty */; + /* \nmigen.decoding = "OP_MFMSR/71" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:277" */ + 7'h47: + /* empty */; + /* \nmigen.decoding = "OP_RFID/70" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:285" */ + 7'h46: + /* empty */; + /* \nmigen.decoding = "OP_SC/73" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:320" */ + 7'h49: + fast3 = \$76 ; + endcase + end + always @* begin + if (\initial ) begin end + fast3_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" *) + casez (trap_op__insn_type) + /* \nmigen.decoding = "OP_TRAP/63" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" */ + 7'h3f: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" *) + casez (should_trap) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" */ + 1'h1: + fast3_ok = 1'h1; endcase + /* \nmigen.decoding = "OP_MTMSRD/72|OP_MTMSR/74" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:235" */ + 7'h48, 7'h4a: + /* empty */; + /* \nmigen.decoding = "OP_MFMSR/71" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:277" */ + 7'h47: + /* empty */; + /* \nmigen.decoding = "OP_RFID/70" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:285" */ + 7'h46: + /* empty */; + /* \nmigen.decoding = "OP_SC/73" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:320" */ + 7'h49: + fast3_ok = 1'h1; endcase end always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:153" *) casez (trap_op__is_32bit) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:153" */ 1'h1: b_s = { rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31:0] }; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:150" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:158" */ default: b_s = rb; endcase end + always @* begin + if (\initial ) begin end + \trapexc_$signal$78 = 1'h0; + \trapexc_$signal$79 = 1'h0; + \trapexc_$signal = 1'h0; + \trapexc_$signal$66 = 1'h0; + \trapexc_$signal$65 = 1'h0; + \trapexc_$signal$67 = 1'h0; + \trapexc_$signal$80 = 1'h0; + \trapexc_$signal$81 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" *) + casez (trap_op__insn_type) + /* \nmigen.decoding = "OP_TRAP/63" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" */ + 7'h3f: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" *) + casez (should_trap) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" */ + 1'h1: + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:207" *) + casez (\$82 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:207" */ + 1'h1: + { \trapexc_$signal$81 , \trapexc_$signal$80 , \trapexc_$signal$67 , \trapexc_$signal$65 , \trapexc_$signal$66 , \trapexc_$signal , \trapexc_$signal$79 , \trapexc_$signal$78 } = trap_op__ldst_exc; + endcase + endcase + endcase + end always @* begin if (\initial ) begin end msr = 64'h0000000000000000; msr_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" *) casez (trap_op__insn_type) /* \nmigen.decoding = "OP_TRAP/63" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" */ 7'h3f: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" *) casez (should_trap) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" */ 1'h1: begin msr = trap_op__msr; @@ -150588,39 +161121,39 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m end endcase /* \nmigen.decoding = "OP_MTMSRD/72|OP_MTMSR/74" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:223" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:235" */ 7'h48, 7'h4a: begin - { msr_ok, msr } = \$75 ; + { msr_ok, msr } = \$86 ; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:227" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:239" *) casez (trap_op__insn[21]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:227" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:239" */ 1'h1: begin msr[1] = ra[1]; msr[15] = ra[15]; end - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:231" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:243" */ default: begin (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" *) - casez (\$77 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:246" *) + casez (\$88 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:246" */ 1'h1: begin msr[11:1] = ra[11:1]; msr[59:13] = ra[59:13]; msr[63:61] = ra[63:61]; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" *) - casez (\$83 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:253" *) + casez (\$94 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:253" */ 1'h1: msr[34:32] = trap_op__msr[34:32]; endcase end - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:244" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" */ default: begin msr[11:1] = ra[11:1]; @@ -150639,9 +161172,9 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m endcase end endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" *) - casez (\$85 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:268" *) + casez (\$96 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:268" */ 1'h1: begin msr[60] = trap_op__msr[60]; @@ -150653,27 +161186,27 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m end end /* \nmigen.decoding = "OP_MFMSR/71" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:265" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:277" */ 7'h47: /* empty */; /* \nmigen.decoding = "OP_RFID/70" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:273" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:285" */ 7'h46: begin msr[15:0] = fast2[15:0]; msr[26:22] = fast2[26:22]; msr[63:31] = fast2[63:31]; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" *) - casez (\$87 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:298" *) + casez (\$98 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:298" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:283" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:299" *) casez (trap_op__msr[60]) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:283" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:299" */ 1'h1: msr[12] = fast2[12]; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:285" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:301" */ default: msr[12] = trap_op__msr[12]; endcase @@ -150688,9 +161221,9 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m msr[4] = 1'h1; end endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" *) - casez (\$93 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:312" *) + casez (\$104 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:312" */ 1'h1: msr[34:32] = trap_op__msr[34:32]; endcase @@ -150699,7 +161232,7 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m end end /* \nmigen.decoding = "OP_SC/73" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:304" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:320" */ 7'h49: begin msr = trap_op__msr; @@ -150724,21 +161257,34 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m end endcase end + always @* begin + if (\initial ) begin end + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:153" *) + casez (trap_op__is_32bit) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:153" */ + 1'h1: + a = \$18 ; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:158" */ + default: + a = ra; + endcase + end always @* begin if (\initial ) begin end o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" *) casez (trap_op__insn_type) /* \nmigen.decoding = "OP_TRAP/63" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" */ 7'h3f: /* empty */; /* \nmigen.decoding = "OP_MTMSRD/72|OP_MTMSR/74" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:223" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:235" */ 7'h48, 7'h4a: /* empty */; /* \nmigen.decoding = "OP_MFMSR/71" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:265" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:277" */ 7'h47: o = trap_op__msr; endcase @@ -150746,64 +161292,97 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m always @* begin if (\initial ) begin end o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" *) casez (trap_op__insn_type) /* \nmigen.decoding = "OP_TRAP/63" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" */ 7'h3f: /* empty */; /* \nmigen.decoding = "OP_MTMSRD/72|OP_MTMSR/74" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:223" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:235" */ 7'h48, 7'h4a: /* empty */; /* \nmigen.decoding = "OP_MFMSR/71" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:265" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:277" */ 7'h47: o_ok = 1'h1; endcase end always @* begin if (\initial ) begin end - (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" *) - casez (trap_op__is_32bit) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" */ - 1'h1: - a = \$13 ; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:150" */ - default: - a = ra; + svstate = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" *) + casez (trap_op__insn_type) + /* \nmigen.decoding = "OP_TRAP/63" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" */ + 7'h3f: + /* empty */; + /* \nmigen.decoding = "OP_MTMSRD/72|OP_MTMSR/74" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:235" */ + 7'h48, 7'h4a: + /* empty */; + /* \nmigen.decoding = "OP_MFMSR/71" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:277" */ + 7'h47: + /* empty */; + /* \nmigen.decoding = "OP_RFID/70" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:285" */ + 7'h46: + svstate = trap_op__svstate; + endcase + end + always @* begin + if (\initial ) begin end + svstate_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" *) + casez (trap_op__insn_type) + /* \nmigen.decoding = "OP_TRAP/63" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" */ + 7'h3f: + /* empty */; + /* \nmigen.decoding = "OP_MTMSRD/72|OP_MTMSR/74" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:235" */ + 7'h48, 7'h4a: + /* empty */; + /* \nmigen.decoding = "OP_MFMSR/71" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:277" */ + 7'h47: + /* empty */; + /* \nmigen.decoding = "OP_RFID/70" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:285" */ + 7'h46: + svstate_ok = 1'h1; endcase end always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:153" *) casez (trap_op__is_32bit) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:153" */ 1'h1: - b = \$15 ; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:150" */ + b = \$20 ; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:158" */ default: b = rb; endcase end - assign \$39 = \$40 ; - assign { \trap_op__ldst_exc$10 , \trap_op__trapaddr$9 , \trap_op__traptype$8 , \trap_op__is_32bit$7 , \trap_op__cia$6 , \trap_op__msr$5 , \trap_op__insn$4 , \trap_op__fn_unit$3 , \trap_op__insn_type$2 } = { trap_op__ldst_exc, trap_op__trapaddr, trap_op__traptype, trap_op__is_32bit, trap_op__cia, trap_op__msr, trap_op__insn, trap_op__fn_unit, trap_op__insn_type }; + assign \$44 = \$45 ; + assign { \trap_op__SV_Ptype$15 , \trap_op__sv_saturate$14 , \trap_op__sv_pred_dz$13 , \trap_op__sv_pred_sz$12 , \trap_op__ldst_exc$11 , \trap_op__trapaddr$10 , \trap_op__traptype$9 , \trap_op__is_32bit$8 , \trap_op__svstate$7 , \trap_op__cia$6 , \trap_op__msr$5 , \trap_op__insn$4 , \trap_op__fn_unit$3 , \trap_op__insn_type$2 } = { trap_op__SV_Ptype, trap_op__sv_saturate, trap_op__sv_pred_dz, trap_op__sv_pred_sz, trap_op__ldst_exc, trap_op__trapaddr, trap_op__traptype, trap_op__is_32bit, trap_op__svstate, trap_op__cia, trap_op__msr, trap_op__insn, trap_op__fn_unit, trap_op__insn_type }; assign \muxid$1 = muxid; - assign should_trap = \$33 ; + assign should_trap = \$38 ; assign trap_bits = { lt_s, gt_s, equal, lt_u, gt_u }; - assign equal = \$25 ; - assign gt_u = \$23 ; - assign lt_u = \$21 ; - assign gt_s = \$19 ; - assign lt_s = \$17 ; + assign equal = \$30 ; + assign gt_u = \$28 ; + assign lt_u = \$26 ; + assign gt_s = \$24 ; + assign lt_s = \$22 ; assign to = trap_op__insn[25:21]; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main" *) (* generator = "nMigen" *) -module \main$51 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, ra, rb, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , o, o_ok, \xer_so$20 , muxid); +module \main$51 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__SV_Ptype, ra, rb, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__SV_Ptype$23 , o, o_ok, \xer_so$24 , muxid); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) wire \$101 ; @@ -150859,42 +161438,42 @@ module \main$51 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_dat wire \$151 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) wire \$153 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) wire \$155 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) + wire \$157 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" *) + wire \$159 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" *) - wire [63:0] \$157 ; + wire [63:0] \$161 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" *) - wire \$158 ; + wire \$162 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" *) - wire [63:0] \$161 ; + wire [63:0] \$165 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" *) - wire [7:0] \$162 ; + wire [7:0] \$166 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" *) - wire [7:0] \$164 ; + wire [7:0] \$168 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" *) - wire [7:0] \$166 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \$169 ; + wire [7:0] \$170 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \$173 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" *) - wire \$171 ; + wire \$175 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" *) - wire \$173 ; + wire \$177 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" *) - wire [63:0] \$175 ; + wire [63:0] \$179 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" *) - wire [31:0] \$176 ; + wire [31:0] \$180 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" *) - wire [63:0] \$179 ; + wire [63:0] \$183 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" *) - wire [63:0] \$21 ; + wire [63:0] \$25 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" *) - wire [63:0] \$23 ; + wire [63:0] \$27 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" *) - wire [63:0] \$25 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) - wire \$27 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) - wire \$29 ; + wire [63:0] \$29 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) wire \$31 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) @@ -150983,67 +161562,81 @@ module \main$51 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_dat reg [63:0] cntz_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:99" *) reg count_right; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] logical_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \logical_op__SV_Ptype$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [3:0] logical_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [3:0] \logical_op__data_len$18 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] logical_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] logical_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \logical_op__fn_unit$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \logical_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] logical_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \logical_op__imm_data__data$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__imm_data__ok$5 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] logical_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [1:0] \logical_op__input_carry$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] logical_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \logical_op__insn$19 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -151120,7 +161713,9 @@ module \main$51 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_dat (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] logical_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -151197,60 +161792,82 @@ module \main$51 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_dat (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] \logical_op__insn_type$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__invert_in$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__invert_out$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__is_32bit$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__is_signed$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__oe__oe$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__oe__ok$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__output_carry$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__rc__ok$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__rc__rc$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input logical_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \logical_op__sv_pred_dz$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input logical_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \logical_op__sv_pred_sz$20 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] logical_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \logical_op__sv_saturate$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__write_cr0$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__zero_a$11 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] \muxid$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] o; reg [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output o_ok; reg o_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:84" *) @@ -151263,92 +161880,92 @@ module \main$51 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_dat reg [63:0] popcount_data_len; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30" *) wire [63:0] popcount_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \xer_so$20 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \xer_so$24 ; assign \$99 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32]; assign \$101 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32]; assign \$103 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32]; assign \$105 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32]; - assign \$107 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40]; - assign \$109 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40]; + assign \$107 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32]; + assign \$109 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32]; assign \$111 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40]; assign \$113 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40]; assign \$115 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40]; assign \$117 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40]; assign \$119 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40]; assign \$121 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40]; - assign \$123 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48]; - assign \$125 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48]; + assign \$123 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40]; + assign \$125 = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40]; assign \$127 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48]; assign \$129 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48]; assign \$131 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48]; assign \$133 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48]; assign \$135 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48]; assign \$137 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48]; - assign \$139 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56]; - assign \$141 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56]; + assign \$139 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48]; + assign \$141 = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48]; assign \$143 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56]; assign \$145 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56]; assign \$147 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56]; assign \$149 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56]; assign \$151 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56]; assign \$153 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56]; - assign \$155 = logical_op__data_len[3] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" *) 1'h1; - assign \$158 = par0 ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" *) par1; - assign \$157 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" *) \$158 ; - assign \$162 = clz_lz - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" *) 6'h20; - assign \$164 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" *) clz_lz; - assign \$166 = logical_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" *) \$162 : \$164 ; - assign \$161 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" *) \$166 ; - assign \$169 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) logical_op__data_len; - assign \$171 = ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" *) { ra[24], ra[16], ra[8], ra[0] }; - assign \$173 = ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" *) { ra[56], ra[48], ra[40], ra[32] }; - assign \$176 = count_right ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" *) { a32[0], a32[1], a32[2], a32[3], a32[4], a32[5], a32[6], a32[7], a32[8], a32[9], a32[10], a32[11], a32[12], a32[13], a32[14], a32[15], a32[16], a32[17], a32[18], a32[19], a32[20], a32[21], a32[22], a32[23], a32[24], a32[25], a32[26], a32[27], a32[28], a32[29], a32[30], a32[31] } : a32; - assign \$175 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" *) \$176 ; - assign \$179 = count_right ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" *) { ra[0], ra[1], ra[2], ra[3], ra[4], ra[5], ra[6], ra[7], ra[8], ra[9], ra[10], ra[11], ra[12], ra[13], ra[14], ra[15], ra[16], ra[17], ra[18], ra[19], ra[20], ra[21], ra[22], ra[23], ra[24], ra[25], ra[26], ra[27], ra[28], ra[29], ra[30], ra[31], ra[32], ra[33], ra[34], ra[35], ra[36], ra[37], ra[38], ra[39], ra[40], ra[41], ra[42], ra[43], ra[44], ra[45], ra[46], ra[47], ra[48], ra[49], ra[50], ra[51], ra[52], ra[53], ra[54], ra[55], ra[56], ra[57], ra[58], ra[59], ra[60], ra[61], ra[62], ra[63] } : ra; - assign \$21 = ra & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" *) rb; - assign \$23 = ra | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" *) rb; - assign \$25 = ra ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" *) rb; - assign \$27 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0]; - assign \$29 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0]; + assign \$155 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56]; + assign \$157 = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56]; + assign \$159 = logical_op__data_len[3] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" *) 1'h1; + assign \$162 = par0 ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" *) par1; + assign \$161 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" *) \$162 ; + assign \$166 = clz_lz - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" *) 6'h20; + assign \$168 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" *) clz_lz; + assign \$170 = logical_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" *) \$166 : \$168 ; + assign \$165 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" *) \$170 ; + assign \$173 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) logical_op__data_len; + assign \$175 = ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" *) { ra[24], ra[16], ra[8], ra[0] }; + assign \$177 = ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" *) { ra[56], ra[48], ra[40], ra[32] }; + assign \$180 = count_right ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" *) { a32[0], a32[1], a32[2], a32[3], a32[4], a32[5], a32[6], a32[7], a32[8], a32[9], a32[10], a32[11], a32[12], a32[13], a32[14], a32[15], a32[16], a32[17], a32[18], a32[19], a32[20], a32[21], a32[22], a32[23], a32[24], a32[25], a32[26], a32[27], a32[28], a32[29], a32[30], a32[31] } : a32; + assign \$179 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" *) \$180 ; + assign \$183 = count_right ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" *) { ra[0], ra[1], ra[2], ra[3], ra[4], ra[5], ra[6], ra[7], ra[8], ra[9], ra[10], ra[11], ra[12], ra[13], ra[14], ra[15], ra[16], ra[17], ra[18], ra[19], ra[20], ra[21], ra[22], ra[23], ra[24], ra[25], ra[26], ra[27], ra[28], ra[29], ra[30], ra[31], ra[32], ra[33], ra[34], ra[35], ra[36], ra[37], ra[38], ra[39], ra[40], ra[41], ra[42], ra[43], ra[44], ra[45], ra[46], ra[47], ra[48], ra[49], ra[50], ra[51], ra[52], ra[53], ra[54], ra[55], ra[56], ra[57], ra[58], ra[59], ra[60], ra[61], ra[62], ra[63] } : ra; + assign \$25 = ra & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" *) rb; + assign \$27 = ra | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" *) rb; + assign \$29 = ra ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" *) rb; assign \$31 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0]; assign \$33 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0]; assign \$35 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0]; assign \$37 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0]; assign \$39 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0]; assign \$41 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0]; - assign \$43 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8]; - assign \$45 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8]; + assign \$43 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0]; + assign \$45 = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0]; assign \$47 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8]; assign \$49 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8]; assign \$51 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8]; assign \$53 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8]; assign \$55 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8]; assign \$57 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8]; - assign \$59 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16]; - assign \$61 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16]; + assign \$59 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8]; + assign \$61 = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8]; assign \$63 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16]; assign \$65 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16]; assign \$67 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16]; assign \$69 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16]; assign \$71 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16]; assign \$73 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16]; - assign \$75 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24]; - assign \$77 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24]; + assign \$75 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16]; + assign \$77 = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16]; assign \$79 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24]; assign \$81 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24]; assign \$83 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24]; assign \$85 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24]; assign \$87 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24]; assign \$89 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24]; - assign \$91 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32]; - assign \$93 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32]; + assign \$91 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24]; + assign \$93 = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24]; assign \$95 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32]; assign \$97 = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32]; bpermd bpermd ( @@ -151375,19 +161992,19 @@ module \main$51 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_dat /* \nmigen.decoding = "OP_AND/4" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" */ 7'h04: - o = \$21 ; + o = \$25 ; /* \nmigen.decoding = "OP_OR/53" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" */ 7'h35: - o = \$23 ; + o = \$27 ; /* \nmigen.decoding = "OP_XOR/67" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" */ 7'h43: - o = \$25 ; + o = \$29 ; /* \nmigen.decoding = "OP_CMPB/11" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" */ 7'h0b: - o = { \$139 , \$141 , \$143 , \$145 , \$147 , \$149 , \$151 , \$153 , \$123 , \$125 , \$127 , \$129 , \$131 , \$133 , \$135 , \$137 , \$107 , \$109 , \$111 , \$113 , \$115 , \$117 , \$119 , \$121 , \$91 , \$93 , \$95 , \$97 , \$99 , \$101 , \$103 , \$105 , \$75 , \$77 , \$79 , \$81 , \$83 , \$85 , \$87 , \$89 , \$59 , \$61 , \$63 , \$65 , \$67 , \$69 , \$71 , \$73 , \$43 , \$45 , \$47 , \$49 , \$51 , \$53 , \$55 , \$57 , \$27 , \$29 , \$31 , \$33 , \$35 , \$37 , \$39 , \$41 }; + o = { \$143 , \$145 , \$147 , \$149 , \$151 , \$153 , \$155 , \$157 , \$127 , \$129 , \$131 , \$133 , \$135 , \$137 , \$139 , \$141 , \$111 , \$113 , \$115 , \$117 , \$119 , \$121 , \$123 , \$125 , \$95 , \$97 , \$99 , \$101 , \$103 , \$105 , \$107 , \$109 , \$79 , \$81 , \$83 , \$85 , \$87 , \$89 , \$91 , \$93 , \$63 , \$65 , \$67 , \$69 , \$71 , \$73 , \$75 , \$77 , \$47 , \$49 , \$51 , \$53 , \$55 , \$57 , \$59 , \$61 , \$31 , \$33 , \$35 , \$37 , \$39 , \$41 , \$43 , \$45 }; /* \nmigen.decoding = "OP_POPCNT/54" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" */ 7'h36: @@ -151397,10 +162014,10 @@ module \main$51 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_dat 7'h37: (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" *) - casez (\$155 ) + casez (\$159 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" */ 1'h1: - o = \$157 ; + o = \$161 ; /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:90" */ default: begin @@ -151411,7 +162028,7 @@ module \main$51 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_dat /* \nmigen.decoding = "OP_CNTZ/14" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" */ 7'h0e: - o = \$161 ; + o = \$165 ; /* \nmigen.decoding = "OP_BPERM/9" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:118" */ 7'h09: @@ -151613,7 +162230,7 @@ module \main$51 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_dat /* \nmigen.decoding = "OP_POPCNT/54" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" */ 7'h36: - popcount_data_len = \$169 ; + popcount_data_len = \$173 ; endcase end always @* begin @@ -151644,7 +162261,7 @@ module \main$51 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_dat /* \nmigen.decoding = "OP_PRTY/55" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" */ 7'h37: - par0 = \$171 ; + par0 = \$175 ; endcase end always @* begin @@ -151675,7 +162292,7 @@ module \main$51 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_dat /* \nmigen.decoding = "OP_PRTY/55" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" */ 7'h37: - par1 = \$173 ; + par1 = \$177 ; endcase end always @* begin @@ -151785,48 +162402,48 @@ module \main$51 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_dat casez (logical_op__is_32bit) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:106" */ 1'h1: - cntz_i = \$175 ; + cntz_i = \$179 ; /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:108" */ default: - cntz_i = \$179 ; + cntz_i = \$183 ; endcase endcase end - assign { \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; + assign { \logical_op__SV_Ptype$23 , \logical_op__sv_saturate$22 , \logical_op__sv_pred_dz$21 , \logical_op__sv_pred_sz$20 , \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__SV_Ptype, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; assign \muxid$1 = muxid; - assign \xer_so$20 = xer_so; + assign \xer_so$24 = xer_so; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.main" *) (* generator = "nMigen" *) -module \main$9 (cr_op__insn_type, cr_op__fn_unit, cr_op__insn, ra, rb, full_cr, cr_a, cr_b, cr_c, \muxid$1 , \cr_op__insn_type$2 , \cr_op__fn_unit$3 , \cr_op__insn$4 , o, o_ok, \full_cr$5 , full_cr_ok, \cr_a$6 , cr_a_ok, muxid); +module \main$9 (cr_op__insn_type, cr_op__fn_unit, cr_op__insn, cr_op__sv_pred_sz, cr_op__sv_pred_dz, cr_op__sv_saturate, cr_op__SV_Ptype, ra, rb, full_cr, cr_a, cr_b, cr_c, \muxid$1 , \cr_op__insn_type$2 , \cr_op__fn_unit$3 , \cr_op__insn$4 , \cr_op__sv_pred_sz$5 , \cr_op__sv_pred_dz$6 , \cr_op__sv_saturate$7 , \cr_op__SV_Ptype$8 , o, o_ok, \full_cr$9 , full_cr_ok, \cr_a$10 , cr_a_ok, muxid); reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [4:0] \$11 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" *) - wire [2:0] \$10 ; + wire [2:0] \$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" *) + wire [2:0] \$14 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" *) - wire [2:0] \$12 ; + wire [2:0] \$16 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" *) - wire [2:0] \$13 ; + wire [2:0] \$17 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" *) - wire [2:0] \$15 ; + wire [2:0] \$19 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" *) - wire [2:0] \$16 ; + wire [2:0] \$20 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" *) - wire \$18 ; + wire \$22 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" *) - wire \$20 ; + wire \$24 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" *) - wire \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \$24 ; + wire \$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \$28 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" *) - wire [64:0] \$26 ; + wire [64:0] \$30 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" *) - wire [63:0] \$27 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [4:0] \$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" *) - wire [2:0] \$9 ; + wire [63:0] \$31 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:131" *) reg [1:0] BC; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:82" *) @@ -151841,57 +162458,71 @@ module \main$9 (cr_op__insn_type, cr_op__fn_unit, cr_op__insn, ra, rb, full_cr, reg bit_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:81" *) reg [1:0] bt; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [3:0] \cr_a$6 ; - reg [3:0] \cr_a$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [3:0] \cr_a$10 ; + reg [3:0] \cr_a$10 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_a_ok; reg cr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [3:0] cr_b; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:136" *) reg cr_bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [3:0] cr_c; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] cr_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \cr_op__SV_Ptype$8 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] cr_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] cr_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \cr_op__fn_unit$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \cr_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] cr_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \cr_op__insn$4 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -151968,7 +162599,9 @@ module \main$9 (cr_op__insn_type, cr_op__fn_unit, cr_op__insn, ra, rb, full_cr, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] cr_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -152045,14 +162678,36 @@ module \main$9 (cr_op__insn_type, cr_op__fn_unit, cr_op__insn, ra, rb, full_cr, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] \cr_op__insn_type$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input cr_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \cr_op__sv_pred_dz$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input cr_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \cr_op__sv_pred_sz$5 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] cr_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \cr_op__sv_saturate$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [31:0] full_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [31:0] \full_cr$5 ; - reg [31:0] \full_cr$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [31:0] \full_cr$9 ; + reg [31:0] \full_cr$9 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output full_cr_ok; reg full_cr_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" *) @@ -152061,29 +162716,29 @@ module \main$9 (cr_op__insn_type, cr_op__fn_unit, cr_op__insn, ra, rb, full_cr, input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] \muxid$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] o; reg [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output o_ok; reg o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] rb; - assign \$10 = 2'h3 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" *) cr_op__insn[22:21]; - assign \$13 = 2'h3 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" *) cr_op__insn[17:16]; - assign \$16 = 2'h3 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" *) cr_op__insn[12:11]; - assign \$18 = bit_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" *) lut[3] : lut[1]; - assign \$20 = bit_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" *) lut[2] : lut[0]; - assign \$22 = bit_b ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" *) \$18 : \$20 ; - assign \$24 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) full_cr; - assign \$27 = cr_bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" *) ra : rb; - assign \$26 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" *) \$27 ; - assign \$7 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) cr_a; - always @* begin - if (\initial ) begin end - \cr_a$6 = 4'h0; + assign \$11 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) cr_a; + assign \$14 = 2'h3 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" *) cr_op__insn[22:21]; + assign \$17 = 2'h3 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" *) cr_op__insn[17:16]; + assign \$20 = 2'h3 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" *) cr_op__insn[12:11]; + assign \$22 = bit_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" *) lut[3] : lut[1]; + assign \$24 = bit_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" *) lut[2] : lut[0]; + assign \$26 = bit_b ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" *) \$22 : \$24 ; + assign \$28 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) full_cr; + assign \$31 = cr_bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" *) ra : rb; + assign \$30 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" *) \$31 ; + always @* begin + if (\initial ) begin end + \cr_a$10 = 4'h0; cr_a_ok = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" *) casez (cr_op__insn_type) @@ -152091,25 +162746,25 @@ module \main$9 (cr_op__insn_type, cr_op__fn_unit, cr_op__insn, ra, rb, full_cr, /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" */ 7'h2a: begin - { cr_a_ok, \cr_a$6 } = \$7 ; + { cr_a_ok, \cr_a$10 } = \$11 ; cr_a_ok = 1'h1; end /* \nmigen.decoding = "OP_CROP/69" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" */ 7'h45: begin - \cr_a$6 = cr_c; + \cr_a$10 = cr_c; (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:105" *) casez (bt) 2'h0: - \cr_a$6 [0] = bit_o; + \cr_a$10 [0] = bit_o; 2'h1: - \cr_a$6 [1] = bit_o; + \cr_a$10 [1] = bit_o; 2'h2: - \cr_a$6 [2] = bit_o; + \cr_a$10 [2] = bit_o; 2'h?: - \cr_a$6 [3] = bit_o; + \cr_a$10 [3] = bit_o; endcase begin cr_a_ok = 1'h1; @@ -152158,14 +162813,14 @@ module \main$9 (cr_op__insn_type, cr_op__fn_unit, cr_op__insn, ra, rb, full_cr, /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:118" */ 7'h2d: begin - o = \$24 ; + o = \$28 ; o_ok = 1'h1; end /* \nmigen.decoding = "OP_ISEL/35" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:127" */ 7'h23: begin - { o_ok, o } = \$26 ; + { o_ok, o } = \$30 ; o_ok = 1'h1; end /* \nmigen.decoding = "OP_SETB/59" */ @@ -152283,7 +162938,7 @@ module \main$9 (cr_op__insn_type, cr_op__fn_unit, cr_op__insn, ra, rb, full_cr, /* \nmigen.decoding = "OP_CROP/69" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" */ 7'h45: - bt = \$9 [1:0]; + bt = \$13 [1:0]; endcase end always @* begin @@ -152298,7 +162953,7 @@ module \main$9 (cr_op__insn_type, cr_op__fn_unit, cr_op__insn, ra, rb, full_cr, /* \nmigen.decoding = "OP_CROP/69" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" */ 7'h45: - ba = \$12 [1:0]; + ba = \$16 [1:0]; endcase end always @* begin @@ -152313,7 +162968,7 @@ module \main$9 (cr_op__insn_type, cr_op__fn_unit, cr_op__insn, ra, rb, full_cr, /* \nmigen.decoding = "OP_CROP/69" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" */ 7'h45: - bb = \$15 [1:0]; + bb = \$19 [1:0]; endcase end always @* begin @@ -152380,12 +163035,12 @@ module \main$9 (cr_op__insn_type, cr_op__fn_unit, cr_op__insn, ra, rb, full_cr, /* \nmigen.decoding = "OP_CROP/69" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" */ 7'h45: - bit_o = \$22 ; + bit_o = \$26 ; endcase end always @* begin if (\initial ) begin end - \full_cr$5 = 32'd0; + \full_cr$9 = 32'd0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" *) casez (cr_op__insn_type) /* \nmigen.decoding = "OP_MCRF/42" */ @@ -152399,19 +163054,19 @@ module \main$9 (cr_op__insn_type, cr_op__fn_unit, cr_op__insn, ra, rb, full_cr, /* \nmigen.decoding = "OP_MTCRF/48" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:109" */ 7'h30: - \full_cr$5 = ra[31:0]; + \full_cr$9 = ra[31:0]; endcase end - assign \$9 = \$10 ; - assign \$12 = \$13 ; - assign \$15 = \$16 ; - assign { \cr_op__insn$4 , \cr_op__fn_unit$3 , \cr_op__insn_type$2 } = { cr_op__insn, cr_op__fn_unit, cr_op__insn_type }; + assign \$13 = \$14 ; + assign \$16 = \$17 ; + assign \$19 = \$20 ; + assign { \cr_op__SV_Ptype$8 , \cr_op__sv_saturate$7 , \cr_op__sv_pred_dz$6 , \cr_op__sv_pred_sz$5 , \cr_op__insn$4 , \cr_op__fn_unit$3 , \cr_op__insn_type$2 } = { cr_op__SV_Ptype, cr_op__sv_saturate, cr_op__sv_pred_dz, cr_op__sv_pred_sz, cr_op__insn, cr_op__fn_unit, cr_op__insn_type }; assign \muxid$1 = muxid; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0" *) (* generator = "nMigen" *) -module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, oper_i_alu_mul0__imm_data__data, oper_i_alu_mul0__imm_data__ok, oper_i_alu_mul0__rc__rc, oper_i_alu_mul0__rc__ok, oper_i_alu_mul0__oe__oe, oper_i_alu_mul0__oe__ok, oper_i_alu_mul0__write_cr0, oper_i_alu_mul0__is_32bit, oper_i_alu_mul0__is_signed, oper_i_alu_mul0__insn, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, cr_a_ok, dest2_o, xer_ov_ok, dest3_o, xer_so_ok, dest4_o, coresync_clk); +module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, oper_i_alu_mul0__imm_data__data, oper_i_alu_mul0__imm_data__ok, oper_i_alu_mul0__rc__rc, oper_i_alu_mul0__rc__ok, oper_i_alu_mul0__oe__oe, oper_i_alu_mul0__oe__ok, oper_i_alu_mul0__write_cr0, oper_i_alu_mul0__is_32bit, oper_i_alu_mul0__is_signed, oper_i_alu_mul0__insn, oper_i_alu_mul0__sv_pred_sz, oper_i_alu_mul0__sv_pred_dz, oper_i_alu_mul0__sv_saturate, oper_i_alu_mul0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, cr_a_ok, dest2_o, xer_ov_ok, dest3_o, xer_so_ok, dest4_o, coresync_clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) wire \$10 ; @@ -152559,38 +163214,47 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, reg \alu_l_r_alu$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alu_l_s_alu; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [3:0] alu_mul0_cr_a; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] alu_mul0_mul_op__SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \alu_mul0_mul_op__SV_Ptype$next ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] alu_mul0_mul_op__fn_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] \alu_mul0_mul_op__fn_unit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] alu_mul0_mul_op__fn_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] \alu_mul0_mul_op__fn_unit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] alu_mul0_mul_op__imm_data__data = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] \alu_mul0_mul_op__imm_data__data$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_mul0_mul_op__imm_data__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_mul0_mul_op__imm_data__ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] alu_mul0_mul_op__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] \alu_mul0_mul_op__insn$next ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -152667,57 +163331,75 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] alu_mul0_mul_op__insn_type = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] \alu_mul0_mul_op__insn_type$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_mul0_mul_op__is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_mul0_mul_op__is_32bit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_mul0_mul_op__is_signed = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_mul0_mul_op__is_signed$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_mul0_mul_op__oe__oe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_mul0_mul_op__oe__oe$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_mul0_mul_op__oe__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_mul0_mul_op__oe__ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_mul0_mul_op__rc__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_mul0_mul_op__rc__ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_mul0_mul_op__rc__rc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_mul0_mul_op__rc__rc$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg alu_mul0_mul_op__sv_pred_dz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \alu_mul0_mul_op__sv_pred_dz$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg alu_mul0_mul_op__sv_pred_sz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \alu_mul0_mul_op__sv_pred_sz$next ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] alu_mul0_mul_op__sv_saturate = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \alu_mul0_mul_op__sv_saturate$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_mul0_mul_op__write_cr0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_mul0_mul_op__write_cr0$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) wire alu_mul0_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire alu_mul0_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] alu_mul0_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire alu_mul0_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) wire alu_mul0_p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] alu_mul0_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] alu_mul0_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [1:0] alu_mul0_xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire alu_mul0_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire \alu_mul0_xer_so$1 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" *) wire alu_pulse; @@ -152731,11 +163413,11 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_a_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) output cu_busy_o; @@ -152803,7 +163485,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) output dest4_o; reg dest4_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire opc_l_q_opc; @@ -152815,28 +163497,35 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, reg opc_l_s_opc = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) reg \opc_l_s_opc$next ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_mul0__SV_Ptype; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] oper_i_alu_mul0__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] oper_i_alu_mul0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] oper_i_alu_mul0__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_mul0__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] oper_i_alu_mul0__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -152913,21 +163602,33 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] oper_i_alu_mul0__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_mul0__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_mul0__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_mul0__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_mul0__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_mul0__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_mul0__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_mul0__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_mul0__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_mul0__sv_saturate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_mul0__write_cr0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *) reg [3:0] prev_wr_go = 4'h0; @@ -153005,9 +163706,9 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, wire src_sel; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" *) wire wr_any; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_so_ok; assign \$100 = \$96 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) \$98 ; assign \$102 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; @@ -153119,6 +163820,14 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, alu_mul0_mul_op__is_signed <= \alu_mul0_mul_op__is_signed$next ; always @(posedge coresync_clk) alu_mul0_mul_op__insn <= \alu_mul0_mul_op__insn$next ; + always @(posedge coresync_clk) + alu_mul0_mul_op__sv_pred_sz <= \alu_mul0_mul_op__sv_pred_sz$next ; + always @(posedge coresync_clk) + alu_mul0_mul_op__sv_pred_dz <= \alu_mul0_mul_op__sv_pred_dz$next ; + always @(posedge coresync_clk) + alu_mul0_mul_op__sv_saturate <= \alu_mul0_mul_op__sv_saturate$next ; + always @(posedge coresync_clk) + alu_mul0_mul_op__SV_Ptype <= \alu_mul0_mul_op__SV_Ptype$next ; always @(posedge coresync_clk) req_l_r_req <= \req_l_r_req$next ; always @(posedge coresync_clk) @@ -153157,6 +163866,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, .coresync_rst(coresync_rst), .cr_a(alu_mul0_cr_a), .cr_a_ok(cr_a_ok), + .mul_op__SV_Ptype(alu_mul0_mul_op__SV_Ptype), .mul_op__fn_unit(alu_mul0_mul_op__fn_unit), .mul_op__imm_data__data(alu_mul0_mul_op__imm_data__data), .mul_op__imm_data__ok(alu_mul0_mul_op__imm_data__ok), @@ -153168,6 +163878,9 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, .mul_op__oe__ok(alu_mul0_mul_op__oe__ok), .mul_op__rc__ok(alu_mul0_mul_op__rc__ok), .mul_op__rc__rc(alu_mul0_mul_op__rc__rc), + .mul_op__sv_pred_dz(alu_mul0_mul_op__sv_pred_dz), + .mul_op__sv_pred_sz(alu_mul0_mul_op__sv_pred_sz), + .mul_op__sv_saturate(alu_mul0_mul_op__sv_saturate), .mul_op__write_cr0(alu_mul0_mul_op__write_cr0), .n_ready_i(alu_mul0_n_ready_i), .n_valid_o(alu_mul0_n_valid_o), @@ -153237,7 +163950,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \rok_l_s_rdok$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_s_rdok$next = 1'h0; @@ -153246,7 +163959,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \rok_l_r_rdok$next = \$64 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_r_rdok$next = 1'h1; @@ -153255,7 +163968,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \rst_l_s_rst$next = all_rd; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_s_rst$next = 1'h0; @@ -153264,7 +163977,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \rst_l_r_rst$next = rst_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_r_rst$next = 1'h1; @@ -153273,7 +163986,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \opc_l_s_opc$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_s_opc$next = 1'h0; @@ -153282,7 +163995,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \opc_l_r_opc$next = req_done; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_r_opc$next = 1'h1; @@ -153291,7 +164004,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_s_src$next = 3'h0; @@ -153300,7 +164013,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \src_l_r_src$next = reset_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_r_src$next = 3'h7; @@ -153309,7 +164022,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \req_l_s_req$next = \$66 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_s_req$next = 4'h0; @@ -153318,7 +164031,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \req_l_r_req$next = \$68 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_r_req$next = 4'hf; @@ -153338,13 +164051,17 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, \alu_mul0_mul_op__is_32bit$next = alu_mul0_mul_op__is_32bit; \alu_mul0_mul_op__is_signed$next = alu_mul0_mul_op__is_signed; \alu_mul0_mul_op__insn$next = alu_mul0_mul_op__insn; + \alu_mul0_mul_op__sv_pred_sz$next = alu_mul0_mul_op__sv_pred_sz; + \alu_mul0_mul_op__sv_pred_dz$next = alu_mul0_mul_op__sv_pred_dz; + \alu_mul0_mul_op__sv_saturate$next = alu_mul0_mul_op__sv_saturate; + \alu_mul0_mul_op__SV_Ptype$next = alu_mul0_mul_op__SV_Ptype; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *) casez (cu_issue_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" */ 1'h1: - { \alu_mul0_mul_op__insn$next , \alu_mul0_mul_op__is_signed$next , \alu_mul0_mul_op__is_32bit$next , \alu_mul0_mul_op__write_cr0$next , \alu_mul0_mul_op__oe__ok$next , \alu_mul0_mul_op__oe__oe$next , \alu_mul0_mul_op__rc__ok$next , \alu_mul0_mul_op__rc__rc$next , \alu_mul0_mul_op__imm_data__ok$next , \alu_mul0_mul_op__imm_data__data$next , \alu_mul0_mul_op__fn_unit$next , \alu_mul0_mul_op__insn_type$next } = { oper_i_alu_mul0__insn, oper_i_alu_mul0__is_signed, oper_i_alu_mul0__is_32bit, oper_i_alu_mul0__write_cr0, oper_i_alu_mul0__oe__ok, oper_i_alu_mul0__oe__oe, oper_i_alu_mul0__rc__ok, oper_i_alu_mul0__rc__rc, oper_i_alu_mul0__imm_data__ok, oper_i_alu_mul0__imm_data__data, oper_i_alu_mul0__fn_unit, oper_i_alu_mul0__insn_type }; + { \alu_mul0_mul_op__SV_Ptype$next , \alu_mul0_mul_op__sv_saturate$next , \alu_mul0_mul_op__sv_pred_dz$next , \alu_mul0_mul_op__sv_pred_sz$next , \alu_mul0_mul_op__insn$next , \alu_mul0_mul_op__is_signed$next , \alu_mul0_mul_op__is_32bit$next , \alu_mul0_mul_op__write_cr0$next , \alu_mul0_mul_op__oe__ok$next , \alu_mul0_mul_op__oe__oe$next , \alu_mul0_mul_op__rc__ok$next , \alu_mul0_mul_op__rc__rc$next , \alu_mul0_mul_op__imm_data__ok$next , \alu_mul0_mul_op__imm_data__data$next , \alu_mul0_mul_op__fn_unit$next , \alu_mul0_mul_op__insn_type$next } = { oper_i_alu_mul0__SV_Ptype, oper_i_alu_mul0__sv_saturate, oper_i_alu_mul0__sv_pred_dz, oper_i_alu_mul0__sv_pred_sz, oper_i_alu_mul0__insn, oper_i_alu_mul0__is_signed, oper_i_alu_mul0__is_32bit, oper_i_alu_mul0__write_cr0, oper_i_alu_mul0__oe__ok, oper_i_alu_mul0__oe__oe, oper_i_alu_mul0__rc__ok, oper_i_alu_mul0__rc__rc, oper_i_alu_mul0__imm_data__ok, oper_i_alu_mul0__imm_data__data, oper_i_alu_mul0__fn_unit, oper_i_alu_mul0__insn_type }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -153373,7 +164090,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, 1'h1: { \data_r0__o_ok$next , \data_r0__o$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r0__o_ok$next = 1'h0; @@ -153395,7 +164112,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, 1'h1: { \data_r1__cr_a_ok$next , \data_r1__cr_a$next } = 5'h00; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r1__cr_a_ok$next = 1'h0; @@ -153417,7 +164134,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, 1'h1: { \data_r2__xer_ov_ok$next , \data_r2__xer_ov$next } = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r2__xer_ov_ok$next = 1'h0; @@ -153439,7 +164156,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, 1'h1: { \data_r3__xer_so_ok$next , \data_r3__xer_so$next } = 2'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r3__xer_so_ok$next = 1'h0; @@ -153478,7 +164195,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \alui_l_r_alui$next = \$88 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alui_l_r_alui$next = 1'h1; @@ -153487,7 +164204,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \alu_l_r_alu$next = \$90 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alu_l_r_alu$next = 1'h1; @@ -153536,7 +164253,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \prev_wr_go$next = \$20 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \prev_wr_go$next = 4'h0; @@ -153576,94 +164293,108 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.mul1" *) (* generator = "nMigen" *) -module mul1(mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, ra, rb, xer_so, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \ra$14 , \rb$15 , \xer_so$16 , neg_res, neg_res32, muxid); +module mul1(mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, mul_op__sv_pred_sz, mul_op__sv_pred_dz, mul_op__sv_saturate, mul_op__SV_Ptype, ra, rb, xer_so, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \mul_op__sv_pred_sz$14 , \mul_op__sv_pred_dz$15 , \mul_op__sv_saturate$16 , \mul_op__SV_Ptype$17 , \ra$18 , \rb$19 , \xer_so$20 , neg_res, neg_res32, muxid); (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" *) - wire \$17 ; + wire \$21 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" *) - wire \$19 ; + wire \$23 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" *) - wire \$21 ; + wire \$25 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" *) - wire \$23 ; + wire \$27 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" *) - wire \$25 ; + wire \$29 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" *) - wire \$27 ; + wire \$31 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" *) - wire \$29 ; + wire \$33 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" *) - wire \$31 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" *) - wire [64:0] \$33 ; + wire \$35 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" *) - wire [64:0] \$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [64:0] \$36 ; + wire [64:0] \$37 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" *) wire [64:0] \$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [64:0] \$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" *) + wire [64:0] \$42 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" *) - wire [64:0] \$41 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [64:0] \$43 ; + wire [64:0] \$44 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" *) wire [64:0] \$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [64:0] \$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" *) + wire [64:0] \$49 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *) - wire [31:0] \$47 ; + wire [31:0] \$51 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *) - wire [31:0] \$49 ; + wire [31:0] \$53 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:50" *) wire [63:0] abs_a; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:51" *) wire [63:0] abs_b; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:30" *) wire is_32bit; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] mul_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \mul_op__SV_Ptype$17 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] mul_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] mul_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \mul_op__fn_unit$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \mul_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] mul_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \mul_op__imm_data__data$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__imm_data__ok$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] mul_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \mul_op__insn$13 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -153740,7 +164471,9 @@ module mul1(mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] mul_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -153817,35 +164550,57 @@ module mul1(mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] \mul_op__insn_type$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__is_32bit$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__is_signed$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__oe__oe$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__oe__ok$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__rc__ok$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__rc__rc$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input mul_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \mul_op__sv_pred_dz$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input mul_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \mul_op__sv_pred_sz$14 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] mul_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \mul_op__sv_saturate$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__write_cr0$10 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; @@ -153855,14 +164610,14 @@ module mul1(mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__ output neg_res; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *) output neg_res32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - output [63:0] \ra$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + output [63:0] \ra$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - output [63:0] \rb$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + output [63:0] \rb$19 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:33" *) wire sign32_a; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:34" *) @@ -153871,98 +164626,112 @@ module mul1(mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__ wire sign_a; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:32" *) wire sign_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - output \xer_so$16 ; - assign \$17 = mul_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" *) ra[31] : ra[63]; - assign \$19 = \$17 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" *) mul_op__is_signed; - assign \$21 = mul_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" *) rb[31] : rb[63]; - assign \$23 = \$21 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" *) mul_op__is_signed; - assign \$25 = ra[31] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" *) mul_op__is_signed; - assign \$27 = rb[31] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" *) mul_op__is_signed; - assign \$29 = sign_a ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" *) sign_b; - assign \$31 = sign32_a ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" *) sign32_b; - assign \$34 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" *) ra; - assign \$36 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) ra; - assign \$38 = sign_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" *) \$34 : \$36 ; - assign \$41 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" *) rb; - assign \$43 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) rb; - assign \$45 = sign_b ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" *) \$41 : \$43 ; - assign \$47 = is_32bit ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *) 32'd0 : abs_a[63:32]; - assign \$49 = is_32bit ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *) 32'd0 : abs_b[63:32]; - assign \$33 = \$38 ; - assign \$40 = \$45 ; - assign { \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2 } = { mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type }; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + output \xer_so$20 ; + assign \$21 = mul_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" *) ra[31] : ra[63]; + assign \$23 = \$21 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" *) mul_op__is_signed; + assign \$25 = mul_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" *) rb[31] : rb[63]; + assign \$27 = \$25 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" *) mul_op__is_signed; + assign \$29 = ra[31] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" *) mul_op__is_signed; + assign \$31 = rb[31] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" *) mul_op__is_signed; + assign \$33 = sign_a ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" *) sign_b; + assign \$35 = sign32_a ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" *) sign32_b; + assign \$38 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" *) ra; + assign \$40 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) ra; + assign \$42 = sign_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" *) \$38 : \$40 ; + assign \$45 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" *) rb; + assign \$47 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) rb; + assign \$49 = sign_b ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" *) \$45 : \$47 ; + assign \$51 = is_32bit ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *) 32'd0 : abs_a[63:32]; + assign \$53 = is_32bit ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *) 32'd0 : abs_b[63:32]; + assign \$37 = \$42 ; + assign \$44 = \$49 ; + assign { \mul_op__SV_Ptype$17 , \mul_op__sv_saturate$16 , \mul_op__sv_pred_dz$15 , \mul_op__sv_pred_sz$14 , \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2 } = { mul_op__SV_Ptype, mul_op__sv_saturate, mul_op__sv_pred_dz, mul_op__sv_pred_sz, mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type }; assign \muxid$1 = muxid; - assign \xer_so$16 = xer_so; - assign \rb$15 [63:32] = \$49 ; - assign \rb$15 [31:0] = abs_b[31:0]; - assign \ra$14 [63:32] = \$47 ; - assign \ra$14 [31:0] = abs_a[31:0]; - assign abs_b = \$45 [63:0]; - assign abs_a = \$38 [63:0]; - assign neg_res32 = \$31 ; - assign neg_res = \$29 ; - assign sign32_b = \$27 ; - assign sign32_a = \$25 ; - assign sign_b = \$23 ; - assign sign_a = \$19 ; + assign \xer_so$20 = xer_so; + assign \rb$19 [63:32] = \$53 ; + assign \rb$19 [31:0] = abs_b[31:0]; + assign \ra$18 [63:32] = \$51 ; + assign \ra$18 [31:0] = abs_a[31:0]; + assign abs_b = \$49 [63:0]; + assign abs_a = \$42 [63:0]; + assign neg_res32 = \$35 ; + assign neg_res = \$33 ; + assign sign32_b = \$31 ; + assign sign32_a = \$29 ; + assign sign_b = \$27 ; + assign sign_a = \$23 ; assign is_32bit = mul_op__is_32bit; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.mul2" *) (* generator = "nMigen" *) -module mul2(mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, ra, rb, xer_so, neg_res, neg_res32, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , o, \xer_so$14 , \neg_res$15 , \neg_res32$16 , muxid); +module mul2(mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, mul_op__sv_pred_sz, mul_op__sv_pred_dz, mul_op__sv_saturate, mul_op__SV_Ptype, ra, rb, xer_so, neg_res, neg_res32, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \mul_op__sv_pred_sz$14 , \mul_op__sv_pred_dz$15 , \mul_op__sv_saturate$16 , \mul_op__SV_Ptype$17 , o, \xer_so$18 , \neg_res$19 , \neg_res32$20 , muxid); (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" *) - wire [128:0] \$17 ; + wire [128:0] \$21 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" *) - wire [127:0] \$18 ; + wire [127:0] \$22 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] mul_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \mul_op__SV_Ptype$17 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] mul_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] mul_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \mul_op__fn_unit$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \mul_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] mul_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \mul_op__imm_data__data$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__imm_data__ok$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] mul_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \mul_op__insn$13 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -154039,7 +164808,9 @@ module mul2(mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] mul_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -154116,35 +164887,57 @@ module mul2(mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] \mul_op__insn_type$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__is_32bit$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__is_signed$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__oe__oe$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__oe__ok$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__rc__ok$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__rc__rc$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input mul_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \mul_op__sv_pred_dz$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input mul_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \mul_op__sv_pred_sz$14 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] mul_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \mul_op__sv_saturate$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__write_cr0$10 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; @@ -154153,110 +164946,124 @@ module mul2(mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *) input neg_res; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *) - output \neg_res$15 ; + output \neg_res$19 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *) input neg_res32; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *) - output \neg_res32$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + output \neg_res32$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) output [128:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - output \xer_so$14 ; - assign \$18 = ra * (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" *) rb; - assign \$17 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" *) \$18 ; - assign { \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2 } = { mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type }; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + output \xer_so$18 ; + assign \$22 = ra * (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" *) rb; + assign \$21 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" *) \$22 ; + assign { \mul_op__SV_Ptype$17 , \mul_op__sv_saturate$16 , \mul_op__sv_pred_dz$15 , \mul_op__sv_pred_sz$14 , \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2 } = { mul_op__SV_Ptype, mul_op__sv_saturate, mul_op__sv_pred_dz, mul_op__sv_pred_sz, mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type }; assign \muxid$1 = muxid; - assign \xer_so$14 = xer_so; - assign \neg_res32$16 = neg_res32; - assign \neg_res$15 = neg_res; - assign o = \$17 ; + assign \xer_so$18 = xer_so; + assign \neg_res32$20 = neg_res32; + assign \neg_res$19 = neg_res; + assign o = \$21 ; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.mul3" *) (* generator = "nMigen" *) -module mul3(mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, o, xer_so, neg_res, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \o$14 , o_ok, xer_ov, xer_ov_ok, \xer_so$15 , xer_so_ok, muxid); +module mul3(mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, mul_op__sv_pred_sz, mul_op__sv_pred_dz, mul_op__sv_saturate, mul_op__SV_Ptype, o, xer_so, neg_res, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \mul_op__sv_pred_sz$14 , \mul_op__sv_pred_dz$15 , \mul_op__sv_saturate$16 , \mul_op__SV_Ptype$17 , \o$18 , o_ok, xer_ov, xer_ov_ok, \xer_so$19 , xer_so_ok, muxid); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" *) - wire [129:0] \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" *) - wire [129:0] \$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [129:0] \$19 ; + wire [129:0] \$20 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" *) wire [129:0] \$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [129:0] \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" *) + wire [129:0] \$25 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *) - wire \$23 ; + wire \$27 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *) - wire \$25 ; + wire \$29 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *) - wire \$26 ; + wire \$30 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *) - wire \$29 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) - wire \$31 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) wire \$33 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) - wire \$34 ; + wire \$35 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) wire \$37 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [1:0] \$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) + wire \$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) + wire \$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [1:0] \$43 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:36" *) wire is_32bit; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:40" *) wire [128:0] mul_o; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] mul_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \mul_op__SV_Ptype$17 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] mul_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] mul_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \mul_op__fn_unit$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \mul_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] mul_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \mul_op__imm_data__data$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__imm_data__ok$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] mul_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \mul_op__insn$13 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -154333,7 +165140,9 @@ module mul3(mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] mul_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -154410,35 +165219,57 @@ module mul3(mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] \mul_op__insn_type$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__is_32bit$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__is_signed$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__oe__oe$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__oe__ok$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__rc__ok$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__rc__rc$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input mul_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \mul_op__sv_pred_dz$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input mul_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \mul_op__sv_pred_sz$14 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] mul_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \mul_op__sv_saturate$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__write_cr0$10 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:60" *) reg mul_ov; @@ -154448,55 +165279,55 @@ module mul3(mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__ output [1:0] \muxid$1 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *) input neg_res; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [128:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [63:0] \o$14 ; - reg [63:0] \o$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [63:0] \o$18 ; + reg [63:0] \o$18 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output o_ok; reg o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [1:0] xer_ov; reg [1:0] xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ov_ok; reg xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \xer_so$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \xer_so$19 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_so_ok; - assign \$17 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" *) o; - assign \$19 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) o; - assign \$21 = neg_res ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" *) \$17 : \$19 ; - assign \$23 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *) mul_o[63:31]; - assign \$26 = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *) mul_o[63:31]; - assign \$25 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *) \$26 ; - assign \$29 = \$23 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *) \$25 ; - assign \$31 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) mul_o[127:63]; - assign \$34 = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) mul_o[127:63]; - assign \$33 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) \$34 ; - assign \$37 = \$31 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) \$33 ; - assign \$39 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) xer_so; - always @* begin - if (\initial ) begin end - \o$14 = 64'h0000000000000000; + assign \$21 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" *) o; + assign \$23 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) o; + assign \$25 = neg_res ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" *) \$21 : \$23 ; + assign \$27 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *) mul_o[63:31]; + assign \$30 = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *) mul_o[63:31]; + assign \$29 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *) \$30 ; + assign \$33 = \$27 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *) \$29 ; + assign \$35 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) mul_o[127:63]; + assign \$38 = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) mul_o[127:63]; + assign \$37 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) \$38 ; + assign \$41 = \$35 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) \$37 ; + assign \$43 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) xer_so; + always @* begin + if (\initial ) begin end + \o$18 = 64'h0000000000000000; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" *) casez (mul_op__insn_type) /* \nmigen.decoding = "OP_MUL_H32/52" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:46" */ 7'h34: - \o$14 = { mul_o[63:32], mul_o[63:32] }; + \o$18 = { mul_o[63:32], mul_o[63:32] }; /* \nmigen.decoding = "OP_MUL_H64/51" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50" */ 7'h33: - \o$14 = mul_o[127:64]; + \o$18 = mul_o[127:64]; /* \nmigen.decoding = "OP_MUL_L64/50" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:54" */ 7'h32: - \o$14 = mul_o[63:0]; + \o$18 = mul_o[63:0]; endcase end always @* begin @@ -154539,10 +165370,10 @@ module mul3(mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__ casez (is_32bit) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:61" */ 1'h1: - mul_ov = \$29 ; + mul_ov = \$33 ; /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:66" */ default: - mul_ov = \$37 ; + mul_ov = \$41 ; endcase endcase end @@ -154584,70 +165415,84 @@ module mul3(mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__ xer_ov_ok = 1'h1; endcase end - assign \$16 = \$21 ; - assign { \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2 } = { mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type }; + assign \$20 = \$25 ; + assign { \mul_op__SV_Ptype$17 , \mul_op__sv_saturate$16 , \mul_op__sv_pred_dz$15 , \mul_op__sv_pred_sz$14 , \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2 } = { mul_op__SV_Ptype, mul_op__sv_saturate, mul_op__sv_pred_dz, mul_op__sv_pred_sz, mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type }; assign \muxid$1 = muxid; - assign { xer_so_ok, \xer_so$15 } = \$39 ; - assign mul_o = \$21 [128:0]; + assign { xer_so_ok, \xer_so$19 } = \$43 ; + assign mul_o = \$25 [128:0]; assign is_32bit = mul_op__is_32bit; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1" *) (* generator = "nMigen" *) -module mul_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, ra, rb, xer_so, neg_res, neg_res32, p_valid_i, p_ready_o, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \ra$14 , \rb$15 , \xer_so$16 , coresync_clk); +module mul_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, mul_op__sv_pred_sz, mul_op__sv_pred_dz, mul_op__sv_saturate, mul_op__SV_Ptype, ra, rb, xer_so, neg_res, neg_res32, p_valid_i, p_ready_o, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \mul_op__sv_pred_sz$14 , \mul_op__sv_pred_dz$15 , \mul_op__sv_saturate$16 , \mul_op__SV_Ptype$17 , \ra$18 , \rb$19 , \xer_so$20 , coresync_clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) - wire \$50 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + wire \$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] input_mul_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \input_mul_op__SV_Ptype$37 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] input_mul_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] input_mul_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \input_mul_op__fn_unit$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \input_mul_op__fn_unit$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] input_mul_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \input_mul_op__imm_data__data$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \input_mul_op__imm_data__data$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_mul_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_mul_op__imm_data__ok$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_mul_op__imm_data__ok$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] input_mul_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \input_mul_op__insn$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \input_mul_op__insn$33 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -154723,7 +165568,9 @@ module mul_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, mul_op__insn_type, m (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] input_mul_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -154800,98 +165647,134 @@ module mul_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, mul_op__insn_type, m (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \input_mul_op__insn_type$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \input_mul_op__insn_type$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_mul_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_mul_op__is_32bit$27 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_mul_op__is_32bit$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_mul_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_mul_op__is_signed$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_mul_op__is_signed$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_mul_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_mul_op__oe__oe$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_mul_op__oe__oe$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_mul_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_mul_op__oe__ok$25 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_mul_op__oe__ok$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_mul_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_mul_op__rc__ok$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_mul_op__rc__ok$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_mul_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_mul_op__rc__rc$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_mul_op__rc__rc$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire input_mul_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_mul_op__sv_pred_dz$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire input_mul_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_mul_op__sv_pred_sz$34 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] input_mul_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \input_mul_op__sv_saturate$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_mul_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_mul_op__write_cr0$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_mul_op__write_cr0$30 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] input_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \input_muxid$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [1:0] \input_muxid$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] input_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \input_ra$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \input_ra$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] input_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \input_rb$31 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \input_rb$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire input_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire \input_xer_so$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire \input_xer_so$40 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] mul1_mul_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \mul1_mul_op__SV_Ptype$57 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] mul1_mul_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] mul1_mul_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \mul1_mul_op__fn_unit$35 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \mul1_mul_op__fn_unit$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] mul1_mul_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \mul1_mul_op__imm_data__data$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \mul1_mul_op__imm_data__data$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul1_mul_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul1_mul_op__imm_data__ok$37 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul1_mul_op__imm_data__ok$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] mul1_mul_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \mul1_mul_op__insn$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \mul1_mul_op__insn$53 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -154967,7 +165850,9 @@ module mul_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, mul_op__insn_type, m (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] mul1_mul_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -155044,136 +165929,182 @@ module mul_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, mul_op__insn_type, m (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \mul1_mul_op__insn_type$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \mul1_mul_op__insn_type$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul1_mul_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul1_mul_op__is_32bit$43 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul1_mul_op__is_32bit$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul1_mul_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul1_mul_op__is_signed$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul1_mul_op__is_signed$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul1_mul_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul1_mul_op__oe__oe$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul1_mul_op__oe__oe$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul1_mul_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul1_mul_op__oe__ok$41 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul1_mul_op__oe__ok$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul1_mul_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul1_mul_op__rc__ok$39 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul1_mul_op__rc__ok$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul1_mul_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul1_mul_op__rc__rc$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul1_mul_op__rc__rc$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire mul1_mul_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul1_mul_op__sv_pred_dz$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire mul1_mul_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul1_mul_op__sv_pred_sz$54 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] mul1_mul_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \mul1_mul_op__sv_saturate$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul1_mul_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul1_mul_op__write_cr0$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul1_mul_op__write_cr0$50 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] mul1_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \mul1_muxid$33 ; + wire [1:0] \mul1_muxid$41 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *) wire mul1_neg_res; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *) wire mul1_neg_res32; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] mul1_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \mul1_ra$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \mul1_ra$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] mul1_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \mul1_rb$47 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \mul1_rb$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire mul1_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire \mul1_xer_so$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire \mul1_xer_so$60 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] mul_op__SV_Ptype; + reg [1:0] mul_op__SV_Ptype = 2'h0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] \mul_op__SV_Ptype$17 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \mul_op__SV_Ptype$80 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \mul_op__SV_Ptype$next ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] mul_op__fn_unit; - reg [13:0] mul_op__fn_unit = 14'h0000; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] mul_op__fn_unit; + reg [14:0] mul_op__fn_unit = 15'h0000; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] \mul_op__fn_unit$3 ; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] \mul_op__fn_unit$3 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \mul_op__fn_unit$54 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] \mul_op__fn_unit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \mul_op__fn_unit$66 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] \mul_op__fn_unit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] mul_op__imm_data__data; reg [63:0] mul_op__imm_data__data = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] \mul_op__imm_data__data$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \mul_op__imm_data__data$55 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \mul_op__imm_data__data$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] \mul_op__imm_data__data$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output mul_op__imm_data__ok; reg mul_op__imm_data__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \mul_op__imm_data__ok$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_op__imm_data__ok$56 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__imm_data__ok$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \mul_op__imm_data__ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] mul_op__insn; reg [31:0] mul_op__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] \mul_op__insn$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \mul_op__insn$64 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \mul_op__insn$76 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] \mul_op__insn$next ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -155250,7 +166181,9 @@ module mul_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, mul_op__insn_type, m (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] mul_op__insn_type; reg [6:0] mul_op__insn_type = 7'h00; (* enum_base_type = "MicrOp" *) @@ -155328,7 +166261,9 @@ module mul_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, mul_op__insn_type, m (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] \mul_op__insn_type$2 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -155405,72 +166340,113 @@ module mul_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, mul_op__insn_type, m (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \mul_op__insn_type$53 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \mul_op__insn_type$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] \mul_op__insn_type$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output mul_op__is_32bit; reg mul_op__is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \mul_op__is_32bit$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_op__is_32bit$62 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__is_32bit$74 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \mul_op__is_32bit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output mul_op__is_signed; reg mul_op__is_signed = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \mul_op__is_signed$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_op__is_signed$63 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__is_signed$75 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \mul_op__is_signed$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output mul_op__oe__oe; reg mul_op__oe__oe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_op__oe__oe$59 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__oe__oe$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \mul_op__oe__oe$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \mul_op__oe__oe$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output mul_op__oe__ok; reg mul_op__oe__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_op__oe__ok$60 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__oe__ok$72 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \mul_op__oe__ok$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \mul_op__oe__ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output mul_op__rc__ok; reg mul_op__rc__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_op__rc__ok$58 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \mul_op__rc__ok$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__rc__ok$70 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \mul_op__rc__ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output mul_op__rc__rc; reg mul_op__rc__rc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_op__rc__rc$57 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \mul_op__rc__rc$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__rc__rc$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \mul_op__rc__rc$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output mul_op__sv_pred_dz; + reg mul_op__sv_pred_dz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input \mul_op__sv_pred_dz$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__sv_pred_dz$78 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \mul_op__sv_pred_dz$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output mul_op__sv_pred_sz; + reg mul_op__sv_pred_sz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input \mul_op__sv_pred_sz$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__sv_pred_sz$77 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \mul_op__sv_pred_sz$next ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] mul_op__sv_saturate; + reg [1:0] mul_op__sv_saturate = 2'h0; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] \mul_op__sv_saturate$16 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \mul_op__sv_saturate$79 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \mul_op__sv_saturate$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output mul_op__write_cr0; reg mul_op__write_cr0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \mul_op__write_cr0$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_op__write_cr0$61 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__write_cr0$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \mul_op__write_cr0$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] muxid; @@ -155478,7 +166454,7 @@ module mul_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, mul_op__insn_type, m (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] \muxid$1 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \muxid$52 ; + wire [1:0] \muxid$64 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) reg [1:0] \muxid$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *) @@ -155491,14 +166467,14 @@ module mul_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, mul_op__insn_type, m output neg_res; reg neg_res = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *) - wire \neg_res$68 ; + wire \neg_res$84 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *) reg \neg_res$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *) output neg_res32; reg neg_res32 = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *) - wire \neg_res32$69 ; + wire \neg_res32$85 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *) reg \neg_res32$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) @@ -155506,41 +166482,41 @@ module mul_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, mul_op__insn_type, m (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) input p_valid_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *) - wire \p_valid_i$49 ; + wire \p_valid_i$61 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *) wire p_valid_i_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg r_busy = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg \r_busy$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) output [63:0] ra; reg [63:0] ra = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - input [63:0] \ra$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \ra$65 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + input [63:0] \ra$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \ra$81 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) reg [63:0] \ra$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) output [63:0] rb; reg [63:0] rb = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - input [63:0] \rb$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \rb$66 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + input [63:0] \rb$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \rb$82 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) reg [63:0] \rb$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) output xer_so; reg xer_so = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - input \xer_so$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire \xer_so$67 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + input \xer_so$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire \xer_so$83 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) reg \xer_so$next ; - assign \$50 = \p_valid_i$49 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; + assign \$62 = \p_valid_i$61 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; always @(posedge coresync_clk) neg_res32 <= \neg_res32$next ; always @(posedge coresync_clk) @@ -155575,79 +166551,103 @@ module mul_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, mul_op__insn_type, m mul_op__is_signed <= \mul_op__is_signed$next ; always @(posedge coresync_clk) mul_op__insn <= \mul_op__insn$next ; + always @(posedge coresync_clk) + mul_op__sv_pred_sz <= \mul_op__sv_pred_sz$next ; + always @(posedge coresync_clk) + mul_op__sv_pred_dz <= \mul_op__sv_pred_dz$next ; + always @(posedge coresync_clk) + mul_op__sv_saturate <= \mul_op__sv_saturate$next ; + always @(posedge coresync_clk) + mul_op__SV_Ptype <= \mul_op__SV_Ptype$next ; always @(posedge coresync_clk) muxid <= \muxid$next ; always @(posedge coresync_clk) r_busy <= \r_busy$next ; \input$95 \input ( + .mul_op__SV_Ptype(input_mul_op__SV_Ptype), + .\mul_op__SV_Ptype$17 (\input_mul_op__SV_Ptype$37 ), .mul_op__fn_unit(input_mul_op__fn_unit), - .\mul_op__fn_unit$3 (\input_mul_op__fn_unit$19 ), + .\mul_op__fn_unit$3 (\input_mul_op__fn_unit$23 ), .mul_op__imm_data__data(input_mul_op__imm_data__data), - .\mul_op__imm_data__data$4 (\input_mul_op__imm_data__data$20 ), + .\mul_op__imm_data__data$4 (\input_mul_op__imm_data__data$24 ), .mul_op__imm_data__ok(input_mul_op__imm_data__ok), - .\mul_op__imm_data__ok$5 (\input_mul_op__imm_data__ok$21 ), + .\mul_op__imm_data__ok$5 (\input_mul_op__imm_data__ok$25 ), .mul_op__insn(input_mul_op__insn), - .\mul_op__insn$13 (\input_mul_op__insn$29 ), + .\mul_op__insn$13 (\input_mul_op__insn$33 ), .mul_op__insn_type(input_mul_op__insn_type), - .\mul_op__insn_type$2 (\input_mul_op__insn_type$18 ), + .\mul_op__insn_type$2 (\input_mul_op__insn_type$22 ), .mul_op__is_32bit(input_mul_op__is_32bit), - .\mul_op__is_32bit$11 (\input_mul_op__is_32bit$27 ), + .\mul_op__is_32bit$11 (\input_mul_op__is_32bit$31 ), .mul_op__is_signed(input_mul_op__is_signed), - .\mul_op__is_signed$12 (\input_mul_op__is_signed$28 ), + .\mul_op__is_signed$12 (\input_mul_op__is_signed$32 ), .mul_op__oe__oe(input_mul_op__oe__oe), - .\mul_op__oe__oe$8 (\input_mul_op__oe__oe$24 ), + .\mul_op__oe__oe$8 (\input_mul_op__oe__oe$28 ), .mul_op__oe__ok(input_mul_op__oe__ok), - .\mul_op__oe__ok$9 (\input_mul_op__oe__ok$25 ), + .\mul_op__oe__ok$9 (\input_mul_op__oe__ok$29 ), .mul_op__rc__ok(input_mul_op__rc__ok), - .\mul_op__rc__ok$7 (\input_mul_op__rc__ok$23 ), + .\mul_op__rc__ok$7 (\input_mul_op__rc__ok$27 ), .mul_op__rc__rc(input_mul_op__rc__rc), - .\mul_op__rc__rc$6 (\input_mul_op__rc__rc$22 ), + .\mul_op__rc__rc$6 (\input_mul_op__rc__rc$26 ), + .mul_op__sv_pred_dz(input_mul_op__sv_pred_dz), + .\mul_op__sv_pred_dz$15 (\input_mul_op__sv_pred_dz$35 ), + .mul_op__sv_pred_sz(input_mul_op__sv_pred_sz), + .\mul_op__sv_pred_sz$14 (\input_mul_op__sv_pred_sz$34 ), + .mul_op__sv_saturate(input_mul_op__sv_saturate), + .\mul_op__sv_saturate$16 (\input_mul_op__sv_saturate$36 ), .mul_op__write_cr0(input_mul_op__write_cr0), - .\mul_op__write_cr0$10 (\input_mul_op__write_cr0$26 ), + .\mul_op__write_cr0$10 (\input_mul_op__write_cr0$30 ), .muxid(input_muxid), - .\muxid$1 (\input_muxid$17 ), + .\muxid$1 (\input_muxid$21 ), .ra(input_ra), - .\ra$14 (\input_ra$30 ), + .\ra$18 (\input_ra$38 ), .rb(input_rb), - .\rb$15 (\input_rb$31 ), + .\rb$19 (\input_rb$39 ), .xer_so(input_xer_so), - .\xer_so$16 (\input_xer_so$32 ) + .\xer_so$20 (\input_xer_so$40 ) ); mul1 mul1 ( + .mul_op__SV_Ptype(mul1_mul_op__SV_Ptype), + .\mul_op__SV_Ptype$17 (\mul1_mul_op__SV_Ptype$57 ), .mul_op__fn_unit(mul1_mul_op__fn_unit), - .\mul_op__fn_unit$3 (\mul1_mul_op__fn_unit$35 ), + .\mul_op__fn_unit$3 (\mul1_mul_op__fn_unit$43 ), .mul_op__imm_data__data(mul1_mul_op__imm_data__data), - .\mul_op__imm_data__data$4 (\mul1_mul_op__imm_data__data$36 ), + .\mul_op__imm_data__data$4 (\mul1_mul_op__imm_data__data$44 ), .mul_op__imm_data__ok(mul1_mul_op__imm_data__ok), - .\mul_op__imm_data__ok$5 (\mul1_mul_op__imm_data__ok$37 ), + .\mul_op__imm_data__ok$5 (\mul1_mul_op__imm_data__ok$45 ), .mul_op__insn(mul1_mul_op__insn), - .\mul_op__insn$13 (\mul1_mul_op__insn$45 ), + .\mul_op__insn$13 (\mul1_mul_op__insn$53 ), .mul_op__insn_type(mul1_mul_op__insn_type), - .\mul_op__insn_type$2 (\mul1_mul_op__insn_type$34 ), + .\mul_op__insn_type$2 (\mul1_mul_op__insn_type$42 ), .mul_op__is_32bit(mul1_mul_op__is_32bit), - .\mul_op__is_32bit$11 (\mul1_mul_op__is_32bit$43 ), + .\mul_op__is_32bit$11 (\mul1_mul_op__is_32bit$51 ), .mul_op__is_signed(mul1_mul_op__is_signed), - .\mul_op__is_signed$12 (\mul1_mul_op__is_signed$44 ), + .\mul_op__is_signed$12 (\mul1_mul_op__is_signed$52 ), .mul_op__oe__oe(mul1_mul_op__oe__oe), - .\mul_op__oe__oe$8 (\mul1_mul_op__oe__oe$40 ), + .\mul_op__oe__oe$8 (\mul1_mul_op__oe__oe$48 ), .mul_op__oe__ok(mul1_mul_op__oe__ok), - .\mul_op__oe__ok$9 (\mul1_mul_op__oe__ok$41 ), + .\mul_op__oe__ok$9 (\mul1_mul_op__oe__ok$49 ), .mul_op__rc__ok(mul1_mul_op__rc__ok), - .\mul_op__rc__ok$7 (\mul1_mul_op__rc__ok$39 ), + .\mul_op__rc__ok$7 (\mul1_mul_op__rc__ok$47 ), .mul_op__rc__rc(mul1_mul_op__rc__rc), - .\mul_op__rc__rc$6 (\mul1_mul_op__rc__rc$38 ), + .\mul_op__rc__rc$6 (\mul1_mul_op__rc__rc$46 ), + .mul_op__sv_pred_dz(mul1_mul_op__sv_pred_dz), + .\mul_op__sv_pred_dz$15 (\mul1_mul_op__sv_pred_dz$55 ), + .mul_op__sv_pred_sz(mul1_mul_op__sv_pred_sz), + .\mul_op__sv_pred_sz$14 (\mul1_mul_op__sv_pred_sz$54 ), + .mul_op__sv_saturate(mul1_mul_op__sv_saturate), + .\mul_op__sv_saturate$16 (\mul1_mul_op__sv_saturate$56 ), .mul_op__write_cr0(mul1_mul_op__write_cr0), - .\mul_op__write_cr0$10 (\mul1_mul_op__write_cr0$42 ), + .\mul_op__write_cr0$10 (\mul1_mul_op__write_cr0$50 ), .muxid(mul1_muxid), - .\muxid$1 (\mul1_muxid$33 ), + .\muxid$1 (\mul1_muxid$41 ), .neg_res(mul1_neg_res), .neg_res32(mul1_neg_res32), .ra(mul1_ra), - .\ra$14 (\mul1_ra$46 ), + .\ra$18 (\mul1_ra$58 ), .rb(mul1_rb), - .\rb$15 (\mul1_rb$47 ), + .\rb$19 (\mul1_rb$59 ), .xer_so(mul1_xer_so), - .\xer_so$16 (\mul1_xer_so$48 ) + .\xer_so$20 (\mul1_xer_so$60 ) ); \n$94 n ( .n_ready_i(n_ready_i), @@ -155669,7 +166669,7 @@ module mul_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, mul_op__insn_type, m 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -155682,10 +166682,10 @@ module mul_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, mul_op__insn_type, m casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \muxid$next = \muxid$52 ; + \muxid$next = \muxid$64 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \muxid$next = \muxid$52 ; + \muxid$next = \muxid$64 ; endcase end always @* begin @@ -155702,16 +166702,20 @@ module mul_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, mul_op__insn_type, m \mul_op__is_32bit$next = mul_op__is_32bit; \mul_op__is_signed$next = mul_op__is_signed; \mul_op__insn$next = mul_op__insn; + \mul_op__sv_pred_sz$next = mul_op__sv_pred_sz; + \mul_op__sv_pred_dz$next = mul_op__sv_pred_dz; + \mul_op__sv_saturate$next = mul_op__sv_saturate; + \mul_op__SV_Ptype$next = mul_op__SV_Ptype; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \mul_op__insn$next , \mul_op__is_signed$next , \mul_op__is_32bit$next , \mul_op__write_cr0$next , \mul_op__oe__ok$next , \mul_op__oe__oe$next , \mul_op__rc__ok$next , \mul_op__rc__rc$next , \mul_op__imm_data__ok$next , \mul_op__imm_data__data$next , \mul_op__fn_unit$next , \mul_op__insn_type$next } = { \mul_op__insn$64 , \mul_op__is_signed$63 , \mul_op__is_32bit$62 , \mul_op__write_cr0$61 , \mul_op__oe__ok$60 , \mul_op__oe__oe$59 , \mul_op__rc__ok$58 , \mul_op__rc__rc$57 , \mul_op__imm_data__ok$56 , \mul_op__imm_data__data$55 , \mul_op__fn_unit$54 , \mul_op__insn_type$53 }; + { \mul_op__SV_Ptype$next , \mul_op__sv_saturate$next , \mul_op__sv_pred_dz$next , \mul_op__sv_pred_sz$next , \mul_op__insn$next , \mul_op__is_signed$next , \mul_op__is_32bit$next , \mul_op__write_cr0$next , \mul_op__oe__ok$next , \mul_op__oe__oe$next , \mul_op__rc__ok$next , \mul_op__rc__rc$next , \mul_op__imm_data__ok$next , \mul_op__imm_data__data$next , \mul_op__fn_unit$next , \mul_op__insn_type$next } = { \mul_op__SV_Ptype$80 , \mul_op__sv_saturate$79 , \mul_op__sv_pred_dz$78 , \mul_op__sv_pred_sz$77 , \mul_op__insn$76 , \mul_op__is_signed$75 , \mul_op__is_32bit$74 , \mul_op__write_cr0$73 , \mul_op__oe__ok$72 , \mul_op__oe__oe$71 , \mul_op__rc__ok$70 , \mul_op__rc__rc$69 , \mul_op__imm_data__ok$68 , \mul_op__imm_data__data$67 , \mul_op__fn_unit$66 , \mul_op__insn_type$65 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \mul_op__insn$next , \mul_op__is_signed$next , \mul_op__is_32bit$next , \mul_op__write_cr0$next , \mul_op__oe__ok$next , \mul_op__oe__oe$next , \mul_op__rc__ok$next , \mul_op__rc__rc$next , \mul_op__imm_data__ok$next , \mul_op__imm_data__data$next , \mul_op__fn_unit$next , \mul_op__insn_type$next } = { \mul_op__insn$64 , \mul_op__is_signed$63 , \mul_op__is_32bit$62 , \mul_op__write_cr0$61 , \mul_op__oe__ok$60 , \mul_op__oe__oe$59 , \mul_op__rc__ok$58 , \mul_op__rc__rc$57 , \mul_op__imm_data__ok$56 , \mul_op__imm_data__data$55 , \mul_op__fn_unit$54 , \mul_op__insn_type$53 }; + { \mul_op__SV_Ptype$next , \mul_op__sv_saturate$next , \mul_op__sv_pred_dz$next , \mul_op__sv_pred_sz$next , \mul_op__insn$next , \mul_op__is_signed$next , \mul_op__is_32bit$next , \mul_op__write_cr0$next , \mul_op__oe__ok$next , \mul_op__oe__oe$next , \mul_op__rc__ok$next , \mul_op__rc__rc$next , \mul_op__imm_data__ok$next , \mul_op__imm_data__data$next , \mul_op__fn_unit$next , \mul_op__insn_type$next } = { \mul_op__SV_Ptype$80 , \mul_op__sv_saturate$79 , \mul_op__sv_pred_dz$78 , \mul_op__sv_pred_sz$77 , \mul_op__insn$76 , \mul_op__is_signed$75 , \mul_op__is_32bit$74 , \mul_op__write_cr0$73 , \mul_op__oe__ok$72 , \mul_op__oe__oe$71 , \mul_op__rc__ok$70 , \mul_op__rc__rc$69 , \mul_op__imm_data__ok$68 , \mul_op__imm_data__data$67 , \mul_op__fn_unit$66 , \mul_op__insn_type$65 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -155731,10 +166735,10 @@ module mul_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, mul_op__insn_type, m casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \ra$next = \ra$65 ; + \ra$next = \ra$81 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \ra$next = \ra$65 ; + \ra$next = \ra$81 ; endcase end always @* begin @@ -155744,10 +166748,10 @@ module mul_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, mul_op__insn_type, m casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \rb$next = \rb$66 ; + \rb$next = \rb$82 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \rb$next = \rb$66 ; + \rb$next = \rb$82 ; endcase end always @* begin @@ -155757,10 +166761,10 @@ module mul_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, mul_op__insn_type, m casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \xer_so$next = \xer_so$67 ; + \xer_so$next = \xer_so$83 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \xer_so$next = \xer_so$67 ; + \xer_so$next = \xer_so$83 ; endcase end always @* begin @@ -155770,10 +166774,10 @@ module mul_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, mul_op__insn_type, m casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \neg_res$next = \neg_res$68 ; + \neg_res$next = \neg_res$84 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \neg_res$next = \neg_res$68 ; + \neg_res$next = \neg_res$84 ; endcase end always @* begin @@ -155783,92 +166787,106 @@ module mul_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, mul_op__insn_type, m casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \neg_res32$next = \neg_res32$69 ; + \neg_res32$next = \neg_res32$85 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \neg_res32$next = \neg_res32$69 ; + \neg_res32$next = \neg_res32$85 ; endcase end assign p_ready_o = n_i_rdy_data; assign n_valid_o = r_busy; - assign \neg_res32$69 = mul1_neg_res32; - assign \neg_res$68 = mul1_neg_res; - assign \xer_so$67 = \mul1_xer_so$48 ; - assign \rb$66 = \mul1_rb$47 ; - assign \ra$65 = \mul1_ra$46 ; - assign { \mul_op__insn$64 , \mul_op__is_signed$63 , \mul_op__is_32bit$62 , \mul_op__write_cr0$61 , \mul_op__oe__ok$60 , \mul_op__oe__oe$59 , \mul_op__rc__ok$58 , \mul_op__rc__rc$57 , \mul_op__imm_data__ok$56 , \mul_op__imm_data__data$55 , \mul_op__fn_unit$54 , \mul_op__insn_type$53 } = { \mul1_mul_op__insn$45 , \mul1_mul_op__is_signed$44 , \mul1_mul_op__is_32bit$43 , \mul1_mul_op__write_cr0$42 , \mul1_mul_op__oe__ok$41 , \mul1_mul_op__oe__oe$40 , \mul1_mul_op__rc__ok$39 , \mul1_mul_op__rc__rc$38 , \mul1_mul_op__imm_data__ok$37 , \mul1_mul_op__imm_data__data$36 , \mul1_mul_op__fn_unit$35 , \mul1_mul_op__insn_type$34 }; - assign \muxid$52 = \mul1_muxid$33 ; - assign p_valid_i_p_ready_o = \$50 ; + assign \neg_res32$85 = mul1_neg_res32; + assign \neg_res$84 = mul1_neg_res; + assign \xer_so$83 = \mul1_xer_so$60 ; + assign \rb$82 = \mul1_rb$59 ; + assign \ra$81 = \mul1_ra$58 ; + assign { \mul_op__SV_Ptype$80 , \mul_op__sv_saturate$79 , \mul_op__sv_pred_dz$78 , \mul_op__sv_pred_sz$77 , \mul_op__insn$76 , \mul_op__is_signed$75 , \mul_op__is_32bit$74 , \mul_op__write_cr0$73 , \mul_op__oe__ok$72 , \mul_op__oe__oe$71 , \mul_op__rc__ok$70 , \mul_op__rc__rc$69 , \mul_op__imm_data__ok$68 , \mul_op__imm_data__data$67 , \mul_op__fn_unit$66 , \mul_op__insn_type$65 } = { \mul1_mul_op__SV_Ptype$57 , \mul1_mul_op__sv_saturate$56 , \mul1_mul_op__sv_pred_dz$55 , \mul1_mul_op__sv_pred_sz$54 , \mul1_mul_op__insn$53 , \mul1_mul_op__is_signed$52 , \mul1_mul_op__is_32bit$51 , \mul1_mul_op__write_cr0$50 , \mul1_mul_op__oe__ok$49 , \mul1_mul_op__oe__oe$48 , \mul1_mul_op__rc__ok$47 , \mul1_mul_op__rc__rc$46 , \mul1_mul_op__imm_data__ok$45 , \mul1_mul_op__imm_data__data$44 , \mul1_mul_op__fn_unit$43 , \mul1_mul_op__insn_type$42 }; + assign \muxid$64 = \mul1_muxid$41 ; + assign p_valid_i_p_ready_o = \$62 ; assign n_i_rdy_data = n_ready_i; - assign \p_valid_i$49 = p_valid_i; - assign mul1_xer_so = \input_xer_so$32 ; - assign mul1_rb = \input_rb$31 ; - assign mul1_ra = \input_ra$30 ; - assign { mul1_mul_op__insn, mul1_mul_op__is_signed, mul1_mul_op__is_32bit, mul1_mul_op__write_cr0, mul1_mul_op__oe__ok, mul1_mul_op__oe__oe, mul1_mul_op__rc__ok, mul1_mul_op__rc__rc, mul1_mul_op__imm_data__ok, mul1_mul_op__imm_data__data, mul1_mul_op__fn_unit, mul1_mul_op__insn_type } = { \input_mul_op__insn$29 , \input_mul_op__is_signed$28 , \input_mul_op__is_32bit$27 , \input_mul_op__write_cr0$26 , \input_mul_op__oe__ok$25 , \input_mul_op__oe__oe$24 , \input_mul_op__rc__ok$23 , \input_mul_op__rc__rc$22 , \input_mul_op__imm_data__ok$21 , \input_mul_op__imm_data__data$20 , \input_mul_op__fn_unit$19 , \input_mul_op__insn_type$18 }; - assign mul1_muxid = \input_muxid$17 ; - assign input_xer_so = \xer_so$16 ; - assign input_rb = \rb$15 ; - assign input_ra = \ra$14 ; - assign { input_mul_op__insn, input_mul_op__is_signed, input_mul_op__is_32bit, input_mul_op__write_cr0, input_mul_op__oe__ok, input_mul_op__oe__oe, input_mul_op__rc__ok, input_mul_op__rc__rc, input_mul_op__imm_data__ok, input_mul_op__imm_data__data, input_mul_op__fn_unit, input_mul_op__insn_type } = { \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2 }; + assign \p_valid_i$61 = p_valid_i; + assign mul1_xer_so = \input_xer_so$40 ; + assign mul1_rb = \input_rb$39 ; + assign mul1_ra = \input_ra$38 ; + assign { mul1_mul_op__SV_Ptype, mul1_mul_op__sv_saturate, mul1_mul_op__sv_pred_dz, mul1_mul_op__sv_pred_sz, mul1_mul_op__insn, mul1_mul_op__is_signed, mul1_mul_op__is_32bit, mul1_mul_op__write_cr0, mul1_mul_op__oe__ok, mul1_mul_op__oe__oe, mul1_mul_op__rc__ok, mul1_mul_op__rc__rc, mul1_mul_op__imm_data__ok, mul1_mul_op__imm_data__data, mul1_mul_op__fn_unit, mul1_mul_op__insn_type } = { \input_mul_op__SV_Ptype$37 , \input_mul_op__sv_saturate$36 , \input_mul_op__sv_pred_dz$35 , \input_mul_op__sv_pred_sz$34 , \input_mul_op__insn$33 , \input_mul_op__is_signed$32 , \input_mul_op__is_32bit$31 , \input_mul_op__write_cr0$30 , \input_mul_op__oe__ok$29 , \input_mul_op__oe__oe$28 , \input_mul_op__rc__ok$27 , \input_mul_op__rc__rc$26 , \input_mul_op__imm_data__ok$25 , \input_mul_op__imm_data__data$24 , \input_mul_op__fn_unit$23 , \input_mul_op__insn_type$22 }; + assign mul1_muxid = \input_muxid$21 ; + assign input_xer_so = \xer_so$20 ; + assign input_rb = \rb$19 ; + assign input_ra = \ra$18 ; + assign { input_mul_op__SV_Ptype, input_mul_op__sv_saturate, input_mul_op__sv_pred_dz, input_mul_op__sv_pred_sz, input_mul_op__insn, input_mul_op__is_signed, input_mul_op__is_32bit, input_mul_op__write_cr0, input_mul_op__oe__ok, input_mul_op__oe__oe, input_mul_op__rc__ok, input_mul_op__rc__rc, input_mul_op__imm_data__ok, input_mul_op__imm_data__data, input_mul_op__fn_unit, input_mul_op__insn_type } = { \mul_op__SV_Ptype$17 , \mul_op__sv_saturate$16 , \mul_op__sv_pred_dz$15 , \mul_op__sv_pred_sz$14 , \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2 }; assign input_muxid = \muxid$1 ; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2" *) (* generator = "nMigen" *) -module mul_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, ra, rb, xer_so, neg_res, neg_res32, n_valid_o, n_ready_i, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , o, \xer_so$14 , \neg_res$15 , \neg_res32$16 , coresync_clk); +module mul_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, mul_op__sv_pred_sz, mul_op__sv_pred_dz, mul_op__sv_saturate, mul_op__SV_Ptype, ra, rb, xer_so, neg_res, neg_res32, n_valid_o, n_ready_i, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \mul_op__sv_pred_sz$14 , \mul_op__sv_pred_dz$15 , \mul_op__sv_saturate$16 , \mul_op__SV_Ptype$17 , o, \xer_so$18 , \neg_res$19 , \neg_res32$20 , coresync_clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) - wire \$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + wire \$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] mul2_mul_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \mul2_mul_op__SV_Ptype$37 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] mul2_mul_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] mul2_mul_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \mul2_mul_op__fn_unit$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \mul2_mul_op__fn_unit$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] mul2_mul_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \mul2_mul_op__imm_data__data$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \mul2_mul_op__imm_data__data$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul2_mul_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul2_mul_op__imm_data__ok$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul2_mul_op__imm_data__ok$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] mul2_mul_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \mul2_mul_op__insn$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \mul2_mul_op__insn$33 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -155944,7 +166962,9 @@ module mul_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] mul2_mul_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -156021,139 +167041,185 @@ module mul_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \mul2_mul_op__insn_type$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \mul2_mul_op__insn_type$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul2_mul_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul2_mul_op__is_32bit$27 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul2_mul_op__is_32bit$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul2_mul_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul2_mul_op__is_signed$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul2_mul_op__is_signed$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul2_mul_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul2_mul_op__oe__oe$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul2_mul_op__oe__oe$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul2_mul_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul2_mul_op__oe__ok$25 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul2_mul_op__oe__ok$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul2_mul_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul2_mul_op__rc__ok$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul2_mul_op__rc__ok$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul2_mul_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul2_mul_op__rc__rc$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul2_mul_op__rc__rc$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire mul2_mul_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul2_mul_op__sv_pred_dz$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire mul2_mul_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul2_mul_op__sv_pred_sz$34 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] mul2_mul_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \mul2_mul_op__sv_saturate$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul2_mul_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul2_mul_op__write_cr0$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul2_mul_op__write_cr0$30 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] mul2_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \mul2_muxid$17 ; + wire [1:0] \mul2_muxid$21 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *) wire mul2_neg_res; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *) - wire \mul2_neg_res$31 ; + wire \mul2_neg_res$39 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *) wire mul2_neg_res32; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *) - wire \mul2_neg_res32$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire \mul2_neg_res32$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [128:0] mul2_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] mul2_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] mul2_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire mul2_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire \mul2_xer_so$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire \mul2_xer_so$38 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] mul_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \mul_op__SV_Ptype$17 ; + reg [1:0] \mul_op__SV_Ptype$17 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \mul_op__SV_Ptype$17$next ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \mul_op__SV_Ptype$60 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] mul_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] mul_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \mul_op__fn_unit$3 ; - reg [13:0] \mul_op__fn_unit$3 = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] \mul_op__fn_unit$3$next ; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \mul_op__fn_unit$3 ; + reg [14:0] \mul_op__fn_unit$3 = 15'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] \mul_op__fn_unit$3$next ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \mul_op__fn_unit$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \mul_op__fn_unit$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] mul_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \mul_op__imm_data__data$39 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \mul_op__imm_data__data$4 ; reg [63:0] \mul_op__imm_data__data$4 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] \mul_op__imm_data__data$4$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \mul_op__imm_data__data$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_op__imm_data__ok$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__imm_data__ok$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__imm_data__ok$5 ; reg \mul_op__imm_data__ok$5 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \mul_op__imm_data__ok$5$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] mul_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \mul_op__insn$13 ; reg [31:0] \mul_op__insn$13 = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] \mul_op__insn$13$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \mul_op__insn$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \mul_op__insn$56 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -156229,7 +167295,9 @@ module mul_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] mul_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -156306,10 +167374,12 @@ module mul_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] \mul_op__insn_type$2 ; reg [6:0] \mul_op__insn_type$2 = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] \mul_op__insn_type$2$next ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -156386,71 +167456,112 @@ module mul_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \mul_op__insn_type$37 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \mul_op__insn_type$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__is_32bit$11 ; reg \mul_op__is_32bit$11 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \mul_op__is_32bit$11$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_op__is_32bit$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__is_32bit$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__is_signed$12 ; reg \mul_op__is_signed$12 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \mul_op__is_signed$12$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_op__is_signed$47 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__is_signed$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_op__oe__oe$43 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__oe__oe$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__oe__oe$8 ; reg \mul_op__oe__oe$8 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \mul_op__oe__oe$8$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_op__oe__ok$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__oe__ok$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__oe__ok$9 ; reg \mul_op__oe__ok$9 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \mul_op__oe__ok$9$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_op__rc__ok$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__rc__ok$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__rc__ok$7 ; reg \mul_op__rc__ok$7 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \mul_op__rc__ok$7$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_op__rc__rc$41 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__rc__rc$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__rc__rc$6 ; reg \mul_op__rc__rc$6 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \mul_op__rc__rc$6$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input mul_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \mul_op__sv_pred_dz$15 ; + reg \mul_op__sv_pred_dz$15 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \mul_op__sv_pred_dz$15$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__sv_pred_dz$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input mul_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \mul_op__sv_pred_sz$14 ; + reg \mul_op__sv_pred_sz$14 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \mul_op__sv_pred_sz$14$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__sv_pred_sz$57 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] mul_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \mul_op__sv_saturate$16 ; + reg [1:0] \mul_op__sv_saturate$16 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \mul_op__sv_saturate$16$next ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \mul_op__sv_saturate$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__write_cr0$10 ; reg \mul_op__write_cr0$10 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \mul_op__write_cr0$10$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_op__write_cr0$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__write_cr0$53 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) @@ -156459,7 +167570,7 @@ module mul_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) reg [1:0] \muxid$1$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \muxid$36 ; + wire [1:0] \muxid$44 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *) wire n_i_rdy_data; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) @@ -156469,60 +167580,60 @@ module mul_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *) input neg_res; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *) - output \neg_res$15 ; - reg \neg_res$15 = 1'h0; + output \neg_res$19 ; + reg \neg_res$19 = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *) - reg \neg_res$15$next ; + reg \neg_res$19$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *) - wire \neg_res$51 ; + wire \neg_res$63 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *) input neg_res32; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *) - output \neg_res32$16 ; - reg \neg_res32$16 = 1'h0; + output \neg_res32$20 ; + reg \neg_res32$20 = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *) - reg \neg_res32$16$next ; + reg \neg_res32$20$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *) - wire \neg_res32$52 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire \neg_res32$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) output [128:0] o; reg [128:0] o = 129'h000000000000000000000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [128:0] \o$49 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [128:0] \o$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) reg [128:0] \o$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) input p_valid_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *) - wire \p_valid_i$33 ; + wire \p_valid_i$41 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *) wire p_valid_i_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg r_busy = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg \r_busy$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - output \xer_so$14 ; - reg \xer_so$14 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - reg \xer_so$14$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire \xer_so$50 ; - assign \$34 = \p_valid_i$33 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + output \xer_so$18 ; + reg \xer_so$18 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + reg \xer_so$18$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire \xer_so$62 ; + assign \$42 = \p_valid_i$41 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; always @(posedge coresync_clk) - \neg_res32$16 <= \neg_res32$16$next ; + \neg_res32$20 <= \neg_res32$20$next ; always @(posedge coresync_clk) - \neg_res$15 <= \neg_res$15$next ; + \neg_res$19 <= \neg_res$19$next ; always @(posedge coresync_clk) - \xer_so$14 <= \xer_so$14$next ; + \xer_so$18 <= \xer_so$18$next ; always @(posedge coresync_clk) o <= \o$next ; always @(posedge coresync_clk) @@ -156549,46 +167660,62 @@ module mul_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m \mul_op__is_signed$12 <= \mul_op__is_signed$12$next ; always @(posedge coresync_clk) \mul_op__insn$13 <= \mul_op__insn$13$next ; + always @(posedge coresync_clk) + \mul_op__sv_pred_sz$14 <= \mul_op__sv_pred_sz$14$next ; + always @(posedge coresync_clk) + \mul_op__sv_pred_dz$15 <= \mul_op__sv_pred_dz$15$next ; + always @(posedge coresync_clk) + \mul_op__sv_saturate$16 <= \mul_op__sv_saturate$16$next ; + always @(posedge coresync_clk) + \mul_op__SV_Ptype$17 <= \mul_op__SV_Ptype$17$next ; always @(posedge coresync_clk) \muxid$1 <= \muxid$1$next ; always @(posedge coresync_clk) r_busy <= \r_busy$next ; mul2 mul2 ( + .mul_op__SV_Ptype(mul2_mul_op__SV_Ptype), + .\mul_op__SV_Ptype$17 (\mul2_mul_op__SV_Ptype$37 ), .mul_op__fn_unit(mul2_mul_op__fn_unit), - .\mul_op__fn_unit$3 (\mul2_mul_op__fn_unit$19 ), + .\mul_op__fn_unit$3 (\mul2_mul_op__fn_unit$23 ), .mul_op__imm_data__data(mul2_mul_op__imm_data__data), - .\mul_op__imm_data__data$4 (\mul2_mul_op__imm_data__data$20 ), + .\mul_op__imm_data__data$4 (\mul2_mul_op__imm_data__data$24 ), .mul_op__imm_data__ok(mul2_mul_op__imm_data__ok), - .\mul_op__imm_data__ok$5 (\mul2_mul_op__imm_data__ok$21 ), + .\mul_op__imm_data__ok$5 (\mul2_mul_op__imm_data__ok$25 ), .mul_op__insn(mul2_mul_op__insn), - .\mul_op__insn$13 (\mul2_mul_op__insn$29 ), + .\mul_op__insn$13 (\mul2_mul_op__insn$33 ), .mul_op__insn_type(mul2_mul_op__insn_type), - .\mul_op__insn_type$2 (\mul2_mul_op__insn_type$18 ), + .\mul_op__insn_type$2 (\mul2_mul_op__insn_type$22 ), .mul_op__is_32bit(mul2_mul_op__is_32bit), - .\mul_op__is_32bit$11 (\mul2_mul_op__is_32bit$27 ), + .\mul_op__is_32bit$11 (\mul2_mul_op__is_32bit$31 ), .mul_op__is_signed(mul2_mul_op__is_signed), - .\mul_op__is_signed$12 (\mul2_mul_op__is_signed$28 ), + .\mul_op__is_signed$12 (\mul2_mul_op__is_signed$32 ), .mul_op__oe__oe(mul2_mul_op__oe__oe), - .\mul_op__oe__oe$8 (\mul2_mul_op__oe__oe$24 ), + .\mul_op__oe__oe$8 (\mul2_mul_op__oe__oe$28 ), .mul_op__oe__ok(mul2_mul_op__oe__ok), - .\mul_op__oe__ok$9 (\mul2_mul_op__oe__ok$25 ), + .\mul_op__oe__ok$9 (\mul2_mul_op__oe__ok$29 ), .mul_op__rc__ok(mul2_mul_op__rc__ok), - .\mul_op__rc__ok$7 (\mul2_mul_op__rc__ok$23 ), + .\mul_op__rc__ok$7 (\mul2_mul_op__rc__ok$27 ), .mul_op__rc__rc(mul2_mul_op__rc__rc), - .\mul_op__rc__rc$6 (\mul2_mul_op__rc__rc$22 ), + .\mul_op__rc__rc$6 (\mul2_mul_op__rc__rc$26 ), + .mul_op__sv_pred_dz(mul2_mul_op__sv_pred_dz), + .\mul_op__sv_pred_dz$15 (\mul2_mul_op__sv_pred_dz$35 ), + .mul_op__sv_pred_sz(mul2_mul_op__sv_pred_sz), + .\mul_op__sv_pred_sz$14 (\mul2_mul_op__sv_pred_sz$34 ), + .mul_op__sv_saturate(mul2_mul_op__sv_saturate), + .\mul_op__sv_saturate$16 (\mul2_mul_op__sv_saturate$36 ), .mul_op__write_cr0(mul2_mul_op__write_cr0), - .\mul_op__write_cr0$10 (\mul2_mul_op__write_cr0$26 ), + .\mul_op__write_cr0$10 (\mul2_mul_op__write_cr0$30 ), .muxid(mul2_muxid), - .\muxid$1 (\mul2_muxid$17 ), + .\muxid$1 (\mul2_muxid$21 ), .neg_res(mul2_neg_res), - .\neg_res$15 (\mul2_neg_res$31 ), + .\neg_res$19 (\mul2_neg_res$39 ), .neg_res32(mul2_neg_res32), - .\neg_res32$16 (\mul2_neg_res32$32 ), + .\neg_res32$20 (\mul2_neg_res32$40 ), .o(mul2_o), .ra(mul2_ra), .rb(mul2_rb), .xer_so(mul2_xer_so), - .\xer_so$14 (\mul2_xer_so$30 ) + .\xer_so$18 (\mul2_xer_so$38 ) ); \n$97 n ( .n_ready_i(n_ready_i), @@ -156610,7 +167737,7 @@ module mul_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -156623,10 +167750,10 @@ module mul_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \muxid$1$next = \muxid$36 ; + \muxid$1$next = \muxid$44 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \muxid$1$next = \muxid$36 ; + \muxid$1$next = \muxid$44 ; endcase end always @* begin @@ -156643,16 +167770,20 @@ module mul_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m \mul_op__is_32bit$11$next = \mul_op__is_32bit$11 ; \mul_op__is_signed$12$next = \mul_op__is_signed$12 ; \mul_op__insn$13$next = \mul_op__insn$13 ; + \mul_op__sv_pred_sz$14$next = \mul_op__sv_pred_sz$14 ; + \mul_op__sv_pred_dz$15$next = \mul_op__sv_pred_dz$15 ; + \mul_op__sv_saturate$16$next = \mul_op__sv_saturate$16 ; + \mul_op__SV_Ptype$17$next = \mul_op__SV_Ptype$17 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \mul_op__insn$13$next , \mul_op__is_signed$12$next , \mul_op__is_32bit$11$next , \mul_op__write_cr0$10$next , \mul_op__oe__ok$9$next , \mul_op__oe__oe$8$next , \mul_op__rc__ok$7$next , \mul_op__rc__rc$6$next , \mul_op__imm_data__ok$5$next , \mul_op__imm_data__data$4$next , \mul_op__fn_unit$3$next , \mul_op__insn_type$2$next } = { \mul_op__insn$48 , \mul_op__is_signed$47 , \mul_op__is_32bit$46 , \mul_op__write_cr0$45 , \mul_op__oe__ok$44 , \mul_op__oe__oe$43 , \mul_op__rc__ok$42 , \mul_op__rc__rc$41 , \mul_op__imm_data__ok$40 , \mul_op__imm_data__data$39 , \mul_op__fn_unit$38 , \mul_op__insn_type$37 }; + { \mul_op__SV_Ptype$17$next , \mul_op__sv_saturate$16$next , \mul_op__sv_pred_dz$15$next , \mul_op__sv_pred_sz$14$next , \mul_op__insn$13$next , \mul_op__is_signed$12$next , \mul_op__is_32bit$11$next , \mul_op__write_cr0$10$next , \mul_op__oe__ok$9$next , \mul_op__oe__oe$8$next , \mul_op__rc__ok$7$next , \mul_op__rc__rc$6$next , \mul_op__imm_data__ok$5$next , \mul_op__imm_data__data$4$next , \mul_op__fn_unit$3$next , \mul_op__insn_type$2$next } = { \mul_op__SV_Ptype$60 , \mul_op__sv_saturate$59 , \mul_op__sv_pred_dz$58 , \mul_op__sv_pred_sz$57 , \mul_op__insn$56 , \mul_op__is_signed$55 , \mul_op__is_32bit$54 , \mul_op__write_cr0$53 , \mul_op__oe__ok$52 , \mul_op__oe__oe$51 , \mul_op__rc__ok$50 , \mul_op__rc__rc$49 , \mul_op__imm_data__ok$48 , \mul_op__imm_data__data$47 , \mul_op__fn_unit$46 , \mul_op__insn_type$45 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \mul_op__insn$13$next , \mul_op__is_signed$12$next , \mul_op__is_32bit$11$next , \mul_op__write_cr0$10$next , \mul_op__oe__ok$9$next , \mul_op__oe__oe$8$next , \mul_op__rc__ok$7$next , \mul_op__rc__rc$6$next , \mul_op__imm_data__ok$5$next , \mul_op__imm_data__data$4$next , \mul_op__fn_unit$3$next , \mul_op__insn_type$2$next } = { \mul_op__insn$48 , \mul_op__is_signed$47 , \mul_op__is_32bit$46 , \mul_op__write_cr0$45 , \mul_op__oe__ok$44 , \mul_op__oe__oe$43 , \mul_op__rc__ok$42 , \mul_op__rc__rc$41 , \mul_op__imm_data__ok$40 , \mul_op__imm_data__data$39 , \mul_op__fn_unit$38 , \mul_op__insn_type$37 }; + { \mul_op__SV_Ptype$17$next , \mul_op__sv_saturate$16$next , \mul_op__sv_pred_dz$15$next , \mul_op__sv_pred_sz$14$next , \mul_op__insn$13$next , \mul_op__is_signed$12$next , \mul_op__is_32bit$11$next , \mul_op__write_cr0$10$next , \mul_op__oe__ok$9$next , \mul_op__oe__oe$8$next , \mul_op__rc__ok$7$next , \mul_op__rc__rc$6$next , \mul_op__imm_data__ok$5$next , \mul_op__imm_data__data$4$next , \mul_op__fn_unit$3$next , \mul_op__insn_type$2$next } = { \mul_op__SV_Ptype$60 , \mul_op__sv_saturate$59 , \mul_op__sv_pred_dz$58 , \mul_op__sv_pred_sz$57 , \mul_op__insn$56 , \mul_op__is_signed$55 , \mul_op__is_32bit$54 , \mul_op__write_cr0$53 , \mul_op__oe__ok$52 , \mul_op__oe__oe$51 , \mul_op__rc__ok$50 , \mul_op__rc__rc$49 , \mul_op__imm_data__ok$48 , \mul_op__imm_data__data$47 , \mul_op__fn_unit$46 , \mul_op__insn_type$45 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -156672,147 +167803,161 @@ module mul_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \o$next = \o$49 ; + \o$next = \o$61 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \o$next = \o$49 ; + \o$next = \o$61 ; endcase end always @* begin if (\initial ) begin end - \xer_so$14$next = \xer_so$14 ; + \xer_so$18$next = \xer_so$18 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \xer_so$14$next = \xer_so$50 ; + \xer_so$18$next = \xer_so$62 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \xer_so$14$next = \xer_so$50 ; + \xer_so$18$next = \xer_so$62 ; endcase end always @* begin if (\initial ) begin end - \neg_res$15$next = \neg_res$15 ; + \neg_res$19$next = \neg_res$19 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \neg_res$15$next = \neg_res$51 ; + \neg_res$19$next = \neg_res$63 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \neg_res$15$next = \neg_res$51 ; + \neg_res$19$next = \neg_res$63 ; endcase end always @* begin if (\initial ) begin end - \neg_res32$16$next = \neg_res32$16 ; + \neg_res32$20$next = \neg_res32$20 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \neg_res32$16$next = \neg_res32$52 ; + \neg_res32$20$next = \neg_res32$64 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \neg_res32$16$next = \neg_res32$52 ; + \neg_res32$20$next = \neg_res32$64 ; endcase end assign p_ready_o = n_i_rdy_data; assign n_valid_o = r_busy; - assign \neg_res32$52 = \mul2_neg_res32$32 ; - assign \neg_res$51 = \mul2_neg_res$31 ; - assign \xer_so$50 = \mul2_xer_so$30 ; - assign \o$49 = mul2_o; - assign { \mul_op__insn$48 , \mul_op__is_signed$47 , \mul_op__is_32bit$46 , \mul_op__write_cr0$45 , \mul_op__oe__ok$44 , \mul_op__oe__oe$43 , \mul_op__rc__ok$42 , \mul_op__rc__rc$41 , \mul_op__imm_data__ok$40 , \mul_op__imm_data__data$39 , \mul_op__fn_unit$38 , \mul_op__insn_type$37 } = { \mul2_mul_op__insn$29 , \mul2_mul_op__is_signed$28 , \mul2_mul_op__is_32bit$27 , \mul2_mul_op__write_cr0$26 , \mul2_mul_op__oe__ok$25 , \mul2_mul_op__oe__oe$24 , \mul2_mul_op__rc__ok$23 , \mul2_mul_op__rc__rc$22 , \mul2_mul_op__imm_data__ok$21 , \mul2_mul_op__imm_data__data$20 , \mul2_mul_op__fn_unit$19 , \mul2_mul_op__insn_type$18 }; - assign \muxid$36 = \mul2_muxid$17 ; - assign p_valid_i_p_ready_o = \$34 ; + assign \neg_res32$64 = \mul2_neg_res32$40 ; + assign \neg_res$63 = \mul2_neg_res$39 ; + assign \xer_so$62 = \mul2_xer_so$38 ; + assign \o$61 = mul2_o; + assign { \mul_op__SV_Ptype$60 , \mul_op__sv_saturate$59 , \mul_op__sv_pred_dz$58 , \mul_op__sv_pred_sz$57 , \mul_op__insn$56 , \mul_op__is_signed$55 , \mul_op__is_32bit$54 , \mul_op__write_cr0$53 , \mul_op__oe__ok$52 , \mul_op__oe__oe$51 , \mul_op__rc__ok$50 , \mul_op__rc__rc$49 , \mul_op__imm_data__ok$48 , \mul_op__imm_data__data$47 , \mul_op__fn_unit$46 , \mul_op__insn_type$45 } = { \mul2_mul_op__SV_Ptype$37 , \mul2_mul_op__sv_saturate$36 , \mul2_mul_op__sv_pred_dz$35 , \mul2_mul_op__sv_pred_sz$34 , \mul2_mul_op__insn$33 , \mul2_mul_op__is_signed$32 , \mul2_mul_op__is_32bit$31 , \mul2_mul_op__write_cr0$30 , \mul2_mul_op__oe__ok$29 , \mul2_mul_op__oe__oe$28 , \mul2_mul_op__rc__ok$27 , \mul2_mul_op__rc__rc$26 , \mul2_mul_op__imm_data__ok$25 , \mul2_mul_op__imm_data__data$24 , \mul2_mul_op__fn_unit$23 , \mul2_mul_op__insn_type$22 }; + assign \muxid$44 = \mul2_muxid$21 ; + assign p_valid_i_p_ready_o = \$42 ; assign n_i_rdy_data = n_ready_i; - assign \p_valid_i$33 = p_valid_i; + assign \p_valid_i$41 = p_valid_i; assign mul2_neg_res32 = neg_res32; assign mul2_neg_res = neg_res; assign mul2_xer_so = xer_so; assign mul2_rb = rb; assign mul2_ra = ra; - assign { mul2_mul_op__insn, mul2_mul_op__is_signed, mul2_mul_op__is_32bit, mul2_mul_op__write_cr0, mul2_mul_op__oe__ok, mul2_mul_op__oe__oe, mul2_mul_op__rc__ok, mul2_mul_op__rc__rc, mul2_mul_op__imm_data__ok, mul2_mul_op__imm_data__data, mul2_mul_op__fn_unit, mul2_mul_op__insn_type } = { mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type }; + assign { mul2_mul_op__SV_Ptype, mul2_mul_op__sv_saturate, mul2_mul_op__sv_pred_dz, mul2_mul_op__sv_pred_sz, mul2_mul_op__insn, mul2_mul_op__is_signed, mul2_mul_op__is_32bit, mul2_mul_op__write_cr0, mul2_mul_op__oe__ok, mul2_mul_op__oe__oe, mul2_mul_op__rc__ok, mul2_mul_op__rc__rc, mul2_mul_op__imm_data__ok, mul2_mul_op__imm_data__data, mul2_mul_op__fn_unit, mul2_mul_op__insn_type } = { mul_op__SV_Ptype, mul_op__sv_saturate, mul_op__sv_pred_dz, mul_op__sv_pred_sz, mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type }; assign mul2_muxid = muxid; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3" *) (* generator = "nMigen" *) -module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, o, xer_so, neg_res, neg_res32, n_valid_o, n_ready_i, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \o$14 , o_ok, cr_a, cr_a_ok, xer_ov, xer_ov_ok, \xer_so$15 , xer_so_ok, coresync_clk); +module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, mul_op__sv_pred_sz, mul_op__sv_pred_dz, mul_op__sv_saturate, mul_op__SV_Ptype, o, xer_so, neg_res, neg_res32, n_valid_o, n_ready_i, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \mul_op__sv_pred_sz$14 , \mul_op__sv_pred_dz$15 , \mul_op__sv_saturate$16 , \mul_op__SV_Ptype$17 , \o$18 , o_ok, cr_a, cr_a_ok, xer_ov, xer_ov_ok, \xer_so$19 , xer_so_ok, coresync_clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) - wire \$56 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + wire \$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [3:0] cr_a; reg [3:0] cr_a = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [3:0] \cr_a$51 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [3:0] \cr_a$73 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [3:0] \cr_a$63 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [3:0] \cr_a$89 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [3:0] \cr_a$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_a_ok; reg cr_a_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \cr_a_ok$50 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \cr_a_ok$52 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \cr_a_ok$74 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \cr_a_ok$62 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \cr_a_ok$64 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \cr_a_ok$90 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \cr_a_ok$next ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] mul3_mul_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \mul3_mul_op__SV_Ptype$36 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] mul3_mul_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] mul3_mul_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \mul3_mul_op__fn_unit$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \mul3_mul_op__fn_unit$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] mul3_mul_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \mul3_mul_op__imm_data__data$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \mul3_mul_op__imm_data__data$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul3_mul_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul3_mul_op__imm_data__ok$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul3_mul_op__imm_data__ok$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] mul3_mul_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \mul3_mul_op__insn$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \mul3_mul_op__insn$32 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -156888,7 +168033,9 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] mul3_mul_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -156965,139 +168112,185 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \mul3_mul_op__insn_type$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \mul3_mul_op__insn_type$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul3_mul_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul3_mul_op__is_32bit$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul3_mul_op__is_32bit$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul3_mul_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul3_mul_op__is_signed$27 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul3_mul_op__is_signed$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul3_mul_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul3_mul_op__oe__oe$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul3_mul_op__oe__oe$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul3_mul_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul3_mul_op__oe__ok$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul3_mul_op__oe__ok$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul3_mul_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul3_mul_op__rc__ok$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul3_mul_op__rc__ok$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul3_mul_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul3_mul_op__rc__rc$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul3_mul_op__rc__rc$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire mul3_mul_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul3_mul_op__sv_pred_dz$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire mul3_mul_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul3_mul_op__sv_pred_sz$33 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] mul3_mul_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \mul3_mul_op__sv_saturate$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire mul3_mul_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul3_mul_op__write_cr0$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul3_mul_op__write_cr0$29 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] mul3_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \mul3_muxid$16 ; + wire [1:0] \mul3_muxid$20 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *) wire mul3_neg_res; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [128:0] mul3_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \mul3_o$29 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \mul3_o$37 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire mul3_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [1:0] mul3_xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire mul3_xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire mul3_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \mul3_xer_so$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \mul3_xer_so$38 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire mul3_xer_so_ok; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] mul_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \mul_op__SV_Ptype$17 ; + reg [1:0] \mul_op__SV_Ptype$17 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \mul_op__SV_Ptype$17$next ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \mul_op__SV_Ptype$86 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] mul_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] mul_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \mul_op__fn_unit$3 ; - reg [13:0] \mul_op__fn_unit$3 = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] \mul_op__fn_unit$3$next ; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \mul_op__fn_unit$3 ; + reg [14:0] \mul_op__fn_unit$3 = 15'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] \mul_op__fn_unit$3$next ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \mul_op__fn_unit$60 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \mul_op__fn_unit$72 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] mul_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \mul_op__imm_data__data$4 ; reg [63:0] \mul_op__imm_data__data$4 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] \mul_op__imm_data__data$4$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \mul_op__imm_data__data$61 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \mul_op__imm_data__data$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__imm_data__ok$5 ; reg \mul_op__imm_data__ok$5 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \mul_op__imm_data__ok$5$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_op__imm_data__ok$62 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__imm_data__ok$74 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] mul_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \mul_op__insn$13 ; reg [31:0] \mul_op__insn$13 = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] \mul_op__insn$13$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \mul_op__insn$70 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \mul_op__insn$82 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -157173,7 +168366,9 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] mul_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -157250,10 +168445,12 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] \mul_op__insn_type$2 ; reg [6:0] \mul_op__insn_type$2 = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] \mul_op__insn_type$2$next ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -157330,71 +168527,112 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \mul_op__insn_type$59 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \mul_op__insn_type$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__is_32bit$11 ; reg \mul_op__is_32bit$11 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \mul_op__is_32bit$11$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_op__is_32bit$68 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__is_32bit$80 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__is_signed$12 ; reg \mul_op__is_signed$12 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \mul_op__is_signed$12$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_op__is_signed$69 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__is_signed$81 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_op__oe__oe$65 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__oe__oe$77 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__oe__oe$8 ; reg \mul_op__oe__oe$8 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \mul_op__oe__oe$8$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_op__oe__ok$66 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__oe__ok$78 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__oe__ok$9 ; reg \mul_op__oe__ok$9 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \mul_op__oe__ok$9$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_op__rc__ok$64 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__rc__ok$7 ; reg \mul_op__rc__ok$7 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \mul_op__rc__ok$7$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__rc__ok$76 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__rc__rc$6 ; reg \mul_op__rc__rc$6 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \mul_op__rc__rc$6$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_op__rc__rc$63 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__rc__rc$75 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input mul_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \mul_op__sv_pred_dz$15 ; + reg \mul_op__sv_pred_dz$15 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \mul_op__sv_pred_dz$15$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__sv_pred_dz$84 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input mul_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \mul_op__sv_pred_sz$14 ; + reg \mul_op__sv_pred_sz$14 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \mul_op__sv_pred_sz$14$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__sv_pred_sz$83 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] mul_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \mul_op__sv_saturate$16 ; + reg [1:0] \mul_op__sv_saturate$16 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \mul_op__sv_saturate$16$next ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \mul_op__sv_saturate$85 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__write_cr0$10 ; reg \mul_op__write_cr0$10 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \mul_op__write_cr0$10$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \mul_op__write_cr0$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \mul_op__write_cr0$79 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) @@ -157403,7 +168641,7 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) reg [1:0] \muxid$1$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \muxid$58 ; + wire [1:0] \muxid$70 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *) wire n_i_rdy_data; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) @@ -157415,75 +168653,89 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *) input neg_res32; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *) - wire \neg_res32$49 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire \neg_res32$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [128:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [63:0] \o$14 ; - reg [63:0] \o$14 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg [63:0] \o$14$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \o$71 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [63:0] \o$18 ; + reg [63:0] \o$18 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg [63:0] \o$18$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \o$87 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output o_ok; reg o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \o_ok$72 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \o_ok$88 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \o_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [3:0] output_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [3:0] \output_cr_a$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [3:0] \output_cr_a$58 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire output_cr_a_ok; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] output_mul_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \output_mul_op__SV_Ptype$55 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] output_mul_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] output_mul_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \output_mul_op__fn_unit$33 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \output_mul_op__fn_unit$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] output_mul_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \output_mul_op__imm_data__data$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \output_mul_op__imm_data__data$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_mul_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_mul_op__imm_data__ok$35 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_mul_op__imm_data__ok$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] output_mul_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \output_mul_op__insn$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \output_mul_op__insn$51 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -157559,7 +168811,9 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] output_mul_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -157636,109 +168890,131 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \output_mul_op__insn_type$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \output_mul_op__insn_type$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_mul_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_mul_op__is_32bit$41 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_mul_op__is_32bit$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_mul_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_mul_op__is_signed$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_mul_op__is_signed$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_mul_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_mul_op__oe__oe$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_mul_op__oe__oe$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_mul_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_mul_op__oe__ok$39 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_mul_op__oe__ok$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_mul_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_mul_op__rc__ok$37 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_mul_op__rc__ok$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_mul_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_mul_op__rc__rc$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_mul_op__rc__rc$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire output_mul_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_mul_op__sv_pred_dz$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire output_mul_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_mul_op__sv_pred_sz$52 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] output_mul_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \output_mul_op__sv_saturate$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_mul_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_mul_op__write_cr0$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_mul_op__write_cr0$48 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] output_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \output_muxid$31 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \output_muxid$39 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] output_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \output_o$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \output_o$56 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire output_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \output_o_ok$45 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \output_o_ok$57 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [1:0] output_xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [1:0] \output_xer_ov$47 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [1:0] \output_xer_ov$59 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire output_xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire output_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \output_xer_so$48 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \output_xer_so$60 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire output_xer_so_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) input p_valid_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *) - wire \p_valid_i$55 ; + wire \p_valid_i$67 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *) wire p_valid_i_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg r_busy = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg \r_busy$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [1:0] xer_ov; reg [1:0] xer_ov = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [1:0] \xer_ov$75 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [1:0] \xer_ov$91 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [1:0] \xer_ov$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ov_ok; reg xer_ov_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_ov_ok$53 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_ov_ok$76 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_ov_ok$65 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_ov_ok$92 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \xer_ov_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \xer_so$15 ; - reg \xer_so$15 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg \xer_so$15$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_so$77 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \xer_so$19 ; + reg \xer_so$19 = 1'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg \xer_so$19$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_so$93 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_so_ok; reg xer_so_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_so_ok$54 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_so_ok$78 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_so_ok$66 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_so_ok$94 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \xer_so_ok$next ; - assign \$56 = \p_valid_i$55 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; + assign \$68 = \p_valid_i$67 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; always @(posedge coresync_clk) - \xer_so$15 <= \xer_so$15$next ; + \xer_so$19 <= \xer_so$19$next ; always @(posedge coresync_clk) xer_so_ok <= \xer_so_ok$next ; always @(posedge coresync_clk) @@ -157750,7 +169026,7 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m always @(posedge coresync_clk) cr_a_ok <= \cr_a_ok$next ; always @(posedge coresync_clk) - \o$14 <= \o$14$next ; + \o$18 <= \o$18$next ; always @(posedge coresync_clk) o_ok <= \o_ok$next ; always @(posedge coresync_clk) @@ -157777,45 +169053,61 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m \mul_op__is_signed$12 <= \mul_op__is_signed$12$next ; always @(posedge coresync_clk) \mul_op__insn$13 <= \mul_op__insn$13$next ; + always @(posedge coresync_clk) + \mul_op__sv_pred_sz$14 <= \mul_op__sv_pred_sz$14$next ; + always @(posedge coresync_clk) + \mul_op__sv_pred_dz$15 <= \mul_op__sv_pred_dz$15$next ; + always @(posedge coresync_clk) + \mul_op__sv_saturate$16 <= \mul_op__sv_saturate$16$next ; + always @(posedge coresync_clk) + \mul_op__SV_Ptype$17 <= \mul_op__SV_Ptype$17$next ; always @(posedge coresync_clk) \muxid$1 <= \muxid$1$next ; always @(posedge coresync_clk) r_busy <= \r_busy$next ; mul3 mul3 ( + .mul_op__SV_Ptype(mul3_mul_op__SV_Ptype), + .\mul_op__SV_Ptype$17 (\mul3_mul_op__SV_Ptype$36 ), .mul_op__fn_unit(mul3_mul_op__fn_unit), - .\mul_op__fn_unit$3 (\mul3_mul_op__fn_unit$18 ), + .\mul_op__fn_unit$3 (\mul3_mul_op__fn_unit$22 ), .mul_op__imm_data__data(mul3_mul_op__imm_data__data), - .\mul_op__imm_data__data$4 (\mul3_mul_op__imm_data__data$19 ), + .\mul_op__imm_data__data$4 (\mul3_mul_op__imm_data__data$23 ), .mul_op__imm_data__ok(mul3_mul_op__imm_data__ok), - .\mul_op__imm_data__ok$5 (\mul3_mul_op__imm_data__ok$20 ), + .\mul_op__imm_data__ok$5 (\mul3_mul_op__imm_data__ok$24 ), .mul_op__insn(mul3_mul_op__insn), - .\mul_op__insn$13 (\mul3_mul_op__insn$28 ), + .\mul_op__insn$13 (\mul3_mul_op__insn$32 ), .mul_op__insn_type(mul3_mul_op__insn_type), - .\mul_op__insn_type$2 (\mul3_mul_op__insn_type$17 ), + .\mul_op__insn_type$2 (\mul3_mul_op__insn_type$21 ), .mul_op__is_32bit(mul3_mul_op__is_32bit), - .\mul_op__is_32bit$11 (\mul3_mul_op__is_32bit$26 ), + .\mul_op__is_32bit$11 (\mul3_mul_op__is_32bit$30 ), .mul_op__is_signed(mul3_mul_op__is_signed), - .\mul_op__is_signed$12 (\mul3_mul_op__is_signed$27 ), + .\mul_op__is_signed$12 (\mul3_mul_op__is_signed$31 ), .mul_op__oe__oe(mul3_mul_op__oe__oe), - .\mul_op__oe__oe$8 (\mul3_mul_op__oe__oe$23 ), + .\mul_op__oe__oe$8 (\mul3_mul_op__oe__oe$27 ), .mul_op__oe__ok(mul3_mul_op__oe__ok), - .\mul_op__oe__ok$9 (\mul3_mul_op__oe__ok$24 ), + .\mul_op__oe__ok$9 (\mul3_mul_op__oe__ok$28 ), .mul_op__rc__ok(mul3_mul_op__rc__ok), - .\mul_op__rc__ok$7 (\mul3_mul_op__rc__ok$22 ), + .\mul_op__rc__ok$7 (\mul3_mul_op__rc__ok$26 ), .mul_op__rc__rc(mul3_mul_op__rc__rc), - .\mul_op__rc__rc$6 (\mul3_mul_op__rc__rc$21 ), + .\mul_op__rc__rc$6 (\mul3_mul_op__rc__rc$25 ), + .mul_op__sv_pred_dz(mul3_mul_op__sv_pred_dz), + .\mul_op__sv_pred_dz$15 (\mul3_mul_op__sv_pred_dz$34 ), + .mul_op__sv_pred_sz(mul3_mul_op__sv_pred_sz), + .\mul_op__sv_pred_sz$14 (\mul3_mul_op__sv_pred_sz$33 ), + .mul_op__sv_saturate(mul3_mul_op__sv_saturate), + .\mul_op__sv_saturate$16 (\mul3_mul_op__sv_saturate$35 ), .mul_op__write_cr0(mul3_mul_op__write_cr0), - .\mul_op__write_cr0$10 (\mul3_mul_op__write_cr0$25 ), + .\mul_op__write_cr0$10 (\mul3_mul_op__write_cr0$29 ), .muxid(mul3_muxid), - .\muxid$1 (\mul3_muxid$16 ), + .\muxid$1 (\mul3_muxid$20 ), .neg_res(mul3_neg_res), .o(mul3_o), - .\o$14 (\mul3_o$29 ), + .\o$18 (\mul3_o$37 ), .o_ok(mul3_o_ok), .xer_ov(mul3_xer_ov), .xer_ov_ok(mul3_xer_ov_ok), .xer_so(mul3_xer_so), - .\xer_so$15 (\mul3_xer_so$30 ), + .\xer_so$19 (\mul3_xer_so$38 ), .xer_so_ok(mul3_xer_so_ok) ); \n$99 n ( @@ -157824,43 +169116,51 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m ); \output$100 \output ( .cr_a(output_cr_a), - .\cr_a$16 (\output_cr_a$46 ), + .\cr_a$20 (\output_cr_a$58 ), .cr_a_ok(output_cr_a_ok), + .mul_op__SV_Ptype(output_mul_op__SV_Ptype), + .\mul_op__SV_Ptype$17 (\output_mul_op__SV_Ptype$55 ), .mul_op__fn_unit(output_mul_op__fn_unit), - .\mul_op__fn_unit$3 (\output_mul_op__fn_unit$33 ), + .\mul_op__fn_unit$3 (\output_mul_op__fn_unit$41 ), .mul_op__imm_data__data(output_mul_op__imm_data__data), - .\mul_op__imm_data__data$4 (\output_mul_op__imm_data__data$34 ), + .\mul_op__imm_data__data$4 (\output_mul_op__imm_data__data$42 ), .mul_op__imm_data__ok(output_mul_op__imm_data__ok), - .\mul_op__imm_data__ok$5 (\output_mul_op__imm_data__ok$35 ), + .\mul_op__imm_data__ok$5 (\output_mul_op__imm_data__ok$43 ), .mul_op__insn(output_mul_op__insn), - .\mul_op__insn$13 (\output_mul_op__insn$43 ), + .\mul_op__insn$13 (\output_mul_op__insn$51 ), .mul_op__insn_type(output_mul_op__insn_type), - .\mul_op__insn_type$2 (\output_mul_op__insn_type$32 ), + .\mul_op__insn_type$2 (\output_mul_op__insn_type$40 ), .mul_op__is_32bit(output_mul_op__is_32bit), - .\mul_op__is_32bit$11 (\output_mul_op__is_32bit$41 ), + .\mul_op__is_32bit$11 (\output_mul_op__is_32bit$49 ), .mul_op__is_signed(output_mul_op__is_signed), - .\mul_op__is_signed$12 (\output_mul_op__is_signed$42 ), + .\mul_op__is_signed$12 (\output_mul_op__is_signed$50 ), .mul_op__oe__oe(output_mul_op__oe__oe), - .\mul_op__oe__oe$8 (\output_mul_op__oe__oe$38 ), + .\mul_op__oe__oe$8 (\output_mul_op__oe__oe$46 ), .mul_op__oe__ok(output_mul_op__oe__ok), - .\mul_op__oe__ok$9 (\output_mul_op__oe__ok$39 ), + .\mul_op__oe__ok$9 (\output_mul_op__oe__ok$47 ), .mul_op__rc__ok(output_mul_op__rc__ok), - .\mul_op__rc__ok$7 (\output_mul_op__rc__ok$37 ), + .\mul_op__rc__ok$7 (\output_mul_op__rc__ok$45 ), .mul_op__rc__rc(output_mul_op__rc__rc), - .\mul_op__rc__rc$6 (\output_mul_op__rc__rc$36 ), + .\mul_op__rc__rc$6 (\output_mul_op__rc__rc$44 ), + .mul_op__sv_pred_dz(output_mul_op__sv_pred_dz), + .\mul_op__sv_pred_dz$15 (\output_mul_op__sv_pred_dz$53 ), + .mul_op__sv_pred_sz(output_mul_op__sv_pred_sz), + .\mul_op__sv_pred_sz$14 (\output_mul_op__sv_pred_sz$52 ), + .mul_op__sv_saturate(output_mul_op__sv_saturate), + .\mul_op__sv_saturate$16 (\output_mul_op__sv_saturate$54 ), .mul_op__write_cr0(output_mul_op__write_cr0), - .\mul_op__write_cr0$10 (\output_mul_op__write_cr0$40 ), + .\mul_op__write_cr0$10 (\output_mul_op__write_cr0$48 ), .muxid(output_muxid), - .\muxid$1 (\output_muxid$31 ), + .\muxid$1 (\output_muxid$39 ), .o(output_o), - .\o$14 (\output_o$44 ), + .\o$18 (\output_o$56 ), .o_ok(output_o_ok), - .\o_ok$15 (\output_o_ok$45 ), + .\o_ok$19 (\output_o_ok$57 ), .xer_ov(output_xer_ov), - .\xer_ov$17 (\output_xer_ov$47 ), + .\xer_ov$21 (\output_xer_ov$59 ), .xer_ov_ok(output_xer_ov_ok), .xer_so(output_xer_so), - .\xer_so$18 (\output_xer_so$48 ), + .\xer_so$22 (\output_xer_so$60 ), .xer_so_ok(output_xer_so_ok) ); \p$98 p ( @@ -157879,7 +169179,7 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -157892,10 +169192,10 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \muxid$1$next = \muxid$58 ; + \muxid$1$next = \muxid$70 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \muxid$1$next = \muxid$58 ; + \muxid$1$next = \muxid$70 ; endcase end always @* begin @@ -157912,16 +169212,20 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m \mul_op__is_32bit$11$next = \mul_op__is_32bit$11 ; \mul_op__is_signed$12$next = \mul_op__is_signed$12 ; \mul_op__insn$13$next = \mul_op__insn$13 ; + \mul_op__sv_pred_sz$14$next = \mul_op__sv_pred_sz$14 ; + \mul_op__sv_pred_dz$15$next = \mul_op__sv_pred_dz$15 ; + \mul_op__sv_saturate$16$next = \mul_op__sv_saturate$16 ; + \mul_op__SV_Ptype$17$next = \mul_op__SV_Ptype$17 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \mul_op__insn$13$next , \mul_op__is_signed$12$next , \mul_op__is_32bit$11$next , \mul_op__write_cr0$10$next , \mul_op__oe__ok$9$next , \mul_op__oe__oe$8$next , \mul_op__rc__ok$7$next , \mul_op__rc__rc$6$next , \mul_op__imm_data__ok$5$next , \mul_op__imm_data__data$4$next , \mul_op__fn_unit$3$next , \mul_op__insn_type$2$next } = { \mul_op__insn$70 , \mul_op__is_signed$69 , \mul_op__is_32bit$68 , \mul_op__write_cr0$67 , \mul_op__oe__ok$66 , \mul_op__oe__oe$65 , \mul_op__rc__ok$64 , \mul_op__rc__rc$63 , \mul_op__imm_data__ok$62 , \mul_op__imm_data__data$61 , \mul_op__fn_unit$60 , \mul_op__insn_type$59 }; + { \mul_op__SV_Ptype$17$next , \mul_op__sv_saturate$16$next , \mul_op__sv_pred_dz$15$next , \mul_op__sv_pred_sz$14$next , \mul_op__insn$13$next , \mul_op__is_signed$12$next , \mul_op__is_32bit$11$next , \mul_op__write_cr0$10$next , \mul_op__oe__ok$9$next , \mul_op__oe__oe$8$next , \mul_op__rc__ok$7$next , \mul_op__rc__rc$6$next , \mul_op__imm_data__ok$5$next , \mul_op__imm_data__data$4$next , \mul_op__fn_unit$3$next , \mul_op__insn_type$2$next } = { \mul_op__SV_Ptype$86 , \mul_op__sv_saturate$85 , \mul_op__sv_pred_dz$84 , \mul_op__sv_pred_sz$83 , \mul_op__insn$82 , \mul_op__is_signed$81 , \mul_op__is_32bit$80 , \mul_op__write_cr0$79 , \mul_op__oe__ok$78 , \mul_op__oe__oe$77 , \mul_op__rc__ok$76 , \mul_op__rc__rc$75 , \mul_op__imm_data__ok$74 , \mul_op__imm_data__data$73 , \mul_op__fn_unit$72 , \mul_op__insn_type$71 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \mul_op__insn$13$next , \mul_op__is_signed$12$next , \mul_op__is_32bit$11$next , \mul_op__write_cr0$10$next , \mul_op__oe__ok$9$next , \mul_op__oe__oe$8$next , \mul_op__rc__ok$7$next , \mul_op__rc__rc$6$next , \mul_op__imm_data__ok$5$next , \mul_op__imm_data__data$4$next , \mul_op__fn_unit$3$next , \mul_op__insn_type$2$next } = { \mul_op__insn$70 , \mul_op__is_signed$69 , \mul_op__is_32bit$68 , \mul_op__write_cr0$67 , \mul_op__oe__ok$66 , \mul_op__oe__oe$65 , \mul_op__rc__ok$64 , \mul_op__rc__rc$63 , \mul_op__imm_data__ok$62 , \mul_op__imm_data__data$61 , \mul_op__fn_unit$60 , \mul_op__insn_type$59 }; + { \mul_op__SV_Ptype$17$next , \mul_op__sv_saturate$16$next , \mul_op__sv_pred_dz$15$next , \mul_op__sv_pred_sz$14$next , \mul_op__insn$13$next , \mul_op__is_signed$12$next , \mul_op__is_32bit$11$next , \mul_op__write_cr0$10$next , \mul_op__oe__ok$9$next , \mul_op__oe__oe$8$next , \mul_op__rc__ok$7$next , \mul_op__rc__rc$6$next , \mul_op__imm_data__ok$5$next , \mul_op__imm_data__data$4$next , \mul_op__fn_unit$3$next , \mul_op__insn_type$2$next } = { \mul_op__SV_Ptype$86 , \mul_op__sv_saturate$85 , \mul_op__sv_pred_dz$84 , \mul_op__sv_pred_sz$83 , \mul_op__insn$82 , \mul_op__is_signed$81 , \mul_op__is_32bit$80 , \mul_op__write_cr0$79 , \mul_op__oe__ok$78 , \mul_op__oe__oe$77 , \mul_op__rc__ok$76 , \mul_op__rc__rc$75 , \mul_op__imm_data__ok$74 , \mul_op__imm_data__data$73 , \mul_op__fn_unit$72 , \mul_op__insn_type$71 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -157936,18 +169240,18 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m end always @* begin if (\initial ) begin end - \o$14$next = \o$14 ; + \o$18$next = \o$18 ; \o_ok$next = o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \o_ok$next , \o$14$next } = { \o_ok$72 , \o$71 }; + { \o_ok$next , \o$18$next } = { \o_ok$88 , \o$87 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \o_ok$next , \o$14$next } = { \o_ok$72 , \o$71 }; + { \o_ok$next , \o$18$next } = { \o_ok$88 , \o$87 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \o_ok$next = 1'h0; @@ -157961,12 +169265,12 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$74 , \cr_a$73 }; + { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$90 , \cr_a$89 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$74 , \cr_a$73 }; + { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$90 , \cr_a$89 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \cr_a_ok$next = 1'h0; @@ -157980,12 +169284,12 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$76 , \xer_ov$75 }; + { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$92 , \xer_ov$91 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$76 , \xer_ov$75 }; + { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$92 , \xer_ov$91 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \xer_ov_ok$next = 1'h0; @@ -157993,47 +169297,47 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m end always @* begin if (\initial ) begin end - \xer_so$15$next = \xer_so$15 ; + \xer_so$19$next = \xer_so$19 ; \xer_so_ok$next = xer_so_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \xer_so_ok$next , \xer_so$15$next } = { \xer_so_ok$78 , \xer_so$77 }; + { \xer_so_ok$next , \xer_so$19$next } = { \xer_so_ok$94 , \xer_so$93 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \xer_so_ok$next , \xer_so$15$next } = { \xer_so_ok$78 , \xer_so$77 }; + { \xer_so_ok$next , \xer_so$19$next } = { \xer_so_ok$94 , \xer_so$93 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \xer_so_ok$next = 1'h0; endcase end - assign \cr_a$51 = 4'h0; - assign \cr_a_ok$52 = 1'h0; + assign \cr_a$63 = 4'h0; + assign \cr_a_ok$64 = 1'h0; assign p_ready_o = n_i_rdy_data; assign n_valid_o = r_busy; - assign { \xer_so_ok$78 , \xer_so$77 } = { output_xer_so_ok, \output_xer_so$48 }; - assign { \xer_ov_ok$76 , \xer_ov$75 } = { output_xer_ov_ok, \output_xer_ov$47 }; - assign { \cr_a_ok$74 , \cr_a$73 } = { output_cr_a_ok, \output_cr_a$46 }; - assign { \o_ok$72 , \o$71 } = { \output_o_ok$45 , \output_o$44 }; - assign { \mul_op__insn$70 , \mul_op__is_signed$69 , \mul_op__is_32bit$68 , \mul_op__write_cr0$67 , \mul_op__oe__ok$66 , \mul_op__oe__oe$65 , \mul_op__rc__ok$64 , \mul_op__rc__rc$63 , \mul_op__imm_data__ok$62 , \mul_op__imm_data__data$61 , \mul_op__fn_unit$60 , \mul_op__insn_type$59 } = { \output_mul_op__insn$43 , \output_mul_op__is_signed$42 , \output_mul_op__is_32bit$41 , \output_mul_op__write_cr0$40 , \output_mul_op__oe__ok$39 , \output_mul_op__oe__oe$38 , \output_mul_op__rc__ok$37 , \output_mul_op__rc__rc$36 , \output_mul_op__imm_data__ok$35 , \output_mul_op__imm_data__data$34 , \output_mul_op__fn_unit$33 , \output_mul_op__insn_type$32 }; - assign \muxid$58 = \output_muxid$31 ; - assign p_valid_i_p_ready_o = \$56 ; + assign { \xer_so_ok$94 , \xer_so$93 } = { output_xer_so_ok, \output_xer_so$60 }; + assign { \xer_ov_ok$92 , \xer_ov$91 } = { output_xer_ov_ok, \output_xer_ov$59 }; + assign { \cr_a_ok$90 , \cr_a$89 } = { output_cr_a_ok, \output_cr_a$58 }; + assign { \o_ok$88 , \o$87 } = { \output_o_ok$57 , \output_o$56 }; + assign { \mul_op__SV_Ptype$86 , \mul_op__sv_saturate$85 , \mul_op__sv_pred_dz$84 , \mul_op__sv_pred_sz$83 , \mul_op__insn$82 , \mul_op__is_signed$81 , \mul_op__is_32bit$80 , \mul_op__write_cr0$79 , \mul_op__oe__ok$78 , \mul_op__oe__oe$77 , \mul_op__rc__ok$76 , \mul_op__rc__rc$75 , \mul_op__imm_data__ok$74 , \mul_op__imm_data__data$73 , \mul_op__fn_unit$72 , \mul_op__insn_type$71 } = { \output_mul_op__SV_Ptype$55 , \output_mul_op__sv_saturate$54 , \output_mul_op__sv_pred_dz$53 , \output_mul_op__sv_pred_sz$52 , \output_mul_op__insn$51 , \output_mul_op__is_signed$50 , \output_mul_op__is_32bit$49 , \output_mul_op__write_cr0$48 , \output_mul_op__oe__ok$47 , \output_mul_op__oe__oe$46 , \output_mul_op__rc__ok$45 , \output_mul_op__rc__rc$44 , \output_mul_op__imm_data__ok$43 , \output_mul_op__imm_data__data$42 , \output_mul_op__fn_unit$41 , \output_mul_op__insn_type$40 }; + assign \muxid$70 = \output_muxid$39 ; + assign p_valid_i_p_ready_o = \$68 ; assign n_i_rdy_data = n_ready_i; - assign \p_valid_i$55 = p_valid_i; - assign { \xer_so_ok$54 , output_xer_so } = { mul3_xer_so_ok, \mul3_xer_so$30 }; - assign { \xer_ov_ok$53 , output_xer_ov } = { mul3_xer_ov_ok, mul3_xer_ov }; - assign { \cr_a_ok$50 , output_cr_a } = 5'h00; - assign { output_o_ok, output_o } = { mul3_o_ok, \mul3_o$29 }; - assign { output_mul_op__insn, output_mul_op__is_signed, output_mul_op__is_32bit, output_mul_op__write_cr0, output_mul_op__oe__ok, output_mul_op__oe__oe, output_mul_op__rc__ok, output_mul_op__rc__rc, output_mul_op__imm_data__ok, output_mul_op__imm_data__data, output_mul_op__fn_unit, output_mul_op__insn_type } = { \mul3_mul_op__insn$28 , \mul3_mul_op__is_signed$27 , \mul3_mul_op__is_32bit$26 , \mul3_mul_op__write_cr0$25 , \mul3_mul_op__oe__ok$24 , \mul3_mul_op__oe__oe$23 , \mul3_mul_op__rc__ok$22 , \mul3_mul_op__rc__rc$21 , \mul3_mul_op__imm_data__ok$20 , \mul3_mul_op__imm_data__data$19 , \mul3_mul_op__fn_unit$18 , \mul3_mul_op__insn_type$17 }; - assign output_muxid = \mul3_muxid$16 ; - assign \neg_res32$49 = neg_res32; + assign \p_valid_i$67 = p_valid_i; + assign { \xer_so_ok$66 , output_xer_so } = { mul3_xer_so_ok, \mul3_xer_so$38 }; + assign { \xer_ov_ok$65 , output_xer_ov } = { mul3_xer_ov_ok, mul3_xer_ov }; + assign { \cr_a_ok$62 , output_cr_a } = 5'h00; + assign { output_o_ok, output_o } = { mul3_o_ok, \mul3_o$37 }; + assign { output_mul_op__SV_Ptype, output_mul_op__sv_saturate, output_mul_op__sv_pred_dz, output_mul_op__sv_pred_sz, output_mul_op__insn, output_mul_op__is_signed, output_mul_op__is_32bit, output_mul_op__write_cr0, output_mul_op__oe__ok, output_mul_op__oe__oe, output_mul_op__rc__ok, output_mul_op__rc__rc, output_mul_op__imm_data__ok, output_mul_op__imm_data__data, output_mul_op__fn_unit, output_mul_op__insn_type } = { \mul3_mul_op__SV_Ptype$36 , \mul3_mul_op__sv_saturate$35 , \mul3_mul_op__sv_pred_dz$34 , \mul3_mul_op__sv_pred_sz$33 , \mul3_mul_op__insn$32 , \mul3_mul_op__is_signed$31 , \mul3_mul_op__is_32bit$30 , \mul3_mul_op__write_cr0$29 , \mul3_mul_op__oe__ok$28 , \mul3_mul_op__oe__oe$27 , \mul3_mul_op__rc__ok$26 , \mul3_mul_op__rc__rc$25 , \mul3_mul_op__imm_data__ok$24 , \mul3_mul_op__imm_data__data$23 , \mul3_mul_op__fn_unit$22 , \mul3_mul_op__insn_type$21 }; + assign output_muxid = \mul3_muxid$20 ; + assign \neg_res32$61 = neg_res32; assign mul3_neg_res = neg_res; assign mul3_xer_so = xer_so; assign mul3_o = o; - assign { mul3_mul_op__insn, mul3_mul_op__is_signed, mul3_mul_op__is_32bit, mul3_mul_op__write_cr0, mul3_mul_op__oe__ok, mul3_mul_op__oe__oe, mul3_mul_op__rc__ok, mul3_mul_op__rc__rc, mul3_mul_op__imm_data__ok, mul3_mul_op__imm_data__data, mul3_mul_op__fn_unit, mul3_mul_op__insn_type } = { mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type }; + assign { mul3_mul_op__SV_Ptype, mul3_mul_op__sv_saturate, mul3_mul_op__sv_pred_dz, mul3_mul_op__sv_pred_sz, mul3_mul_op__insn, mul3_mul_op__is_signed, mul3_mul_op__is_32bit, mul3_mul_op__write_cr0, mul3_mul_op__oe__ok, mul3_mul_op__oe__oe, mul3_mul_op__rc__ok, mul3_mul_op__rc__rc, mul3_mul_op__imm_data__ok, mul3_mul_op__imm_data__data, mul3_mul_op__fn_unit, mul3_mul_op__insn_type } = { mul_op__SV_Ptype, mul_op__sv_saturate, mul_op__sv_pred_dz, mul_op__sv_pred_sz, mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type }; assign mul3_muxid = muxid; endmodule @@ -158447,9 +169751,9 @@ module opc_l(coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -158478,7 +169782,7 @@ module opc_l(coresync_rst, s_opc, r_opc, q_opc, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -158509,9 +169813,9 @@ module \opc_l$102 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -158540,7 +169844,7 @@ module \opc_l$102 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -158571,9 +169875,9 @@ module \opc_l$11 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -158602,7 +169906,7 @@ module \opc_l$11 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -158633,9 +169937,9 @@ module \opc_l$120 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -158664,7 +169968,7 @@ module \opc_l$120 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -158695,9 +169999,9 @@ module \opc_l$126 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -158726,7 +170030,7 @@ module \opc_l$126 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -158757,9 +170061,9 @@ module \opc_l$24 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -158788,7 +170092,7 @@ module \opc_l$24 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -158819,9 +170123,9 @@ module \opc_l$40 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -158850,7 +170154,7 @@ module \opc_l$40 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -158881,9 +170185,9 @@ module \opc_l$56 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -158912,7 +170216,7 @@ module \opc_l$56 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -158943,9 +170247,9 @@ module \opc_l$68 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -158974,7 +170278,7 @@ module \opc_l$68 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -159005,9 +170309,9 @@ module \opc_l$85 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -159036,7 +170340,7 @@ module \opc_l$85 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -159049,95 +170353,111 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.output" *) (* generator = "nMigen" *) -module \output (alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, o, o_ok, cr_a, xer_ca, xer_ov, xer_so, \muxid$1 , \alu_op__insn_type$2 , \alu_op__fn_unit$3 , \alu_op__imm_data__data$4 , \alu_op__imm_data__ok$5 , \alu_op__rc__rc$6 , \alu_op__rc__ok$7 , \alu_op__oe__oe$8 , \alu_op__oe__ok$9 , \alu_op__invert_in$10 , \alu_op__zero_a$11 , \alu_op__invert_out$12 , \alu_op__write_cr0$13 , \alu_op__input_carry$14 , \alu_op__output_carry$15 , \alu_op__is_32bit$16 , \alu_op__is_signed$17 , \alu_op__data_len$18 , \alu_op__insn$19 , \o$20 , \o_ok$21 , \cr_a$22 , cr_a_ok, \xer_ca$23 , xer_ca_ok, \xer_ov$24 , xer_ov_ok, \xer_so$25 , xer_so_ok, muxid); +module \output (alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, alu_op__sv_pred_sz, alu_op__sv_pred_dz, alu_op__sv_saturate, alu_op__SV_Ptype, o, o_ok, cr_a, xer_ca, xer_ov, xer_so, \muxid$1 , \alu_op__insn_type$2 , \alu_op__fn_unit$3 , \alu_op__imm_data__data$4 , \alu_op__imm_data__ok$5 , \alu_op__rc__rc$6 , \alu_op__rc__ok$7 , \alu_op__oe__oe$8 , \alu_op__oe__ok$9 , \alu_op__invert_in$10 , \alu_op__zero_a$11 , \alu_op__invert_out$12 , \alu_op__write_cr0$13 , \alu_op__input_carry$14 , \alu_op__output_carry$15 , \alu_op__is_32bit$16 , \alu_op__is_signed$17 , \alu_op__data_len$18 , \alu_op__insn$19 , \alu_op__sv_pred_sz$20 , \alu_op__sv_pred_dz$21 , \alu_op__sv_saturate$22 , \alu_op__SV_Ptype$23 , \o$24 , \o_ok$25 , \cr_a$26 , cr_a_ok, \xer_ca$27 , xer_ca_ok, \xer_ov$28 , xer_ov_ok, \xer_so$29 , xer_so_ok, muxid); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *) - wire \$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) - wire [64:0] \$29 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) - wire [63:0] \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [64:0] \$33 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) - wire \$35 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *) - wire \$37 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *) - wire \$39 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) + wire \$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *) + wire \$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" *) + wire [64:0] \$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" *) + wire [63:0] \$36 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [64:0] \$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" *) wire \$41 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:80" *) wire \$43 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) wire \$45 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) wire \$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) + wire \$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *) + wire \$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:90" *) + wire \$53 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" *) - wire \$50 ; + wire \$56 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" *) - wire \$52 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \$58 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] alu_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \alu_op__SV_Ptype$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [3:0] alu_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [3:0] \alu_op__data_len$18 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] alu_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] alu_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \alu_op__fn_unit$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \alu_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] alu_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \alu_op__imm_data__data$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__imm_data__ok$5 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] alu_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [1:0] \alu_op__input_carry$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] alu_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \alu_op__insn$19 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -159214,7 +170534,9 @@ module \output (alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] alu_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -159291,129 +170613,152 @@ module \output (alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] \alu_op__insn_type$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__invert_in$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__invert_out$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__is_32bit$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__is_signed$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__oe__oe$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__oe__ok$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__output_carry$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__rc__ok$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__rc__rc$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input alu_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \alu_op__sv_pred_dz$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input alu_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \alu_op__sv_pred_sz$20 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] alu_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \alu_op__sv_saturate$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__write_cr0$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__zero_a$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:73" *) reg [3:0] cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [3:0] \cr_a$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [3:0] \cr_a$26 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" *) wire is_cmp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" *) wire is_cmpeqb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" *) wire is_negative; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" *) wire is_nzero; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" *) - wire is_positive; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" *) + wire is_positive; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" *) wire msb_test; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] \muxid$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [63:0] \o$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" *) - reg [64:0] \o$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [63:0] \o$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:39" *) + reg [64:0] \o$32 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \o_ok$21 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \o_ok$25 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" *) wire oe; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" *) - wire \oe$49 ; + wire \oe$55 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" *) reg so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52" *) wire [63:0] target; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [1:0] xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [1:0] \xer_ca$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [1:0] \xer_ca$27 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [1:0] xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [1:0] \xer_ov$24 ; - reg [1:0] \xer_ov$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [1:0] \xer_ov$28 ; + reg [1:0] \xer_ov$28 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ov_ok; reg xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \xer_so$25 ; - reg \xer_so$25 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \xer_so$29 ; + reg \xer_so$29 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_so_ok; reg xer_so_ok; - assign \$26 = alu_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *) alu_op__oe__ok; - assign \$30 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) o; - assign \$29 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) \$30 ; - assign \$33 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) o; - assign \$35 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) 7'h0a; - assign \$37 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *) 7'h0c; - assign \$39 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *) target; - assign \$41 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) msb_test; - assign \$43 = is_nzero & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) \$41 ; - assign \$45 = is_cmpeqb | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) is_cmp; - assign \$47 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" *) is_nzero; - assign \$50 = alu_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" *) alu_op__oe__ok; - assign \$52 = xer_so | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" *) xer_ov[0]; + assign \$30 = alu_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *) alu_op__oe__ok; + assign \$33 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *) alu_op__sv_pred_dz; + assign \$36 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" *) o; + assign \$35 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" *) \$36 ; + assign \$39 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) o; + assign \$41 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" *) 7'h0a; + assign \$43 = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:80" *) 7'h0c; + assign \$45 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) target; + assign \$47 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) msb_test; + assign \$49 = is_nzero & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) \$47 ; + assign \$51 = is_cmpeqb | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *) is_cmp; + assign \$53 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:90" *) is_nzero; + assign \$56 = alu_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" *) alu_op__oe__ok; + assign \$58 = xer_so | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" *) xer_ov[0]; always @* begin if (\initial ) begin end (* full_case = 32'd1 *) @@ -159421,7 +170766,7 @@ module \output (alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_ casez (oe) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" */ 1'h1: - so = \xer_so$25 ; + so = \xer_so$29 ; /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:32" */ default: so = xer_so; @@ -159430,44 +170775,50 @@ module \output (alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_ always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) - casez (\$45 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *) + casez (\$51 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" */ 1'h1: cr0 = cr_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:89" */ default: - cr0 = { is_negative, is_positive, \$47 , so }; + cr0 = { is_negative, is_positive, \$53 , so }; endcase end always @* begin if (\initial ) begin end - (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" *) - casez (alu_op__invert_out) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" */ + \o$32 = 65'h00000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *) + casez (\$33 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" */ 1'h1: - \o$28 = \$29 ; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" */ - default: - \o$28 = \$33 ; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) + casez (alu_op__invert_out) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" */ + 1'h1: + \o$32 = \$35 ; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:43" */ + default: + \o$32 = \$39 ; + endcase endcase end always @* begin if (\initial ) begin end - \xer_so$25 = 1'h0; + \xer_so$29 = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *) - casez (\oe$49 ) + casez (\oe$55 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */ 1'h1: - \xer_so$25 = \$52 ; + \xer_so$29 = \$58 ; endcase end always @* begin if (\initial ) begin end xer_so_ok = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *) - casez (\oe$49 ) + casez (\oe$55 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */ 1'h1: xer_so_ok = 1'h1; @@ -159475,134 +170826,150 @@ module \output (alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_ end always @* begin if (\initial ) begin end - \xer_ov$24 = 2'h0; + \xer_ov$28 = 2'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *) - casez (\oe$49 ) + casez (\oe$55 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */ 1'h1: - \xer_ov$24 = xer_ov; + \xer_ov$28 = xer_ov; endcase end always @* begin if (\initial ) begin end xer_ov_ok = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *) - casez (\oe$49 ) + casez (\oe$55 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */ 1'h1: xer_ov_ok = 1'h1; endcase end - assign \oe$49 = \$50 ; - assign { \alu_op__insn$19 , \alu_op__data_len$18 , \alu_op__is_signed$17 , \alu_op__is_32bit$16 , \alu_op__output_carry$15 , \alu_op__input_carry$14 , \alu_op__write_cr0$13 , \alu_op__invert_out$12 , \alu_op__zero_a$11 , \alu_op__invert_in$10 , \alu_op__oe__ok$9 , \alu_op__oe__oe$8 , \alu_op__rc__ok$7 , \alu_op__rc__rc$6 , \alu_op__imm_data__ok$5 , \alu_op__imm_data__data$4 , \alu_op__fn_unit$3 , \alu_op__insn_type$2 } = { alu_op__insn, alu_op__data_len, alu_op__is_signed, alu_op__is_32bit, alu_op__output_carry, alu_op__input_carry, alu_op__write_cr0, alu_op__invert_out, alu_op__zero_a, alu_op__invert_in, alu_op__oe__ok, alu_op__oe__oe, alu_op__rc__ok, alu_op__rc__rc, alu_op__imm_data__ok, alu_op__imm_data__data, alu_op__fn_unit, alu_op__insn_type }; + assign \oe$55 = \$56 ; + assign { \alu_op__SV_Ptype$23 , \alu_op__sv_saturate$22 , \alu_op__sv_pred_dz$21 , \alu_op__sv_pred_sz$20 , \alu_op__insn$19 , \alu_op__data_len$18 , \alu_op__is_signed$17 , \alu_op__is_32bit$16 , \alu_op__output_carry$15 , \alu_op__input_carry$14 , \alu_op__write_cr0$13 , \alu_op__invert_out$12 , \alu_op__zero_a$11 , \alu_op__invert_in$10 , \alu_op__oe__ok$9 , \alu_op__oe__oe$8 , \alu_op__rc__ok$7 , \alu_op__rc__rc$6 , \alu_op__imm_data__ok$5 , \alu_op__imm_data__data$4 , \alu_op__fn_unit$3 , \alu_op__insn_type$2 } = { alu_op__SV_Ptype, alu_op__sv_saturate, alu_op__sv_pred_dz, alu_op__sv_pred_sz, alu_op__insn, alu_op__data_len, alu_op__is_signed, alu_op__is_32bit, alu_op__output_carry, alu_op__input_carry, alu_op__write_cr0, alu_op__invert_out, alu_op__zero_a, alu_op__invert_in, alu_op__oe__ok, alu_op__oe__oe, alu_op__rc__ok, alu_op__rc__rc, alu_op__imm_data__ok, alu_op__imm_data__data, alu_op__fn_unit, alu_op__insn_type }; assign \muxid$1 = muxid; assign cr_a_ok = alu_op__write_cr0; - assign \cr_a$22 = cr0; - assign \o_ok$21 = o_ok; - assign \o$20 = \o$28 [63:0]; - assign is_positive = \$43 ; + assign \cr_a$26 = cr0; + assign \o_ok$25 = o_ok; + assign \o$24 = \o$32 [63:0]; + assign is_positive = \$49 ; assign is_negative = msb_test; - assign is_nzero = \$39 ; + assign is_nzero = \$45 ; assign msb_test = target[63]; - assign is_cmpeqb = \$37 ; - assign is_cmp = \$35 ; + assign is_cmpeqb = \$43 ; + assign is_cmp = \$41 ; assign xer_ca_ok = alu_op__output_carry; - assign \xer_ca$23 = xer_ca; - assign target = \o$28 [63:0]; - assign oe = \$26 ; + assign \xer_ca$27 = xer_ca; + assign target = \o$32 [63:0]; + assign oe = \$30 ; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.output" *) (* generator = "nMigen" *) -module \output$100 (mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, o, o_ok, cr_a, xer_ov, xer_so, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \o$14 , \o_ok$15 , \cr_a$16 , cr_a_ok, \xer_ov$17 , xer_ov_ok, \xer_so$18 , xer_so_ok, muxid); +module \output$100 (mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, mul_op__sv_pred_sz, mul_op__sv_pred_dz, mul_op__sv_saturate, mul_op__SV_Ptype, o, o_ok, cr_a, xer_ov, xer_so, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \mul_op__sv_pred_sz$14 , \mul_op__sv_pred_dz$15 , \mul_op__sv_saturate$16 , \mul_op__SV_Ptype$17 , \o$18 , \o_ok$19 , \cr_a$20 , cr_a_ok, \xer_ov$21 , xer_ov_ok, \xer_so$22 , xer_so_ok, muxid); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *) - wire \$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [64:0] \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) - wire \$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *) + wire \$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *) wire \$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *) - wire \$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [64:0] \$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" *) wire \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:80" *) wire \$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) wire \$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) wire \$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) + wire \$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *) + wire \$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:90" *) + wire \$42 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" *) - wire \$39 ; + wire \$45 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" *) - wire \$41 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" *) + wire \$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:73" *) reg [3:0] cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [3:0] \cr_a$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [3:0] \cr_a$20 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" *) wire is_cmp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" *) wire is_cmpeqb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" *) wire is_negative; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" *) wire is_nzero; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" *) - wire is_positive; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" *) + wire is_positive; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" *) wire msb_test; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] mul_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \mul_op__SV_Ptype$17 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] mul_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] mul_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \mul_op__fn_unit$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \mul_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] mul_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \mul_op__imm_data__data$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__imm_data__ok$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] mul_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \mul_op__insn$13 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -159679,7 +171046,9 @@ module \output$100 (mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] mul_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -159756,85 +171125,108 @@ module \output$100 (mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] \mul_op__insn_type$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__is_32bit$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__is_signed$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__oe__oe$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__oe__ok$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__rc__ok$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__rc__rc$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input mul_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \mul_op__sv_pred_dz$15 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input mul_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \mul_op__sv_pred_sz$14 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] mul_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \mul_op__sv_saturate$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input mul_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \mul_op__write_cr0$10 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] \muxid$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [63:0] \o$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" *) - wire [64:0] \o$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [63:0] \o$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:39" *) + reg [64:0] \o$25 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \o_ok$15 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \o_ok$19 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" *) wire oe; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" *) - wire \oe$38 ; + wire \oe$44 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" *) reg so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52" *) wire [63:0] target; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [1:0] xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [1:0] \xer_ov$17 ; - reg [1:0] \xer_ov$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [1:0] \xer_ov$21 ; + reg [1:0] \xer_ov$21 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ov_ok; reg xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \xer_so$18 ; - reg \xer_so$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \xer_so$22 ; + reg \xer_so$22 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_so_ok; reg xer_so_ok; - assign \$19 = mul_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *) mul_op__oe__ok; - assign \$22 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) o; - assign \$24 = mul_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) 7'h0a; - assign \$26 = mul_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *) 7'h0c; - assign \$28 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *) target; - assign \$30 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) msb_test; - assign \$32 = is_nzero & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) \$30 ; - assign \$34 = is_cmpeqb | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) is_cmp; - assign \$36 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" *) is_nzero; - assign \$39 = mul_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" *) mul_op__oe__ok; - assign \$41 = xer_so | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" *) xer_ov[0]; + assign \$23 = mul_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *) mul_op__oe__ok; + assign \$26 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *) mul_op__sv_pred_dz; + assign \$28 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) o; + assign \$30 = mul_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" *) 7'h0a; + assign \$32 = mul_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:80" *) 7'h0c; + assign \$34 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) target; + assign \$36 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) msb_test; + assign \$38 = is_nzero & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) \$36 ; + assign \$40 = is_cmpeqb | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *) is_cmp; + assign \$42 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:90" *) is_nzero; + assign \$45 = mul_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" *) mul_op__oe__ok; + assign \$47 = xer_so | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" *) xer_ov[0]; always @* begin if (\initial ) begin end (* full_case = 32'd1 *) @@ -159842,7 +171234,7 @@ module \output$100 (mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, casez (oe) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" */ 1'h1: - so = \xer_so$18 ; + so = \xer_so$22 ; /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:32" */ default: so = xer_so; @@ -159851,31 +171243,41 @@ module \output$100 (mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) - casez (\$34 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *) + casez (\$40 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" */ 1'h1: cr0 = cr_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:89" */ default: - cr0 = { is_negative, is_positive, \$36 , so }; + cr0 = { is_negative, is_positive, \$42 , so }; endcase end always @* begin if (\initial ) begin end - \xer_so$18 = 1'h0; + \o$25 = 65'h00000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *) + casez (\$26 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" */ + 1'h1: + \o$25 = \$28 ; + endcase + end + always @* begin + if (\initial ) begin end + \xer_so$22 = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *) - casez (\oe$38 ) + casez (\oe$44 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */ 1'h1: - \xer_so$18 = \$41 ; + \xer_so$22 = \$47 ; endcase end always @* begin if (\initial ) begin end xer_so_ok = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *) - casez (\oe$38 ) + casez (\oe$44 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */ 1'h1: xer_so_ok = 1'h1; @@ -159883,157 +171285,172 @@ module \output$100 (mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, end always @* begin if (\initial ) begin end - \xer_ov$17 = 2'h0; + \xer_ov$21 = 2'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *) - casez (\oe$38 ) + casez (\oe$44 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */ 1'h1: - \xer_ov$17 = xer_ov; + \xer_ov$21 = xer_ov; endcase end always @* begin if (\initial ) begin end xer_ov_ok = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *) - casez (\oe$38 ) + casez (\oe$44 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */ 1'h1: xer_ov_ok = 1'h1; endcase end - assign \oe$38 = \$39 ; - assign { \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2 } = { mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type }; + assign \oe$44 = \$45 ; + assign { \mul_op__SV_Ptype$17 , \mul_op__sv_saturate$16 , \mul_op__sv_pred_dz$15 , \mul_op__sv_pred_sz$14 , \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2 } = { mul_op__SV_Ptype, mul_op__sv_saturate, mul_op__sv_pred_dz, mul_op__sv_pred_sz, mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type }; assign \muxid$1 = muxid; assign cr_a_ok = mul_op__write_cr0; - assign \cr_a$16 = cr0; - assign \o_ok$15 = o_ok; - assign \o$14 = \o$21 [63:0]; - assign is_positive = \$32 ; + assign \cr_a$20 = cr0; + assign \o_ok$19 = o_ok; + assign \o$18 = \o$25 [63:0]; + assign is_positive = \$38 ; assign is_negative = msb_test; - assign is_nzero = \$28 ; + assign is_nzero = \$34 ; assign msb_test = target[63]; - assign is_cmpeqb = \$26 ; - assign is_cmp = \$24 ; - assign target = \o$21 [63:0]; - assign \o$21 = \$22 ; - assign oe = \$19 ; + assign is_cmpeqb = \$32 ; + assign is_cmp = \$30 ; + assign target = \o$25 [63:0]; + assign oe = \$23 ; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.output" *) (* generator = "nMigen" *) -module \output$118 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, o, o_ok, cr_a, xer_so, xer_ca, \muxid$1 , \sr_op__insn_type$2 , \sr_op__fn_unit$3 , \sr_op__imm_data__data$4 , \sr_op__imm_data__ok$5 , \sr_op__rc__rc$6 , \sr_op__rc__ok$7 , \sr_op__oe__oe$8 , \sr_op__oe__ok$9 , \sr_op__write_cr0$10 , \sr_op__invert_in$11 , \sr_op__input_carry$12 , \sr_op__output_carry$13 , \sr_op__input_cr$14 , \sr_op__output_cr$15 , \sr_op__is_32bit$16 , \sr_op__is_signed$17 , \sr_op__insn$18 , \o$19 , \o_ok$20 , \cr_a$21 , cr_a_ok, \xer_ca$22 , xer_ca_ok, muxid); +module \output$118 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, sr_op__sv_pred_sz, sr_op__sv_pred_dz, sr_op__sv_saturate, sr_op__SV_Ptype, o, o_ok, cr_a, xer_so, xer_ca, \muxid$1 , \sr_op__insn_type$2 , \sr_op__fn_unit$3 , \sr_op__imm_data__data$4 , \sr_op__imm_data__ok$5 , \sr_op__rc__rc$6 , \sr_op__rc__ok$7 , \sr_op__oe__oe$8 , \sr_op__oe__ok$9 , \sr_op__write_cr0$10 , \sr_op__invert_in$11 , \sr_op__input_carry$12 , \sr_op__output_carry$13 , \sr_op__input_cr$14 , \sr_op__output_cr$15 , \sr_op__is_32bit$16 , \sr_op__is_signed$17 , \sr_op__insn$18 , \sr_op__sv_pred_sz$19 , \sr_op__sv_pred_dz$20 , \sr_op__sv_saturate$21 , \sr_op__SV_Ptype$22 , \o$23 , \o_ok$24 , \cr_a$25 , cr_a_ok, \xer_ca$26 , xer_ca_ok, muxid); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [64:0] \$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) - wire \$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *) wire \$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *) - wire \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [64:0] \$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" *) wire \$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:80" *) wire \$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) wire \$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) wire \$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) + wire \$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *) + wire \$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:90" *) + wire \$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:73" *) reg [3:0] cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [3:0] \cr_a$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [3:0] \cr_a$25 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" *) wire is_cmp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" *) wire is_cmpeqb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" *) wire is_negative; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" *) wire is_nzero; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" *) - wire is_positive; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" *) + wire is_positive; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" *) wire msb_test; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] \muxid$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [63:0] \o$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" *) - wire [64:0] \o$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [63:0] \o$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:39" *) + reg [64:0] \o$27 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \o_ok$20 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \o_ok$24 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] sr_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \sr_op__SV_Ptype$22 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] sr_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] sr_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \sr_op__fn_unit$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \sr_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] sr_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \sr_op__imm_data__data$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__imm_data__ok$5 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] sr_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [1:0] \sr_op__input_carry$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__input_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__input_cr$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] sr_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \sr_op__insn$18 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -160110,7 +171527,9 @@ module \output$118 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] sr_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -160187,200 +171606,248 @@ module \output$118 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] \sr_op__insn_type$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__invert_in$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__is_32bit$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__is_signed$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__oe__oe$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__oe__ok$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__output_carry$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__output_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__output_cr$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__rc__ok$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__rc__rc$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input sr_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \sr_op__sv_pred_dz$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input sr_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \sr_op__sv_pred_sz$19 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] sr_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \sr_op__sv_saturate$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__write_cr0$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52" *) wire [63:0] target; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [1:0] xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [1:0] \xer_ca$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [1:0] \xer_ca$26 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input xer_so; - assign \$24 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) o; - assign \$26 = sr_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) 7'h0a; - assign \$28 = sr_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *) 7'h0c; - assign \$30 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *) target; - assign \$32 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) msb_test; - assign \$34 = is_nzero & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) \$32 ; - assign \$36 = is_cmpeqb | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) is_cmp; - assign \$38 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" *) is_nzero; + assign \$28 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *) sr_op__sv_pred_dz; + assign \$30 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) o; + assign \$32 = sr_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" *) 7'h0a; + assign \$34 = sr_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:80" *) 7'h0c; + assign \$36 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) target; + assign \$38 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) msb_test; + assign \$40 = is_nzero & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) \$38 ; + assign \$42 = is_cmpeqb | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *) is_cmp; + assign \$44 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:90" *) is_nzero; + always @* begin + if (\initial ) begin end + \o$27 = 65'h00000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *) + casez (\$28 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" */ + 1'h1: + \o$27 = \$30 ; + endcase + end always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) - casez (\$36 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *) + casez (\$42 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" */ 1'h1: cr0 = cr_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:89" */ default: - cr0 = { is_negative, is_positive, \$38 , xer_so }; + cr0 = { is_negative, is_positive, \$44 , xer_so }; endcase end - assign { \sr_op__insn$18 , \sr_op__is_signed$17 , \sr_op__is_32bit$16 , \sr_op__output_cr$15 , \sr_op__input_cr$14 , \sr_op__output_carry$13 , \sr_op__input_carry$12 , \sr_op__invert_in$11 , \sr_op__write_cr0$10 , \sr_op__oe__ok$9 , \sr_op__oe__oe$8 , \sr_op__rc__ok$7 , \sr_op__rc__rc$6 , \sr_op__imm_data__ok$5 , \sr_op__imm_data__data$4 , \sr_op__fn_unit$3 , \sr_op__insn_type$2 } = { sr_op__insn, sr_op__is_signed, sr_op__is_32bit, sr_op__output_cr, sr_op__input_cr, sr_op__output_carry, sr_op__input_carry, sr_op__invert_in, sr_op__write_cr0, sr_op__oe__ok, sr_op__oe__oe, sr_op__rc__ok, sr_op__rc__rc, sr_op__imm_data__ok, sr_op__imm_data__data, sr_op__fn_unit, sr_op__insn_type }; + assign { \sr_op__SV_Ptype$22 , \sr_op__sv_saturate$21 , \sr_op__sv_pred_dz$20 , \sr_op__sv_pred_sz$19 , \sr_op__insn$18 , \sr_op__is_signed$17 , \sr_op__is_32bit$16 , \sr_op__output_cr$15 , \sr_op__input_cr$14 , \sr_op__output_carry$13 , \sr_op__input_carry$12 , \sr_op__invert_in$11 , \sr_op__write_cr0$10 , \sr_op__oe__ok$9 , \sr_op__oe__oe$8 , \sr_op__rc__ok$7 , \sr_op__rc__rc$6 , \sr_op__imm_data__ok$5 , \sr_op__imm_data__data$4 , \sr_op__fn_unit$3 , \sr_op__insn_type$2 } = { sr_op__SV_Ptype, sr_op__sv_saturate, sr_op__sv_pred_dz, sr_op__sv_pred_sz, sr_op__insn, sr_op__is_signed, sr_op__is_32bit, sr_op__output_cr, sr_op__input_cr, sr_op__output_carry, sr_op__input_carry, sr_op__invert_in, sr_op__write_cr0, sr_op__oe__ok, sr_op__oe__oe, sr_op__rc__ok, sr_op__rc__rc, sr_op__imm_data__ok, sr_op__imm_data__data, sr_op__fn_unit, sr_op__insn_type }; assign \muxid$1 = muxid; assign cr_a_ok = sr_op__write_cr0; - assign \cr_a$21 = cr0; - assign \o_ok$20 = o_ok; - assign \o$19 = \o$23 [63:0]; - assign is_positive = \$34 ; + assign \cr_a$25 = cr0; + assign \o_ok$24 = o_ok; + assign \o$23 = \o$27 [63:0]; + assign is_positive = \$40 ; assign is_negative = msb_test; - assign is_nzero = \$30 ; + assign is_nzero = \$36 ; assign msb_test = target[63]; - assign is_cmpeqb = \$28 ; - assign is_cmp = \$26 ; + assign is_cmpeqb = \$34 ; + assign is_cmp = \$32 ; assign xer_ca_ok = sr_op__output_carry; - assign \xer_ca$22 = xer_ca; - assign target = \o$23 [63:0]; - assign \o$23 = \$24 ; + assign \xer_ca$26 = xer_ca; + assign target = \o$27 [63:0]; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.output" *) (* generator = "nMigen" *) -module \output$54 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, o, o_ok, cr_a, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \o$20 , \o_ok$21 , \cr_a$22 , cr_a_ok, muxid); +module \output$54 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__SV_Ptype, o, o_ok, cr_a, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__SV_Ptype$23 , \o$24 , \o_ok$25 , \cr_a$26 , cr_a_ok, muxid); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) - wire [64:0] \$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) - wire [63:0] \$25 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [64:0] \$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) - wire \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *) - wire \$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *) - wire \$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *) + wire \$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" *) + wire [64:0] \$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" *) + wire [63:0] \$31 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [64:0] \$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" *) wire \$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:80" *) wire \$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) wire \$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) wire \$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) + wire \$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *) + wire \$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:90" *) + wire \$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:73" *) reg [3:0] cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [3:0] \cr_a$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [3:0] \cr_a$26 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" *) wire is_cmp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" *) wire is_cmpeqb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" *) wire is_negative; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" *) wire is_nzero; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" *) wire is_positive; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] logical_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \logical_op__SV_Ptype$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [3:0] logical_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [3:0] \logical_op__data_len$18 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] logical_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] logical_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \logical_op__fn_unit$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \logical_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] logical_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \logical_op__imm_data__data$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__imm_data__ok$5 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] logical_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [1:0] \logical_op__input_carry$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] logical_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \logical_op__insn$19 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -160457,7 +171924,9 @@ module \output$54 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_d (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] logical_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -160534,232 +172003,277 @@ module \output$54 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_d (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] \logical_op__insn_type$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__invert_in$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__invert_out$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__is_32bit$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__is_signed$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__oe__oe$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__oe__ok$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__output_carry$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__rc__ok$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__rc__rc$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input logical_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \logical_op__sv_pred_dz$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input logical_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \logical_op__sv_pred_sz$20 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] logical_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \logical_op__sv_saturate$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__write_cr0$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__zero_a$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" *) wire msb_test; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] \muxid$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [63:0] \o$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" *) - reg [64:0] \o$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [63:0] \o$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:39" *) + reg [64:0] \o$27 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \o_ok$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \o_ok$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52" *) wire [63:0] target; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input xer_so; - assign \$25 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) o; - assign \$24 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) \$25 ; - assign \$28 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) o; - assign \$30 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) 7'h0a; - assign \$32 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *) 7'h0c; - assign \$34 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *) target; - assign \$36 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) msb_test; - assign \$38 = is_nzero & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) \$36 ; - assign \$40 = is_cmpeqb | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) is_cmp; - assign \$42 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" *) is_nzero; - always @* begin - if (\initial ) begin end - (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" *) - casez (logical_op__invert_out) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" */ + assign \$28 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *) logical_op__sv_pred_dz; + assign \$31 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" *) o; + assign \$30 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" *) \$31 ; + assign \$34 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) o; + assign \$36 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" *) 7'h0a; + assign \$38 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:80" *) 7'h0c; + assign \$40 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) target; + assign \$42 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) msb_test; + assign \$44 = is_nzero & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) \$42 ; + assign \$46 = is_cmpeqb | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *) is_cmp; + assign \$48 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:90" *) is_nzero; + always @* begin + if (\initial ) begin end + \o$27 = 65'h00000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *) + casez (\$28 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" */ 1'h1: - \o$23 = \$24 ; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" */ - default: - \o$23 = \$28 ; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) + casez (logical_op__invert_out) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" */ + 1'h1: + \o$27 = \$30 ; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:43" */ + default: + \o$27 = \$34 ; + endcase endcase end always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) - casez (\$40 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *) + casez (\$46 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" */ 1'h1: cr0 = cr_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:89" */ default: - cr0 = { is_negative, is_positive, \$42 , xer_so }; + cr0 = { is_negative, is_positive, \$48 , xer_so }; endcase end - assign { \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; + assign { \logical_op__SV_Ptype$23 , \logical_op__sv_saturate$22 , \logical_op__sv_pred_dz$21 , \logical_op__sv_pred_sz$20 , \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__SV_Ptype, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; assign \muxid$1 = muxid; assign cr_a_ok = logical_op__write_cr0; - assign \cr_a$22 = cr0; - assign \o_ok$21 = o_ok; - assign \o$20 = \o$23 [63:0]; - assign is_positive = \$38 ; + assign \cr_a$26 = cr0; + assign \o_ok$25 = o_ok; + assign \o$24 = \o$27 [63:0]; + assign is_positive = \$44 ; assign is_negative = msb_test; - assign is_nzero = \$34 ; + assign is_nzero = \$40 ; assign msb_test = target[63]; - assign is_cmpeqb = \$32 ; - assign is_cmp = \$30 ; - assign target = \o$23 [63:0]; + assign is_cmpeqb = \$38 ; + assign is_cmp = \$36 ; + assign target = \o$27 [63:0]; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.output" *) (* generator = "nMigen" *) -module \output$83 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, o, o_ok, cr_a, xer_ov, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \o$20 , \o_ok$21 , \cr_a$22 , cr_a_ok, \xer_ov$23 , xer_ov_ok, \xer_so$24 , xer_so_ok, muxid); +module \output$83 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__SV_Ptype, o, o_ok, cr_a, xer_ov, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__SV_Ptype$23 , \o$24 , \o_ok$25 , \cr_a$26 , cr_a_ok, \xer_ov$27 , xer_ov_ok, \xer_so$28 , xer_so_ok, muxid); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *) - wire \$25 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) - wire [64:0] \$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) - wire [63:0] \$29 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [64:0] \$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) - wire \$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *) - wire \$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *) - wire \$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) + wire \$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *) + wire \$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" *) + wire [64:0] \$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" *) + wire [63:0] \$35 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [64:0] \$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" *) wire \$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:80" *) wire \$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) wire \$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) wire \$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) + wire \$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *) + wire \$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:90" *) + wire \$52 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" *) - wire \$49 ; + wire \$55 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" *) - wire \$51 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" *) + wire \$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:73" *) reg [3:0] cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [3:0] \cr_a$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [3:0] \cr_a$26 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" *) wire is_cmp; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" *) wire is_cmpeqb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" *) wire is_negative; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" *) wire is_nzero; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" *) wire is_positive; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] logical_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \logical_op__SV_Ptype$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [3:0] logical_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [3:0] \logical_op__data_len$18 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] logical_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] logical_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \logical_op__fn_unit$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \logical_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] logical_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \logical_op__imm_data__data$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__imm_data__ok$5 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] logical_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [1:0] \logical_op__input_carry$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] logical_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \logical_op__insn$19 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -160836,7 +172350,9 @@ module \output$83 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_d (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] logical_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -160913,105 +172429,128 @@ module \output$83 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_d (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] \logical_op__insn_type$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__invert_in$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__invert_out$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__is_32bit$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__is_signed$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__oe__oe$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__oe__ok$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__output_carry$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__rc__ok$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__rc__rc$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input logical_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \logical_op__sv_pred_dz$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input logical_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \logical_op__sv_pred_sz$20 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] logical_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \logical_op__sv_saturate$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__write_cr0$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__zero_a$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" *) wire msb_test; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] \muxid$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [63:0] \o$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" *) - reg [64:0] \o$27 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [63:0] \o$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:39" *) + reg [64:0] \o$31 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \o_ok$21 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \o_ok$25 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" *) wire oe; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" *) - wire \oe$48 ; + wire \oe$54 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" *) reg so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52" *) wire [63:0] target; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [1:0] xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [1:0] \xer_ov$23 ; - reg [1:0] \xer_ov$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [1:0] \xer_ov$27 ; + reg [1:0] \xer_ov$27 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ov_ok; reg xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \xer_so$24 ; - reg \xer_so$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \xer_so$28 ; + reg \xer_so$28 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_so_ok; reg xer_so_ok; - assign \$25 = logical_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *) logical_op__oe__ok; - assign \$29 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) o; - assign \$28 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) \$29 ; - assign \$32 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) o; - assign \$34 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) 7'h0a; - assign \$36 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *) 7'h0c; - assign \$38 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *) target; - assign \$40 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) msb_test; - assign \$42 = is_nzero & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) \$40 ; - assign \$44 = is_cmpeqb | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) is_cmp; - assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" *) is_nzero; - assign \$49 = logical_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" *) logical_op__oe__ok; - assign \$51 = xer_so | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" *) xer_ov[0]; + assign \$29 = logical_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *) logical_op__oe__ok; + assign \$32 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *) logical_op__sv_pred_dz; + assign \$35 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" *) o; + assign \$34 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" *) \$35 ; + assign \$38 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) o; + assign \$40 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" *) 7'h0a; + assign \$42 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:80" *) 7'h0c; + assign \$44 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) target; + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) msb_test; + assign \$48 = is_nzero & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) \$46 ; + assign \$50 = is_cmpeqb | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *) is_cmp; + assign \$52 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:90" *) is_nzero; + assign \$55 = logical_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" *) logical_op__oe__ok; + assign \$57 = xer_so | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" *) xer_ov[0]; always @* begin if (\initial ) begin end (* full_case = 32'd1 *) @@ -161019,7 +172558,7 @@ module \output$83 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_d casez (oe) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" */ 1'h1: - so = \xer_so$24 ; + so = \xer_so$28 ; /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:32" */ default: so = xer_so; @@ -161028,44 +172567,50 @@ module \output$83 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_d always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) - casez (\$44 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" *) + casez (\$50 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" */ 1'h1: cr0 = cr_a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:89" */ default: - cr0 = { is_negative, is_positive, \$46 , so }; + cr0 = { is_negative, is_positive, \$52 , so }; endcase end always @* begin if (\initial ) begin end - (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" *) - casez (logical_op__invert_out) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" */ + \o$31 = 65'h00000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" *) + casez (\$32 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:37" */ 1'h1: - \o$27 = \$28 ; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" */ - default: - \o$27 = \$32 ; + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) + casez (logical_op__invert_out) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" */ + 1'h1: + \o$31 = \$34 ; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:43" */ + default: + \o$31 = \$38 ; + endcase endcase end always @* begin if (\initial ) begin end - \xer_so$24 = 1'h0; + \xer_so$28 = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *) - casez (\oe$48 ) + casez (\oe$54 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */ 1'h1: - \xer_so$24 = \$51 ; + \xer_so$28 = \$57 ; endcase end always @* begin if (\initial ) begin end xer_so_ok = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *) - casez (\oe$48 ) + casez (\oe$54 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */ 1'h1: xer_so_ok = 1'h1; @@ -161073,83 +172618,83 @@ module \output$83 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_d end always @* begin if (\initial ) begin end - \xer_ov$23 = 2'h0; + \xer_ov$27 = 2'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *) - casez (\oe$48 ) + casez (\oe$54 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */ 1'h1: - \xer_ov$23 = xer_ov; + \xer_ov$27 = xer_ov; endcase end always @* begin if (\initial ) begin end xer_ov_ok = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *) - casez (\oe$48 ) + casez (\oe$54 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" */ 1'h1: xer_ov_ok = 1'h1; endcase end - assign \oe$48 = \$49 ; - assign { \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; + assign \oe$54 = \$55 ; + assign { \logical_op__SV_Ptype$23 , \logical_op__sv_saturate$22 , \logical_op__sv_pred_dz$21 , \logical_op__sv_pred_sz$20 , \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__SV_Ptype, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; assign \muxid$1 = muxid; assign cr_a_ok = logical_op__write_cr0; - assign \cr_a$22 = cr0; - assign \o_ok$21 = o_ok; - assign \o$20 = \o$27 [63:0]; - assign is_positive = \$42 ; + assign \cr_a$26 = cr0; + assign \o_ok$25 = o_ok; + assign \o$24 = \o$31 [63:0]; + assign is_positive = \$48 ; assign is_negative = msb_test; - assign is_nzero = \$38 ; + assign is_nzero = \$44 ; assign msb_test = target[63]; - assign is_cmpeqb = \$36 ; - assign is_cmp = \$34 ; - assign target = \o$27 [63:0]; - assign oe = \$25 ; + assign is_cmpeqb = \$42 ; + assign is_cmp = \$40 ; + assign target = \o$31 [63:0]; + assign oe = \$29 ; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.output_stage" *) (* generator = "nMigen" *) -module output_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, xer_so, divisor_neg, dividend_neg, dive_abs_ov32, dive_abs_ov64, div_by_zero, quotient_root, remainder, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , o, o_ok, xer_ov, xer_ov_ok, \xer_so$20 , muxid); +module output_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__SV_Ptype, xer_so, divisor_neg, dividend_neg, dive_abs_ov32, dive_abs_ov64, div_by_zero, quotient_root, remainder, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__SV_Ptype$23 , o, o_ok, xer_ov, xer_ov_ok, \xer_so$24 , muxid); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" *) - wire \$21 ; + wire \$25 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" *) - wire [64:0] \$23 ; + wire [64:0] \$27 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" *) - wire [64:0] \$25 ; + wire [64:0] \$29 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" *) - wire [64:0] \$27 ; + wire [64:0] \$31 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" *) - wire [64:0] \$29 ; + wire [64:0] \$33 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" *) - wire [64:0] \$30 ; + wire [64:0] \$34 ; (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) - wire [64:0] \$32 ; + wire [64:0] \$36 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" *) - wire [64:0] \$34 ; + wire [64:0] \$38 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" *) - wire \$36 ; + wire \$40 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" *) - wire \$38 ; + wire \$42 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" *) - wire \$40 ; + wire \$44 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" *) - wire \$42 ; + wire \$46 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" *) - wire [63:0] \$44 ; + wire [63:0] \$48 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" *) - wire \$46 ; + wire \$50 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" *) - wire [63:0] \$48 ; + wire [63:0] \$52 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" *) - wire [63:0] \$50 ; + wire [63:0] \$54 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" *) - wire [63:0] \$52 ; + wire [63:0] \$56 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" *) - wire [63:0] \$54 ; + wire [63:0] \$58 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" *) - wire [63:0] \$56 ; + wire [63:0] \$60 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) input div_by_zero; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *) @@ -161160,67 +172705,81 @@ module output_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_ input dividend_neg; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *) input divisor_neg; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] logical_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \logical_op__SV_Ptype$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [3:0] logical_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [3:0] \logical_op__data_len$18 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] logical_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] logical_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \logical_op__fn_unit$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \logical_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] logical_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \logical_op__imm_data__data$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__imm_data__ok$5 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] logical_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [1:0] \logical_op__input_carry$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] logical_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \logical_op__insn$19 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -161297,7 +172856,9 @@ module output_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] logical_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -161374,60 +172935,82 @@ module output_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] \logical_op__insn_type$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__invert_in$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__invert_out$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__is_32bit$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__is_signed$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__oe__oe$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__oe__ok$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__output_carry$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__rc__ok$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__rc__rc$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input logical_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \logical_op__sv_pred_dz$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input logical_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \logical_op__sv_pred_sz$20 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] logical_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \logical_op__sv_saturate$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__write_cr0$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__zero_a$11 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] \muxid$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] o; reg [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output o_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:75" *) reg ov; @@ -161447,37 +173030,37 @@ module output_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_ wire [31:0] remainder_s32; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:99" *) wire [63:0] remainder_s32_as_s64; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [1:0] xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \xer_so$20 ; - assign \$21 = dividend_neg ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" *) divisor_neg; - assign \$23 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" *) quotient_root; - assign \$25 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" *) quotient_root; - assign \$27 = quotient_neg ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" *) \$23 : \$25 ; - assign \$30 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" *) remainder[127:64]; - assign \$32 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) remainder[127:64]; - assign \$34 = remainder_neg ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" *) \$30 : \$32 ; - assign \$36 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" *) logical_op__is_32bit; - assign \$38 = quotient_65[64] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" *) quotient_65[63]; - assign \$40 = logical_op__is_signed & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" *) \$38 ; - assign \$42 = quotient_65[32] != (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" *) quotient_65[31]; - assign \$44 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" *) $signed(remainder_s32); - assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" *) ov; - assign \$48 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" *) quotient_65[31:0]; - assign \$50 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" *) quotient_65[31:0]; - assign \$52 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" *) quotient_65[31:0]; - assign \$54 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" *) quotient_65[31:0]; - assign \$56 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" *) remainder_64[31:0]; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \xer_so$24 ; + assign \$25 = dividend_neg ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" *) divisor_neg; + assign \$27 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" *) quotient_root; + assign \$29 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" *) quotient_root; + assign \$31 = quotient_neg ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" *) \$27 : \$29 ; + assign \$34 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" *) remainder[127:64]; + assign \$36 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) remainder[127:64]; + assign \$38 = remainder_neg ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" *) \$34 : \$36 ; + assign \$40 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" *) logical_op__is_32bit; + assign \$42 = quotient_65[64] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" *) quotient_65[63]; + assign \$44 = logical_op__is_signed & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" *) \$42 ; + assign \$46 = quotient_65[32] != (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" *) quotient_65[31]; + assign \$48 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" *) $signed(remainder_s32); + assign \$50 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" *) ov; + assign \$52 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" *) quotient_65[31:0]; + assign \$54 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" *) quotient_65[31:0]; + assign \$56 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" *) quotient_65[31:0]; + assign \$58 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" *) quotient_65[31:0]; + assign \$60 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" *) remainder_64[31:0]; always @* begin if (\initial ) begin end o = 64'h0000000000000000; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" *) - casez (\$46 ) + casez (\$50 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" */ 1'h1: (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:103" *) @@ -161495,10 +173078,10 @@ module output_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_ casez (logical_op__is_signed) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:106" */ 1'h1: - o = \$48 ; + o = \$52 ; /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:109" */ default: - o = \$50 ; + o = \$54 ; endcase /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:111" */ default: @@ -161517,10 +173100,10 @@ module output_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_ casez (logical_op__is_signed) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:115" */ 1'h1: - o = \$52 ; + o = \$56 ; /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:118" */ default: - o = \$54 ; + o = \$58 ; endcase /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:120" */ default: @@ -161542,7 +173125,7 @@ module output_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_ o = remainder_s32_as_s64; /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:127" */ default: - o = \$56 ; + o = \$60 ; endcase /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:129" */ default: @@ -161555,7 +173138,7 @@ module output_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_ if (\initial ) begin end (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76" *) - casez ({ logical_op__is_signed, \$36 , div_by_zero }) + casez ({ logical_op__is_signed, \$40 , div_by_zero }) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76" */ 3'b??1: ov = 1'h1; @@ -161564,7 +173147,7 @@ module output_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_ begin ov = dive_abs_ov64; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" *) - casez (\$40 ) + casez (\$44 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" */ 1'h1: ov = 1'h1; @@ -161575,7 +173158,7 @@ module output_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_ begin ov = dive_abs_ov32; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" *) - casez (\$42 ) + casez (\$46 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" */ 1'h1: ov = 1'h1; @@ -161586,19 +173169,19 @@ module output_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_ ov = dive_abs_ov32; endcase end - assign \$29 = \$34 ; - assign { \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; + assign \$33 = \$38 ; + assign { \logical_op__SV_Ptype$23 , \logical_op__sv_saturate$22 , \logical_op__sv_pred_dz$21 , \logical_op__sv_pred_sz$20 , \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__SV_Ptype, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; assign \muxid$1 = muxid; - assign \xer_so$20 = xer_so; - assign remainder_s32_as_s64 = \$44 ; + assign \xer_so$24 = xer_so; + assign remainder_s32_as_s64 = \$48 ; assign remainder_s32 = remainder_64[31:0]; assign o_ok = 1'h1; assign xer_ov = { ov, ov }; assign xer_ov_ok = 1'h1; - assign remainder_64 = \$34 [63:0]; - assign quotient_65 = \$27 ; + assign remainder_64 = \$38 [63:0]; + assign quotient_65 = \$31 ; assign remainder_neg = dividend_neg; - assign quotient_neg = \$21 ; + assign quotient_neg = \$25 ; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.alu_alu0.p" *) @@ -162022,11 +173605,11 @@ endmodule (* generator = "nMigen" *) module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_busy_o, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, x_mask_i, x_addr_i, ldst_port0_addr_ok_o, m_ld_data_o, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i_ok, ldst_port0_st_data_i, x_st_data_i, x_busy_o, \ldst_port0_exc_$signal , x_ld_i, x_st_i, m_valid_i, x_valid_i, coresync_clk); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:278" *) wire \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:220" *) wire \$11 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:226" *) wire \$13 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$15 ; @@ -162034,55 +173617,55 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu wire \$17 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$19 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) - wire [3:0] \$21 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$21 ; (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) wire [3:0] \$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) - wire \$25 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) + wire [3:0] \$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" *) wire \$27 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" *) wire \$29 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:234" *) wire \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" *) wire \$31 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" *) wire \$33 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:270" *) wire \$35 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" *) wire \$37 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" *) - wire \$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" *) - wire [175:0] \$41 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257" *) - wire [175:0] \$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" *) - wire [7:0] \$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" *) - wire [175:0] \$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" *) - wire \$48 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224" *) + wire \$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" *) + wire \$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:269" *) + wire [175:0] \$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:268" *) + wire [175:0] \$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:269" *) + wire [7:0] \$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:269" *) + wire [175:0] \$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:235" *) wire \$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:270" *) wire \$50 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:270" *) wire \$52 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" *) wire \$54 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" *) - wire [318:0] \$56 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" *) - wire [7:0] \$57 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" *) - wire [318:0] \$59 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" *) - wire \$61 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:278" *) + wire \$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:282" *) + wire [318:0] \$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:282" *) + wire [7:0] \$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:282" *) + wire [318:0] \$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:278" *) wire \$63 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *) wire \$65 ; @@ -162090,23 +173673,25 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu wire \$67 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *) wire \$69 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" *) wire \$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *) wire \$71 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" *) wire \$73 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" *) wire \$75 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" *) wire \$77 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" *) wire \$79 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" *) wire \$81 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$83 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) + wire \$85 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:220" *) wire \$9 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire adrok_l_q_addr_acked; @@ -162118,11 +173703,11 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu reg adrok_l_s_addr_acked = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) reg \adrok_l_s_addr_acked$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:213" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" *) reg busy_delay = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:213" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" *) reg \busy_delay$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:214" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:218" *) wire busy_edge; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire busy_l_q_busy; @@ -162130,9 +173715,9 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu reg busy_l_r_busy; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) reg busy_l_s_busy; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire cyc_l_q_cyc; @@ -162150,9 +173735,9 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu reg ld_active_r_ld_active; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire ld_active_s_ld_active; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:255" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:266" *) wire [63:0] lddata; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:206" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:209" *) wire lds; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) reg lds_dly = 1'h0; @@ -162160,32 +173745,32 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu wire \lds_dly$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) wire lds_rise; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [47:0] ldst_port0_addr_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input ldst_port0_addr_i_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" *) output ldst_port0_addr_ok_o; reg ldst_port0_addr_ok_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" *) output ldst_port0_busy_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103" *) input [3:0] ldst_port0_data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) input \ldst_port0_exc_$signal ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" *) - input ldst_port0_is_ld_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *) + input ldst_port0_is_ld_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:100" *) input ldst_port0_is_st_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] ldst_port0_ld_data_o; reg [63:0] ldst_port0_ld_data_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output ldst_port0_ld_data_o_ok; reg ldst_port0_ld_data_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [63:0] ldst_port0_st_data_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input ldst_port0_st_data_i_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131" *) reg [3:0] lenexp_addr_i; @@ -162209,9 +173794,11 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu input [63:0] m_ld_data_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:61" *) output m_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:280" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:225" *) + wire misalign; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:291" *) reg reset_delay = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:280" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:291" *) wire \reset_delay$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire reset_l_q_reset; @@ -162233,9 +173820,9 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu reg st_done_s_st_done = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) reg \st_done_s_st_done$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:270" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:281" *) reg [63:0] stdata; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210" *) wire sts; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) reg sts_dly = 1'h0; @@ -162266,47 +173853,48 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu output x_st_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" *) output x_valid_i; - assign \$9 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" *) busy_delay; - assign \$11 = ldst_port0_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" *) \$9 ; - assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) lds_dly; - assign \$15 = lds & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$13 ; - assign \$17 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) sts_dly; - assign \$1 = st_active_q_st_active & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" *) ldst_port0_st_data_i_ok; - assign \$19 = sts & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$17 ; - assign \$21 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) ldst_port0_addr_i[2:0]; + assign \$9 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:220" *) busy_delay; + assign \$11 = ldst_port0_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:220" *) \$9 ; + assign \$13 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:226" *) lenexp_lexp_o[63:8]; + assign \$15 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) lds_dly; + assign \$17 = lds & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$15 ; + assign \$1 = st_active_q_st_active & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:278" *) ldst_port0_st_data_i_ok; + assign \$19 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) sts_dly; + assign \$21 = sts & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$19 ; assign \$23 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) ldst_port0_addr_i[2:0]; - assign \$25 = ldst_port0_addr_i_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) adrok_l_qn_addr_acked; - assign \$27 = ldst_port0_addr_i_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) adrok_l_qn_addr_acked; - assign \$29 = ldst_port0_addr_i_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) adrok_l_qn_addr_acked; - assign \$31 = ldst_port0_addr_i_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) adrok_l_qn_addr_acked; - assign \$33 = ld_active_q_ld_active & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" *) adrok_l_q_addr_acked; - assign \$35 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" *) lsui_busy; - assign \$38 = x_busy_o | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" *) lsui_busy; - assign \$3 = ldst_port0_is_ld_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" *) ldst_port0_is_st_i; - assign \$37 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" *) \$38 ; - assign \$42 = m_ld_data_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257" *) lenexp_rexp_o; - assign \$44 = lenexp_addr_i * (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" *) 4'h8; - assign \$46 = \$42 >>> (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" *) \$44 ; - assign \$48 = ld_active_q_ld_active & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" *) adrok_l_q_addr_acked; - assign \$50 = ld_active_q_ld_active & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" *) adrok_l_q_addr_acked; - assign \$52 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" *) lsui_busy; - assign \$54 = st_active_q_st_active & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" *) ldst_port0_st_data_i_ok; - assign \$57 = lenexp_addr_i * (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" *) 4'h8; - assign \$5 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224" *) busy_delay; - assign \$59 = ldst_port0_st_data_i <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" *) \$57 ; - assign \$61 = st_active_q_st_active & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" *) ldst_port0_st_data_i_ok; - assign \$63 = ldst_port0_is_ld_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *) ldst_port0_is_st_i; - assign \$65 = \$63 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *) valid_l_q_valid; - assign \$67 = ldst_port0_is_ld_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *) ldst_port0_is_st_i; - assign \$69 = \$67 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *) valid_l_q_valid; - assign \$71 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" *) x_busy_o; - assign \$73 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" *) ldst_port0_is_st_i; - assign \$75 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" *) ldst_port0_busy_o; - assign \$77 = \$73 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" *) \$75 ; - assign \$7 = ldst_port0_addr_i_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) adrok_l_qn_addr_acked; - assign \$79 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" *) x_busy_o; - assign \$81 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) lsui_active_dly; - assign \$83 = lsui_active & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$81 ; + assign \$25 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) ldst_port0_addr_i[2:0]; + assign \$27 = ldst_port0_addr_i_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" *) adrok_l_qn_addr_acked; + assign \$29 = ldst_port0_addr_i_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" *) adrok_l_qn_addr_acked; + assign \$31 = ldst_port0_addr_i_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" *) adrok_l_qn_addr_acked; + assign \$33 = ldst_port0_addr_i_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" *) adrok_l_qn_addr_acked; + assign \$35 = ld_active_q_ld_active & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:270" *) adrok_l_q_addr_acked; + assign \$37 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" *) lsui_busy; + assign \$3 = ldst_port0_is_ld_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:234" *) ldst_port0_is_st_i; + assign \$40 = x_busy_o | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" *) lsui_busy; + assign \$39 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" *) \$40 ; + assign \$44 = m_ld_data_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:268" *) lenexp_rexp_o; + assign \$46 = lenexp_addr_i * (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:269" *) 4'h8; + assign \$48 = \$44 >>> (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:269" *) \$46 ; + assign \$50 = ld_active_q_ld_active & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:270" *) adrok_l_q_addr_acked; + assign \$52 = ld_active_q_ld_active & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:270" *) adrok_l_q_addr_acked; + assign \$54 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" *) lsui_busy; + assign \$56 = st_active_q_st_active & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:278" *) ldst_port0_st_data_i_ok; + assign \$5 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:235" *) busy_delay; + assign \$59 = lenexp_addr_i * (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:282" *) 4'h8; + assign \$61 = ldst_port0_st_data_i <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:282" *) \$59 ; + assign \$63 = st_active_q_st_active & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:278" *) ldst_port0_st_data_i_ok; + assign \$65 = ldst_port0_is_ld_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *) ldst_port0_is_st_i; + assign \$67 = \$65 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *) valid_l_q_valid; + assign \$69 = ldst_port0_is_ld_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *) ldst_port0_is_st_i; + assign \$71 = \$69 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *) valid_l_q_valid; + assign \$73 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" *) x_busy_o; + assign \$75 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" *) ldst_port0_is_st_i; + assign \$77 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" *) ldst_port0_busy_o; + assign \$7 = ldst_port0_addr_i_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" *) adrok_l_qn_addr_acked; + assign \$79 = \$75 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" *) \$77 ; + assign \$81 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" *) x_busy_o; + assign \$83 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) lsui_active_dly; + assign \$85 = lsui_active & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$83 ; always @(posedge coresync_clk) lsui_active_dly <= \lsui_active_dly$next ; always @(posedge coresync_clk) @@ -162389,13 +173977,13 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu always @* begin if (\initial ) begin end \st_done_s_st_done$next = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:278" *) casez (\$1 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:278" */ 1'h1: \st_done_s_st_done$next = 1'h1; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \st_done_s_st_done$next = 1'h0; @@ -162404,9 +173992,9 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu always @* begin if (\initial ) begin end st_done_r_st_done = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:297" *) casez (reset_l_q_reset) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:297" */ 1'h1: st_done_r_st_done = 1'h1; endcase @@ -162414,7 +174002,7 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu always @* begin if (\initial ) begin end \busy_delay$next = ldst_port0_busy_o; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \busy_delay$next = 1'h0; @@ -162423,9 +174011,9 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu always @* begin if (\initial ) begin end st_active_r_st_active = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:297" *) casez (reset_l_q_reset) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:297" */ 1'h1: st_active_r_st_active = 1'h1; endcase @@ -162433,15 +174021,15 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu always @* begin if (\initial ) begin end lenexp_len_i = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:239" *) casez (ld_active_q_ld_active) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:239" */ 1'h1: lenexp_len_i = ldst_port0_data_len; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:251" *) casez (st_active_q_st_active) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:251" */ 1'h1: lenexp_len_i = ldst_port0_data_len; endcase @@ -162449,40 +174037,40 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu always @* begin if (\initial ) begin end lenexp_addr_i = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:239" *) casez (ld_active_q_ld_active) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:239" */ 1'h1: - lenexp_addr_i = \$21 ; + lenexp_addr_i = \$23 ; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:251" *) casez (st_active_q_st_active) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:251" */ 1'h1: - lenexp_addr_i = \$23 ; + lenexp_addr_i = \$25 ; endcase end always @* begin if (\initial ) begin end valid_l_s_valid = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:239" *) casez (ld_active_q_ld_active) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:239" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) - casez (\$25 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" *) + casez (\$27 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" */ 1'h1: valid_l_s_valid = 1'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:251" *) casez (st_active_q_st_active) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:251" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" *) casez (ldst_port0_addr_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" */ 1'h1: valid_l_s_valid = 1'h1; endcase @@ -162491,24 +174079,24 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu always @* begin if (\initial ) begin end x_mask_i = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:239" *) casez (ld_active_q_ld_active) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:239" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) - casez (\$27 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" *) + casez (\$29 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" */ 1'h1: x_mask_i = lenexp_lexp_o[7:0]; endcase endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:251" *) casez (st_active_q_st_active) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:251" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" *) casez (ldst_port0_addr_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" */ 1'h1: x_mask_i = lenexp_lexp_o[7:0]; endcase @@ -162517,24 +174105,24 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu always @* begin if (\initial ) begin end x_addr_i = 48'h000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:239" *) casez (ld_active_q_ld_active) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:239" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) - casez (\$29 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" *) + casez (\$31 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" */ 1'h1: x_addr_i = ldst_port0_addr_i; endcase endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:251" *) casez (st_active_q_st_active) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:251" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" *) casez (ldst_port0_addr_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" */ 1'h1: x_addr_i = ldst_port0_addr_i; endcase @@ -162543,28 +174131,28 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu always @* begin if (\initial ) begin end ldst_port0_addr_ok_o = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:239" *) casez (ld_active_q_ld_active) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:239" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) - casez (\$31 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" *) + casez (\$33 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" */ 1'h1: ldst_port0_addr_ok_o = 1'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:251" *) casez (st_active_q_st_active) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:251" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" *) casez (ldst_port0_addr_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" *) casez (adrok_l_qn_addr_acked) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" */ 1'h1: ldst_port0_addr_ok_o = 1'h1; endcase @@ -162574,75 +174162,75 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu always @* begin if (\initial ) begin end reset_l_s_reset = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" *) - casez (\$33 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:270" *) + casez (\$35 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:270" */ 1'h1: - reset_l_s_reset = \$35 ; + reset_l_s_reset = \$37 ; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:276" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:287" *) casez (st_done_q_st_done) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:276" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:287" */ 1'h1: - reset_l_s_reset = \$37 ; + reset_l_s_reset = \$39 ; endcase end always @* begin if (\initial ) begin end reset_l_r_reset = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:297" *) casez (reset_l_q_reset) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:297" */ 1'h1: reset_l_r_reset = 1'h1; endcase end always @* begin if (\initial ) begin end - ldst_port0_ld_data_o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" *) - casez (\$48 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" */ + ld_active_r_ld_active = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:297" *) + casez (reset_l_q_reset) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:297" */ 1'h1: - ldst_port0_ld_data_o = lddata; + ld_active_r_ld_active = 1'h1; endcase end always @* begin if (\initial ) begin end - ld_active_r_ld_active = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" *) - casez (reset_l_q_reset) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" */ + ldst_port0_ld_data_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:270" *) + casez (\$50 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:270" */ 1'h1: - ld_active_r_ld_active = 1'h1; + ldst_port0_ld_data_o = lddata; endcase end always @* begin if (\initial ) begin end ldst_port0_ld_data_o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" *) - casez (\$50 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:270" *) + casez (\$52 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:270" */ 1'h1: - ldst_port0_ld_data_o_ok = \$52 ; + ldst_port0_ld_data_o_ok = \$54 ; endcase end always @* begin if (\initial ) begin end stdata = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" *) - casez (\$54 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:278" *) + casez (\$56 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:278" */ 1'h1: - stdata = \$56 [63:0]; + stdata = \$58 [63:0]; endcase end always @* begin if (\initial ) begin end x_st_data_i = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" *) - casez (\$61 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:278" *) + casez (\$63 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:278" */ 1'h1: x_st_data_i = stdata; endcase @@ -162656,7 +174244,7 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:86" */ 2'h0: (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *) - casez (\$65 ) + casez (\$67 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" */ 1'h1: lsui_busy = 1'h1; @@ -162676,7 +174264,7 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:86" */ 2'h0: (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *) - casez (\$69 ) + casez (\$71 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" */ 1'h1: \fsm_state$next = 2'h1; @@ -162685,7 +174273,7 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:91" */ 2'h1: (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" *) - casez (\$71 ) + casez (\$73 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" */ 1'h1: \fsm_state$next = 2'h2; @@ -162694,13 +174282,13 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:97" */ 2'h2: (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" *) - casez (\$77 ) + casez (\$79 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" */ 1'h1: \fsm_state$next = 2'h0; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \fsm_state$next = 2'h0; @@ -162709,9 +174297,9 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu always @* begin if (\initial ) begin end cyc_l_s_cyc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:299" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:310" *) casez (reset_l_s_reset) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:299" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:310" */ 1'h1: cyc_l_s_cyc = 1'h1; endcase @@ -162719,7 +174307,7 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu always @* begin if (\initial ) begin end \lsui_active_dly$next = lsui_active; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \lsui_active_dly$next = 1'h0; @@ -162728,9 +174316,9 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu always @* begin if (\initial ) begin end cyc_l_r_cyc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:302" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:313" *) casez (cyc_l_q_cyc) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:302" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:313" */ 1'h1: cyc_l_r_cyc = 1'h1; endcase @@ -162738,9 +174326,9 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu always @* begin if (\initial ) begin end busy_l_s_busy = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:234" *) casez (\$3 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:234" */ 1'h1: busy_l_s_busy = \$5 ; endcase @@ -162748,15 +174336,15 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu always @* begin if (\initial ) begin end busy_l_r_busy = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:294" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:305" *) casez (\ldst_port0_exc_$signal ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:294" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:305" */ 1'h1: busy_l_r_busy = 1'h1; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:302" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:313" *) casez (cyc_l_q_cyc) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:302" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:313" */ 1'h1: busy_l_r_busy = 1'h1; endcase @@ -162764,34 +174352,34 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu always @* begin if (\initial ) begin end \adrok_l_s_addr_acked$next = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:239" *) casez (ld_active_q_ld_active) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:239" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" *) casez (\$7 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" */ 1'h1: \adrok_l_s_addr_acked$next = 1'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:251" *) casez (st_active_q_st_active) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:251" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" *) casez (ldst_port0_addr_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" *) casez (adrok_l_qn_addr_acked) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" */ 1'h1: \adrok_l_s_addr_acked$next = 1'h1; endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \adrok_l_s_addr_acked$next = 1'h0; @@ -162800,37 +174388,38 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu always @* begin if (\initial ) begin end adrok_l_r_addr_acked = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:282" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:293" *) casez (reset_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:282" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:293" */ 1'h1: adrok_l_r_addr_acked = 1'h1; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:297" *) casez (reset_l_q_reset) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:297" */ 1'h1: adrok_l_r_addr_acked = 1'h1; endcase end - assign \$41 = \$46 ; - assign \$56 = \$59 ; + assign \$43 = \$48 ; + assign \$58 = \$61 ; assign valid_l_r_valid = lsui_active_rise; - assign lsui_active_rise = \$83 ; - assign lsui_active = \$79 ; + assign lsui_active_rise = \$85 ; + assign lsui_active = \$81 ; assign x_valid_i = valid_l_q_valid; assign m_valid_i = valid_l_q_valid; assign x_st_i = ldst_port0_is_st_i; assign x_ld_i = ldst_port0_is_ld_i; assign ldst_port0_busy_o = busy_l_q_busy; assign \reset_delay$next = reset_l_q_reset; - assign lddata = \$46 [63:0]; + assign lddata = \$48 [63:0]; assign st_active_s_st_active = sts_rise; - assign sts_rise = \$19 ; + assign sts_rise = \$21 ; assign \sts_dly$next = sts; assign ld_active_s_ld_active = lds_rise; - assign lds_rise = \$15 ; + assign lds_rise = \$17 ; assign \lds_dly$next = lds; + assign misalign = \$13 ; assign busy_edge = \$11 ; assign sts = ldst_port0_is_st_i; assign lds = ldst_port0_is_ld_i; @@ -162838,96 +174427,120 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.cr0.alu_cr0.pipe" *) (* generator = "nMigen" *) -module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__fn_unit, cr_op__insn, ra, rb, full_cr, cr_a, cr_b, cr_c, n_valid_o, n_ready_i, \muxid$1 , \cr_op__insn_type$2 , \cr_op__fn_unit$3 , \cr_op__insn$4 , o, o_ok, \full_cr$5 , full_cr_ok, \cr_a$6 , cr_a_ok, coresync_clk); +module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__fn_unit, cr_op__insn, cr_op__sv_pred_sz, cr_op__sv_pred_dz, cr_op__sv_saturate, cr_op__SV_Ptype, ra, rb, full_cr, cr_a, cr_b, cr_c, n_valid_o, n_ready_i, \muxid$1 , \cr_op__insn_type$2 , \cr_op__fn_unit$3 , \cr_op__insn$4 , \cr_op__sv_pred_sz$5 , \cr_op__sv_pred_dz$6 , \cr_op__sv_saturate$7 , \cr_op__SV_Ptype$8 , o, o_ok, \full_cr$9 , full_cr_ok, \cr_a$10 , cr_a_ok, coresync_clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) - wire \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + wire \$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [3:0] \cr_a$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [3:0] \cr_a$6 ; - reg [3:0] \cr_a$6 = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg [3:0] \cr_a$6$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [3:0] \cr_a$10 ; + reg [3:0] \cr_a$10 = 4'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg [3:0] \cr_a$10$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [3:0] \cr_a$36 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_a_ok; reg cr_a_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \cr_a_ok$25 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \cr_a_ok$37 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \cr_a_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [3:0] cr_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [3:0] cr_c; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] cr_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \cr_op__SV_Ptype$31 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \cr_op__SV_Ptype$8 ; + reg [1:0] \cr_op__SV_Ptype$8 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \cr_op__SV_Ptype$8$next ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] cr_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] cr_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \cr_op__fn_unit$18 ; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \cr_op__fn_unit$26 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \cr_op__fn_unit$3 ; - reg [13:0] \cr_op__fn_unit$3 = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] \cr_op__fn_unit$3$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \cr_op__fn_unit$3 ; + reg [14:0] \cr_op__fn_unit$3 = 15'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] \cr_op__fn_unit$3$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] cr_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \cr_op__insn$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \cr_op__insn$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \cr_op__insn$4 ; reg [31:0] \cr_op__insn$4 = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] \cr_op__insn$4$next ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -163004,7 +174617,9 @@ module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] cr_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -163081,8 +174696,13 @@ module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \cr_op__insn_type$17 ; + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [6:0] \cr_op__insn_type$2 ; + reg [6:0] \cr_op__insn_type$2 = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [6:0] \cr_op__insn_type$2$next ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -163158,75 +174778,127 @@ module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [6:0] \cr_op__insn_type$2 ; - reg [6:0] \cr_op__insn_type$2 = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [6:0] \cr_op__insn_type$2$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \cr_op__insn_type$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input cr_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \cr_op__sv_pred_dz$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \cr_op__sv_pred_dz$6 ; + reg \cr_op__sv_pred_dz$6 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \cr_op__sv_pred_dz$6$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input cr_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \cr_op__sv_pred_sz$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \cr_op__sv_pred_sz$5 ; + reg \cr_op__sv_pred_sz$5 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \cr_op__sv_pred_sz$5$next ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] cr_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \cr_op__sv_saturate$30 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \cr_op__sv_saturate$7 ; + reg [1:0] \cr_op__sv_saturate$7 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \cr_op__sv_saturate$7$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [31:0] full_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [31:0] \full_cr$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [31:0] \full_cr$5 ; - reg [31:0] \full_cr$5 = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg [31:0] \full_cr$5$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [31:0] \full_cr$34 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [31:0] \full_cr$9 ; + reg [31:0] \full_cr$9 = 32'd0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg [31:0] \full_cr$9$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output full_cr_ok; reg full_cr_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \full_cr_ok$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \full_cr_ok$35 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \full_cr_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [3:0] main_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [3:0] \main_cr_a$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [3:0] \main_cr_a$20 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire main_cr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [3:0] main_cr_b; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [3:0] main_cr_c; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] main_cr_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \main_cr_op__SV_Ptype$18 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] main_cr_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] main_cr_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \main_cr_op__fn_unit$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \main_cr_op__fn_unit$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] main_cr_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \main_cr_op__insn$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \main_cr_op__insn$14 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -163302,7 +174974,9 @@ module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] main_cr_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -163379,25 +175053,47 @@ module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__ (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \main_cr_op__insn_type$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \main_cr_op__insn_type$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire main_cr_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_cr_op__sv_pred_dz$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire main_cr_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_cr_op__sv_pred_sz$15 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] main_cr_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \main_cr_op__sv_saturate$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [31:0] main_full_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [31:0] \main_full_cr$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [31:0] \main_full_cr$19 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire main_full_cr_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] main_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \main_muxid$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \main_muxid$11 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] main_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire main_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] main_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] main_rb; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; @@ -163407,50 +175103,50 @@ module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) reg [1:0] \muxid$1$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \muxid$16 ; + wire [1:0] \muxid$24 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *) wire n_i_rdy_data; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] o; reg [63:0] o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \o$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \o$32 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [63:0] \o$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output o_ok; reg o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \o_ok$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \o_ok$33 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \o_ok$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) input p_valid_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *) - wire \p_valid_i$13 ; + wire \p_valid_i$21 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *) wire p_valid_i_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg r_busy = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg \r_busy$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] rb; - assign \$14 = \p_valid_i$13 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; + assign \$22 = \p_valid_i$21 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; always @(posedge coresync_clk) - \cr_a$6 <= \cr_a$6$next ; + \cr_a$10 <= \cr_a$10$next ; always @(posedge coresync_clk) cr_a_ok <= \cr_a_ok$next ; always @(posedge coresync_clk) - \full_cr$5 <= \full_cr$5$next ; + \full_cr$9 <= \full_cr$9$next ; always @(posedge coresync_clk) full_cr_ok <= \full_cr_ok$next ; always @(posedge coresync_clk) @@ -163463,27 +175159,43 @@ module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__ \cr_op__fn_unit$3 <= \cr_op__fn_unit$3$next ; always @(posedge coresync_clk) \cr_op__insn$4 <= \cr_op__insn$4$next ; + always @(posedge coresync_clk) + \cr_op__sv_pred_sz$5 <= \cr_op__sv_pred_sz$5$next ; + always @(posedge coresync_clk) + \cr_op__sv_pred_dz$6 <= \cr_op__sv_pred_dz$6$next ; + always @(posedge coresync_clk) + \cr_op__sv_saturate$7 <= \cr_op__sv_saturate$7$next ; + always @(posedge coresync_clk) + \cr_op__SV_Ptype$8 <= \cr_op__SV_Ptype$8$next ; always @(posedge coresync_clk) \muxid$1 <= \muxid$1$next ; always @(posedge coresync_clk) r_busy <= \r_busy$next ; \main$9 main ( .cr_a(main_cr_a), - .\cr_a$6 (\main_cr_a$12 ), + .\cr_a$10 (\main_cr_a$20 ), .cr_a_ok(main_cr_a_ok), .cr_b(main_cr_b), .cr_c(main_cr_c), + .cr_op__SV_Ptype(main_cr_op__SV_Ptype), + .\cr_op__SV_Ptype$8 (\main_cr_op__SV_Ptype$18 ), .cr_op__fn_unit(main_cr_op__fn_unit), - .\cr_op__fn_unit$3 (\main_cr_op__fn_unit$9 ), + .\cr_op__fn_unit$3 (\main_cr_op__fn_unit$13 ), .cr_op__insn(main_cr_op__insn), - .\cr_op__insn$4 (\main_cr_op__insn$10 ), + .\cr_op__insn$4 (\main_cr_op__insn$14 ), .cr_op__insn_type(main_cr_op__insn_type), - .\cr_op__insn_type$2 (\main_cr_op__insn_type$8 ), + .\cr_op__insn_type$2 (\main_cr_op__insn_type$12 ), + .cr_op__sv_pred_dz(main_cr_op__sv_pred_dz), + .\cr_op__sv_pred_dz$6 (\main_cr_op__sv_pred_dz$16 ), + .cr_op__sv_pred_sz(main_cr_op__sv_pred_sz), + .\cr_op__sv_pred_sz$5 (\main_cr_op__sv_pred_sz$15 ), + .cr_op__sv_saturate(main_cr_op__sv_saturate), + .\cr_op__sv_saturate$7 (\main_cr_op__sv_saturate$17 ), .full_cr(main_full_cr), - .\full_cr$5 (\main_full_cr$11 ), + .\full_cr$9 (\main_full_cr$19 ), .full_cr_ok(main_full_cr_ok), .muxid(main_muxid), - .\muxid$1 (\main_muxid$7 ), + .\muxid$1 (\main_muxid$11 ), .o(main_o), .o_ok(main_o_ok), .ra(main_ra), @@ -163509,7 +175221,7 @@ module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__ 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -163522,10 +175234,10 @@ module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__ casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \muxid$1$next = \muxid$16 ; + \muxid$1$next = \muxid$24 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \muxid$1$next = \muxid$16 ; + \muxid$1$next = \muxid$24 ; endcase end always @* begin @@ -163533,14 +175245,18 @@ module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__ \cr_op__insn_type$2$next = \cr_op__insn_type$2 ; \cr_op__fn_unit$3$next = \cr_op__fn_unit$3 ; \cr_op__insn$4$next = \cr_op__insn$4 ; + \cr_op__sv_pred_sz$5$next = \cr_op__sv_pred_sz$5 ; + \cr_op__sv_pred_dz$6$next = \cr_op__sv_pred_dz$6 ; + \cr_op__sv_saturate$7$next = \cr_op__sv_saturate$7 ; + \cr_op__SV_Ptype$8$next = \cr_op__SV_Ptype$8 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \cr_op__insn$4$next , \cr_op__fn_unit$3$next , \cr_op__insn_type$2$next } = { \cr_op__insn$19 , \cr_op__fn_unit$18 , \cr_op__insn_type$17 }; + { \cr_op__SV_Ptype$8$next , \cr_op__sv_saturate$7$next , \cr_op__sv_pred_dz$6$next , \cr_op__sv_pred_sz$5$next , \cr_op__insn$4$next , \cr_op__fn_unit$3$next , \cr_op__insn_type$2$next } = { \cr_op__SV_Ptype$31 , \cr_op__sv_saturate$30 , \cr_op__sv_pred_dz$29 , \cr_op__sv_pred_sz$28 , \cr_op__insn$27 , \cr_op__fn_unit$26 , \cr_op__insn_type$25 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \cr_op__insn$4$next , \cr_op__fn_unit$3$next , \cr_op__insn_type$2$next } = { \cr_op__insn$19 , \cr_op__fn_unit$18 , \cr_op__insn_type$17 }; + { \cr_op__SV_Ptype$8$next , \cr_op__sv_saturate$7$next , \cr_op__sv_pred_dz$6$next , \cr_op__sv_pred_sz$5$next , \cr_op__insn$4$next , \cr_op__fn_unit$3$next , \cr_op__insn_type$2$next } = { \cr_op__SV_Ptype$31 , \cr_op__sv_saturate$30 , \cr_op__sv_pred_dz$29 , \cr_op__sv_pred_sz$28 , \cr_op__insn$27 , \cr_op__fn_unit$26 , \cr_op__insn_type$25 }; endcase end always @* begin @@ -163551,12 +175267,12 @@ module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__ casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \o_ok$next , \o$next } = { \o_ok$21 , \o$20 }; + { \o_ok$next , \o$next } = { \o_ok$33 , \o$32 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \o_ok$next , \o$next } = { \o_ok$21 , \o$20 }; + { \o_ok$next , \o$next } = { \o_ok$33 , \o$32 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \o_ok$next = 1'h0; @@ -163564,18 +175280,18 @@ module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__ end always @* begin if (\initial ) begin end - \full_cr$5$next = \full_cr$5 ; + \full_cr$9$next = \full_cr$9 ; \full_cr_ok$next = full_cr_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \full_cr_ok$next , \full_cr$5$next } = { \full_cr_ok$23 , \full_cr$22 }; + { \full_cr_ok$next , \full_cr$9$next } = { \full_cr_ok$35 , \full_cr$34 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \full_cr_ok$next , \full_cr$5$next } = { \full_cr_ok$23 , \full_cr$22 }; + { \full_cr_ok$next , \full_cr$9$next } = { \full_cr_ok$35 , \full_cr$34 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \full_cr_ok$next = 1'h0; @@ -163583,18 +175299,18 @@ module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__ end always @* begin if (\initial ) begin end - \cr_a$6$next = \cr_a$6 ; + \cr_a$10$next = \cr_a$10 ; \cr_a_ok$next = cr_a_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \cr_a_ok$next , \cr_a$6$next } = { \cr_a_ok$25 , \cr_a$24 }; + { \cr_a_ok$next , \cr_a$10$next } = { \cr_a_ok$37 , \cr_a$36 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \cr_a_ok$next , \cr_a$6$next } = { \cr_a_ok$25 , \cr_a$24 }; + { \cr_a_ok$next , \cr_a$10$next } = { \cr_a_ok$37 , \cr_a$36 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \cr_a_ok$next = 1'h0; @@ -163602,119 +175318,143 @@ module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__ end assign p_ready_o = n_i_rdy_data; assign n_valid_o = r_busy; - assign { \cr_a_ok$25 , \cr_a$24 } = { main_cr_a_ok, \main_cr_a$12 }; - assign { \full_cr_ok$23 , \full_cr$22 } = { main_full_cr_ok, \main_full_cr$11 }; - assign { \o_ok$21 , \o$20 } = { main_o_ok, main_o }; - assign { \cr_op__insn$19 , \cr_op__fn_unit$18 , \cr_op__insn_type$17 } = { \main_cr_op__insn$10 , \main_cr_op__fn_unit$9 , \main_cr_op__insn_type$8 }; - assign \muxid$16 = \main_muxid$7 ; - assign p_valid_i_p_ready_o = \$14 ; + assign { \cr_a_ok$37 , \cr_a$36 } = { main_cr_a_ok, \main_cr_a$20 }; + assign { \full_cr_ok$35 , \full_cr$34 } = { main_full_cr_ok, \main_full_cr$19 }; + assign { \o_ok$33 , \o$32 } = { main_o_ok, main_o }; + assign { \cr_op__SV_Ptype$31 , \cr_op__sv_saturate$30 , \cr_op__sv_pred_dz$29 , \cr_op__sv_pred_sz$28 , \cr_op__insn$27 , \cr_op__fn_unit$26 , \cr_op__insn_type$25 } = { \main_cr_op__SV_Ptype$18 , \main_cr_op__sv_saturate$17 , \main_cr_op__sv_pred_dz$16 , \main_cr_op__sv_pred_sz$15 , \main_cr_op__insn$14 , \main_cr_op__fn_unit$13 , \main_cr_op__insn_type$12 }; + assign \muxid$24 = \main_muxid$11 ; + assign p_valid_i_p_ready_o = \$22 ; assign n_i_rdy_data = n_ready_i; - assign \p_valid_i$13 = p_valid_i; + assign \p_valid_i$21 = p_valid_i; assign main_cr_c = cr_c; assign main_cr_b = cr_b; assign main_cr_a = cr_a; assign main_full_cr = full_cr; assign main_rb = rb; assign main_ra = ra; - assign { main_cr_op__insn, main_cr_op__fn_unit, main_cr_op__insn_type } = { cr_op__insn, cr_op__fn_unit, cr_op__insn_type }; + assign { main_cr_op__SV_Ptype, main_cr_op__sv_saturate, main_cr_op__sv_pred_dz, main_cr_op__sv_pred_sz, main_cr_op__insn, main_cr_op__fn_unit, main_cr_op__insn_type } = { cr_op__SV_Ptype, cr_op__sv_saturate, cr_op__sv_pred_dz, cr_op__sv_pred_sz, cr_op__insn, cr_op__fn_unit, cr_op__insn_type }; assign main_muxid = muxid; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.branch0.alu_branch0.pipe" *) (* generator = "nMigen" *) -module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_op__imm_data__data, br_op__imm_data__ok, br_op__lk, br_op__is_32bit, fast1, fast2, cr_a, n_valid_o, n_ready_i, \muxid$1 , \br_op__cia$2 , \br_op__insn_type$3 , \br_op__fn_unit$4 , \br_op__insn$5 , \br_op__imm_data__data$6 , \br_op__imm_data__ok$7 , \br_op__lk$8 , \br_op__is_32bit$9 , \fast1$10 , fast1_ok, \fast2$11 , fast2_ok, nia, nia_ok, coresync_clk); +module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_op__imm_data__data, br_op__imm_data__ok, br_op__lk, br_op__is_32bit, br_op__sv_pred_sz, br_op__sv_pred_dz, br_op__sv_saturate, br_op__SV_Ptype, fast1, fast2, cr_a, n_valid_o, n_ready_i, \muxid$1 , \br_op__cia$2 , \br_op__insn_type$3 , \br_op__fn_unit$4 , \br_op__insn$5 , \br_op__imm_data__data$6 , \br_op__imm_data__ok$7 , \br_op__lk$8 , \br_op__is_32bit$9 , \br_op__sv_pred_sz$10 , \br_op__sv_pred_dz$11 , \br_op__sv_saturate$12 , \br_op__SV_Ptype$13 , \fast1$14 , fast1_ok, \fast2$15 , fast2_ok, nia, nia_ok, coresync_clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) - wire \$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \$32 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] br_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \br_op__SV_Ptype$13 ; + reg [1:0] \br_op__SV_Ptype$13 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \br_op__SV_Ptype$13$next ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \br_op__SV_Ptype$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] br_op__cia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \br_op__cia$2 ; reg [63:0] \br_op__cia$2 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] \br_op__cia$2$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \br_op__cia$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \br_op__cia$35 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] br_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] br_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \br_op__fn_unit$29 ; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \br_op__fn_unit$37 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \br_op__fn_unit$4 ; - reg [13:0] \br_op__fn_unit$4 = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] \br_op__fn_unit$4$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \br_op__fn_unit$4 ; + reg [14:0] \br_op__fn_unit$4 = 15'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] \br_op__fn_unit$4$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] br_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \br_op__imm_data__data$31 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \br_op__imm_data__data$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \br_op__imm_data__data$6 ; reg [63:0] \br_op__imm_data__data$6 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] \br_op__imm_data__data$6$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input br_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \br_op__imm_data__ok$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \br_op__imm_data__ok$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \br_op__imm_data__ok$7 ; reg \br_op__imm_data__ok$7 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \br_op__imm_data__ok$7$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] br_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \br_op__insn$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \br_op__insn$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \br_op__insn$5 ; reg [31:0] \br_op__insn$5 = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] \br_op__insn$5$next ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -163791,7 +175531,9 @@ module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__i (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] br_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -163868,8 +175610,13 @@ module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__i (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \br_op__insn_type$28 ; + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [6:0] \br_op__insn_type$3 ; + reg [6:0] \br_op__insn_type$3 = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [6:0] \br_op__insn_type$3$next ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -163945,117 +175692,169 @@ module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__i (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [6:0] \br_op__insn_type$3 ; - reg [6:0] \br_op__insn_type$3 = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [6:0] \br_op__insn_type$3$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \br_op__insn_type$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input br_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \br_op__is_32bit$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \br_op__is_32bit$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \br_op__is_32bit$9 ; reg \br_op__is_32bit$9 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \br_op__is_32bit$9$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input br_op__lk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \br_op__lk$33 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \br_op__lk$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \br_op__lk$8 ; reg \br_op__lk$8 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \br_op__lk$8$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input br_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \br_op__sv_pred_dz$11 ; + reg \br_op__sv_pred_dz$11 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \br_op__sv_pred_dz$11$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \br_op__sv_pred_dz$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input br_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \br_op__sv_pred_sz$10 ; + reg \br_op__sv_pred_sz$10 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \br_op__sv_pred_sz$10$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \br_op__sv_pred_sz$43 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] br_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \br_op__sv_saturate$12 ; + reg [1:0] \br_op__sv_saturate$12 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \br_op__sv_saturate$12$next ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \br_op__sv_saturate$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [63:0] \fast1$10 ; - reg [63:0] \fast1$10 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg [63:0] \fast1$10$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \fast1$35 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [63:0] \fast1$14 ; + reg [63:0] \fast1$14 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg [63:0] \fast1$14$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \fast1$47 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output fast1_ok; reg fast1_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \fast1_ok$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \fast1_ok$48 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \fast1_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] fast2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [63:0] \fast2$11 ; - reg [63:0] \fast2$11 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg [63:0] \fast2$11$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \fast2$37 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [63:0] \fast2$15 ; + reg [63:0] \fast2$15 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg [63:0] \fast2$15$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \fast2$49 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output fast2_ok; reg fast2_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \fast2_ok$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \fast2_ok$50 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \fast2_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] main_br_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \main_br_op__SV_Ptype$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] main_br_op__cia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \main_br_op__cia$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \main_br_op__cia$17 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] main_br_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] main_br_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \main_br_op__fn_unit$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \main_br_op__fn_unit$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] main_br_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \main_br_op__imm_data__data$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \main_br_op__imm_data__data$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_br_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_br_op__imm_data__ok$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_br_op__imm_data__ok$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] main_br_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \main_br_op__insn$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \main_br_op__insn$20 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -164131,7 +175930,9 @@ module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__i (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] main_br_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -164208,37 +176009,59 @@ module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__i (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \main_br_op__insn_type$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \main_br_op__insn_type$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_br_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_br_op__is_32bit$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_br_op__is_32bit$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_br_op__lk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_br_op__lk$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_br_op__lk$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire main_br_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_br_op__sv_pred_dz$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire main_br_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_br_op__sv_pred_sz$25 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] main_br_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \main_br_op__sv_saturate$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [3:0] main_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] main_fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \main_fast1$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \main_fast1$29 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire main_fast1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] main_fast2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \main_fast2$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \main_fast2$30 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire main_fast2_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] main_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \main_muxid$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \main_muxid$16 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] main_nia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire main_nia_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; @@ -164248,50 +176071,50 @@ module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__i (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) reg [1:0] \muxid$1$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \muxid$26 ; + wire [1:0] \muxid$34 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *) wire n_i_rdy_data; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] nia; reg [63:0] nia = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \nia$39 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \nia$51 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [63:0] \nia$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output nia_ok; reg nia_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \nia_ok$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \nia_ok$52 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \nia_ok$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) input p_valid_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *) - wire \p_valid_i$23 ; + wire \p_valid_i$31 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *) wire p_valid_i_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg r_busy = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg \r_busy$next ; - assign \$24 = \p_valid_i$23 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; + assign \$32 = \p_valid_i$31 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; always @(posedge coresync_clk) nia <= \nia$next ; always @(posedge coresync_clk) nia_ok <= \nia_ok$next ; always @(posedge coresync_clk) - \fast2$11 <= \fast2$11$next ; + \fast2$15 <= \fast2$15$next ; always @(posedge coresync_clk) fast2_ok <= \fast2_ok$next ; always @(posedge coresync_clk) - \fast1$10 <= \fast1$10$next ; + \fast1$14 <= \fast1$14$next ; always @(posedge coresync_clk) fast1_ok <= \fast1_ok$next ; always @(posedge coresync_clk) @@ -164310,36 +176133,52 @@ module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__i \br_op__lk$8 <= \br_op__lk$8$next ; always @(posedge coresync_clk) \br_op__is_32bit$9 <= \br_op__is_32bit$9$next ; + always @(posedge coresync_clk) + \br_op__sv_pred_sz$10 <= \br_op__sv_pred_sz$10$next ; + always @(posedge coresync_clk) + \br_op__sv_pred_dz$11 <= \br_op__sv_pred_dz$11$next ; + always @(posedge coresync_clk) + \br_op__sv_saturate$12 <= \br_op__sv_saturate$12$next ; + always @(posedge coresync_clk) + \br_op__SV_Ptype$13 <= \br_op__SV_Ptype$13$next ; always @(posedge coresync_clk) \muxid$1 <= \muxid$1$next ; always @(posedge coresync_clk) r_busy <= \r_busy$next ; \main$22 main ( + .br_op__SV_Ptype(main_br_op__SV_Ptype), + .\br_op__SV_Ptype$13 (\main_br_op__SV_Ptype$28 ), .br_op__cia(main_br_op__cia), - .\br_op__cia$2 (\main_br_op__cia$13 ), + .\br_op__cia$2 (\main_br_op__cia$17 ), .br_op__fn_unit(main_br_op__fn_unit), - .\br_op__fn_unit$4 (\main_br_op__fn_unit$15 ), + .\br_op__fn_unit$4 (\main_br_op__fn_unit$19 ), .br_op__imm_data__data(main_br_op__imm_data__data), - .\br_op__imm_data__data$6 (\main_br_op__imm_data__data$17 ), + .\br_op__imm_data__data$6 (\main_br_op__imm_data__data$21 ), .br_op__imm_data__ok(main_br_op__imm_data__ok), - .\br_op__imm_data__ok$7 (\main_br_op__imm_data__ok$18 ), + .\br_op__imm_data__ok$7 (\main_br_op__imm_data__ok$22 ), .br_op__insn(main_br_op__insn), - .\br_op__insn$5 (\main_br_op__insn$16 ), + .\br_op__insn$5 (\main_br_op__insn$20 ), .br_op__insn_type(main_br_op__insn_type), - .\br_op__insn_type$3 (\main_br_op__insn_type$14 ), + .\br_op__insn_type$3 (\main_br_op__insn_type$18 ), .br_op__is_32bit(main_br_op__is_32bit), - .\br_op__is_32bit$9 (\main_br_op__is_32bit$20 ), + .\br_op__is_32bit$9 (\main_br_op__is_32bit$24 ), .br_op__lk(main_br_op__lk), - .\br_op__lk$8 (\main_br_op__lk$19 ), + .\br_op__lk$8 (\main_br_op__lk$23 ), + .br_op__sv_pred_dz(main_br_op__sv_pred_dz), + .\br_op__sv_pred_dz$11 (\main_br_op__sv_pred_dz$26 ), + .br_op__sv_pred_sz(main_br_op__sv_pred_sz), + .\br_op__sv_pred_sz$10 (\main_br_op__sv_pred_sz$25 ), + .br_op__sv_saturate(main_br_op__sv_saturate), + .\br_op__sv_saturate$12 (\main_br_op__sv_saturate$27 ), .cr_a(main_cr_a), .fast1(main_fast1), - .\fast1$10 (\main_fast1$21 ), + .\fast1$14 (\main_fast1$29 ), .fast1_ok(main_fast1_ok), .fast2(main_fast2), - .\fast2$11 (\main_fast2$22 ), + .\fast2$15 (\main_fast2$30 ), .fast2_ok(main_fast2_ok), .muxid(main_muxid), - .\muxid$1 (\main_muxid$12 ), + .\muxid$1 (\main_muxid$16 ), .nia(main_nia), .nia_ok(main_nia_ok) ); @@ -164363,7 +176202,7 @@ module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__i 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -164376,10 +176215,10 @@ module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__i casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \muxid$1$next = \muxid$26 ; + \muxid$1$next = \muxid$34 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \muxid$1$next = \muxid$26 ; + \muxid$1$next = \muxid$34 ; endcase end always @* begin @@ -164392,16 +176231,20 @@ module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__i \br_op__imm_data__ok$7$next = \br_op__imm_data__ok$7 ; \br_op__lk$8$next = \br_op__lk$8 ; \br_op__is_32bit$9$next = \br_op__is_32bit$9 ; + \br_op__sv_pred_sz$10$next = \br_op__sv_pred_sz$10 ; + \br_op__sv_pred_dz$11$next = \br_op__sv_pred_dz$11 ; + \br_op__sv_saturate$12$next = \br_op__sv_saturate$12 ; + \br_op__SV_Ptype$13$next = \br_op__SV_Ptype$13 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \br_op__is_32bit$9$next , \br_op__lk$8$next , \br_op__imm_data__ok$7$next , \br_op__imm_data__data$6$next , \br_op__insn$5$next , \br_op__fn_unit$4$next , \br_op__insn_type$3$next , \br_op__cia$2$next } = { \br_op__is_32bit$34 , \br_op__lk$33 , \br_op__imm_data__ok$32 , \br_op__imm_data__data$31 , \br_op__insn$30 , \br_op__fn_unit$29 , \br_op__insn_type$28 , \br_op__cia$27 }; + { \br_op__SV_Ptype$13$next , \br_op__sv_saturate$12$next , \br_op__sv_pred_dz$11$next , \br_op__sv_pred_sz$10$next , \br_op__is_32bit$9$next , \br_op__lk$8$next , \br_op__imm_data__ok$7$next , \br_op__imm_data__data$6$next , \br_op__insn$5$next , \br_op__fn_unit$4$next , \br_op__insn_type$3$next , \br_op__cia$2$next } = { \br_op__SV_Ptype$46 , \br_op__sv_saturate$45 , \br_op__sv_pred_dz$44 , \br_op__sv_pred_sz$43 , \br_op__is_32bit$42 , \br_op__lk$41 , \br_op__imm_data__ok$40 , \br_op__imm_data__data$39 , \br_op__insn$38 , \br_op__fn_unit$37 , \br_op__insn_type$36 , \br_op__cia$35 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \br_op__is_32bit$9$next , \br_op__lk$8$next , \br_op__imm_data__ok$7$next , \br_op__imm_data__data$6$next , \br_op__insn$5$next , \br_op__fn_unit$4$next , \br_op__insn_type$3$next , \br_op__cia$2$next } = { \br_op__is_32bit$34 , \br_op__lk$33 , \br_op__imm_data__ok$32 , \br_op__imm_data__data$31 , \br_op__insn$30 , \br_op__fn_unit$29 , \br_op__insn_type$28 , \br_op__cia$27 }; + { \br_op__SV_Ptype$13$next , \br_op__sv_saturate$12$next , \br_op__sv_pred_dz$11$next , \br_op__sv_pred_sz$10$next , \br_op__is_32bit$9$next , \br_op__lk$8$next , \br_op__imm_data__ok$7$next , \br_op__imm_data__data$6$next , \br_op__insn$5$next , \br_op__fn_unit$4$next , \br_op__insn_type$3$next , \br_op__cia$2$next } = { \br_op__SV_Ptype$46 , \br_op__sv_saturate$45 , \br_op__sv_pred_dz$44 , \br_op__sv_pred_sz$43 , \br_op__is_32bit$42 , \br_op__lk$41 , \br_op__imm_data__ok$40 , \br_op__imm_data__data$39 , \br_op__insn$38 , \br_op__fn_unit$37 , \br_op__insn_type$36 , \br_op__cia$35 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -164412,18 +176255,18 @@ module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__i end always @* begin if (\initial ) begin end - \fast1$10$next = \fast1$10 ; + \fast1$14$next = \fast1$14 ; \fast1_ok$next = fast1_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \fast1_ok$next , \fast1$10$next } = { \fast1_ok$36 , \fast1$35 }; + { \fast1_ok$next , \fast1$14$next } = { \fast1_ok$48 , \fast1$47 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \fast1_ok$next , \fast1$10$next } = { \fast1_ok$36 , \fast1$35 }; + { \fast1_ok$next , \fast1$14$next } = { \fast1_ok$48 , \fast1$47 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \fast1_ok$next = 1'h0; @@ -164431,18 +176274,18 @@ module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__i end always @* begin if (\initial ) begin end - \fast2$11$next = \fast2$11 ; + \fast2$15$next = \fast2$15 ; \fast2_ok$next = fast2_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \fast2_ok$next , \fast2$11$next } = { \fast2_ok$38 , \fast2$37 }; + { \fast2_ok$next , \fast2$15$next } = { \fast2_ok$50 , \fast2$49 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \fast2_ok$next , \fast2$11$next } = { \fast2_ok$38 , \fast2$37 }; + { \fast2_ok$next , \fast2$15$next } = { \fast2_ok$50 , \fast2$49 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \fast2_ok$next = 1'h0; @@ -164456,12 +176299,12 @@ module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__i casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \nia_ok$next , \nia$next } = { \nia_ok$40 , \nia$39 }; + { \nia_ok$next , \nia$next } = { \nia_ok$52 , \nia$51 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \nia_ok$next , \nia$next } = { \nia_ok$40 , \nia$39 }; + { \nia_ok$next , \nia$next } = { \nia_ok$52 , \nia$51 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \nia_ok$next = 1'h0; @@ -164469,46 +176312,46 @@ module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__i end assign p_ready_o = n_i_rdy_data; assign n_valid_o = r_busy; - assign { \nia_ok$40 , \nia$39 } = { main_nia_ok, main_nia }; - assign { \fast2_ok$38 , \fast2$37 } = { main_fast2_ok, \main_fast2$22 }; - assign { \fast1_ok$36 , \fast1$35 } = { main_fast1_ok, \main_fast1$21 }; - assign { \br_op__is_32bit$34 , \br_op__lk$33 , \br_op__imm_data__ok$32 , \br_op__imm_data__data$31 , \br_op__insn$30 , \br_op__fn_unit$29 , \br_op__insn_type$28 , \br_op__cia$27 } = { \main_br_op__is_32bit$20 , \main_br_op__lk$19 , \main_br_op__imm_data__ok$18 , \main_br_op__imm_data__data$17 , \main_br_op__insn$16 , \main_br_op__fn_unit$15 , \main_br_op__insn_type$14 , \main_br_op__cia$13 }; - assign \muxid$26 = \main_muxid$12 ; - assign p_valid_i_p_ready_o = \$24 ; + assign { \nia_ok$52 , \nia$51 } = { main_nia_ok, main_nia }; + assign { \fast2_ok$50 , \fast2$49 } = { main_fast2_ok, \main_fast2$30 }; + assign { \fast1_ok$48 , \fast1$47 } = { main_fast1_ok, \main_fast1$29 }; + assign { \br_op__SV_Ptype$46 , \br_op__sv_saturate$45 , \br_op__sv_pred_dz$44 , \br_op__sv_pred_sz$43 , \br_op__is_32bit$42 , \br_op__lk$41 , \br_op__imm_data__ok$40 , \br_op__imm_data__data$39 , \br_op__insn$38 , \br_op__fn_unit$37 , \br_op__insn_type$36 , \br_op__cia$35 } = { \main_br_op__SV_Ptype$28 , \main_br_op__sv_saturate$27 , \main_br_op__sv_pred_dz$26 , \main_br_op__sv_pred_sz$25 , \main_br_op__is_32bit$24 , \main_br_op__lk$23 , \main_br_op__imm_data__ok$22 , \main_br_op__imm_data__data$21 , \main_br_op__insn$20 , \main_br_op__fn_unit$19 , \main_br_op__insn_type$18 , \main_br_op__cia$17 }; + assign \muxid$34 = \main_muxid$16 ; + assign p_valid_i_p_ready_o = \$32 ; assign n_i_rdy_data = n_ready_i; - assign \p_valid_i$23 = p_valid_i; + assign \p_valid_i$31 = p_valid_i; assign main_cr_a = cr_a; assign main_fast2 = fast2; assign main_fast1 = fast1; - assign { main_br_op__is_32bit, main_br_op__lk, main_br_op__imm_data__ok, main_br_op__imm_data__data, main_br_op__insn, main_br_op__fn_unit, main_br_op__insn_type, main_br_op__cia } = { br_op__is_32bit, br_op__lk, br_op__imm_data__ok, br_op__imm_data__data, br_op__insn, br_op__fn_unit, br_op__insn_type, br_op__cia }; + assign { main_br_op__SV_Ptype, main_br_op__sv_saturate, main_br_op__sv_pred_dz, main_br_op__sv_pred_sz, main_br_op__is_32bit, main_br_op__lk, main_br_op__imm_data__ok, main_br_op__imm_data__data, main_br_op__insn, main_br_op__fn_unit, main_br_op__insn_type, main_br_op__cia } = { br_op__SV_Ptype, br_op__sv_saturate, br_op__sv_pred_dz, br_op__sv_pred_sz, br_op__is_32bit, br_op__lk, br_op__imm_data__ok, br_op__imm_data__data, br_op__insn, br_op__fn_unit, br_op__insn_type, br_op__cia }; assign main_muxid = muxid; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.spr0.alu_spr0.pipe" *) (* generator = "nMigen" *) -module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32bit, ra, spr1, fast1, xer_so, xer_ov, xer_ca, n_valid_o, n_ready_i, \muxid$1 , \spr_op__insn_type$2 , \spr_op__fn_unit$3 , \spr_op__insn$4 , \spr_op__is_32bit$5 , o, o_ok, \spr1$6 , spr1_ok, \fast1$7 , fast1_ok, \xer_so$8 , xer_so_ok, \xer_ov$9 , xer_ov_ok, \xer_ca$10 , xer_ca_ok, coresync_clk); +module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32bit, spr_op__sv_pred_sz, spr_op__sv_pred_dz, spr_op__sv_saturate, spr_op__SV_Ptype, ra, spr1, fast1, xer_so, xer_ov, xer_ca, n_valid_o, n_ready_i, \muxid$1 , \spr_op__insn_type$2 , \spr_op__fn_unit$3 , \spr_op__insn$4 , \spr_op__is_32bit$5 , \spr_op__sv_pred_sz$6 , \spr_op__sv_pred_dz$7 , \spr_op__sv_saturate$8 , \spr_op__SV_Ptype$9 , o, o_ok, \spr1$10 , spr1_ok, \fast1$11 , fast1_ok, \xer_so$12 , xer_so_ok, \xer_ov$13 , xer_ov_ok, \xer_ca$14 , xer_ca_ok, coresync_clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) - wire \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + wire \$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \fast1$33 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [63:0] \fast1$7 ; - reg [63:0] \fast1$7 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg [63:0] \fast1$7$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [63:0] \fast1$11 ; + reg [63:0] \fast1$11 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg [63:0] \fast1$11$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \fast1$45 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output fast1_ok; reg fast1_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \fast1_ok$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \fast1_ok$46 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \fast1_ok$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; @@ -164518,117 +176361,131 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) reg [1:0] \muxid$1$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \muxid$24 ; + wire [1:0] \muxid$32 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *) wire n_i_rdy_data; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] o; reg [63:0] o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \o$29 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \o$41 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [63:0] \o$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output o_ok; reg o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \o_ok$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \o_ok$42 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \o_ok$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) input p_valid_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *) - wire \p_valid_i$21 ; + wire \p_valid_i$29 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *) wire p_valid_i_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg r_busy = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg \r_busy$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] spr1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \spr1$31 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [63:0] \spr1$6 ; - reg [63:0] \spr1$6 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg [63:0] \spr1$6$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [63:0] \spr1$10 ; + reg [63:0] \spr1$10 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg [63:0] \spr1$10$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \spr1$43 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output spr1_ok; reg spr1_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \spr1_ok$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \spr1_ok$44 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \spr1_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] spr_main_fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \spr_main_fast1$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \spr_main_fast1$25 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire spr_main_fast1_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] spr_main_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \spr_main_muxid$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \spr_main_muxid$15 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] spr_main_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire spr_main_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] spr_main_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] spr_main_spr1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \spr_main_spr1$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \spr_main_spr1$24 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire spr_main_spr1_ok; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] spr_main_spr_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \spr_main_spr_op__SV_Ptype$23 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] spr_main_spr_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] spr_main_spr_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \spr_main_spr_op__fn_unit$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \spr_main_spr_op__fn_unit$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] spr_main_spr_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \spr_main_spr_op__insn$14 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \spr_main_spr_op__insn$18 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -164704,7 +176561,9 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] spr_main_spr_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -164781,92 +176640,138 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \spr_main_spr_op__insn_type$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \spr_main_spr_op__insn_type$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire spr_main_spr_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \spr_main_spr_op__is_32bit$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \spr_main_spr_op__is_32bit$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire spr_main_spr_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \spr_main_spr_op__sv_pred_dz$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire spr_main_spr_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \spr_main_spr_op__sv_pred_sz$20 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] spr_main_spr_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \spr_main_spr_op__sv_saturate$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [1:0] spr_main_xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [1:0] \spr_main_xer_ca$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [1:0] \spr_main_xer_ca$28 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire spr_main_xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [1:0] spr_main_xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [1:0] \spr_main_xer_ov$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [1:0] \spr_main_xer_ov$27 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire spr_main_xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire spr_main_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \spr_main_xer_so$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \spr_main_xer_so$26 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire spr_main_xer_so_ok; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] spr_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \spr_op__SV_Ptype$40 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \spr_op__SV_Ptype$9 ; + reg [1:0] \spr_op__SV_Ptype$9 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \spr_op__SV_Ptype$9$next ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] spr_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] spr_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \spr_op__fn_unit$26 ; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \spr_op__fn_unit$3 ; + reg [14:0] \spr_op__fn_unit$3 = 15'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] \spr_op__fn_unit$3$next ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \spr_op__fn_unit$3 ; - reg [13:0] \spr_op__fn_unit$3 = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] \spr_op__fn_unit$3$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \spr_op__fn_unit$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] spr_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \spr_op__insn$27 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \spr_op__insn$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \spr_op__insn$4 ; reg [31:0] \spr_op__insn$4 = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] \spr_op__insn$4$next ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -164943,7 +176848,9 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] spr_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -165020,10 +176927,12 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] \spr_op__insn_type$2 ; reg [6:0] \spr_op__insn_type$2 = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] \spr_op__insn_type$2$next ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -165100,84 +177009,125 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \spr_op__insn_type$25 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \spr_op__insn_type$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input spr_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \spr_op__is_32bit$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \spr_op__is_32bit$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \spr_op__is_32bit$5 ; reg \spr_op__is_32bit$5 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \spr_op__is_32bit$5$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input spr_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \spr_op__sv_pred_dz$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \spr_op__sv_pred_dz$7 ; + reg \spr_op__sv_pred_dz$7 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \spr_op__sv_pred_dz$7$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input spr_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \spr_op__sv_pred_sz$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \spr_op__sv_pred_sz$6 ; + reg \spr_op__sv_pred_sz$6 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \spr_op__sv_pred_sz$6$next ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] spr_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \spr_op__sv_saturate$39 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \spr_op__sv_saturate$8 ; + reg [1:0] \spr_op__sv_saturate$8 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \spr_op__sv_saturate$8$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [1:0] xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [1:0] \xer_ca$10 ; - reg [1:0] \xer_ca$10 = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg [1:0] \xer_ca$10$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [1:0] \xer_ca$39 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [1:0] \xer_ca$14 ; + reg [1:0] \xer_ca$14 = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg [1:0] \xer_ca$14$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [1:0] \xer_ca$51 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ca_ok; reg xer_ca_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_ca_ok$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_ca_ok$52 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \xer_ca_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [1:0] xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [1:0] \xer_ov$37 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [1:0] \xer_ov$9 ; - reg [1:0] \xer_ov$9 = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg [1:0] \xer_ov$9$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [1:0] \xer_ov$13 ; + reg [1:0] \xer_ov$13 = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg [1:0] \xer_ov$13$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [1:0] \xer_ov$49 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ov_ok; reg xer_ov_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_ov_ok$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_ov_ok$50 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \xer_ov_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_so$35 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \xer_so$8 ; - reg \xer_so$8 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg \xer_so$8$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \xer_so$12 ; + reg \xer_so$12 = 1'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg \xer_so$12$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_so$47 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_so_ok; reg xer_so_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_so_ok$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_so_ok$48 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \xer_so_ok$next ; - assign \$22 = \p_valid_i$21 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; + assign \$30 = \p_valid_i$29 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; always @(posedge coresync_clk) - \xer_ca$10 <= \xer_ca$10$next ; + \xer_ca$14 <= \xer_ca$14$next ; always @(posedge coresync_clk) xer_ca_ok <= \xer_ca_ok$next ; always @(posedge coresync_clk) - \xer_ov$9 <= \xer_ov$9$next ; + \xer_ov$13 <= \xer_ov$13$next ; always @(posedge coresync_clk) xer_ov_ok <= \xer_ov_ok$next ; always @(posedge coresync_clk) - \xer_so$8 <= \xer_so$8$next ; + \xer_so$12 <= \xer_so$12$next ; always @(posedge coresync_clk) xer_so_ok <= \xer_so_ok$next ; always @(posedge coresync_clk) - \fast1$7 <= \fast1$7$next ; + \fast1$11 <= \fast1$11$next ; always @(posedge coresync_clk) fast1_ok <= \fast1_ok$next ; always @(posedge coresync_clk) - \spr1$6 <= \spr1$6$next ; + \spr1$10 <= \spr1$10$next ; always @(posedge coresync_clk) spr1_ok <= \spr1_ok$next ; always @(posedge coresync_clk) @@ -165192,6 +177142,14 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s \spr_op__insn$4 <= \spr_op__insn$4$next ; always @(posedge coresync_clk) \spr_op__is_32bit$5 <= \spr_op__is_32bit$5$next ; + always @(posedge coresync_clk) + \spr_op__sv_pred_sz$6 <= \spr_op__sv_pred_sz$6$next ; + always @(posedge coresync_clk) + \spr_op__sv_pred_dz$7 <= \spr_op__sv_pred_dz$7$next ; + always @(posedge coresync_clk) + \spr_op__sv_saturate$8 <= \spr_op__sv_saturate$8$next ; + always @(posedge coresync_clk) + \spr_op__SV_Ptype$9 <= \spr_op__SV_Ptype$9$next ; always @(posedge coresync_clk) \muxid$1 <= \muxid$1$next ; always @(posedge coresync_clk) @@ -165206,32 +177164,40 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s ); spr_main spr_main ( .fast1(spr_main_fast1), - .\fast1$7 (\spr_main_fast1$17 ), + .\fast1$11 (\spr_main_fast1$25 ), .fast1_ok(spr_main_fast1_ok), .muxid(spr_main_muxid), - .\muxid$1 (\spr_main_muxid$11 ), + .\muxid$1 (\spr_main_muxid$15 ), .o(spr_main_o), .o_ok(spr_main_o_ok), .ra(spr_main_ra), .spr1(spr_main_spr1), - .\spr1$6 (\spr_main_spr1$16 ), + .\spr1$10 (\spr_main_spr1$24 ), .spr1_ok(spr_main_spr1_ok), + .spr_op__SV_Ptype(spr_main_spr_op__SV_Ptype), + .\spr_op__SV_Ptype$9 (\spr_main_spr_op__SV_Ptype$23 ), .spr_op__fn_unit(spr_main_spr_op__fn_unit), - .\spr_op__fn_unit$3 (\spr_main_spr_op__fn_unit$13 ), + .\spr_op__fn_unit$3 (\spr_main_spr_op__fn_unit$17 ), .spr_op__insn(spr_main_spr_op__insn), - .\spr_op__insn$4 (\spr_main_spr_op__insn$14 ), + .\spr_op__insn$4 (\spr_main_spr_op__insn$18 ), .spr_op__insn_type(spr_main_spr_op__insn_type), - .\spr_op__insn_type$2 (\spr_main_spr_op__insn_type$12 ), + .\spr_op__insn_type$2 (\spr_main_spr_op__insn_type$16 ), .spr_op__is_32bit(spr_main_spr_op__is_32bit), - .\spr_op__is_32bit$5 (\spr_main_spr_op__is_32bit$15 ), + .\spr_op__is_32bit$5 (\spr_main_spr_op__is_32bit$19 ), + .spr_op__sv_pred_dz(spr_main_spr_op__sv_pred_dz), + .\spr_op__sv_pred_dz$7 (\spr_main_spr_op__sv_pred_dz$21 ), + .spr_op__sv_pred_sz(spr_main_spr_op__sv_pred_sz), + .\spr_op__sv_pred_sz$6 (\spr_main_spr_op__sv_pred_sz$20 ), + .spr_op__sv_saturate(spr_main_spr_op__sv_saturate), + .\spr_op__sv_saturate$8 (\spr_main_spr_op__sv_saturate$22 ), .xer_ca(spr_main_xer_ca), - .\xer_ca$10 (\spr_main_xer_ca$20 ), + .\xer_ca$14 (\spr_main_xer_ca$28 ), .xer_ca_ok(spr_main_xer_ca_ok), .xer_ov(spr_main_xer_ov), - .\xer_ov$9 (\spr_main_xer_ov$19 ), + .\xer_ov$13 (\spr_main_xer_ov$27 ), .xer_ov_ok(spr_main_xer_ov_ok), .xer_so(spr_main_xer_so), - .\xer_so$8 (\spr_main_xer_so$18 ), + .\xer_so$12 (\spr_main_xer_so$26 ), .xer_so_ok(spr_main_xer_so_ok) ); always @* begin @@ -165246,7 +177212,7 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -165259,10 +177225,10 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \muxid$1$next = \muxid$24 ; + \muxid$1$next = \muxid$32 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \muxid$1$next = \muxid$24 ; + \muxid$1$next = \muxid$32 ; endcase end always @* begin @@ -165271,14 +177237,18 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s \spr_op__fn_unit$3$next = \spr_op__fn_unit$3 ; \spr_op__insn$4$next = \spr_op__insn$4 ; \spr_op__is_32bit$5$next = \spr_op__is_32bit$5 ; + \spr_op__sv_pred_sz$6$next = \spr_op__sv_pred_sz$6 ; + \spr_op__sv_pred_dz$7$next = \spr_op__sv_pred_dz$7 ; + \spr_op__sv_saturate$8$next = \spr_op__sv_saturate$8 ; + \spr_op__SV_Ptype$9$next = \spr_op__SV_Ptype$9 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \spr_op__is_32bit$5$next , \spr_op__insn$4$next , \spr_op__fn_unit$3$next , \spr_op__insn_type$2$next } = { \spr_op__is_32bit$28 , \spr_op__insn$27 , \spr_op__fn_unit$26 , \spr_op__insn_type$25 }; + { \spr_op__SV_Ptype$9$next , \spr_op__sv_saturate$8$next , \spr_op__sv_pred_dz$7$next , \spr_op__sv_pred_sz$6$next , \spr_op__is_32bit$5$next , \spr_op__insn$4$next , \spr_op__fn_unit$3$next , \spr_op__insn_type$2$next } = { \spr_op__SV_Ptype$40 , \spr_op__sv_saturate$39 , \spr_op__sv_pred_dz$38 , \spr_op__sv_pred_sz$37 , \spr_op__is_32bit$36 , \spr_op__insn$35 , \spr_op__fn_unit$34 , \spr_op__insn_type$33 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \spr_op__is_32bit$5$next , \spr_op__insn$4$next , \spr_op__fn_unit$3$next , \spr_op__insn_type$2$next } = { \spr_op__is_32bit$28 , \spr_op__insn$27 , \spr_op__fn_unit$26 , \spr_op__insn_type$25 }; + { \spr_op__SV_Ptype$9$next , \spr_op__sv_saturate$8$next , \spr_op__sv_pred_dz$7$next , \spr_op__sv_pred_sz$6$next , \spr_op__is_32bit$5$next , \spr_op__insn$4$next , \spr_op__fn_unit$3$next , \spr_op__insn_type$2$next } = { \spr_op__SV_Ptype$40 , \spr_op__sv_saturate$39 , \spr_op__sv_pred_dz$38 , \spr_op__sv_pred_sz$37 , \spr_op__is_32bit$36 , \spr_op__insn$35 , \spr_op__fn_unit$34 , \spr_op__insn_type$33 }; endcase end always @* begin @@ -165289,12 +177259,12 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \o_ok$next , \o$next } = { \o_ok$30 , \o$29 }; + { \o_ok$next , \o$next } = { \o_ok$42 , \o$41 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \o_ok$next , \o$next } = { \o_ok$30 , \o$29 }; + { \o_ok$next , \o$next } = { \o_ok$42 , \o$41 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \o_ok$next = 1'h0; @@ -165302,18 +177272,18 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s end always @* begin if (\initial ) begin end - \spr1$6$next = \spr1$6 ; + \spr1$10$next = \spr1$10 ; \spr1_ok$next = spr1_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \spr1_ok$next , \spr1$6$next } = { \spr1_ok$32 , \spr1$31 }; + { \spr1_ok$next , \spr1$10$next } = { \spr1_ok$44 , \spr1$43 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \spr1_ok$next , \spr1$6$next } = { \spr1_ok$32 , \spr1$31 }; + { \spr1_ok$next , \spr1$10$next } = { \spr1_ok$44 , \spr1$43 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \spr1_ok$next = 1'h0; @@ -165321,18 +177291,18 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s end always @* begin if (\initial ) begin end - \fast1$7$next = \fast1$7 ; + \fast1$11$next = \fast1$11 ; \fast1_ok$next = fast1_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \fast1_ok$next , \fast1$7$next } = { \fast1_ok$34 , \fast1$33 }; + { \fast1_ok$next , \fast1$11$next } = { \fast1_ok$46 , \fast1$45 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \fast1_ok$next , \fast1$7$next } = { \fast1_ok$34 , \fast1$33 }; + { \fast1_ok$next , \fast1$11$next } = { \fast1_ok$46 , \fast1$45 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \fast1_ok$next = 1'h0; @@ -165340,18 +177310,18 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s end always @* begin if (\initial ) begin end - \xer_so$8$next = \xer_so$8 ; + \xer_so$12$next = \xer_so$12 ; \xer_so_ok$next = xer_so_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \xer_so_ok$next , \xer_so$8$next } = { \xer_so_ok$36 , \xer_so$35 }; + { \xer_so_ok$next , \xer_so$12$next } = { \xer_so_ok$48 , \xer_so$47 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \xer_so_ok$next , \xer_so$8$next } = { \xer_so_ok$36 , \xer_so$35 }; + { \xer_so_ok$next , \xer_so$12$next } = { \xer_so_ok$48 , \xer_so$47 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \xer_so_ok$next = 1'h0; @@ -165359,18 +177329,18 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s end always @* begin if (\initial ) begin end - \xer_ov$9$next = \xer_ov$9 ; + \xer_ov$13$next = \xer_ov$13 ; \xer_ov_ok$next = xer_ov_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \xer_ov_ok$next , \xer_ov$9$next } = { \xer_ov_ok$38 , \xer_ov$37 }; + { \xer_ov_ok$next , \xer_ov$13$next } = { \xer_ov_ok$50 , \xer_ov$49 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \xer_ov_ok$next , \xer_ov$9$next } = { \xer_ov_ok$38 , \xer_ov$37 }; + { \xer_ov_ok$next , \xer_ov$13$next } = { \xer_ov_ok$50 , \xer_ov$49 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \xer_ov_ok$next = 1'h0; @@ -165378,18 +177348,18 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s end always @* begin if (\initial ) begin end - \xer_ca$10$next = \xer_ca$10 ; + \xer_ca$14$next = \xer_ca$14 ; \xer_ca_ok$next = xer_ca_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \xer_ca_ok$next , \xer_ca$10$next } = { \xer_ca_ok$40 , \xer_ca$39 }; + { \xer_ca_ok$next , \xer_ca$14$next } = { \xer_ca_ok$52 , \xer_ca$51 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \xer_ca_ok$next , \xer_ca$10$next } = { \xer_ca_ok$40 , \xer_ca$39 }; + { \xer_ca_ok$next , \xer_ca$14$next } = { \xer_ca_ok$52 , \xer_ca$51 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \xer_ca_ok$next = 1'h0; @@ -165397,143 +177367,167 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s end assign p_ready_o = n_i_rdy_data; assign n_valid_o = r_busy; - assign { \xer_ca_ok$40 , \xer_ca$39 } = { spr_main_xer_ca_ok, \spr_main_xer_ca$20 }; - assign { \xer_ov_ok$38 , \xer_ov$37 } = { spr_main_xer_ov_ok, \spr_main_xer_ov$19 }; - assign { \xer_so_ok$36 , \xer_so$35 } = { spr_main_xer_so_ok, \spr_main_xer_so$18 }; - assign { \fast1_ok$34 , \fast1$33 } = { spr_main_fast1_ok, \spr_main_fast1$17 }; - assign { \spr1_ok$32 , \spr1$31 } = { spr_main_spr1_ok, \spr_main_spr1$16 }; - assign { \o_ok$30 , \o$29 } = { spr_main_o_ok, spr_main_o }; - assign { \spr_op__is_32bit$28 , \spr_op__insn$27 , \spr_op__fn_unit$26 , \spr_op__insn_type$25 } = { \spr_main_spr_op__is_32bit$15 , \spr_main_spr_op__insn$14 , \spr_main_spr_op__fn_unit$13 , \spr_main_spr_op__insn_type$12 }; - assign \muxid$24 = \spr_main_muxid$11 ; - assign p_valid_i_p_ready_o = \$22 ; + assign { \xer_ca_ok$52 , \xer_ca$51 } = { spr_main_xer_ca_ok, \spr_main_xer_ca$28 }; + assign { \xer_ov_ok$50 , \xer_ov$49 } = { spr_main_xer_ov_ok, \spr_main_xer_ov$27 }; + assign { \xer_so_ok$48 , \xer_so$47 } = { spr_main_xer_so_ok, \spr_main_xer_so$26 }; + assign { \fast1_ok$46 , \fast1$45 } = { spr_main_fast1_ok, \spr_main_fast1$25 }; + assign { \spr1_ok$44 , \spr1$43 } = { spr_main_spr1_ok, \spr_main_spr1$24 }; + assign { \o_ok$42 , \o$41 } = { spr_main_o_ok, spr_main_o }; + assign { \spr_op__SV_Ptype$40 , \spr_op__sv_saturate$39 , \spr_op__sv_pred_dz$38 , \spr_op__sv_pred_sz$37 , \spr_op__is_32bit$36 , \spr_op__insn$35 , \spr_op__fn_unit$34 , \spr_op__insn_type$33 } = { \spr_main_spr_op__SV_Ptype$23 , \spr_main_spr_op__sv_saturate$22 , \spr_main_spr_op__sv_pred_dz$21 , \spr_main_spr_op__sv_pred_sz$20 , \spr_main_spr_op__is_32bit$19 , \spr_main_spr_op__insn$18 , \spr_main_spr_op__fn_unit$17 , \spr_main_spr_op__insn_type$16 }; + assign \muxid$32 = \spr_main_muxid$15 ; + assign p_valid_i_p_ready_o = \$30 ; assign n_i_rdy_data = n_ready_i; - assign \p_valid_i$21 = p_valid_i; + assign \p_valid_i$29 = p_valid_i; assign spr_main_xer_ca = xer_ca; assign spr_main_xer_ov = xer_ov; assign spr_main_xer_so = xer_so; assign spr_main_fast1 = fast1; assign spr_main_spr1 = spr1; assign spr_main_ra = ra; - assign { spr_main_spr_op__is_32bit, spr_main_spr_op__insn, spr_main_spr_op__fn_unit, spr_main_spr_op__insn_type } = { spr_op__is_32bit, spr_op__insn, spr_op__fn_unit, spr_op__insn_type }; + assign { spr_main_spr_op__SV_Ptype, spr_main_spr_op__sv_saturate, spr_main_spr_op__sv_pred_dz, spr_main_spr_op__sv_pred_sz, spr_main_spr_op__is_32bit, spr_main_spr_op__insn, spr_main_spr_op__fn_unit, spr_main_spr_op__insn_type } = { spr_op__SV_Ptype, spr_op__sv_saturate, spr_op__sv_pred_dz, spr_op__sv_pred_sz, spr_op__is_32bit, spr_op__insn, spr_op__fn_unit, spr_op__insn_type }; assign spr_main_muxid = muxid; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1" *) (* generator = "nMigen" *) -module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, o, o_ok, cr_a, cr_a_ok, xer_ca, xer_ca_ok, xer_ov, xer_ov_ok, xer_so, xer_so_ok, p_valid_i, p_ready_o, \muxid$1 , \alu_op__insn_type$2 , \alu_op__fn_unit$3 , \alu_op__imm_data__data$4 , \alu_op__imm_data__ok$5 , \alu_op__rc__rc$6 , \alu_op__rc__ok$7 , \alu_op__oe__oe$8 , \alu_op__oe__ok$9 , \alu_op__invert_in$10 , \alu_op__zero_a$11 , \alu_op__invert_out$12 , \alu_op__write_cr0$13 , \alu_op__input_carry$14 , \alu_op__output_carry$15 , \alu_op__is_32bit$16 , \alu_op__is_signed$17 , \alu_op__data_len$18 , \alu_op__insn$19 , ra, rb, \xer_so$20 , \xer_ca$21 , coresync_clk); +module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, alu_op__sv_pred_sz, alu_op__sv_pred_dz, alu_op__sv_saturate, alu_op__SV_Ptype, o, o_ok, cr_a, cr_a_ok, xer_ca, xer_ca_ok, xer_ov, xer_ov_ok, xer_so, xer_so_ok, p_valid_i, p_ready_o, \muxid$1 , \alu_op__insn_type$2 , \alu_op__fn_unit$3 , \alu_op__imm_data__data$4 , \alu_op__imm_data__ok$5 , \alu_op__rc__rc$6 , \alu_op__rc__ok$7 , \alu_op__oe__oe$8 , \alu_op__oe__ok$9 , \alu_op__invert_in$10 , \alu_op__zero_a$11 , \alu_op__invert_out$12 , \alu_op__write_cr0$13 , \alu_op__input_carry$14 , \alu_op__output_carry$15 , \alu_op__is_32bit$16 , \alu_op__is_signed$17 , \alu_op__data_len$18 , \alu_op__insn$19 , \alu_op__sv_pred_sz$20 , \alu_op__sv_pred_dz$21 , \alu_op__sv_saturate$22 , \alu_op__SV_Ptype$23 , ra, rb, \xer_so$24 , \xer_ca$25 , coresync_clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) - wire \$67 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \$79 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] alu_op__SV_Ptype; + reg [1:0] alu_op__SV_Ptype = 2'h0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \alu_op__SV_Ptype$103 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] \alu_op__SV_Ptype$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \alu_op__SV_Ptype$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [3:0] alu_op__data_len; reg [3:0] alu_op__data_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [3:0] \alu_op__data_len$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [3:0] \alu_op__data_len$86 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [3:0] \alu_op__data_len$98 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [3:0] \alu_op__data_len$next ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] alu_op__fn_unit; - reg [13:0] alu_op__fn_unit = 14'h0000; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] alu_op__fn_unit; + reg [14:0] alu_op__fn_unit = 15'h0000; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] \alu_op__fn_unit$3 ; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] \alu_op__fn_unit$3 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \alu_op__fn_unit$71 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] \alu_op__fn_unit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \alu_op__fn_unit$83 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] \alu_op__fn_unit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] alu_op__imm_data__data; reg [63:0] alu_op__imm_data__data = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] \alu_op__imm_data__data$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \alu_op__imm_data__data$72 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \alu_op__imm_data__data$84 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] \alu_op__imm_data__data$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output alu_op__imm_data__ok; reg alu_op__imm_data__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \alu_op__imm_data__ok$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__imm_data__ok$73 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__imm_data__ok$85 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_op__imm_data__ok$next ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [1:0] alu_op__input_carry; reg [1:0] alu_op__input_carry = 2'h0; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] \alu_op__input_carry$14 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [1:0] \alu_op__input_carry$82 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \alu_op__input_carry$94 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [1:0] \alu_op__input_carry$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] alu_op__insn; reg [31:0] alu_op__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] \alu_op__insn$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \alu_op__insn$87 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \alu_op__insn$99 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] \alu_op__insn$next ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -165610,7 +177604,9 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] alu_op__insn_type; reg [6:0] alu_op__insn_type = 7'h00; (* enum_base_type = "MicrOp" *) @@ -165688,7 +177684,9 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] \alu_op__insn_type$2 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -165765,189 +177763,244 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \alu_op__insn_type$70 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \alu_op__insn_type$82 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] \alu_op__insn_type$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output alu_op__invert_in; reg alu_op__invert_in = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \alu_op__invert_in$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__invert_in$78 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__invert_in$90 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_op__invert_in$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output alu_op__invert_out; reg alu_op__invert_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \alu_op__invert_out$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__invert_out$80 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__invert_out$92 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_op__invert_out$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output alu_op__is_32bit; reg alu_op__is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \alu_op__is_32bit$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__is_32bit$84 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__is_32bit$96 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_op__is_32bit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output alu_op__is_signed; reg alu_op__is_signed = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \alu_op__is_signed$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__is_signed$85 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__is_signed$97 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_op__is_signed$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output alu_op__oe__oe; reg alu_op__oe__oe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__oe__oe$76 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \alu_op__oe__oe$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__oe__oe$88 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_op__oe__oe$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output alu_op__oe__ok; reg alu_op__oe__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__oe__ok$77 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__oe__ok$89 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \alu_op__oe__ok$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_op__oe__ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output alu_op__output_carry; reg alu_op__output_carry = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \alu_op__output_carry$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__output_carry$83 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__output_carry$95 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_op__output_carry$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output alu_op__rc__ok; reg alu_op__rc__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \alu_op__rc__ok$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__rc__ok$75 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__rc__ok$87 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_op__rc__ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output alu_op__rc__rc; reg alu_op__rc__rc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \alu_op__rc__rc$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__rc__rc$74 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__rc__rc$86 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_op__rc__rc$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output alu_op__sv_pred_dz; + reg alu_op__sv_pred_dz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__sv_pred_dz$101 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input \alu_op__sv_pred_dz$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \alu_op__sv_pred_dz$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output alu_op__sv_pred_sz; + reg alu_op__sv_pred_sz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__sv_pred_sz$100 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input \alu_op__sv_pred_sz$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \alu_op__sv_pred_sz$next ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] alu_op__sv_saturate; + reg [1:0] alu_op__sv_saturate = 2'h0; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \alu_op__sv_saturate$102 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] \alu_op__sv_saturate$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \alu_op__sv_saturate$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output alu_op__write_cr0; reg alu_op__write_cr0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \alu_op__write_cr0$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__write_cr0$81 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__write_cr0$93 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_op__write_cr0$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output alu_op__zero_a; reg alu_op__zero_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \alu_op__zero_a$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__zero_a$79 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__zero_a$91 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_op__zero_a$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [3:0] cr_a; reg [3:0] cr_a = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [3:0] \cr_a$90 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [3:0] \cr_a$106 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [3:0] \cr_a$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_a_ok; reg cr_a_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \cr_a_ok$91 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \cr_a_ok$107 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \cr_a_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] input_alu_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \input_alu_op__SV_Ptype$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [3:0] input_alu_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [3:0] \input_alu_op__data_len$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [3:0] \input_alu_op__data_len$43 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] input_alu_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] input_alu_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \input_alu_op__fn_unit$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \input_alu_op__fn_unit$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] input_alu_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \input_alu_op__imm_data__data$25 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \input_alu_op__imm_data__data$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_alu_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_alu_op__imm_data__ok$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_alu_op__imm_data__ok$30 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [1:0] input_alu_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [1:0] \input_alu_op__input_carry$35 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \input_alu_op__input_carry$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] input_alu_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \input_alu_op__insn$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \input_alu_op__insn$44 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -166023,7 +178076,9 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] input_alu_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -166100,134 +178155,170 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \input_alu_op__insn_type$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \input_alu_op__insn_type$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_alu_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_alu_op__invert_in$31 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_alu_op__invert_in$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_alu_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_alu_op__invert_out$33 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_alu_op__invert_out$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_alu_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_alu_op__is_32bit$37 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_alu_op__is_32bit$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_alu_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_alu_op__is_signed$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_alu_op__is_signed$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_alu_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_alu_op__oe__oe$29 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_alu_op__oe__oe$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_alu_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_alu_op__oe__ok$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_alu_op__oe__ok$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_alu_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_alu_op__output_carry$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_alu_op__output_carry$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_alu_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_alu_op__rc__ok$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_alu_op__rc__ok$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_alu_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_alu_op__rc__rc$27 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_alu_op__rc__rc$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire input_alu_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_alu_op__sv_pred_dz$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire input_alu_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_alu_op__sv_pred_sz$45 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] input_alu_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \input_alu_op__sv_saturate$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_alu_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_alu_op__write_cr0$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_alu_op__write_cr0$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_alu_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_alu_op__zero_a$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_alu_op__zero_a$36 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] input_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \input_muxid$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [1:0] \input_muxid$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] input_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \input_ra$41 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \input_ra$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] input_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \input_rb$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \input_rb$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [1:0] input_xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [1:0] \input_xer_ca$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [1:0] \input_xer_ca$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire input_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire \input_xer_so$43 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire \input_xer_so$51 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] main_alu_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \main_alu_op__SV_Ptype$75 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [3:0] main_alu_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [3:0] \main_alu_op__data_len$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [3:0] \main_alu_op__data_len$70 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] main_alu_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] main_alu_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \main_alu_op__fn_unit$47 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \main_alu_op__fn_unit$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] main_alu_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \main_alu_op__imm_data__data$48 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \main_alu_op__imm_data__data$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_alu_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_alu_op__imm_data__ok$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_alu_op__imm_data__ok$57 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [1:0] main_alu_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [1:0] \main_alu_op__input_carry$58 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \main_alu_op__input_carry$66 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] main_alu_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \main_alu_op__insn$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \main_alu_op__insn$71 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -166303,7 +178394,9 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] main_alu_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -166380,89 +178473,111 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \main_alu_op__insn_type$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \main_alu_op__insn_type$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_alu_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_alu_op__invert_in$54 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_alu_op__invert_in$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_alu_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_alu_op__invert_out$56 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_alu_op__invert_out$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_alu_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_alu_op__is_32bit$60 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_alu_op__is_32bit$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_alu_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_alu_op__is_signed$61 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_alu_op__is_signed$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_alu_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_alu_op__oe__oe$52 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_alu_op__oe__oe$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_alu_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_alu_op__oe__ok$53 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_alu_op__oe__ok$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_alu_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_alu_op__output_carry$59 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_alu_op__output_carry$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_alu_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_alu_op__rc__ok$51 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_alu_op__rc__ok$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_alu_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_alu_op__rc__rc$50 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_alu_op__rc__rc$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire main_alu_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_alu_op__sv_pred_dz$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire main_alu_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_alu_op__sv_pred_sz$72 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] main_alu_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \main_alu_op__sv_saturate$74 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_alu_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_alu_op__write_cr0$57 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_alu_op__write_cr0$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_alu_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_alu_op__zero_a$55 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_alu_op__zero_a$63 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [3:0] main_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire main_cr_a_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] main_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \main_muxid$45 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \main_muxid$53 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] main_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire main_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] main_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] main_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [1:0] main_xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [1:0] \main_xer_ca$64 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [1:0] \main_xer_ca$76 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire main_xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [1:0] main_xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire main_xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire main_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \main_xer_so$65 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \main_xer_so$77 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] muxid; reg [1:0] muxid = 2'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] \muxid$1 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \muxid$69 ; + wire [1:0] \muxid$81 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) reg [1:0] \muxid$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *) @@ -166471,85 +178586,85 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] o; reg [63:0] o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \o$88 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \o$104 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [63:0] \o$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output o_ok; reg o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \o_ok$89 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \o_ok$105 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \o_ok$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) input p_valid_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *) - wire \p_valid_i$66 ; + wire \p_valid_i$78 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *) wire p_valid_i_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg r_busy = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg \r_busy$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [1:0] xer_ca; reg [1:0] xer_ca = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - input [1:0] \xer_ca$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [1:0] \xer_ca$92 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [1:0] \xer_ca$108 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + input [1:0] \xer_ca$25 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [1:0] \xer_ca$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ca_ok; reg xer_ca_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_ca_ok$93 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_ca_ok$109 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \xer_ca_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [1:0] xer_ov; reg [1:0] xer_ov = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [1:0] \xer_ov$94 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [1:0] \xer_ov$110 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [1:0] \xer_ov$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ov_ok; reg xer_ov_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_ov_ok$95 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_ov_ok$111 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \xer_ov_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_so; reg xer_so = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - input \xer_so$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_so$96 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_so$112 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + input \xer_so$24 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \xer_so$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_so_ok; reg xer_so_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_so_ok$97 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_so_ok$98 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_so_ok$113 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_so_ok$114 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \xer_so_ok$next ; - assign \$67 = \p_valid_i$66 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; + assign \$79 = \p_valid_i$78 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; always @(posedge coresync_clk) xer_so <= \xer_so$next ; always @(posedge coresync_clk) @@ -166606,110 +178721,134 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o alu_op__data_len <= \alu_op__data_len$next ; always @(posedge coresync_clk) alu_op__insn <= \alu_op__insn$next ; + always @(posedge coresync_clk) + alu_op__sv_pred_sz <= \alu_op__sv_pred_sz$next ; + always @(posedge coresync_clk) + alu_op__sv_pred_dz <= \alu_op__sv_pred_dz$next ; + always @(posedge coresync_clk) + alu_op__sv_saturate <= \alu_op__sv_saturate$next ; + always @(posedge coresync_clk) + alu_op__SV_Ptype <= \alu_op__SV_Ptype$next ; always @(posedge coresync_clk) muxid <= \muxid$next ; always @(posedge coresync_clk) r_busy <= \r_busy$next ; \input \input ( + .alu_op__SV_Ptype(input_alu_op__SV_Ptype), + .\alu_op__SV_Ptype$23 (\input_alu_op__SV_Ptype$48 ), .alu_op__data_len(input_alu_op__data_len), - .\alu_op__data_len$18 (\input_alu_op__data_len$39 ), + .\alu_op__data_len$18 (\input_alu_op__data_len$43 ), .alu_op__fn_unit(input_alu_op__fn_unit), - .\alu_op__fn_unit$3 (\input_alu_op__fn_unit$24 ), + .\alu_op__fn_unit$3 (\input_alu_op__fn_unit$28 ), .alu_op__imm_data__data(input_alu_op__imm_data__data), - .\alu_op__imm_data__data$4 (\input_alu_op__imm_data__data$25 ), + .\alu_op__imm_data__data$4 (\input_alu_op__imm_data__data$29 ), .alu_op__imm_data__ok(input_alu_op__imm_data__ok), - .\alu_op__imm_data__ok$5 (\input_alu_op__imm_data__ok$26 ), + .\alu_op__imm_data__ok$5 (\input_alu_op__imm_data__ok$30 ), .alu_op__input_carry(input_alu_op__input_carry), - .\alu_op__input_carry$14 (\input_alu_op__input_carry$35 ), + .\alu_op__input_carry$14 (\input_alu_op__input_carry$39 ), .alu_op__insn(input_alu_op__insn), - .\alu_op__insn$19 (\input_alu_op__insn$40 ), + .\alu_op__insn$19 (\input_alu_op__insn$44 ), .alu_op__insn_type(input_alu_op__insn_type), - .\alu_op__insn_type$2 (\input_alu_op__insn_type$23 ), + .\alu_op__insn_type$2 (\input_alu_op__insn_type$27 ), .alu_op__invert_in(input_alu_op__invert_in), - .\alu_op__invert_in$10 (\input_alu_op__invert_in$31 ), + .\alu_op__invert_in$10 (\input_alu_op__invert_in$35 ), .alu_op__invert_out(input_alu_op__invert_out), - .\alu_op__invert_out$12 (\input_alu_op__invert_out$33 ), + .\alu_op__invert_out$12 (\input_alu_op__invert_out$37 ), .alu_op__is_32bit(input_alu_op__is_32bit), - .\alu_op__is_32bit$16 (\input_alu_op__is_32bit$37 ), + .\alu_op__is_32bit$16 (\input_alu_op__is_32bit$41 ), .alu_op__is_signed(input_alu_op__is_signed), - .\alu_op__is_signed$17 (\input_alu_op__is_signed$38 ), + .\alu_op__is_signed$17 (\input_alu_op__is_signed$42 ), .alu_op__oe__oe(input_alu_op__oe__oe), - .\alu_op__oe__oe$8 (\input_alu_op__oe__oe$29 ), + .\alu_op__oe__oe$8 (\input_alu_op__oe__oe$33 ), .alu_op__oe__ok(input_alu_op__oe__ok), - .\alu_op__oe__ok$9 (\input_alu_op__oe__ok$30 ), + .\alu_op__oe__ok$9 (\input_alu_op__oe__ok$34 ), .alu_op__output_carry(input_alu_op__output_carry), - .\alu_op__output_carry$15 (\input_alu_op__output_carry$36 ), + .\alu_op__output_carry$15 (\input_alu_op__output_carry$40 ), .alu_op__rc__ok(input_alu_op__rc__ok), - .\alu_op__rc__ok$7 (\input_alu_op__rc__ok$28 ), + .\alu_op__rc__ok$7 (\input_alu_op__rc__ok$32 ), .alu_op__rc__rc(input_alu_op__rc__rc), - .\alu_op__rc__rc$6 (\input_alu_op__rc__rc$27 ), + .\alu_op__rc__rc$6 (\input_alu_op__rc__rc$31 ), + .alu_op__sv_pred_dz(input_alu_op__sv_pred_dz), + .\alu_op__sv_pred_dz$21 (\input_alu_op__sv_pred_dz$46 ), + .alu_op__sv_pred_sz(input_alu_op__sv_pred_sz), + .\alu_op__sv_pred_sz$20 (\input_alu_op__sv_pred_sz$45 ), + .alu_op__sv_saturate(input_alu_op__sv_saturate), + .\alu_op__sv_saturate$22 (\input_alu_op__sv_saturate$47 ), .alu_op__write_cr0(input_alu_op__write_cr0), - .\alu_op__write_cr0$13 (\input_alu_op__write_cr0$34 ), + .\alu_op__write_cr0$13 (\input_alu_op__write_cr0$38 ), .alu_op__zero_a(input_alu_op__zero_a), - .\alu_op__zero_a$11 (\input_alu_op__zero_a$32 ), + .\alu_op__zero_a$11 (\input_alu_op__zero_a$36 ), .muxid(input_muxid), - .\muxid$1 (\input_muxid$22 ), + .\muxid$1 (\input_muxid$26 ), .ra(input_ra), - .\ra$20 (\input_ra$41 ), + .\ra$24 (\input_ra$49 ), .rb(input_rb), - .\rb$21 (\input_rb$42 ), + .\rb$25 (\input_rb$50 ), .xer_ca(input_xer_ca), - .\xer_ca$23 (\input_xer_ca$44 ), + .\xer_ca$27 (\input_xer_ca$52 ), .xer_so(input_xer_so), - .\xer_so$22 (\input_xer_so$43 ) + .\xer_so$26 (\input_xer_so$51 ) ); main main ( + .alu_op__SV_Ptype(main_alu_op__SV_Ptype), + .\alu_op__SV_Ptype$23 (\main_alu_op__SV_Ptype$75 ), .alu_op__data_len(main_alu_op__data_len), - .\alu_op__data_len$18 (\main_alu_op__data_len$62 ), + .\alu_op__data_len$18 (\main_alu_op__data_len$70 ), .alu_op__fn_unit(main_alu_op__fn_unit), - .\alu_op__fn_unit$3 (\main_alu_op__fn_unit$47 ), + .\alu_op__fn_unit$3 (\main_alu_op__fn_unit$55 ), .alu_op__imm_data__data(main_alu_op__imm_data__data), - .\alu_op__imm_data__data$4 (\main_alu_op__imm_data__data$48 ), + .\alu_op__imm_data__data$4 (\main_alu_op__imm_data__data$56 ), .alu_op__imm_data__ok(main_alu_op__imm_data__ok), - .\alu_op__imm_data__ok$5 (\main_alu_op__imm_data__ok$49 ), + .\alu_op__imm_data__ok$5 (\main_alu_op__imm_data__ok$57 ), .alu_op__input_carry(main_alu_op__input_carry), - .\alu_op__input_carry$14 (\main_alu_op__input_carry$58 ), + .\alu_op__input_carry$14 (\main_alu_op__input_carry$66 ), .alu_op__insn(main_alu_op__insn), - .\alu_op__insn$19 (\main_alu_op__insn$63 ), + .\alu_op__insn$19 (\main_alu_op__insn$71 ), .alu_op__insn_type(main_alu_op__insn_type), - .\alu_op__insn_type$2 (\main_alu_op__insn_type$46 ), + .\alu_op__insn_type$2 (\main_alu_op__insn_type$54 ), .alu_op__invert_in(main_alu_op__invert_in), - .\alu_op__invert_in$10 (\main_alu_op__invert_in$54 ), + .\alu_op__invert_in$10 (\main_alu_op__invert_in$62 ), .alu_op__invert_out(main_alu_op__invert_out), - .\alu_op__invert_out$12 (\main_alu_op__invert_out$56 ), + .\alu_op__invert_out$12 (\main_alu_op__invert_out$64 ), .alu_op__is_32bit(main_alu_op__is_32bit), - .\alu_op__is_32bit$16 (\main_alu_op__is_32bit$60 ), + .\alu_op__is_32bit$16 (\main_alu_op__is_32bit$68 ), .alu_op__is_signed(main_alu_op__is_signed), - .\alu_op__is_signed$17 (\main_alu_op__is_signed$61 ), + .\alu_op__is_signed$17 (\main_alu_op__is_signed$69 ), .alu_op__oe__oe(main_alu_op__oe__oe), - .\alu_op__oe__oe$8 (\main_alu_op__oe__oe$52 ), + .\alu_op__oe__oe$8 (\main_alu_op__oe__oe$60 ), .alu_op__oe__ok(main_alu_op__oe__ok), - .\alu_op__oe__ok$9 (\main_alu_op__oe__ok$53 ), + .\alu_op__oe__ok$9 (\main_alu_op__oe__ok$61 ), .alu_op__output_carry(main_alu_op__output_carry), - .\alu_op__output_carry$15 (\main_alu_op__output_carry$59 ), + .\alu_op__output_carry$15 (\main_alu_op__output_carry$67 ), .alu_op__rc__ok(main_alu_op__rc__ok), - .\alu_op__rc__ok$7 (\main_alu_op__rc__ok$51 ), + .\alu_op__rc__ok$7 (\main_alu_op__rc__ok$59 ), .alu_op__rc__rc(main_alu_op__rc__rc), - .\alu_op__rc__rc$6 (\main_alu_op__rc__rc$50 ), + .\alu_op__rc__rc$6 (\main_alu_op__rc__rc$58 ), + .alu_op__sv_pred_dz(main_alu_op__sv_pred_dz), + .\alu_op__sv_pred_dz$21 (\main_alu_op__sv_pred_dz$73 ), + .alu_op__sv_pred_sz(main_alu_op__sv_pred_sz), + .\alu_op__sv_pred_sz$20 (\main_alu_op__sv_pred_sz$72 ), + .alu_op__sv_saturate(main_alu_op__sv_saturate), + .\alu_op__sv_saturate$22 (\main_alu_op__sv_saturate$74 ), .alu_op__write_cr0(main_alu_op__write_cr0), - .\alu_op__write_cr0$13 (\main_alu_op__write_cr0$57 ), + .\alu_op__write_cr0$13 (\main_alu_op__write_cr0$65 ), .alu_op__zero_a(main_alu_op__zero_a), - .\alu_op__zero_a$11 (\main_alu_op__zero_a$55 ), + .\alu_op__zero_a$11 (\main_alu_op__zero_a$63 ), .cr_a(main_cr_a), .cr_a_ok(main_cr_a_ok), .muxid(main_muxid), - .\muxid$1 (\main_muxid$45 ), + .\muxid$1 (\main_muxid$53 ), .o(main_o), .o_ok(main_o_ok), .ra(main_ra), .rb(main_rb), .xer_ca(main_xer_ca), - .\xer_ca$20 (\main_xer_ca$64 ), + .\xer_ca$24 (\main_xer_ca$76 ), .xer_ca_ok(main_xer_ca_ok), .xer_ov(main_xer_ov), .xer_ov_ok(main_xer_ov_ok), .xer_so(main_xer_so), - .\xer_so$21 (\main_xer_so$65 ) + .\xer_so$25 (\main_xer_so$77 ) ); \n$2 n ( .n_ready_i(n_ready_i), @@ -166719,6 +178858,25 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o .p_ready_o(p_ready_o), .p_valid_i(p_valid_i) ); + always @* begin + if (\initial ) begin end + \o$next = o; + \o_ok$next = o_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \o_ok$next , \o$next } = { \o_ok$105 , \o$104 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \o_ok$next , \o$next } = { \o_ok$105 , \o$104 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + casez (coresync_rst) + 1'h1: + \o_ok$next = 1'h0; + endcase + end always @* begin if (\initial ) begin end \cr_a$next = cr_a; @@ -166727,12 +178885,12 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$91 , \cr_a$90 }; + { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$107 , \cr_a$106 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$91 , \cr_a$90 }; + { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$107 , \cr_a$106 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \cr_a_ok$next = 1'h0; @@ -166746,12 +178904,12 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \xer_ca_ok$next , \xer_ca$next } = { \xer_ca_ok$93 , \xer_ca$92 }; + { \xer_ca_ok$next , \xer_ca$next } = { \xer_ca_ok$109 , \xer_ca$108 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \xer_ca_ok$next , \xer_ca$next } = { \xer_ca_ok$93 , \xer_ca$92 }; + { \xer_ca_ok$next , \xer_ca$next } = { \xer_ca_ok$109 , \xer_ca$108 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \xer_ca_ok$next = 1'h0; @@ -166765,12 +178923,12 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$95 , \xer_ov$94 }; + { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$111 , \xer_ov$110 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$95 , \xer_ov$94 }; + { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$111 , \xer_ov$110 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \xer_ov_ok$next = 1'h0; @@ -166784,12 +178942,12 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$97 , \xer_so$96 }; + { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$113 , \xer_so$112 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$97 , \xer_so$96 }; + { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$113 , \xer_so$112 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \xer_so_ok$next = 1'h0; @@ -166807,7 +178965,7 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -166820,10 +178978,10 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \muxid$next = \muxid$69 ; + \muxid$next = \muxid$81 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \muxid$next = \muxid$69 ; + \muxid$next = \muxid$81 ; endcase end always @* begin @@ -166846,16 +179004,20 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o \alu_op__is_signed$next = alu_op__is_signed; \alu_op__data_len$next = alu_op__data_len; \alu_op__insn$next = alu_op__insn; + \alu_op__sv_pred_sz$next = alu_op__sv_pred_sz; + \alu_op__sv_pred_dz$next = alu_op__sv_pred_dz; + \alu_op__sv_saturate$next = alu_op__sv_saturate; + \alu_op__SV_Ptype$next = alu_op__SV_Ptype; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \alu_op__insn$next , \alu_op__data_len$next , \alu_op__is_signed$next , \alu_op__is_32bit$next , \alu_op__output_carry$next , \alu_op__input_carry$next , \alu_op__write_cr0$next , \alu_op__invert_out$next , \alu_op__zero_a$next , \alu_op__invert_in$next , \alu_op__oe__ok$next , \alu_op__oe__oe$next , \alu_op__rc__ok$next , \alu_op__rc__rc$next , \alu_op__imm_data__ok$next , \alu_op__imm_data__data$next , \alu_op__fn_unit$next , \alu_op__insn_type$next } = { \alu_op__insn$87 , \alu_op__data_len$86 , \alu_op__is_signed$85 , \alu_op__is_32bit$84 , \alu_op__output_carry$83 , \alu_op__input_carry$82 , \alu_op__write_cr0$81 , \alu_op__invert_out$80 , \alu_op__zero_a$79 , \alu_op__invert_in$78 , \alu_op__oe__ok$77 , \alu_op__oe__oe$76 , \alu_op__rc__ok$75 , \alu_op__rc__rc$74 , \alu_op__imm_data__ok$73 , \alu_op__imm_data__data$72 , \alu_op__fn_unit$71 , \alu_op__insn_type$70 }; + { \alu_op__SV_Ptype$next , \alu_op__sv_saturate$next , \alu_op__sv_pred_dz$next , \alu_op__sv_pred_sz$next , \alu_op__insn$next , \alu_op__data_len$next , \alu_op__is_signed$next , \alu_op__is_32bit$next , \alu_op__output_carry$next , \alu_op__input_carry$next , \alu_op__write_cr0$next , \alu_op__invert_out$next , \alu_op__zero_a$next , \alu_op__invert_in$next , \alu_op__oe__ok$next , \alu_op__oe__oe$next , \alu_op__rc__ok$next , \alu_op__rc__rc$next , \alu_op__imm_data__ok$next , \alu_op__imm_data__data$next , \alu_op__fn_unit$next , \alu_op__insn_type$next } = { \alu_op__SV_Ptype$103 , \alu_op__sv_saturate$102 , \alu_op__sv_pred_dz$101 , \alu_op__sv_pred_sz$100 , \alu_op__insn$99 , \alu_op__data_len$98 , \alu_op__is_signed$97 , \alu_op__is_32bit$96 , \alu_op__output_carry$95 , \alu_op__input_carry$94 , \alu_op__write_cr0$93 , \alu_op__invert_out$92 , \alu_op__zero_a$91 , \alu_op__invert_in$90 , \alu_op__oe__ok$89 , \alu_op__oe__oe$88 , \alu_op__rc__ok$87 , \alu_op__rc__rc$86 , \alu_op__imm_data__ok$85 , \alu_op__imm_data__data$84 , \alu_op__fn_unit$83 , \alu_op__insn_type$82 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \alu_op__insn$next , \alu_op__data_len$next , \alu_op__is_signed$next , \alu_op__is_32bit$next , \alu_op__output_carry$next , \alu_op__input_carry$next , \alu_op__write_cr0$next , \alu_op__invert_out$next , \alu_op__zero_a$next , \alu_op__invert_in$next , \alu_op__oe__ok$next , \alu_op__oe__oe$next , \alu_op__rc__ok$next , \alu_op__rc__rc$next , \alu_op__imm_data__ok$next , \alu_op__imm_data__data$next , \alu_op__fn_unit$next , \alu_op__insn_type$next } = { \alu_op__insn$87 , \alu_op__data_len$86 , \alu_op__is_signed$85 , \alu_op__is_32bit$84 , \alu_op__output_carry$83 , \alu_op__input_carry$82 , \alu_op__write_cr0$81 , \alu_op__invert_out$80 , \alu_op__zero_a$79 , \alu_op__invert_in$78 , \alu_op__oe__ok$77 , \alu_op__oe__oe$76 , \alu_op__rc__ok$75 , \alu_op__rc__rc$74 , \alu_op__imm_data__ok$73 , \alu_op__imm_data__data$72 , \alu_op__fn_unit$71 , \alu_op__insn_type$70 }; + { \alu_op__SV_Ptype$next , \alu_op__sv_saturate$next , \alu_op__sv_pred_dz$next , \alu_op__sv_pred_sz$next , \alu_op__insn$next , \alu_op__data_len$next , \alu_op__is_signed$next , \alu_op__is_32bit$next , \alu_op__output_carry$next , \alu_op__input_carry$next , \alu_op__write_cr0$next , \alu_op__invert_out$next , \alu_op__zero_a$next , \alu_op__invert_in$next , \alu_op__oe__ok$next , \alu_op__oe__oe$next , \alu_op__rc__ok$next , \alu_op__rc__rc$next , \alu_op__imm_data__ok$next , \alu_op__imm_data__data$next , \alu_op__fn_unit$next , \alu_op__insn_type$next } = { \alu_op__SV_Ptype$103 , \alu_op__sv_saturate$102 , \alu_op__sv_pred_dz$101 , \alu_op__sv_pred_sz$100 , \alu_op__insn$99 , \alu_op__data_len$98 , \alu_op__is_signed$97 , \alu_op__is_32bit$96 , \alu_op__output_carry$95 , \alu_op__input_carry$94 , \alu_op__write_cr0$93 , \alu_op__invert_out$92 , \alu_op__zero_a$91 , \alu_op__invert_in$90 , \alu_op__oe__ok$89 , \alu_op__oe__oe$88 , \alu_op__rc__ok$87 , \alu_op__rc__rc$86 , \alu_op__imm_data__ok$85 , \alu_op__imm_data__data$84 , \alu_op__fn_unit$83 , \alu_op__insn_type$82 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -166868,158 +179030,153 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o end endcase end - always @* begin - if (\initial ) begin end - \o$next = o; - \o_ok$next = o_ok; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) - casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) - /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ - 2'b?1: - { \o_ok$next , \o$next } = { \o_ok$89 , \o$88 }; - /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ - 2'b1?: - { \o_ok$next , \o$next } = { \o_ok$89 , \o$88 }; - endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) - casez (coresync_rst) - 1'h1: - \o_ok$next = 1'h0; - endcase - end - assign \xer_so_ok$98 = 1'h0; + assign \xer_so_ok$114 = 1'h0; assign p_ready_o = n_i_rdy_data; assign n_valid_o = r_busy; - assign { \xer_so_ok$97 , \xer_so$96 } = { 1'h0, \main_xer_so$65 }; - assign { \xer_ov_ok$95 , \xer_ov$94 } = { main_xer_ov_ok, main_xer_ov }; - assign { \xer_ca_ok$93 , \xer_ca$92 } = { main_xer_ca_ok, \main_xer_ca$64 }; - assign { \cr_a_ok$91 , \cr_a$90 } = { main_cr_a_ok, main_cr_a }; - assign { \o_ok$89 , \o$88 } = { main_o_ok, main_o }; - assign { \alu_op__insn$87 , \alu_op__data_len$86 , \alu_op__is_signed$85 , \alu_op__is_32bit$84 , \alu_op__output_carry$83 , \alu_op__input_carry$82 , \alu_op__write_cr0$81 , \alu_op__invert_out$80 , \alu_op__zero_a$79 , \alu_op__invert_in$78 , \alu_op__oe__ok$77 , \alu_op__oe__oe$76 , \alu_op__rc__ok$75 , \alu_op__rc__rc$74 , \alu_op__imm_data__ok$73 , \alu_op__imm_data__data$72 , \alu_op__fn_unit$71 , \alu_op__insn_type$70 } = { \main_alu_op__insn$63 , \main_alu_op__data_len$62 , \main_alu_op__is_signed$61 , \main_alu_op__is_32bit$60 , \main_alu_op__output_carry$59 , \main_alu_op__input_carry$58 , \main_alu_op__write_cr0$57 , \main_alu_op__invert_out$56 , \main_alu_op__zero_a$55 , \main_alu_op__invert_in$54 , \main_alu_op__oe__ok$53 , \main_alu_op__oe__oe$52 , \main_alu_op__rc__ok$51 , \main_alu_op__rc__rc$50 , \main_alu_op__imm_data__ok$49 , \main_alu_op__imm_data__data$48 , \main_alu_op__fn_unit$47 , \main_alu_op__insn_type$46 }; - assign \muxid$69 = \main_muxid$45 ; - assign p_valid_i_p_ready_o = \$67 ; + assign { \xer_so_ok$113 , \xer_so$112 } = { 1'h0, \main_xer_so$77 }; + assign { \xer_ov_ok$111 , \xer_ov$110 } = { main_xer_ov_ok, main_xer_ov }; + assign { \xer_ca_ok$109 , \xer_ca$108 } = { main_xer_ca_ok, \main_xer_ca$76 }; + assign { \cr_a_ok$107 , \cr_a$106 } = { main_cr_a_ok, main_cr_a }; + assign { \o_ok$105 , \o$104 } = { main_o_ok, main_o }; + assign { \alu_op__SV_Ptype$103 , \alu_op__sv_saturate$102 , \alu_op__sv_pred_dz$101 , \alu_op__sv_pred_sz$100 , \alu_op__insn$99 , \alu_op__data_len$98 , \alu_op__is_signed$97 , \alu_op__is_32bit$96 , \alu_op__output_carry$95 , \alu_op__input_carry$94 , \alu_op__write_cr0$93 , \alu_op__invert_out$92 , \alu_op__zero_a$91 , \alu_op__invert_in$90 , \alu_op__oe__ok$89 , \alu_op__oe__oe$88 , \alu_op__rc__ok$87 , \alu_op__rc__rc$86 , \alu_op__imm_data__ok$85 , \alu_op__imm_data__data$84 , \alu_op__fn_unit$83 , \alu_op__insn_type$82 } = { \main_alu_op__SV_Ptype$75 , \main_alu_op__sv_saturate$74 , \main_alu_op__sv_pred_dz$73 , \main_alu_op__sv_pred_sz$72 , \main_alu_op__insn$71 , \main_alu_op__data_len$70 , \main_alu_op__is_signed$69 , \main_alu_op__is_32bit$68 , \main_alu_op__output_carry$67 , \main_alu_op__input_carry$66 , \main_alu_op__write_cr0$65 , \main_alu_op__invert_out$64 , \main_alu_op__zero_a$63 , \main_alu_op__invert_in$62 , \main_alu_op__oe__ok$61 , \main_alu_op__oe__oe$60 , \main_alu_op__rc__ok$59 , \main_alu_op__rc__rc$58 , \main_alu_op__imm_data__ok$57 , \main_alu_op__imm_data__data$56 , \main_alu_op__fn_unit$55 , \main_alu_op__insn_type$54 }; + assign \muxid$81 = \main_muxid$53 ; + assign p_valid_i_p_ready_o = \$79 ; assign n_i_rdy_data = n_ready_i; - assign \p_valid_i$66 = p_valid_i; - assign main_xer_ca = \input_xer_ca$44 ; - assign main_xer_so = \input_xer_so$43 ; - assign main_rb = \input_rb$42 ; - assign main_ra = \input_ra$41 ; - assign { main_alu_op__insn, main_alu_op__data_len, main_alu_op__is_signed, main_alu_op__is_32bit, main_alu_op__output_carry, main_alu_op__input_carry, main_alu_op__write_cr0, main_alu_op__invert_out, main_alu_op__zero_a, main_alu_op__invert_in, main_alu_op__oe__ok, main_alu_op__oe__oe, main_alu_op__rc__ok, main_alu_op__rc__rc, main_alu_op__imm_data__ok, main_alu_op__imm_data__data, main_alu_op__fn_unit, main_alu_op__insn_type } = { \input_alu_op__insn$40 , \input_alu_op__data_len$39 , \input_alu_op__is_signed$38 , \input_alu_op__is_32bit$37 , \input_alu_op__output_carry$36 , \input_alu_op__input_carry$35 , \input_alu_op__write_cr0$34 , \input_alu_op__invert_out$33 , \input_alu_op__zero_a$32 , \input_alu_op__invert_in$31 , \input_alu_op__oe__ok$30 , \input_alu_op__oe__oe$29 , \input_alu_op__rc__ok$28 , \input_alu_op__rc__rc$27 , \input_alu_op__imm_data__ok$26 , \input_alu_op__imm_data__data$25 , \input_alu_op__fn_unit$24 , \input_alu_op__insn_type$23 }; - assign main_muxid = \input_muxid$22 ; - assign input_xer_ca = \xer_ca$21 ; - assign input_xer_so = \xer_so$20 ; + assign \p_valid_i$78 = p_valid_i; + assign main_xer_ca = \input_xer_ca$52 ; + assign main_xer_so = \input_xer_so$51 ; + assign main_rb = \input_rb$50 ; + assign main_ra = \input_ra$49 ; + assign { main_alu_op__SV_Ptype, main_alu_op__sv_saturate, main_alu_op__sv_pred_dz, main_alu_op__sv_pred_sz, main_alu_op__insn, main_alu_op__data_len, main_alu_op__is_signed, main_alu_op__is_32bit, main_alu_op__output_carry, main_alu_op__input_carry, main_alu_op__write_cr0, main_alu_op__invert_out, main_alu_op__zero_a, main_alu_op__invert_in, main_alu_op__oe__ok, main_alu_op__oe__oe, main_alu_op__rc__ok, main_alu_op__rc__rc, main_alu_op__imm_data__ok, main_alu_op__imm_data__data, main_alu_op__fn_unit, main_alu_op__insn_type } = { \input_alu_op__SV_Ptype$48 , \input_alu_op__sv_saturate$47 , \input_alu_op__sv_pred_dz$46 , \input_alu_op__sv_pred_sz$45 , \input_alu_op__insn$44 , \input_alu_op__data_len$43 , \input_alu_op__is_signed$42 , \input_alu_op__is_32bit$41 , \input_alu_op__output_carry$40 , \input_alu_op__input_carry$39 , \input_alu_op__write_cr0$38 , \input_alu_op__invert_out$37 , \input_alu_op__zero_a$36 , \input_alu_op__invert_in$35 , \input_alu_op__oe__ok$34 , \input_alu_op__oe__oe$33 , \input_alu_op__rc__ok$32 , \input_alu_op__rc__rc$31 , \input_alu_op__imm_data__ok$30 , \input_alu_op__imm_data__data$29 , \input_alu_op__fn_unit$28 , \input_alu_op__insn_type$27 }; + assign main_muxid = \input_muxid$26 ; + assign input_xer_ca = \xer_ca$25 ; + assign input_xer_so = \xer_so$24 ; assign input_rb = rb; assign input_ra = ra; - assign { input_alu_op__insn, input_alu_op__data_len, input_alu_op__is_signed, input_alu_op__is_32bit, input_alu_op__output_carry, input_alu_op__input_carry, input_alu_op__write_cr0, input_alu_op__invert_out, input_alu_op__zero_a, input_alu_op__invert_in, input_alu_op__oe__ok, input_alu_op__oe__oe, input_alu_op__rc__ok, input_alu_op__rc__rc, input_alu_op__imm_data__ok, input_alu_op__imm_data__data, input_alu_op__fn_unit, input_alu_op__insn_type } = { \alu_op__insn$19 , \alu_op__data_len$18 , \alu_op__is_signed$17 , \alu_op__is_32bit$16 , \alu_op__output_carry$15 , \alu_op__input_carry$14 , \alu_op__write_cr0$13 , \alu_op__invert_out$12 , \alu_op__zero_a$11 , \alu_op__invert_in$10 , \alu_op__oe__ok$9 , \alu_op__oe__oe$8 , \alu_op__rc__ok$7 , \alu_op__rc__rc$6 , \alu_op__imm_data__ok$5 , \alu_op__imm_data__data$4 , \alu_op__fn_unit$3 , \alu_op__insn_type$2 }; + assign { input_alu_op__SV_Ptype, input_alu_op__sv_saturate, input_alu_op__sv_pred_dz, input_alu_op__sv_pred_sz, input_alu_op__insn, input_alu_op__data_len, input_alu_op__is_signed, input_alu_op__is_32bit, input_alu_op__output_carry, input_alu_op__input_carry, input_alu_op__write_cr0, input_alu_op__invert_out, input_alu_op__zero_a, input_alu_op__invert_in, input_alu_op__oe__ok, input_alu_op__oe__oe, input_alu_op__rc__ok, input_alu_op__rc__rc, input_alu_op__imm_data__ok, input_alu_op__imm_data__data, input_alu_op__fn_unit, input_alu_op__insn_type } = { \alu_op__SV_Ptype$23 , \alu_op__sv_saturate$22 , \alu_op__sv_pred_dz$21 , \alu_op__sv_pred_sz$20 , \alu_op__insn$19 , \alu_op__data_len$18 , \alu_op__is_signed$17 , \alu_op__is_32bit$16 , \alu_op__output_carry$15 , \alu_op__input_carry$14 , \alu_op__write_cr0$13 , \alu_op__invert_out$12 , \alu_op__zero_a$11 , \alu_op__invert_in$10 , \alu_op__oe__ok$9 , \alu_op__oe__oe$8 , \alu_op__rc__ok$7 , \alu_op__rc__rc$6 , \alu_op__imm_data__ok$5 , \alu_op__imm_data__data$4 , \alu_op__fn_unit$3 , \alu_op__insn_type$2 }; assign input_muxid = \muxid$1 ; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1" *) (* generator = "nMigen" *) -module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, o, o_ok, cr_a, cr_a_ok, xer_so, xer_so_ok, xer_ca, xer_ca_ok, p_valid_i, p_ready_o, \muxid$1 , \sr_op__insn_type$2 , \sr_op__fn_unit$3 , \sr_op__imm_data__data$4 , \sr_op__imm_data__ok$5 , \sr_op__rc__rc$6 , \sr_op__rc__ok$7 , \sr_op__oe__oe$8 , \sr_op__oe__ok$9 , \sr_op__write_cr0$10 , \sr_op__invert_in$11 , \sr_op__input_carry$12 , \sr_op__output_carry$13 , \sr_op__input_cr$14 , \sr_op__output_cr$15 , \sr_op__is_32bit$16 , \sr_op__is_signed$17 , \sr_op__insn$18 , ra, rb, rc, \xer_so$19 , \xer_ca$20 , coresync_clk); +module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, sr_op__sv_pred_sz, sr_op__sv_pred_dz, sr_op__sv_saturate, sr_op__SV_Ptype, o, o_ok, cr_a, cr_a_ok, xer_so, xer_so_ok, xer_ca, xer_ca_ok, p_valid_i, p_ready_o, \muxid$1 , \sr_op__insn_type$2 , \sr_op__fn_unit$3 , \sr_op__imm_data__data$4 , \sr_op__imm_data__ok$5 , \sr_op__rc__rc$6 , \sr_op__rc__ok$7 , \sr_op__oe__oe$8 , \sr_op__oe__ok$9 , \sr_op__write_cr0$10 , \sr_op__invert_in$11 , \sr_op__input_carry$12 , \sr_op__output_carry$13 , \sr_op__input_cr$14 , \sr_op__output_cr$15 , \sr_op__is_32bit$16 , \sr_op__is_signed$17 , \sr_op__insn$18 , \sr_op__sv_pred_sz$19 , \sr_op__sv_pred_dz$20 , \sr_op__sv_saturate$21 , \sr_op__SV_Ptype$22 , ra, rb, rc, \xer_so$23 , \xer_ca$24 , coresync_clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) - wire \$65 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + wire \$77 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [3:0] cr_a; reg [3:0] cr_a = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [3:0] \cr_a$87 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [3:0] \cr_a$89 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [3:0] \cr_a$103 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [3:0] \cr_a$105 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [3:0] \cr_a$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_a_ok; reg cr_a_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \cr_a_ok$88 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \cr_a_ok$90 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \cr_a_ok$104 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \cr_a_ok$106 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \cr_a_ok$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] input_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \input_muxid$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [1:0] \input_muxid$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] input_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \input_ra$39 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \input_ra$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] input_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \input_rb$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \input_rb$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] input_rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \input_rc$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \input_rc$49 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] input_sr_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \input_sr_op__SV_Ptype$46 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] input_sr_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] input_sr_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \input_sr_op__fn_unit$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \input_sr_op__fn_unit$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] input_sr_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \input_sr_op__imm_data__data$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \input_sr_op__imm_data__data$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_sr_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_sr_op__imm_data__ok$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_sr_op__imm_data__ok$29 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [1:0] input_sr_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [1:0] \input_sr_op__input_carry$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \input_sr_op__input_carry$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_sr_op__input_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_sr_op__input_cr$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_sr_op__input_cr$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] input_sr_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \input_sr_op__insn$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \input_sr_op__insn$42 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -167095,7 +179252,9 @@ module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] input_sr_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -167172,132 +179331,168 @@ module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \input_sr_op__insn_type$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \input_sr_op__insn_type$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_sr_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_sr_op__invert_in$31 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_sr_op__invert_in$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_sr_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_sr_op__is_32bit$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_sr_op__is_32bit$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_sr_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_sr_op__is_signed$37 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_sr_op__is_signed$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_sr_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_sr_op__oe__oe$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_sr_op__oe__oe$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_sr_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_sr_op__oe__ok$29 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_sr_op__oe__ok$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_sr_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_sr_op__output_carry$33 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_sr_op__output_carry$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_sr_op__output_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_sr_op__output_cr$35 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_sr_op__output_cr$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_sr_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_sr_op__rc__ok$27 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_sr_op__rc__ok$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_sr_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_sr_op__rc__rc$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_sr_op__rc__rc$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire input_sr_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_sr_op__sv_pred_dz$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire input_sr_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_sr_op__sv_pred_sz$43 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] input_sr_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \input_sr_op__sv_saturate$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_sr_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_sr_op__write_cr0$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_sr_op__write_cr0$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [1:0] input_xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [1:0] \input_xer_ca$43 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [1:0] \input_xer_ca$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire input_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire \input_xer_so$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire \input_xer_so$50 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] main_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \main_muxid$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \main_muxid$52 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] main_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire main_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] main_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] main_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] main_rc; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] main_sr_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \main_sr_op__SV_Ptype$73 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] main_sr_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] main_sr_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \main_sr_op__fn_unit$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \main_sr_op__fn_unit$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] main_sr_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \main_sr_op__imm_data__data$47 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \main_sr_op__imm_data__data$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_sr_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_sr_op__imm_data__ok$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_sr_op__imm_data__ok$56 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [1:0] main_sr_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [1:0] \main_sr_op__input_carry$55 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \main_sr_op__input_carry$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_sr_op__input_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_sr_op__input_cr$57 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_sr_op__input_cr$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] main_sr_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \main_sr_op__insn$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \main_sr_op__insn$69 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -167373,7 +179568,9 @@ module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] main_sr_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -167450,61 +179647,83 @@ module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \main_sr_op__insn_type$45 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \main_sr_op__insn_type$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_sr_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_sr_op__invert_in$54 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_sr_op__invert_in$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_sr_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_sr_op__is_32bit$59 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_sr_op__is_32bit$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_sr_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_sr_op__is_signed$60 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_sr_op__is_signed$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_sr_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_sr_op__oe__oe$51 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_sr_op__oe__oe$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_sr_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_sr_op__oe__ok$52 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_sr_op__oe__ok$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_sr_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_sr_op__output_carry$56 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_sr_op__output_carry$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_sr_op__output_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_sr_op__output_cr$58 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_sr_op__output_cr$66 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_sr_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_sr_op__rc__ok$50 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_sr_op__rc__ok$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_sr_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_sr_op__rc__rc$49 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_sr_op__rc__rc$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire main_sr_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_sr_op__sv_pred_dz$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire main_sr_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_sr_op__sv_pred_sz$70 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] main_sr_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \main_sr_op__sv_saturate$72 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_sr_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_sr_op__write_cr0$53 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_sr_op__write_cr0$61 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [1:0] main_xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire main_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \main_xer_so$62 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \main_xer_so$74 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] muxid; reg [1:0] muxid = 2'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] \muxid$1 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \muxid$67 ; + wire [1:0] \muxid$79 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) reg [1:0] \muxid$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *) @@ -167513,148 +179732,172 @@ module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] o; reg [63:0] o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \o$85 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \o$101 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [63:0] \o$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output o_ok; reg o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \o_ok$86 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \o_ok$102 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \o_ok$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) input p_valid_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *) - wire \p_valid_i$64 ; + wire \p_valid_i$76 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *) wire p_valid_i_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg r_busy = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg \r_busy$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] rc; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] sr_op__SV_Ptype; + reg [1:0] sr_op__SV_Ptype = 2'h0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \sr_op__SV_Ptype$100 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] \sr_op__SV_Ptype$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \sr_op__SV_Ptype$next ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] sr_op__fn_unit; - reg [13:0] sr_op__fn_unit = 14'h0000; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] sr_op__fn_unit; + reg [14:0] sr_op__fn_unit = 15'h0000; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] \sr_op__fn_unit$3 ; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] \sr_op__fn_unit$3 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \sr_op__fn_unit$69 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] \sr_op__fn_unit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \sr_op__fn_unit$81 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] \sr_op__fn_unit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] sr_op__imm_data__data; reg [63:0] sr_op__imm_data__data = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] \sr_op__imm_data__data$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \sr_op__imm_data__data$70 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \sr_op__imm_data__data$82 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] \sr_op__imm_data__data$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output sr_op__imm_data__ok; reg sr_op__imm_data__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \sr_op__imm_data__ok$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__imm_data__ok$71 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__imm_data__ok$83 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \sr_op__imm_data__ok$next ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [1:0] sr_op__input_carry; reg [1:0] sr_op__input_carry = 2'h0; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] \sr_op__input_carry$12 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [1:0] \sr_op__input_carry$78 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \sr_op__input_carry$90 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [1:0] \sr_op__input_carry$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output sr_op__input_cr; reg sr_op__input_cr = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \sr_op__input_cr$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__input_cr$80 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__input_cr$92 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \sr_op__input_cr$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] sr_op__insn; reg [31:0] sr_op__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] \sr_op__insn$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \sr_op__insn$84 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \sr_op__insn$96 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] \sr_op__insn$next ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -167731,7 +179974,9 @@ module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] sr_op__insn_type; reg [6:0] sr_op__insn_type = 7'h00; (* enum_base_type = "MicrOp" *) @@ -167809,7 +180054,9 @@ module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] \sr_op__insn_type$2 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -167886,139 +180133,180 @@ module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \sr_op__insn_type$68 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \sr_op__insn_type$80 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] \sr_op__insn_type$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output sr_op__invert_in; reg sr_op__invert_in = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \sr_op__invert_in$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__invert_in$77 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__invert_in$89 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \sr_op__invert_in$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output sr_op__is_32bit; reg sr_op__is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \sr_op__is_32bit$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__is_32bit$82 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__is_32bit$94 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \sr_op__is_32bit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output sr_op__is_signed; reg sr_op__is_signed = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \sr_op__is_signed$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__is_signed$83 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__is_signed$95 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \sr_op__is_signed$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output sr_op__oe__oe; reg sr_op__oe__oe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__oe__oe$74 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \sr_op__oe__oe$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__oe__oe$86 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \sr_op__oe__oe$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output sr_op__oe__ok; reg sr_op__oe__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__oe__ok$75 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__oe__ok$87 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \sr_op__oe__ok$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \sr_op__oe__ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output sr_op__output_carry; reg sr_op__output_carry = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \sr_op__output_carry$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__output_carry$79 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__output_carry$91 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \sr_op__output_carry$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output sr_op__output_cr; reg sr_op__output_cr = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \sr_op__output_cr$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__output_cr$81 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__output_cr$93 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \sr_op__output_cr$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output sr_op__rc__ok; reg sr_op__rc__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \sr_op__rc__ok$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__rc__ok$73 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__rc__ok$85 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \sr_op__rc__ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output sr_op__rc__rc; reg sr_op__rc__rc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \sr_op__rc__rc$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__rc__rc$72 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__rc__rc$84 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \sr_op__rc__rc$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output sr_op__sv_pred_dz; + reg sr_op__sv_pred_dz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input \sr_op__sv_pred_dz$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__sv_pred_dz$98 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \sr_op__sv_pred_dz$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output sr_op__sv_pred_sz; + reg sr_op__sv_pred_sz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input \sr_op__sv_pred_sz$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__sv_pred_sz$97 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \sr_op__sv_pred_sz$next ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] sr_op__sv_saturate; + reg [1:0] sr_op__sv_saturate = 2'h0; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] \sr_op__sv_saturate$21 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \sr_op__sv_saturate$99 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \sr_op__sv_saturate$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output sr_op__write_cr0; reg sr_op__write_cr0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \sr_op__write_cr0$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__write_cr0$76 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__write_cr0$88 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \sr_op__write_cr0$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [1:0] xer_ca; reg [1:0] xer_ca = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - input [1:0] \xer_ca$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [1:0] \xer_ca$63 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [1:0] \xer_ca$94 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [1:0] \xer_ca$110 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + input [1:0] \xer_ca$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [1:0] \xer_ca$75 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [1:0] \xer_ca$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ca_ok; reg xer_ca_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_ca_ok$95 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_ca_ok$96 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_ca_ok$111 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_ca_ok$112 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \xer_ca_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_so; reg xer_so = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - input \xer_so$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_so$91 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_so$107 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + input \xer_so$23 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \xer_so$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_so_ok; reg xer_so_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_so_ok$92 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_so_ok$93 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_so_ok$108 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_so_ok$109 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \xer_so_ok$next ; - assign \$65 = \p_valid_i$64 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; + assign \$77 = \p_valid_i$76 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; always @(posedge coresync_clk) xer_ca <= \xer_ca$next ; always @(posedge coresync_clk) @@ -168069,103 +180357,127 @@ module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, sr_op__is_signed <= \sr_op__is_signed$next ; always @(posedge coresync_clk) sr_op__insn <= \sr_op__insn$next ; + always @(posedge coresync_clk) + sr_op__sv_pred_sz <= \sr_op__sv_pred_sz$next ; + always @(posedge coresync_clk) + sr_op__sv_pred_dz <= \sr_op__sv_pred_dz$next ; + always @(posedge coresync_clk) + sr_op__sv_saturate <= \sr_op__sv_saturate$next ; + always @(posedge coresync_clk) + sr_op__SV_Ptype <= \sr_op__SV_Ptype$next ; always @(posedge coresync_clk) muxid <= \muxid$next ; always @(posedge coresync_clk) r_busy <= \r_busy$next ; \input$113 \input ( .muxid(input_muxid), - .\muxid$1 (\input_muxid$21 ), + .\muxid$1 (\input_muxid$25 ), .ra(input_ra), - .\ra$19 (\input_ra$39 ), + .\ra$23 (\input_ra$47 ), .rb(input_rb), - .\rb$20 (\input_rb$40 ), + .\rb$24 (\input_rb$48 ), .rc(input_rc), - .\rc$21 (\input_rc$41 ), + .\rc$25 (\input_rc$49 ), + .sr_op__SV_Ptype(input_sr_op__SV_Ptype), + .\sr_op__SV_Ptype$22 (\input_sr_op__SV_Ptype$46 ), .sr_op__fn_unit(input_sr_op__fn_unit), - .\sr_op__fn_unit$3 (\input_sr_op__fn_unit$23 ), + .\sr_op__fn_unit$3 (\input_sr_op__fn_unit$27 ), .sr_op__imm_data__data(input_sr_op__imm_data__data), - .\sr_op__imm_data__data$4 (\input_sr_op__imm_data__data$24 ), + .\sr_op__imm_data__data$4 (\input_sr_op__imm_data__data$28 ), .sr_op__imm_data__ok(input_sr_op__imm_data__ok), - .\sr_op__imm_data__ok$5 (\input_sr_op__imm_data__ok$25 ), + .\sr_op__imm_data__ok$5 (\input_sr_op__imm_data__ok$29 ), .sr_op__input_carry(input_sr_op__input_carry), - .\sr_op__input_carry$12 (\input_sr_op__input_carry$32 ), + .\sr_op__input_carry$12 (\input_sr_op__input_carry$36 ), .sr_op__input_cr(input_sr_op__input_cr), - .\sr_op__input_cr$14 (\input_sr_op__input_cr$34 ), + .\sr_op__input_cr$14 (\input_sr_op__input_cr$38 ), .sr_op__insn(input_sr_op__insn), - .\sr_op__insn$18 (\input_sr_op__insn$38 ), + .\sr_op__insn$18 (\input_sr_op__insn$42 ), .sr_op__insn_type(input_sr_op__insn_type), - .\sr_op__insn_type$2 (\input_sr_op__insn_type$22 ), + .\sr_op__insn_type$2 (\input_sr_op__insn_type$26 ), .sr_op__invert_in(input_sr_op__invert_in), - .\sr_op__invert_in$11 (\input_sr_op__invert_in$31 ), + .\sr_op__invert_in$11 (\input_sr_op__invert_in$35 ), .sr_op__is_32bit(input_sr_op__is_32bit), - .\sr_op__is_32bit$16 (\input_sr_op__is_32bit$36 ), + .\sr_op__is_32bit$16 (\input_sr_op__is_32bit$40 ), .sr_op__is_signed(input_sr_op__is_signed), - .\sr_op__is_signed$17 (\input_sr_op__is_signed$37 ), + .\sr_op__is_signed$17 (\input_sr_op__is_signed$41 ), .sr_op__oe__oe(input_sr_op__oe__oe), - .\sr_op__oe__oe$8 (\input_sr_op__oe__oe$28 ), + .\sr_op__oe__oe$8 (\input_sr_op__oe__oe$32 ), .sr_op__oe__ok(input_sr_op__oe__ok), - .\sr_op__oe__ok$9 (\input_sr_op__oe__ok$29 ), + .\sr_op__oe__ok$9 (\input_sr_op__oe__ok$33 ), .sr_op__output_carry(input_sr_op__output_carry), - .\sr_op__output_carry$13 (\input_sr_op__output_carry$33 ), + .\sr_op__output_carry$13 (\input_sr_op__output_carry$37 ), .sr_op__output_cr(input_sr_op__output_cr), - .\sr_op__output_cr$15 (\input_sr_op__output_cr$35 ), + .\sr_op__output_cr$15 (\input_sr_op__output_cr$39 ), .sr_op__rc__ok(input_sr_op__rc__ok), - .\sr_op__rc__ok$7 (\input_sr_op__rc__ok$27 ), + .\sr_op__rc__ok$7 (\input_sr_op__rc__ok$31 ), .sr_op__rc__rc(input_sr_op__rc__rc), - .\sr_op__rc__rc$6 (\input_sr_op__rc__rc$26 ), + .\sr_op__rc__rc$6 (\input_sr_op__rc__rc$30 ), + .sr_op__sv_pred_dz(input_sr_op__sv_pred_dz), + .\sr_op__sv_pred_dz$20 (\input_sr_op__sv_pred_dz$44 ), + .sr_op__sv_pred_sz(input_sr_op__sv_pred_sz), + .\sr_op__sv_pred_sz$19 (\input_sr_op__sv_pred_sz$43 ), + .sr_op__sv_saturate(input_sr_op__sv_saturate), + .\sr_op__sv_saturate$21 (\input_sr_op__sv_saturate$45 ), .sr_op__write_cr0(input_sr_op__write_cr0), - .\sr_op__write_cr0$10 (\input_sr_op__write_cr0$30 ), + .\sr_op__write_cr0$10 (\input_sr_op__write_cr0$34 ), .xer_ca(input_xer_ca), - .\xer_ca$23 (\input_xer_ca$43 ), + .\xer_ca$27 (\input_xer_ca$51 ), .xer_so(input_xer_so), - .\xer_so$22 (\input_xer_so$42 ) + .\xer_so$26 (\input_xer_so$50 ) ); \main$114 main ( .muxid(main_muxid), - .\muxid$1 (\main_muxid$44 ), + .\muxid$1 (\main_muxid$52 ), .o(main_o), .o_ok(main_o_ok), .ra(main_ra), .rb(main_rb), .rc(main_rc), + .sr_op__SV_Ptype(main_sr_op__SV_Ptype), + .\sr_op__SV_Ptype$22 (\main_sr_op__SV_Ptype$73 ), .sr_op__fn_unit(main_sr_op__fn_unit), - .\sr_op__fn_unit$3 (\main_sr_op__fn_unit$46 ), + .\sr_op__fn_unit$3 (\main_sr_op__fn_unit$54 ), .sr_op__imm_data__data(main_sr_op__imm_data__data), - .\sr_op__imm_data__data$4 (\main_sr_op__imm_data__data$47 ), + .\sr_op__imm_data__data$4 (\main_sr_op__imm_data__data$55 ), .sr_op__imm_data__ok(main_sr_op__imm_data__ok), - .\sr_op__imm_data__ok$5 (\main_sr_op__imm_data__ok$48 ), + .\sr_op__imm_data__ok$5 (\main_sr_op__imm_data__ok$56 ), .sr_op__input_carry(main_sr_op__input_carry), - .\sr_op__input_carry$12 (\main_sr_op__input_carry$55 ), + .\sr_op__input_carry$12 (\main_sr_op__input_carry$63 ), .sr_op__input_cr(main_sr_op__input_cr), - .\sr_op__input_cr$14 (\main_sr_op__input_cr$57 ), + .\sr_op__input_cr$14 (\main_sr_op__input_cr$65 ), .sr_op__insn(main_sr_op__insn), - .\sr_op__insn$18 (\main_sr_op__insn$61 ), + .\sr_op__insn$18 (\main_sr_op__insn$69 ), .sr_op__insn_type(main_sr_op__insn_type), - .\sr_op__insn_type$2 (\main_sr_op__insn_type$45 ), + .\sr_op__insn_type$2 (\main_sr_op__insn_type$53 ), .sr_op__invert_in(main_sr_op__invert_in), - .\sr_op__invert_in$11 (\main_sr_op__invert_in$54 ), + .\sr_op__invert_in$11 (\main_sr_op__invert_in$62 ), .sr_op__is_32bit(main_sr_op__is_32bit), - .\sr_op__is_32bit$16 (\main_sr_op__is_32bit$59 ), + .\sr_op__is_32bit$16 (\main_sr_op__is_32bit$67 ), .sr_op__is_signed(main_sr_op__is_signed), - .\sr_op__is_signed$17 (\main_sr_op__is_signed$60 ), + .\sr_op__is_signed$17 (\main_sr_op__is_signed$68 ), .sr_op__oe__oe(main_sr_op__oe__oe), - .\sr_op__oe__oe$8 (\main_sr_op__oe__oe$51 ), + .\sr_op__oe__oe$8 (\main_sr_op__oe__oe$59 ), .sr_op__oe__ok(main_sr_op__oe__ok), - .\sr_op__oe__ok$9 (\main_sr_op__oe__ok$52 ), + .\sr_op__oe__ok$9 (\main_sr_op__oe__ok$60 ), .sr_op__output_carry(main_sr_op__output_carry), - .\sr_op__output_carry$13 (\main_sr_op__output_carry$56 ), + .\sr_op__output_carry$13 (\main_sr_op__output_carry$64 ), .sr_op__output_cr(main_sr_op__output_cr), - .\sr_op__output_cr$15 (\main_sr_op__output_cr$58 ), + .\sr_op__output_cr$15 (\main_sr_op__output_cr$66 ), .sr_op__rc__ok(main_sr_op__rc__ok), - .\sr_op__rc__ok$7 (\main_sr_op__rc__ok$50 ), + .\sr_op__rc__ok$7 (\main_sr_op__rc__ok$58 ), .sr_op__rc__rc(main_sr_op__rc__rc), - .\sr_op__rc__rc$6 (\main_sr_op__rc__rc$49 ), + .\sr_op__rc__rc$6 (\main_sr_op__rc__rc$57 ), + .sr_op__sv_pred_dz(main_sr_op__sv_pred_dz), + .\sr_op__sv_pred_dz$20 (\main_sr_op__sv_pred_dz$71 ), + .sr_op__sv_pred_sz(main_sr_op__sv_pred_sz), + .\sr_op__sv_pred_sz$19 (\main_sr_op__sv_pred_sz$70 ), + .sr_op__sv_saturate(main_sr_op__sv_saturate), + .\sr_op__sv_saturate$21 (\main_sr_op__sv_saturate$72 ), .sr_op__write_cr0(main_sr_op__write_cr0), - .\sr_op__write_cr0$10 (\main_sr_op__write_cr0$53 ), + .\sr_op__write_cr0$10 (\main_sr_op__write_cr0$61 ), .xer_ca(main_xer_ca), .xer_so(main_xer_so), - .\xer_so$19 (\main_xer_so$62 ) + .\xer_so$23 (\main_xer_so$74 ) ); \n$112 n ( .n_ready_i(n_ready_i), @@ -168175,97 +180487,6 @@ module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, .p_ready_o(p_ready_o), .p_valid_i(p_valid_i) ); - always @* begin - if (\initial ) begin end - \xer_ca$next = xer_ca; - \xer_ca_ok$next = xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) - casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) - /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ - 2'b?1: - { \xer_ca_ok$next , \xer_ca$next } = { \xer_ca_ok$95 , \xer_ca$94 }; - /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ - 2'b1?: - { \xer_ca_ok$next , \xer_ca$next } = { \xer_ca_ok$95 , \xer_ca$94 }; - endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) - casez (coresync_rst) - 1'h1: - \xer_ca_ok$next = 1'h0; - endcase - end - always @* begin - if (\initial ) begin end - \r_busy$next = r_busy; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) - casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) - /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ - 2'b?1: - \r_busy$next = 1'h1; - /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ - 2'b1?: - \r_busy$next = 1'h0; - endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) - casez (coresync_rst) - 1'h1: - \r_busy$next = 1'h0; - endcase - end - always @* begin - if (\initial ) begin end - \muxid$next = muxid; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) - casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) - /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ - 2'b?1: - \muxid$next = \muxid$67 ; - /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ - 2'b1?: - \muxid$next = \muxid$67 ; - endcase - end - always @* begin - if (\initial ) begin end - \sr_op__insn_type$next = sr_op__insn_type; - \sr_op__fn_unit$next = sr_op__fn_unit; - \sr_op__imm_data__data$next = sr_op__imm_data__data; - \sr_op__imm_data__ok$next = sr_op__imm_data__ok; - \sr_op__rc__rc$next = sr_op__rc__rc; - \sr_op__rc__ok$next = sr_op__rc__ok; - \sr_op__oe__oe$next = sr_op__oe__oe; - \sr_op__oe__ok$next = sr_op__oe__ok; - \sr_op__write_cr0$next = sr_op__write_cr0; - \sr_op__invert_in$next = sr_op__invert_in; - \sr_op__input_carry$next = sr_op__input_carry; - \sr_op__output_carry$next = sr_op__output_carry; - \sr_op__input_cr$next = sr_op__input_cr; - \sr_op__output_cr$next = sr_op__output_cr; - \sr_op__is_32bit$next = sr_op__is_32bit; - \sr_op__is_signed$next = sr_op__is_signed; - \sr_op__insn$next = sr_op__insn; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) - casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) - /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ - 2'b?1: - { \sr_op__insn$next , \sr_op__is_signed$next , \sr_op__is_32bit$next , \sr_op__output_cr$next , \sr_op__input_cr$next , \sr_op__output_carry$next , \sr_op__input_carry$next , \sr_op__invert_in$next , \sr_op__write_cr0$next , \sr_op__oe__ok$next , \sr_op__oe__oe$next , \sr_op__rc__ok$next , \sr_op__rc__rc$next , \sr_op__imm_data__ok$next , \sr_op__imm_data__data$next , \sr_op__fn_unit$next , \sr_op__insn_type$next } = { \sr_op__insn$84 , \sr_op__is_signed$83 , \sr_op__is_32bit$82 , \sr_op__output_cr$81 , \sr_op__input_cr$80 , \sr_op__output_carry$79 , \sr_op__input_carry$78 , \sr_op__invert_in$77 , \sr_op__write_cr0$76 , \sr_op__oe__ok$75 , \sr_op__oe__oe$74 , \sr_op__rc__ok$73 , \sr_op__rc__rc$72 , \sr_op__imm_data__ok$71 , \sr_op__imm_data__data$70 , \sr_op__fn_unit$69 , \sr_op__insn_type$68 }; - /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ - 2'b1?: - { \sr_op__insn$next , \sr_op__is_signed$next , \sr_op__is_32bit$next , \sr_op__output_cr$next , \sr_op__input_cr$next , \sr_op__output_carry$next , \sr_op__input_carry$next , \sr_op__invert_in$next , \sr_op__write_cr0$next , \sr_op__oe__ok$next , \sr_op__oe__oe$next , \sr_op__rc__ok$next , \sr_op__rc__rc$next , \sr_op__imm_data__ok$next , \sr_op__imm_data__data$next , \sr_op__fn_unit$next , \sr_op__insn_type$next } = { \sr_op__insn$84 , \sr_op__is_signed$83 , \sr_op__is_32bit$82 , \sr_op__output_cr$81 , \sr_op__input_cr$80 , \sr_op__output_carry$79 , \sr_op__input_carry$78 , \sr_op__invert_in$77 , \sr_op__write_cr0$76 , \sr_op__oe__ok$75 , \sr_op__oe__oe$74 , \sr_op__rc__ok$73 , \sr_op__rc__rc$72 , \sr_op__imm_data__ok$71 , \sr_op__imm_data__data$70 , \sr_op__fn_unit$69 , \sr_op__insn_type$68 }; - endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) - casez (coresync_rst) - 1'h1: - begin - \sr_op__imm_data__data$next = 64'h0000000000000000; - \sr_op__imm_data__ok$next = 1'h0; - \sr_op__rc__rc$next = 1'h0; - \sr_op__rc__ok$next = 1'h0; - \sr_op__oe__oe$next = 1'h0; - \sr_op__oe__ok$next = 1'h0; - end - endcase - end always @* begin if (\initial ) begin end \o$next = o; @@ -168274,12 +180495,12 @@ module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \o_ok$next , \o$next } = { \o_ok$86 , \o$85 }; + { \o_ok$next , \o$next } = { \o_ok$102 , \o$101 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \o_ok$next , \o$next } = { \o_ok$86 , \o$85 }; + { \o_ok$next , \o$next } = { \o_ok$102 , \o$101 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \o_ok$next = 1'h0; @@ -168293,12 +180514,12 @@ module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$88 , \cr_a$87 }; + { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$104 , \cr_a$103 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$88 , \cr_a$87 }; + { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$104 , \cr_a$103 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \cr_a_ok$next = 1'h0; @@ -168312,120 +180533,233 @@ module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$92 , \xer_so$91 }; + { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$108 , \xer_so$107 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$92 , \xer_so$91 }; + { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$108 , \xer_so$107 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \xer_so_ok$next = 1'h0; endcase end - assign \cr_a$89 = 4'h0; - assign \cr_a_ok$90 = 1'h0; - assign \xer_so_ok$93 = 1'h0; - assign \xer_ca_ok$96 = 1'h0; + always @* begin + if (\initial ) begin end + \xer_ca$next = xer_ca; + \xer_ca_ok$next = xer_ca_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \xer_ca_ok$next , \xer_ca$next } = { \xer_ca_ok$111 , \xer_ca$110 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \xer_ca_ok$next , \xer_ca$next } = { \xer_ca_ok$111 , \xer_ca$110 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + casez (coresync_rst) + 1'h1: + \xer_ca_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \r_busy$next = r_busy; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \r_busy$next = 1'h1; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \r_busy$next = 1'h0; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + casez (coresync_rst) + 1'h1: + \r_busy$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \muxid$next = muxid; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \muxid$next = \muxid$79 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \muxid$next = \muxid$79 ; + endcase + end + always @* begin + if (\initial ) begin end + \sr_op__insn_type$next = sr_op__insn_type; + \sr_op__fn_unit$next = sr_op__fn_unit; + \sr_op__imm_data__data$next = sr_op__imm_data__data; + \sr_op__imm_data__ok$next = sr_op__imm_data__ok; + \sr_op__rc__rc$next = sr_op__rc__rc; + \sr_op__rc__ok$next = sr_op__rc__ok; + \sr_op__oe__oe$next = sr_op__oe__oe; + \sr_op__oe__ok$next = sr_op__oe__ok; + \sr_op__write_cr0$next = sr_op__write_cr0; + \sr_op__invert_in$next = sr_op__invert_in; + \sr_op__input_carry$next = sr_op__input_carry; + \sr_op__output_carry$next = sr_op__output_carry; + \sr_op__input_cr$next = sr_op__input_cr; + \sr_op__output_cr$next = sr_op__output_cr; + \sr_op__is_32bit$next = sr_op__is_32bit; + \sr_op__is_signed$next = sr_op__is_signed; + \sr_op__insn$next = sr_op__insn; + \sr_op__sv_pred_sz$next = sr_op__sv_pred_sz; + \sr_op__sv_pred_dz$next = sr_op__sv_pred_dz; + \sr_op__sv_saturate$next = sr_op__sv_saturate; + \sr_op__SV_Ptype$next = sr_op__SV_Ptype; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \sr_op__SV_Ptype$next , \sr_op__sv_saturate$next , \sr_op__sv_pred_dz$next , \sr_op__sv_pred_sz$next , \sr_op__insn$next , \sr_op__is_signed$next , \sr_op__is_32bit$next , \sr_op__output_cr$next , \sr_op__input_cr$next , \sr_op__output_carry$next , \sr_op__input_carry$next , \sr_op__invert_in$next , \sr_op__write_cr0$next , \sr_op__oe__ok$next , \sr_op__oe__oe$next , \sr_op__rc__ok$next , \sr_op__rc__rc$next , \sr_op__imm_data__ok$next , \sr_op__imm_data__data$next , \sr_op__fn_unit$next , \sr_op__insn_type$next } = { \sr_op__SV_Ptype$100 , \sr_op__sv_saturate$99 , \sr_op__sv_pred_dz$98 , \sr_op__sv_pred_sz$97 , \sr_op__insn$96 , \sr_op__is_signed$95 , \sr_op__is_32bit$94 , \sr_op__output_cr$93 , \sr_op__input_cr$92 , \sr_op__output_carry$91 , \sr_op__input_carry$90 , \sr_op__invert_in$89 , \sr_op__write_cr0$88 , \sr_op__oe__ok$87 , \sr_op__oe__oe$86 , \sr_op__rc__ok$85 , \sr_op__rc__rc$84 , \sr_op__imm_data__ok$83 , \sr_op__imm_data__data$82 , \sr_op__fn_unit$81 , \sr_op__insn_type$80 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \sr_op__SV_Ptype$next , \sr_op__sv_saturate$next , \sr_op__sv_pred_dz$next , \sr_op__sv_pred_sz$next , \sr_op__insn$next , \sr_op__is_signed$next , \sr_op__is_32bit$next , \sr_op__output_cr$next , \sr_op__input_cr$next , \sr_op__output_carry$next , \sr_op__input_carry$next , \sr_op__invert_in$next , \sr_op__write_cr0$next , \sr_op__oe__ok$next , \sr_op__oe__oe$next , \sr_op__rc__ok$next , \sr_op__rc__rc$next , \sr_op__imm_data__ok$next , \sr_op__imm_data__data$next , \sr_op__fn_unit$next , \sr_op__insn_type$next } = { \sr_op__SV_Ptype$100 , \sr_op__sv_saturate$99 , \sr_op__sv_pred_dz$98 , \sr_op__sv_pred_sz$97 , \sr_op__insn$96 , \sr_op__is_signed$95 , \sr_op__is_32bit$94 , \sr_op__output_cr$93 , \sr_op__input_cr$92 , \sr_op__output_carry$91 , \sr_op__input_carry$90 , \sr_op__invert_in$89 , \sr_op__write_cr0$88 , \sr_op__oe__ok$87 , \sr_op__oe__oe$86 , \sr_op__rc__ok$85 , \sr_op__rc__rc$84 , \sr_op__imm_data__ok$83 , \sr_op__imm_data__data$82 , \sr_op__fn_unit$81 , \sr_op__insn_type$80 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + casez (coresync_rst) + 1'h1: + begin + \sr_op__imm_data__data$next = 64'h0000000000000000; + \sr_op__imm_data__ok$next = 1'h0; + \sr_op__rc__rc$next = 1'h0; + \sr_op__rc__ok$next = 1'h0; + \sr_op__oe__oe$next = 1'h0; + \sr_op__oe__ok$next = 1'h0; + end + endcase + end + assign \cr_a$105 = 4'h0; + assign \cr_a_ok$106 = 1'h0; + assign \xer_so_ok$109 = 1'h0; + assign \xer_ca_ok$112 = 1'h0; assign p_ready_o = n_i_rdy_data; assign n_valid_o = r_busy; - assign { \xer_ca_ok$95 , \xer_ca$94 } = { 1'h0, main_xer_ca }; - assign { \xer_so_ok$92 , \xer_so$91 } = { 1'h0, \main_xer_so$62 }; - assign { \cr_a_ok$88 , \cr_a$87 } = 5'h00; - assign { \o_ok$86 , \o$85 } = { main_o_ok, main_o }; - assign { \sr_op__insn$84 , \sr_op__is_signed$83 , \sr_op__is_32bit$82 , \sr_op__output_cr$81 , \sr_op__input_cr$80 , \sr_op__output_carry$79 , \sr_op__input_carry$78 , \sr_op__invert_in$77 , \sr_op__write_cr0$76 , \sr_op__oe__ok$75 , \sr_op__oe__oe$74 , \sr_op__rc__ok$73 , \sr_op__rc__rc$72 , \sr_op__imm_data__ok$71 , \sr_op__imm_data__data$70 , \sr_op__fn_unit$69 , \sr_op__insn_type$68 } = { \main_sr_op__insn$61 , \main_sr_op__is_signed$60 , \main_sr_op__is_32bit$59 , \main_sr_op__output_cr$58 , \main_sr_op__input_cr$57 , \main_sr_op__output_carry$56 , \main_sr_op__input_carry$55 , \main_sr_op__invert_in$54 , \main_sr_op__write_cr0$53 , \main_sr_op__oe__ok$52 , \main_sr_op__oe__oe$51 , \main_sr_op__rc__ok$50 , \main_sr_op__rc__rc$49 , \main_sr_op__imm_data__ok$48 , \main_sr_op__imm_data__data$47 , \main_sr_op__fn_unit$46 , \main_sr_op__insn_type$45 }; - assign \muxid$67 = \main_muxid$44 ; - assign p_valid_i_p_ready_o = \$65 ; + assign { \xer_ca_ok$111 , \xer_ca$110 } = { 1'h0, main_xer_ca }; + assign { \xer_so_ok$108 , \xer_so$107 } = { 1'h0, \main_xer_so$74 }; + assign { \cr_a_ok$104 , \cr_a$103 } = 5'h00; + assign { \o_ok$102 , \o$101 } = { main_o_ok, main_o }; + assign { \sr_op__SV_Ptype$100 , \sr_op__sv_saturate$99 , \sr_op__sv_pred_dz$98 , \sr_op__sv_pred_sz$97 , \sr_op__insn$96 , \sr_op__is_signed$95 , \sr_op__is_32bit$94 , \sr_op__output_cr$93 , \sr_op__input_cr$92 , \sr_op__output_carry$91 , \sr_op__input_carry$90 , \sr_op__invert_in$89 , \sr_op__write_cr0$88 , \sr_op__oe__ok$87 , \sr_op__oe__oe$86 , \sr_op__rc__ok$85 , \sr_op__rc__rc$84 , \sr_op__imm_data__ok$83 , \sr_op__imm_data__data$82 , \sr_op__fn_unit$81 , \sr_op__insn_type$80 } = { \main_sr_op__SV_Ptype$73 , \main_sr_op__sv_saturate$72 , \main_sr_op__sv_pred_dz$71 , \main_sr_op__sv_pred_sz$70 , \main_sr_op__insn$69 , \main_sr_op__is_signed$68 , \main_sr_op__is_32bit$67 , \main_sr_op__output_cr$66 , \main_sr_op__input_cr$65 , \main_sr_op__output_carry$64 , \main_sr_op__input_carry$63 , \main_sr_op__invert_in$62 , \main_sr_op__write_cr0$61 , \main_sr_op__oe__ok$60 , \main_sr_op__oe__oe$59 , \main_sr_op__rc__ok$58 , \main_sr_op__rc__rc$57 , \main_sr_op__imm_data__ok$56 , \main_sr_op__imm_data__data$55 , \main_sr_op__fn_unit$54 , \main_sr_op__insn_type$53 }; + assign \muxid$79 = \main_muxid$52 ; + assign p_valid_i_p_ready_o = \$77 ; assign n_i_rdy_data = n_ready_i; - assign \p_valid_i$64 = p_valid_i; - assign \xer_ca$63 = \input_xer_ca$43 ; - assign main_xer_so = \input_xer_so$42 ; - assign main_rc = \input_rc$41 ; - assign main_rb = \input_rb$40 ; - assign main_ra = \input_ra$39 ; - assign { main_sr_op__insn, main_sr_op__is_signed, main_sr_op__is_32bit, main_sr_op__output_cr, main_sr_op__input_cr, main_sr_op__output_carry, main_sr_op__input_carry, main_sr_op__invert_in, main_sr_op__write_cr0, main_sr_op__oe__ok, main_sr_op__oe__oe, main_sr_op__rc__ok, main_sr_op__rc__rc, main_sr_op__imm_data__ok, main_sr_op__imm_data__data, main_sr_op__fn_unit, main_sr_op__insn_type } = { \input_sr_op__insn$38 , \input_sr_op__is_signed$37 , \input_sr_op__is_32bit$36 , \input_sr_op__output_cr$35 , \input_sr_op__input_cr$34 , \input_sr_op__output_carry$33 , \input_sr_op__input_carry$32 , \input_sr_op__invert_in$31 , \input_sr_op__write_cr0$30 , \input_sr_op__oe__ok$29 , \input_sr_op__oe__oe$28 , \input_sr_op__rc__ok$27 , \input_sr_op__rc__rc$26 , \input_sr_op__imm_data__ok$25 , \input_sr_op__imm_data__data$24 , \input_sr_op__fn_unit$23 , \input_sr_op__insn_type$22 }; - assign main_muxid = \input_muxid$21 ; - assign input_xer_ca = \xer_ca$20 ; - assign input_xer_so = \xer_so$19 ; + assign \p_valid_i$76 = p_valid_i; + assign \xer_ca$75 = \input_xer_ca$51 ; + assign main_xer_so = \input_xer_so$50 ; + assign main_rc = \input_rc$49 ; + assign main_rb = \input_rb$48 ; + assign main_ra = \input_ra$47 ; + assign { main_sr_op__SV_Ptype, main_sr_op__sv_saturate, main_sr_op__sv_pred_dz, main_sr_op__sv_pred_sz, main_sr_op__insn, main_sr_op__is_signed, main_sr_op__is_32bit, main_sr_op__output_cr, main_sr_op__input_cr, main_sr_op__output_carry, main_sr_op__input_carry, main_sr_op__invert_in, main_sr_op__write_cr0, main_sr_op__oe__ok, main_sr_op__oe__oe, main_sr_op__rc__ok, main_sr_op__rc__rc, main_sr_op__imm_data__ok, main_sr_op__imm_data__data, main_sr_op__fn_unit, main_sr_op__insn_type } = { \input_sr_op__SV_Ptype$46 , \input_sr_op__sv_saturate$45 , \input_sr_op__sv_pred_dz$44 , \input_sr_op__sv_pred_sz$43 , \input_sr_op__insn$42 , \input_sr_op__is_signed$41 , \input_sr_op__is_32bit$40 , \input_sr_op__output_cr$39 , \input_sr_op__input_cr$38 , \input_sr_op__output_carry$37 , \input_sr_op__input_carry$36 , \input_sr_op__invert_in$35 , \input_sr_op__write_cr0$34 , \input_sr_op__oe__ok$33 , \input_sr_op__oe__oe$32 , \input_sr_op__rc__ok$31 , \input_sr_op__rc__rc$30 , \input_sr_op__imm_data__ok$29 , \input_sr_op__imm_data__data$28 , \input_sr_op__fn_unit$27 , \input_sr_op__insn_type$26 }; + assign main_muxid = \input_muxid$25 ; + assign input_xer_ca = \xer_ca$24 ; + assign input_xer_so = \xer_so$23 ; assign input_rc = rc; assign input_rb = rb; assign input_ra = ra; - assign { input_sr_op__insn, input_sr_op__is_signed, input_sr_op__is_32bit, input_sr_op__output_cr, input_sr_op__input_cr, input_sr_op__output_carry, input_sr_op__input_carry, input_sr_op__invert_in, input_sr_op__write_cr0, input_sr_op__oe__ok, input_sr_op__oe__oe, input_sr_op__rc__ok, input_sr_op__rc__rc, input_sr_op__imm_data__ok, input_sr_op__imm_data__data, input_sr_op__fn_unit, input_sr_op__insn_type } = { \sr_op__insn$18 , \sr_op__is_signed$17 , \sr_op__is_32bit$16 , \sr_op__output_cr$15 , \sr_op__input_cr$14 , \sr_op__output_carry$13 , \sr_op__input_carry$12 , \sr_op__invert_in$11 , \sr_op__write_cr0$10 , \sr_op__oe__ok$9 , \sr_op__oe__oe$8 , \sr_op__rc__ok$7 , \sr_op__rc__rc$6 , \sr_op__imm_data__ok$5 , \sr_op__imm_data__data$4 , \sr_op__fn_unit$3 , \sr_op__insn_type$2 }; + assign { input_sr_op__SV_Ptype, input_sr_op__sv_saturate, input_sr_op__sv_pred_dz, input_sr_op__sv_pred_sz, input_sr_op__insn, input_sr_op__is_signed, input_sr_op__is_32bit, input_sr_op__output_cr, input_sr_op__input_cr, input_sr_op__output_carry, input_sr_op__input_carry, input_sr_op__invert_in, input_sr_op__write_cr0, input_sr_op__oe__ok, input_sr_op__oe__oe, input_sr_op__rc__ok, input_sr_op__rc__rc, input_sr_op__imm_data__ok, input_sr_op__imm_data__data, input_sr_op__fn_unit, input_sr_op__insn_type } = { \sr_op__SV_Ptype$22 , \sr_op__sv_saturate$21 , \sr_op__sv_pred_dz$20 , \sr_op__sv_pred_sz$19 , \sr_op__insn$18 , \sr_op__is_signed$17 , \sr_op__is_32bit$16 , \sr_op__output_cr$15 , \sr_op__input_cr$14 , \sr_op__output_carry$13 , \sr_op__input_carry$12 , \sr_op__invert_in$11 , \sr_op__write_cr0$10 , \sr_op__oe__ok$9 , \sr_op__oe__oe$8 , \sr_op__rc__ok$7 , \sr_op__rc__rc$6 , \sr_op__imm_data__ok$5 , \sr_op__imm_data__data$4 , \sr_op__fn_unit$3 , \sr_op__insn_type$2 }; assign input_muxid = \muxid$1 ; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1" *) (* generator = "nMigen" *) -module \pipe1$32 (coresync_rst, n_valid_o, n_ready_i, muxid, trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, ra, rb, fast1, fast2, p_valid_i, p_ready_o, \muxid$1 , \trap_op__insn_type$2 , \trap_op__fn_unit$3 , \trap_op__insn$4 , \trap_op__msr$5 , \trap_op__cia$6 , \trap_op__is_32bit$7 , \trap_op__traptype$8 , \trap_op__trapaddr$9 , \trap_op__ldst_exc$10 , \ra$11 , \rb$12 , \fast1$13 , \fast2$14 , coresync_clk); +module \pipe1$32 (coresync_rst, n_valid_o, n_ready_i, muxid, trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__svstate, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, trap_op__sv_pred_sz, trap_op__sv_pred_dz, trap_op__sv_saturate, trap_op__SV_Ptype, ra, rb, fast1, fast2, fast3, p_valid_i, p_ready_o, \muxid$1 , \trap_op__insn_type$2 , \trap_op__fn_unit$3 , \trap_op__insn$4 , \trap_op__msr$5 , \trap_op__cia$6 , \trap_op__svstate$7 , \trap_op__is_32bit$8 , \trap_op__traptype$9 , \trap_op__trapaddr$10 , \trap_op__ldst_exc$11 , \trap_op__sv_pred_sz$12 , \trap_op__sv_pred_dz$13 , \trap_op__sv_saturate$14 , \trap_op__SV_Ptype$15 , \ra$16 , \rb$17 , \fast1$18 , \fast2$19 , \fast3$20 , coresync_clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) - wire \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + wire \$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] dummy_fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \dummy_fast1$27 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \dummy_fast1$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] dummy_fast2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \dummy_fast2$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \dummy_fast2$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] dummy_fast3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \dummy_fast3$40 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] dummy_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \dummy_muxid$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [1:0] \dummy_muxid$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] dummy_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \dummy_ra$25 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \dummy_ra$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] dummy_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \dummy_rb$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \dummy_rb$37 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] dummy_trap_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \dummy_trap_op__SV_Ptype$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] dummy_trap_op__cia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \dummy_trap_op__cia$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \dummy_trap_op__cia$26 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] dummy_trap_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] dummy_trap_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \dummy_trap_op__fn_unit$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \dummy_trap_op__fn_unit$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] dummy_trap_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \dummy_trap_op__insn$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \dummy_trap_op__insn$24 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -168501,7 +180835,9 @@ module \pipe1$32 (coresync_rst, n_valid_o, n_ready_i, muxid, trap_op__insn_type, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] dummy_trap_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -168578,53 +180914,88 @@ module \pipe1$32 (coresync_rst, n_valid_o, n_ready_i, muxid, trap_op__insn_type, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \dummy_trap_op__insn_type$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \dummy_trap_op__insn_type$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire dummy_trap_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \dummy_trap_op__is_32bit$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \dummy_trap_op__is_32bit$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [7:0] dummy_trap_op__ldst_exc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [7:0] \dummy_trap_op__ldst_exc$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [7:0] \dummy_trap_op__ldst_exc$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] dummy_trap_op__msr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \dummy_trap_op__msr$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \dummy_trap_op__msr$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire dummy_trap_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \dummy_trap_op__sv_pred_dz$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire dummy_trap_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \dummy_trap_op__sv_pred_sz$32 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] dummy_trap_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \dummy_trap_op__sv_saturate$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] dummy_trap_op__svstate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \dummy_trap_op__svstate$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [12:0] dummy_trap_op__trapaddr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [12:0] \dummy_trap_op__trapaddr$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [12:0] \dummy_trap_op__trapaddr$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [7:0] dummy_trap_op__traptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [7:0] \dummy_trap_op__traptype$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [7:0] \dummy_trap_op__traptype$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) output [63:0] fast1; reg [63:0] fast1 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - input [63:0] \fast1$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \fast1$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + input [63:0] \fast1$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \fast1$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) reg [63:0] \fast1$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) output [63:0] fast2; reg [63:0] fast2 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - input [63:0] \fast2$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \fast2$45 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + input [63:0] \fast2$19 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \fast2$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) reg [63:0] \fast2$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + output [63:0] fast3; + reg [63:0] fast3 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + input [63:0] \fast3$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \fast3$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + reg [63:0] \fast3$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] muxid; reg [1:0] muxid = 2'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] \muxid$1 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \muxid$32 ; + wire [1:0] \muxid$44 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) reg [1:0] \muxid$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *) @@ -168638,102 +181009,126 @@ module \pipe1$32 (coresync_rst, n_valid_o, n_ready_i, muxid, trap_op__insn_type, (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) input p_valid_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *) - wire \p_valid_i$29 ; + wire \p_valid_i$41 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *) wire p_valid_i_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg r_busy = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg \r_busy$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) output [63:0] ra; reg [63:0] ra = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - input [63:0] \ra$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \ra$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + input [63:0] \ra$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \ra$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) reg [63:0] \ra$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) output [63:0] rb; reg [63:0] rb = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - input [63:0] \rb$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \rb$43 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + input [63:0] \rb$17 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \rb$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) reg [63:0] \rb$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] trap_op__SV_Ptype; + reg [1:0] trap_op__SV_Ptype = 2'h0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] \trap_op__SV_Ptype$15 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \trap_op__SV_Ptype$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \trap_op__SV_Ptype$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] trap_op__cia; reg [63:0] trap_op__cia = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \trap_op__cia$37 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \trap_op__cia$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] \trap_op__cia$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] \trap_op__cia$next ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] trap_op__fn_unit; - reg [13:0] trap_op__fn_unit = 14'h0000; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] trap_op__fn_unit; + reg [14:0] trap_op__fn_unit = 15'h0000; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] \trap_op__fn_unit$3 ; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] \trap_op__fn_unit$3 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \trap_op__fn_unit$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] \trap_op__fn_unit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \trap_op__fn_unit$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] \trap_op__fn_unit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] trap_op__insn; reg [31:0] trap_op__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \trap_op__insn$35 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] \trap_op__insn$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \trap_op__insn$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] \trap_op__insn$next ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -168810,7 +181205,9 @@ module \pipe1$32 (coresync_rst, n_valid_o, n_ready_i, muxid, trap_op__insn_type, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] trap_op__insn_type; reg [6:0] trap_op__insn_type = 7'h00; (* enum_base_type = "MicrOp" *) @@ -168888,7 +181285,9 @@ module \pipe1$32 (coresync_rst, n_valid_o, n_ready_i, muxid, trap_op__insn_type, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] \trap_op__insn_type$2 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -168965,56 +181364,108 @@ module \pipe1$32 (coresync_rst, n_valid_o, n_ready_i, muxid, trap_op__insn_type, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \trap_op__insn_type$33 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \trap_op__insn_type$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] \trap_op__insn_type$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output trap_op__is_32bit; reg trap_op__is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \trap_op__is_32bit$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input \trap_op__is_32bit$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \trap_op__is_32bit$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input \trap_op__is_32bit$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \trap_op__is_32bit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [7:0] trap_op__ldst_exc; reg [7:0] trap_op__ldst_exc = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [7:0] \trap_op__ldst_exc$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [7:0] \trap_op__ldst_exc$41 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [7:0] \trap_op__ldst_exc$11 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [7:0] \trap_op__ldst_exc$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [7:0] \trap_op__ldst_exc$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] trap_op__msr; reg [63:0] trap_op__msr = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \trap_op__msr$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \trap_op__msr$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] \trap_op__msr$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] \trap_op__msr$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output trap_op__sv_pred_dz; + reg trap_op__sv_pred_dz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input \trap_op__sv_pred_dz$13 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \trap_op__sv_pred_dz$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \trap_op__sv_pred_dz$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output trap_op__sv_pred_sz; + reg trap_op__sv_pred_sz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input \trap_op__sv_pred_sz$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \trap_op__sv_pred_sz$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \trap_op__sv_pred_sz$next ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] trap_op__sv_saturate; + reg [1:0] trap_op__sv_saturate = 2'h0; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] \trap_op__sv_saturate$14 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \trap_op__sv_saturate$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \trap_op__sv_saturate$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [31:0] trap_op__svstate; + reg [31:0] trap_op__svstate = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \trap_op__svstate$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [31:0] \trap_op__svstate$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [31:0] \trap_op__svstate$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [12:0] trap_op__trapaddr; reg [12:0] trap_op__trapaddr = 13'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [12:0] \trap_op__trapaddr$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [12:0] \trap_op__trapaddr$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [12:0] \trap_op__trapaddr$10 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [12:0] \trap_op__trapaddr$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [12:0] \trap_op__trapaddr$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [7:0] trap_op__traptype; reg [7:0] trap_op__traptype = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [7:0] \trap_op__traptype$39 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [7:0] \trap_op__traptype$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [7:0] \trap_op__traptype$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [7:0] \trap_op__traptype$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [7:0] \trap_op__traptype$next ; - assign \$30 = \p_valid_i$29 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; + assign \$42 = \p_valid_i$41 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; + always @(posedge coresync_clk) + fast3 <= \fast3$next ; always @(posedge coresync_clk) fast2 <= \fast2$next ; always @(posedge coresync_clk) @@ -169033,6 +181484,8 @@ module \pipe1$32 (coresync_rst, n_valid_o, n_ready_i, muxid, trap_op__insn_type, trap_op__msr <= \trap_op__msr$next ; always @(posedge coresync_clk) trap_op__cia <= \trap_op__cia$next ; + always @(posedge coresync_clk) + trap_op__svstate <= \trap_op__svstate$next ; always @(posedge coresync_clk) trap_op__is_32bit <= \trap_op__is_32bit$next ; always @(posedge coresync_clk) @@ -169041,39 +181494,59 @@ module \pipe1$32 (coresync_rst, n_valid_o, n_ready_i, muxid, trap_op__insn_type, trap_op__trapaddr <= \trap_op__trapaddr$next ; always @(posedge coresync_clk) trap_op__ldst_exc <= \trap_op__ldst_exc$next ; + always @(posedge coresync_clk) + trap_op__sv_pred_sz <= \trap_op__sv_pred_sz$next ; + always @(posedge coresync_clk) + trap_op__sv_pred_dz <= \trap_op__sv_pred_dz$next ; + always @(posedge coresync_clk) + trap_op__sv_saturate <= \trap_op__sv_saturate$next ; + always @(posedge coresync_clk) + trap_op__SV_Ptype <= \trap_op__SV_Ptype$next ; always @(posedge coresync_clk) muxid <= \muxid$next ; always @(posedge coresync_clk) r_busy <= \r_busy$next ; dummy dummy ( .fast1(dummy_fast1), - .\fast1$13 (\dummy_fast1$27 ), + .\fast1$18 (\dummy_fast1$38 ), .fast2(dummy_fast2), - .\fast2$14 (\dummy_fast2$28 ), + .\fast2$19 (\dummy_fast2$39 ), + .fast3(dummy_fast3), + .\fast3$20 (\dummy_fast3$40 ), .muxid(dummy_muxid), - .\muxid$1 (\dummy_muxid$15 ), + .\muxid$1 (\dummy_muxid$21 ), .ra(dummy_ra), - .\ra$11 (\dummy_ra$25 ), + .\ra$16 (\dummy_ra$36 ), .rb(dummy_rb), - .\rb$12 (\dummy_rb$26 ), + .\rb$17 (\dummy_rb$37 ), + .trap_op__SV_Ptype(dummy_trap_op__SV_Ptype), + .\trap_op__SV_Ptype$15 (\dummy_trap_op__SV_Ptype$35 ), .trap_op__cia(dummy_trap_op__cia), - .\trap_op__cia$6 (\dummy_trap_op__cia$20 ), + .\trap_op__cia$6 (\dummy_trap_op__cia$26 ), .trap_op__fn_unit(dummy_trap_op__fn_unit), - .\trap_op__fn_unit$3 (\dummy_trap_op__fn_unit$17 ), + .\trap_op__fn_unit$3 (\dummy_trap_op__fn_unit$23 ), .trap_op__insn(dummy_trap_op__insn), - .\trap_op__insn$4 (\dummy_trap_op__insn$18 ), + .\trap_op__insn$4 (\dummy_trap_op__insn$24 ), .trap_op__insn_type(dummy_trap_op__insn_type), - .\trap_op__insn_type$2 (\dummy_trap_op__insn_type$16 ), + .\trap_op__insn_type$2 (\dummy_trap_op__insn_type$22 ), .trap_op__is_32bit(dummy_trap_op__is_32bit), - .\trap_op__is_32bit$7 (\dummy_trap_op__is_32bit$21 ), + .\trap_op__is_32bit$8 (\dummy_trap_op__is_32bit$28 ), .trap_op__ldst_exc(dummy_trap_op__ldst_exc), - .\trap_op__ldst_exc$10 (\dummy_trap_op__ldst_exc$24 ), + .\trap_op__ldst_exc$11 (\dummy_trap_op__ldst_exc$31 ), .trap_op__msr(dummy_trap_op__msr), - .\trap_op__msr$5 (\dummy_trap_op__msr$19 ), + .\trap_op__msr$5 (\dummy_trap_op__msr$25 ), + .trap_op__sv_pred_dz(dummy_trap_op__sv_pred_dz), + .\trap_op__sv_pred_dz$13 (\dummy_trap_op__sv_pred_dz$33 ), + .trap_op__sv_pred_sz(dummy_trap_op__sv_pred_sz), + .\trap_op__sv_pred_sz$12 (\dummy_trap_op__sv_pred_sz$32 ), + .trap_op__sv_saturate(dummy_trap_op__sv_saturate), + .\trap_op__sv_saturate$14 (\dummy_trap_op__sv_saturate$34 ), + .trap_op__svstate(dummy_trap_op__svstate), + .\trap_op__svstate$7 (\dummy_trap_op__svstate$27 ), .trap_op__trapaddr(dummy_trap_op__trapaddr), - .\trap_op__trapaddr$9 (\dummy_trap_op__trapaddr$23 ), + .\trap_op__trapaddr$10 (\dummy_trap_op__trapaddr$30 ), .trap_op__traptype(dummy_trap_op__traptype), - .\trap_op__traptype$8 (\dummy_trap_op__traptype$22 ) + .\trap_op__traptype$9 (\dummy_trap_op__traptype$29 ) ); \n$34 n ( .n_ready_i(n_ready_i), @@ -169095,7 +181568,7 @@ module \pipe1$32 (coresync_rst, n_valid_o, n_ready_i, muxid, trap_op__insn_type, 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -169108,10 +181581,10 @@ module \pipe1$32 (coresync_rst, n_valid_o, n_ready_i, muxid, trap_op__insn_type, casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \muxid$next = \muxid$32 ; + \muxid$next = \muxid$44 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \muxid$next = \muxid$32 ; + \muxid$next = \muxid$44 ; endcase end always @* begin @@ -169121,18 +181594,23 @@ module \pipe1$32 (coresync_rst, n_valid_o, n_ready_i, muxid, trap_op__insn_type, \trap_op__insn$next = trap_op__insn; \trap_op__msr$next = trap_op__msr; \trap_op__cia$next = trap_op__cia; + \trap_op__svstate$next = trap_op__svstate; \trap_op__is_32bit$next = trap_op__is_32bit; \trap_op__traptype$next = trap_op__traptype; \trap_op__trapaddr$next = trap_op__trapaddr; \trap_op__ldst_exc$next = trap_op__ldst_exc; + \trap_op__sv_pred_sz$next = trap_op__sv_pred_sz; + \trap_op__sv_pred_dz$next = trap_op__sv_pred_dz; + \trap_op__sv_saturate$next = trap_op__sv_saturate; + \trap_op__SV_Ptype$next = trap_op__SV_Ptype; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \trap_op__ldst_exc$next , \trap_op__trapaddr$next , \trap_op__traptype$next , \trap_op__is_32bit$next , \trap_op__cia$next , \trap_op__msr$next , \trap_op__insn$next , \trap_op__fn_unit$next , \trap_op__insn_type$next } = { \trap_op__ldst_exc$41 , \trap_op__trapaddr$40 , \trap_op__traptype$39 , \trap_op__is_32bit$38 , \trap_op__cia$37 , \trap_op__msr$36 , \trap_op__insn$35 , \trap_op__fn_unit$34 , \trap_op__insn_type$33 }; + { \trap_op__SV_Ptype$next , \trap_op__sv_saturate$next , \trap_op__sv_pred_dz$next , \trap_op__sv_pred_sz$next , \trap_op__ldst_exc$next , \trap_op__trapaddr$next , \trap_op__traptype$next , \trap_op__is_32bit$next , \trap_op__svstate$next , \trap_op__cia$next , \trap_op__msr$next , \trap_op__insn$next , \trap_op__fn_unit$next , \trap_op__insn_type$next } = { \trap_op__SV_Ptype$58 , \trap_op__sv_saturate$57 , \trap_op__sv_pred_dz$56 , \trap_op__sv_pred_sz$55 , \trap_op__ldst_exc$54 , \trap_op__trapaddr$53 , \trap_op__traptype$52 , \trap_op__is_32bit$51 , \trap_op__svstate$50 , \trap_op__cia$49 , \trap_op__msr$48 , \trap_op__insn$47 , \trap_op__fn_unit$46 , \trap_op__insn_type$45 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \trap_op__ldst_exc$next , \trap_op__trapaddr$next , \trap_op__traptype$next , \trap_op__is_32bit$next , \trap_op__cia$next , \trap_op__msr$next , \trap_op__insn$next , \trap_op__fn_unit$next , \trap_op__insn_type$next } = { \trap_op__ldst_exc$41 , \trap_op__trapaddr$40 , \trap_op__traptype$39 , \trap_op__is_32bit$38 , \trap_op__cia$37 , \trap_op__msr$36 , \trap_op__insn$35 , \trap_op__fn_unit$34 , \trap_op__insn_type$33 }; + { \trap_op__SV_Ptype$next , \trap_op__sv_saturate$next , \trap_op__sv_pred_dz$next , \trap_op__sv_pred_sz$next , \trap_op__ldst_exc$next , \trap_op__trapaddr$next , \trap_op__traptype$next , \trap_op__is_32bit$next , \trap_op__svstate$next , \trap_op__cia$next , \trap_op__msr$next , \trap_op__insn$next , \trap_op__fn_unit$next , \trap_op__insn_type$next } = { \trap_op__SV_Ptype$58 , \trap_op__sv_saturate$57 , \trap_op__sv_pred_dz$56 , \trap_op__sv_pred_sz$55 , \trap_op__ldst_exc$54 , \trap_op__trapaddr$53 , \trap_op__traptype$52 , \trap_op__is_32bit$51 , \trap_op__svstate$50 , \trap_op__cia$49 , \trap_op__msr$48 , \trap_op__insn$47 , \trap_op__fn_unit$46 , \trap_op__insn_type$45 }; endcase end always @* begin @@ -169142,10 +181620,10 @@ module \pipe1$32 (coresync_rst, n_valid_o, n_ready_i, muxid, trap_op__insn_type, casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \ra$next = \ra$42 ; + \ra$next = \ra$59 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \ra$next = \ra$42 ; + \ra$next = \ra$59 ; endcase end always @* begin @@ -169155,10 +181633,10 @@ module \pipe1$32 (coresync_rst, n_valid_o, n_ready_i, muxid, trap_op__insn_type, casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \rb$next = \rb$43 ; + \rb$next = \rb$60 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \rb$next = \rb$43 ; + \rb$next = \rb$60 ; endcase end always @* begin @@ -169168,10 +181646,10 @@ module \pipe1$32 (coresync_rst, n_valid_o, n_ready_i, muxid, trap_op__insn_type, casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \fast1$next = \fast1$44 ; + \fast1$next = \fast1$61 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \fast1$next = \fast1$44 ; + \fast1$next = \fast1$61 ; endcase end always @* begin @@ -169181,148 +181659,187 @@ module \pipe1$32 (coresync_rst, n_valid_o, n_ready_i, muxid, trap_op__insn_type, casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \fast2$next = \fast2$45 ; + \fast2$next = \fast2$62 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \fast2$next = \fast2$45 ; + \fast2$next = \fast2$62 ; + endcase + end + always @* begin + if (\initial ) begin end + \fast3$next = fast3; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \fast3$next = \fast3$63 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \fast3$next = \fast3$63 ; endcase end assign p_ready_o = n_i_rdy_data; assign n_valid_o = r_busy; - assign \fast2$45 = \dummy_fast2$28 ; - assign \fast1$44 = \dummy_fast1$27 ; - assign \rb$43 = \dummy_rb$26 ; - assign \ra$42 = \dummy_ra$25 ; - assign { \trap_op__ldst_exc$41 , \trap_op__trapaddr$40 , \trap_op__traptype$39 , \trap_op__is_32bit$38 , \trap_op__cia$37 , \trap_op__msr$36 , \trap_op__insn$35 , \trap_op__fn_unit$34 , \trap_op__insn_type$33 } = { \dummy_trap_op__ldst_exc$24 , \dummy_trap_op__trapaddr$23 , \dummy_trap_op__traptype$22 , \dummy_trap_op__is_32bit$21 , \dummy_trap_op__cia$20 , \dummy_trap_op__msr$19 , \dummy_trap_op__insn$18 , \dummy_trap_op__fn_unit$17 , \dummy_trap_op__insn_type$16 }; - assign \muxid$32 = \dummy_muxid$15 ; - assign p_valid_i_p_ready_o = \$30 ; + assign \fast3$63 = \dummy_fast3$40 ; + assign \fast2$62 = \dummy_fast2$39 ; + assign \fast1$61 = \dummy_fast1$38 ; + assign \rb$60 = \dummy_rb$37 ; + assign \ra$59 = \dummy_ra$36 ; + assign { \trap_op__SV_Ptype$58 , \trap_op__sv_saturate$57 , \trap_op__sv_pred_dz$56 , \trap_op__sv_pred_sz$55 , \trap_op__ldst_exc$54 , \trap_op__trapaddr$53 , \trap_op__traptype$52 , \trap_op__is_32bit$51 , \trap_op__svstate$50 , \trap_op__cia$49 , \trap_op__msr$48 , \trap_op__insn$47 , \trap_op__fn_unit$46 , \trap_op__insn_type$45 } = { \dummy_trap_op__SV_Ptype$35 , \dummy_trap_op__sv_saturate$34 , \dummy_trap_op__sv_pred_dz$33 , \dummy_trap_op__sv_pred_sz$32 , \dummy_trap_op__ldst_exc$31 , \dummy_trap_op__trapaddr$30 , \dummy_trap_op__traptype$29 , \dummy_trap_op__is_32bit$28 , \dummy_trap_op__svstate$27 , \dummy_trap_op__cia$26 , \dummy_trap_op__msr$25 , \dummy_trap_op__insn$24 , \dummy_trap_op__fn_unit$23 , \dummy_trap_op__insn_type$22 }; + assign \muxid$44 = \dummy_muxid$21 ; + assign p_valid_i_p_ready_o = \$42 ; assign n_i_rdy_data = n_ready_i; - assign \p_valid_i$29 = p_valid_i; - assign dummy_fast2 = \fast2$14 ; - assign dummy_fast1 = \fast1$13 ; - assign dummy_rb = \rb$12 ; - assign dummy_ra = \ra$11 ; - assign { dummy_trap_op__ldst_exc, dummy_trap_op__trapaddr, dummy_trap_op__traptype, dummy_trap_op__is_32bit, dummy_trap_op__cia, dummy_trap_op__msr, dummy_trap_op__insn, dummy_trap_op__fn_unit, dummy_trap_op__insn_type } = { \trap_op__ldst_exc$10 , \trap_op__trapaddr$9 , \trap_op__traptype$8 , \trap_op__is_32bit$7 , \trap_op__cia$6 , \trap_op__msr$5 , \trap_op__insn$4 , \trap_op__fn_unit$3 , \trap_op__insn_type$2 }; + assign \p_valid_i$41 = p_valid_i; + assign dummy_fast3 = \fast3$20 ; + assign dummy_fast2 = \fast2$19 ; + assign dummy_fast1 = \fast1$18 ; + assign dummy_rb = \rb$17 ; + assign dummy_ra = \ra$16 ; + assign { dummy_trap_op__SV_Ptype, dummy_trap_op__sv_saturate, dummy_trap_op__sv_pred_dz, dummy_trap_op__sv_pred_sz, dummy_trap_op__ldst_exc, dummy_trap_op__trapaddr, dummy_trap_op__traptype, dummy_trap_op__is_32bit, dummy_trap_op__svstate, dummy_trap_op__cia, dummy_trap_op__msr, dummy_trap_op__insn, dummy_trap_op__fn_unit, dummy_trap_op__insn_type } = { \trap_op__SV_Ptype$15 , \trap_op__sv_saturate$14 , \trap_op__sv_pred_dz$13 , \trap_op__sv_pred_sz$12 , \trap_op__ldst_exc$11 , \trap_op__trapaddr$10 , \trap_op__traptype$9 , \trap_op__is_32bit$8 , \trap_op__svstate$7 , \trap_op__cia$6 , \trap_op__msr$5 , \trap_op__insn$4 , \trap_op__fn_unit$3 , \trap_op__insn_type$2 }; assign dummy_muxid = \muxid$1 ; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2" *) (* generator = "nMigen" *) -module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, o, o_ok, cr_a, cr_a_ok, xer_ca, xer_ca_ok, xer_ov, xer_ov_ok, xer_so, xer_so_ok, n_valid_o, n_ready_i, \muxid$1 , \alu_op__insn_type$2 , \alu_op__fn_unit$3 , \alu_op__imm_data__data$4 , \alu_op__imm_data__ok$5 , \alu_op__rc__rc$6 , \alu_op__rc__ok$7 , \alu_op__oe__oe$8 , \alu_op__oe__ok$9 , \alu_op__invert_in$10 , \alu_op__zero_a$11 , \alu_op__invert_out$12 , \alu_op__write_cr0$13 , \alu_op__input_carry$14 , \alu_op__output_carry$15 , \alu_op__is_32bit$16 , \alu_op__is_signed$17 , \alu_op__data_len$18 , \alu_op__insn$19 , \o$20 , \o_ok$21 , \cr_a$22 , \cr_a_ok$23 , \xer_ca$24 , \xer_ca_ok$25 , \xer_ov$26 , \xer_ov_ok$27 , \xer_so$28 , \xer_so_ok$29 , coresync_clk); +module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, alu_op__sv_pred_sz, alu_op__sv_pred_dz, alu_op__sv_saturate, alu_op__SV_Ptype, o, o_ok, cr_a, cr_a_ok, xer_ca, xer_ca_ok, xer_ov, xer_ov_ok, xer_so, xer_so_ok, n_valid_o, n_ready_i, \muxid$1 , \alu_op__insn_type$2 , \alu_op__fn_unit$3 , \alu_op__imm_data__data$4 , \alu_op__imm_data__ok$5 , \alu_op__rc__rc$6 , \alu_op__rc__ok$7 , \alu_op__oe__oe$8 , \alu_op__oe__ok$9 , \alu_op__invert_in$10 , \alu_op__zero_a$11 , \alu_op__invert_out$12 , \alu_op__write_cr0$13 , \alu_op__input_carry$14 , \alu_op__output_carry$15 , \alu_op__is_32bit$16 , \alu_op__is_signed$17 , \alu_op__data_len$18 , \alu_op__insn$19 , \alu_op__sv_pred_sz$20 , \alu_op__sv_pred_dz$21 , \alu_op__sv_saturate$22 , \alu_op__SV_Ptype$23 , \o$24 , \o_ok$25 , \cr_a$26 , \cr_a_ok$27 , \xer_ca$28 , \xer_ca_ok$29 , \xer_ov$30 , \xer_ov_ok$31 , \xer_so$32 , \xer_so_ok$33 , coresync_clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) - wire \$60 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + wire \$68 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] alu_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \alu_op__SV_Ptype$23 ; + reg [1:0] \alu_op__SV_Ptype$23 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \alu_op__SV_Ptype$23$next ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \alu_op__SV_Ptype$92 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [3:0] alu_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [3:0] \alu_op__data_len$18 ; reg [3:0] \alu_op__data_len$18 = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [3:0] \alu_op__data_len$18$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [3:0] \alu_op__data_len$79 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [3:0] \alu_op__data_len$87 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] alu_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] alu_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \alu_op__fn_unit$3 ; - reg [13:0] \alu_op__fn_unit$3 = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] \alu_op__fn_unit$3$next ; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \alu_op__fn_unit$3 ; + reg [14:0] \alu_op__fn_unit$3 = 15'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] \alu_op__fn_unit$3$next ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \alu_op__fn_unit$64 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \alu_op__fn_unit$72 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] alu_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \alu_op__imm_data__data$4 ; reg [63:0] \alu_op__imm_data__data$4 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] \alu_op__imm_data__data$4$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \alu_op__imm_data__data$65 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \alu_op__imm_data__data$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__imm_data__ok$5 ; reg \alu_op__imm_data__ok$5 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_op__imm_data__ok$5$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__imm_data__ok$66 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__imm_data__ok$74 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] alu_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [1:0] \alu_op__input_carry$14 ; reg [1:0] \alu_op__input_carry$14 = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [1:0] \alu_op__input_carry$14$next ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [1:0] \alu_op__input_carry$75 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \alu_op__input_carry$83 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] alu_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \alu_op__insn$19 ; reg [31:0] \alu_op__insn$19 = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] \alu_op__insn$19$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \alu_op__insn$80 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \alu_op__insn$88 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -169398,7 +181915,9 @@ module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] alu_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -169475,10 +181994,12 @@ module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] \alu_op__insn_type$2 ; reg [6:0] \alu_op__insn_type$2 = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] \alu_op__insn_type$2$next ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -169555,131 +182076,172 @@ module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \alu_op__insn_type$63 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \alu_op__insn_type$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__invert_in$10 ; reg \alu_op__invert_in$10 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_op__invert_in$10$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__invert_in$71 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__invert_in$79 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__invert_out$12 ; reg \alu_op__invert_out$12 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_op__invert_out$12$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__invert_out$73 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__invert_out$81 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__is_32bit$16 ; reg \alu_op__is_32bit$16 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_op__is_32bit$16$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__is_32bit$77 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__is_32bit$85 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__is_signed$17 ; reg \alu_op__is_signed$17 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_op__is_signed$17$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__is_signed$78 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__is_signed$86 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__oe__oe$69 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__oe__oe$77 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__oe__oe$8 ; reg \alu_op__oe__oe$8 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_op__oe__oe$8$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__oe__ok$70 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__oe__ok$78 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__oe__ok$9 ; reg \alu_op__oe__ok$9 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_op__oe__ok$9$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__output_carry$15 ; reg \alu_op__output_carry$15 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_op__output_carry$15$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__output_carry$76 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__output_carry$84 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__rc__ok$68 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__rc__ok$7 ; reg \alu_op__rc__ok$7 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_op__rc__ok$7$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__rc__ok$76 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__rc__rc$6 ; reg \alu_op__rc__rc$6 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_op__rc__rc$6$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__rc__rc$67 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__rc__rc$75 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input alu_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \alu_op__sv_pred_dz$21 ; + reg \alu_op__sv_pred_dz$21 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \alu_op__sv_pred_dz$21$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__sv_pred_dz$90 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input alu_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \alu_op__sv_pred_sz$20 ; + reg \alu_op__sv_pred_sz$20 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \alu_op__sv_pred_sz$20$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__sv_pred_sz$89 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] alu_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \alu_op__sv_saturate$22 ; + reg [1:0] \alu_op__sv_saturate$22 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \alu_op__sv_saturate$22$next ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \alu_op__sv_saturate$91 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__write_cr0$13 ; reg \alu_op__write_cr0$13 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_op__write_cr0$13$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__write_cr0$74 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__write_cr0$82 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input alu_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \alu_op__zero_a$11 ; reg \alu_op__zero_a$11 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_op__zero_a$11$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \alu_op__zero_a$72 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \alu_op__zero_a$80 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [3:0] \cr_a$22 ; - reg [3:0] \cr_a$22 = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg [3:0] \cr_a$22$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [3:0] \cr_a$83 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [3:0] \cr_a$26 ; + reg [3:0] \cr_a$26 = 4'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg [3:0] \cr_a$26$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [3:0] \cr_a$95 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input cr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \cr_a_ok$23 ; - reg \cr_a_ok$23 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg \cr_a_ok$23$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \cr_a_ok$55 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \cr_a_ok$84 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \cr_a_ok$27 ; + reg \cr_a_ok$27 = 1'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg \cr_a_ok$27$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \cr_a_ok$63 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \cr_a_ok$96 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) @@ -169688,93 +182250,107 @@ module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_o (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) reg [1:0] \muxid$1$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \muxid$62 ; + wire [1:0] \muxid$70 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *) wire n_i_rdy_data; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [63:0] \o$20 ; - reg [63:0] \o$20 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg [63:0] \o$20$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \o$81 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [63:0] \o$24 ; + reg [63:0] \o$24 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg [63:0] \o$24$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \o$93 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \o_ok$21 ; - reg \o_ok$21 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg \o_ok$21$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \o_ok$82 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \o_ok$25 ; + reg \o_ok$25 = 1'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg \o_ok$25$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \o_ok$94 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] output_alu_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \output_alu_op__SV_Ptype$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [3:0] output_alu_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [3:0] \output_alu_op__data_len$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [3:0] \output_alu_op__data_len$51 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] output_alu_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] output_alu_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \output_alu_op__fn_unit$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \output_alu_op__fn_unit$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] output_alu_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \output_alu_op__imm_data__data$33 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \output_alu_op__imm_data__data$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_alu_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_alu_op__imm_data__ok$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_alu_op__imm_data__ok$38 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [1:0] output_alu_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [1:0] \output_alu_op__input_carry$43 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \output_alu_op__input_carry$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] output_alu_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \output_alu_op__insn$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \output_alu_op__insn$52 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -169850,7 +182426,9 @@ module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] output_alu_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -169927,181 +182505,203 @@ module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_o (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \output_alu_op__insn_type$31 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \output_alu_op__insn_type$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_alu_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_alu_op__invert_in$39 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_alu_op__invert_in$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_alu_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_alu_op__invert_out$41 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_alu_op__invert_out$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_alu_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_alu_op__is_32bit$45 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_alu_op__is_32bit$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_alu_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_alu_op__is_signed$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_alu_op__is_signed$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_alu_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_alu_op__oe__oe$37 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_alu_op__oe__oe$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_alu_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_alu_op__oe__ok$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_alu_op__oe__ok$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_alu_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_alu_op__output_carry$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_alu_op__output_carry$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_alu_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_alu_op__rc__ok$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_alu_op__rc__ok$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_alu_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_alu_op__rc__rc$35 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_alu_op__rc__rc$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire output_alu_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_alu_op__sv_pred_dz$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire output_alu_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_alu_op__sv_pred_sz$53 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] output_alu_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \output_alu_op__sv_saturate$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_alu_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_alu_op__write_cr0$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_alu_op__write_cr0$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_alu_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_alu_op__zero_a$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_alu_op__zero_a$44 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [3:0] output_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [3:0] \output_cr_a$51 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [3:0] \output_cr_a$59 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire output_cr_a_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] output_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \output_muxid$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \output_muxid$34 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] output_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \output_o$49 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \output_o$57 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire output_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \output_o_ok$50 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \output_o_ok$58 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [1:0] output_xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [1:0] \output_xer_ca$52 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [1:0] \output_xer_ca$60 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire output_xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [1:0] output_xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [1:0] \output_xer_ov$53 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [1:0] \output_xer_ov$61 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire output_xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire output_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \output_xer_so$54 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \output_xer_so$62 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire output_xer_so_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) input p_valid_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *) - wire \p_valid_i$59 ; + wire \p_valid_i$67 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *) wire p_valid_i_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg r_busy = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg \r_busy$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [1:0] xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [1:0] \xer_ca$24 ; - reg [1:0] \xer_ca$24 = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg [1:0] \xer_ca$24$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [1:0] \xer_ca$85 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [1:0] \xer_ca$28 ; + reg [1:0] \xer_ca$28 = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg [1:0] \xer_ca$28$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [1:0] \xer_ca$97 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \xer_ca_ok$25 ; - reg \xer_ca_ok$25 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg \xer_ca_ok$25$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_ca_ok$56 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_ca_ok$86 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \xer_ca_ok$29 ; + reg \xer_ca_ok$29 = 1'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg \xer_ca_ok$29$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_ca_ok$64 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_ca_ok$98 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [1:0] xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [1:0] \xer_ov$26 ; - reg [1:0] \xer_ov$26 = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg [1:0] \xer_ov$26$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [1:0] \xer_ov$87 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [1:0] \xer_ov$30 ; + reg [1:0] \xer_ov$30 = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg [1:0] \xer_ov$30$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [1:0] \xer_ov$99 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \xer_ov_ok$27 ; - reg \xer_ov_ok$27 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg \xer_ov_ok$27$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_ov_ok$57 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_ov_ok$88 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_ov_ok$100 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \xer_ov_ok$31 ; + reg \xer_ov_ok$31 = 1'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg \xer_ov_ok$31$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_ov_ok$65 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \xer_so$28 ; - reg \xer_so$28 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg \xer_so$28$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_so$89 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_so$101 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \xer_so$32 ; + reg \xer_so$32 = 1'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg \xer_so$32$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input xer_so_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \xer_so_ok$29 ; - reg \xer_so_ok$29 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg \xer_so_ok$29$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_so_ok$58 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_so_ok$90 ; - assign \$60 = \p_valid_i$59 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_so_ok$102 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \xer_so_ok$33 ; + reg \xer_so_ok$33 = 1'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg \xer_so_ok$33$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_so_ok$66 ; + assign \$68 = \p_valid_i$67 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; always @(posedge coresync_clk) - \xer_so$28 <= \xer_so$28$next ; + \xer_so$32 <= \xer_so$32$next ; always @(posedge coresync_clk) - \xer_so_ok$29 <= \xer_so_ok$29$next ; + \xer_so_ok$33 <= \xer_so_ok$33$next ; always @(posedge coresync_clk) - \xer_ov$26 <= \xer_ov$26$next ; + \xer_ov$30 <= \xer_ov$30$next ; always @(posedge coresync_clk) - \xer_ov_ok$27 <= \xer_ov_ok$27$next ; + \xer_ov_ok$31 <= \xer_ov_ok$31$next ; always @(posedge coresync_clk) - \xer_ca$24 <= \xer_ca$24$next ; + \xer_ca$28 <= \xer_ca$28$next ; always @(posedge coresync_clk) - \xer_ca_ok$25 <= \xer_ca_ok$25$next ; + \xer_ca_ok$29 <= \xer_ca_ok$29$next ; always @(posedge coresync_clk) - \cr_a$22 <= \cr_a$22$next ; + \cr_a$26 <= \cr_a$26$next ; always @(posedge coresync_clk) - \cr_a_ok$23 <= \cr_a_ok$23$next ; + \cr_a_ok$27 <= \cr_a_ok$27$next ; always @(posedge coresync_clk) - \o$20 <= \o$20$next ; + \o$24 <= \o$24$next ; always @(posedge coresync_clk) - \o_ok$21 <= \o_ok$21$next ; + \o_ok$25 <= \o_ok$25$next ; always @(posedge coresync_clk) \alu_op__insn_type$2 <= \alu_op__insn_type$2$next ; always @(posedge coresync_clk) @@ -170138,6 +182738,14 @@ module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_o \alu_op__data_len$18 <= \alu_op__data_len$18$next ; always @(posedge coresync_clk) \alu_op__insn$19 <= \alu_op__insn$19$next ; + always @(posedge coresync_clk) + \alu_op__sv_pred_sz$20 <= \alu_op__sv_pred_sz$20$next ; + always @(posedge coresync_clk) + \alu_op__sv_pred_dz$21 <= \alu_op__sv_pred_dz$21$next ; + always @(posedge coresync_clk) + \alu_op__sv_saturate$22 <= \alu_op__sv_saturate$22$next ; + always @(posedge coresync_clk) + \alu_op__SV_Ptype$23 <= \alu_op__SV_Ptype$23$next ; always @(posedge coresync_clk) \muxid$1 <= \muxid$1$next ; always @(posedge coresync_clk) @@ -170147,65 +182755,92 @@ module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_o .n_valid_o(n_valid_o) ); \output \output ( + .alu_op__SV_Ptype(output_alu_op__SV_Ptype), + .\alu_op__SV_Ptype$23 (\output_alu_op__SV_Ptype$56 ), .alu_op__data_len(output_alu_op__data_len), - .\alu_op__data_len$18 (\output_alu_op__data_len$47 ), + .\alu_op__data_len$18 (\output_alu_op__data_len$51 ), .alu_op__fn_unit(output_alu_op__fn_unit), - .\alu_op__fn_unit$3 (\output_alu_op__fn_unit$32 ), + .\alu_op__fn_unit$3 (\output_alu_op__fn_unit$36 ), .alu_op__imm_data__data(output_alu_op__imm_data__data), - .\alu_op__imm_data__data$4 (\output_alu_op__imm_data__data$33 ), + .\alu_op__imm_data__data$4 (\output_alu_op__imm_data__data$37 ), .alu_op__imm_data__ok(output_alu_op__imm_data__ok), - .\alu_op__imm_data__ok$5 (\output_alu_op__imm_data__ok$34 ), + .\alu_op__imm_data__ok$5 (\output_alu_op__imm_data__ok$38 ), .alu_op__input_carry(output_alu_op__input_carry), - .\alu_op__input_carry$14 (\output_alu_op__input_carry$43 ), + .\alu_op__input_carry$14 (\output_alu_op__input_carry$47 ), .alu_op__insn(output_alu_op__insn), - .\alu_op__insn$19 (\output_alu_op__insn$48 ), + .\alu_op__insn$19 (\output_alu_op__insn$52 ), .alu_op__insn_type(output_alu_op__insn_type), - .\alu_op__insn_type$2 (\output_alu_op__insn_type$31 ), + .\alu_op__insn_type$2 (\output_alu_op__insn_type$35 ), .alu_op__invert_in(output_alu_op__invert_in), - .\alu_op__invert_in$10 (\output_alu_op__invert_in$39 ), + .\alu_op__invert_in$10 (\output_alu_op__invert_in$43 ), .alu_op__invert_out(output_alu_op__invert_out), - .\alu_op__invert_out$12 (\output_alu_op__invert_out$41 ), + .\alu_op__invert_out$12 (\output_alu_op__invert_out$45 ), .alu_op__is_32bit(output_alu_op__is_32bit), - .\alu_op__is_32bit$16 (\output_alu_op__is_32bit$45 ), + .\alu_op__is_32bit$16 (\output_alu_op__is_32bit$49 ), .alu_op__is_signed(output_alu_op__is_signed), - .\alu_op__is_signed$17 (\output_alu_op__is_signed$46 ), + .\alu_op__is_signed$17 (\output_alu_op__is_signed$50 ), .alu_op__oe__oe(output_alu_op__oe__oe), - .\alu_op__oe__oe$8 (\output_alu_op__oe__oe$37 ), + .\alu_op__oe__oe$8 (\output_alu_op__oe__oe$41 ), .alu_op__oe__ok(output_alu_op__oe__ok), - .\alu_op__oe__ok$9 (\output_alu_op__oe__ok$38 ), + .\alu_op__oe__ok$9 (\output_alu_op__oe__ok$42 ), .alu_op__output_carry(output_alu_op__output_carry), - .\alu_op__output_carry$15 (\output_alu_op__output_carry$44 ), + .\alu_op__output_carry$15 (\output_alu_op__output_carry$48 ), .alu_op__rc__ok(output_alu_op__rc__ok), - .\alu_op__rc__ok$7 (\output_alu_op__rc__ok$36 ), + .\alu_op__rc__ok$7 (\output_alu_op__rc__ok$40 ), .alu_op__rc__rc(output_alu_op__rc__rc), - .\alu_op__rc__rc$6 (\output_alu_op__rc__rc$35 ), + .\alu_op__rc__rc$6 (\output_alu_op__rc__rc$39 ), + .alu_op__sv_pred_dz(output_alu_op__sv_pred_dz), + .\alu_op__sv_pred_dz$21 (\output_alu_op__sv_pred_dz$54 ), + .alu_op__sv_pred_sz(output_alu_op__sv_pred_sz), + .\alu_op__sv_pred_sz$20 (\output_alu_op__sv_pred_sz$53 ), + .alu_op__sv_saturate(output_alu_op__sv_saturate), + .\alu_op__sv_saturate$22 (\output_alu_op__sv_saturate$55 ), .alu_op__write_cr0(output_alu_op__write_cr0), - .\alu_op__write_cr0$13 (\output_alu_op__write_cr0$42 ), + .\alu_op__write_cr0$13 (\output_alu_op__write_cr0$46 ), .alu_op__zero_a(output_alu_op__zero_a), - .\alu_op__zero_a$11 (\output_alu_op__zero_a$40 ), + .\alu_op__zero_a$11 (\output_alu_op__zero_a$44 ), .cr_a(output_cr_a), - .\cr_a$22 (\output_cr_a$51 ), + .\cr_a$26 (\output_cr_a$59 ), .cr_a_ok(output_cr_a_ok), .muxid(output_muxid), - .\muxid$1 (\output_muxid$30 ), + .\muxid$1 (\output_muxid$34 ), .o(output_o), - .\o$20 (\output_o$49 ), + .\o$24 (\output_o$57 ), .o_ok(output_o_ok), - .\o_ok$21 (\output_o_ok$50 ), + .\o_ok$25 (\output_o_ok$58 ), .xer_ca(output_xer_ca), - .\xer_ca$23 (\output_xer_ca$52 ), + .\xer_ca$27 (\output_xer_ca$60 ), .xer_ca_ok(output_xer_ca_ok), .xer_ov(output_xer_ov), - .\xer_ov$24 (\output_xer_ov$53 ), + .\xer_ov$28 (\output_xer_ov$61 ), .xer_ov_ok(output_xer_ov_ok), .xer_so(output_xer_so), - .\xer_so$25 (\output_xer_so$54 ), + .\xer_so$29 (\output_xer_so$62 ), .xer_so_ok(output_xer_so_ok) ); \p$3 p ( .p_ready_o(p_ready_o), .p_valid_i(p_valid_i) ); + always @* begin + if (\initial ) begin end + \xer_so$32$next = \xer_so$32 ; + \xer_so_ok$33$next = \xer_so_ok$33 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \xer_so_ok$33$next , \xer_so$32$next } = { \xer_so_ok$102 , \xer_so$101 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \xer_so_ok$33$next , \xer_so$32$next } = { \xer_so_ok$102 , \xer_so$101 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + casez (coresync_rst) + 1'h1: + \xer_so_ok$33$next = 1'h0; + endcase + end always @* begin if (\initial ) begin end \r_busy$next = r_busy; @@ -170218,7 +182853,7 @@ module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_o 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -170231,10 +182866,10 @@ module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_o casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \muxid$1$next = \muxid$62 ; + \muxid$1$next = \muxid$70 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \muxid$1$next = \muxid$62 ; + \muxid$1$next = \muxid$70 ; endcase end always @* begin @@ -170257,16 +182892,20 @@ module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_o \alu_op__is_signed$17$next = \alu_op__is_signed$17 ; \alu_op__data_len$18$next = \alu_op__data_len$18 ; \alu_op__insn$19$next = \alu_op__insn$19 ; + \alu_op__sv_pred_sz$20$next = \alu_op__sv_pred_sz$20 ; + \alu_op__sv_pred_dz$21$next = \alu_op__sv_pred_dz$21 ; + \alu_op__sv_saturate$22$next = \alu_op__sv_saturate$22 ; + \alu_op__SV_Ptype$23$next = \alu_op__SV_Ptype$23 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \alu_op__insn$19$next , \alu_op__data_len$18$next , \alu_op__is_signed$17$next , \alu_op__is_32bit$16$next , \alu_op__output_carry$15$next , \alu_op__input_carry$14$next , \alu_op__write_cr0$13$next , \alu_op__invert_out$12$next , \alu_op__zero_a$11$next , \alu_op__invert_in$10$next , \alu_op__oe__ok$9$next , \alu_op__oe__oe$8$next , \alu_op__rc__ok$7$next , \alu_op__rc__rc$6$next , \alu_op__imm_data__ok$5$next , \alu_op__imm_data__data$4$next , \alu_op__fn_unit$3$next , \alu_op__insn_type$2$next } = { \alu_op__insn$80 , \alu_op__data_len$79 , \alu_op__is_signed$78 , \alu_op__is_32bit$77 , \alu_op__output_carry$76 , \alu_op__input_carry$75 , \alu_op__write_cr0$74 , \alu_op__invert_out$73 , \alu_op__zero_a$72 , \alu_op__invert_in$71 , \alu_op__oe__ok$70 , \alu_op__oe__oe$69 , \alu_op__rc__ok$68 , \alu_op__rc__rc$67 , \alu_op__imm_data__ok$66 , \alu_op__imm_data__data$65 , \alu_op__fn_unit$64 , \alu_op__insn_type$63 }; + { \alu_op__SV_Ptype$23$next , \alu_op__sv_saturate$22$next , \alu_op__sv_pred_dz$21$next , \alu_op__sv_pred_sz$20$next , \alu_op__insn$19$next , \alu_op__data_len$18$next , \alu_op__is_signed$17$next , \alu_op__is_32bit$16$next , \alu_op__output_carry$15$next , \alu_op__input_carry$14$next , \alu_op__write_cr0$13$next , \alu_op__invert_out$12$next , \alu_op__zero_a$11$next , \alu_op__invert_in$10$next , \alu_op__oe__ok$9$next , \alu_op__oe__oe$8$next , \alu_op__rc__ok$7$next , \alu_op__rc__rc$6$next , \alu_op__imm_data__ok$5$next , \alu_op__imm_data__data$4$next , \alu_op__fn_unit$3$next , \alu_op__insn_type$2$next } = { \alu_op__SV_Ptype$92 , \alu_op__sv_saturate$91 , \alu_op__sv_pred_dz$90 , \alu_op__sv_pred_sz$89 , \alu_op__insn$88 , \alu_op__data_len$87 , \alu_op__is_signed$86 , \alu_op__is_32bit$85 , \alu_op__output_carry$84 , \alu_op__input_carry$83 , \alu_op__write_cr0$82 , \alu_op__invert_out$81 , \alu_op__zero_a$80 , \alu_op__invert_in$79 , \alu_op__oe__ok$78 , \alu_op__oe__oe$77 , \alu_op__rc__ok$76 , \alu_op__rc__rc$75 , \alu_op__imm_data__ok$74 , \alu_op__imm_data__data$73 , \alu_op__fn_unit$72 , \alu_op__insn_type$71 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \alu_op__insn$19$next , \alu_op__data_len$18$next , \alu_op__is_signed$17$next , \alu_op__is_32bit$16$next , \alu_op__output_carry$15$next , \alu_op__input_carry$14$next , \alu_op__write_cr0$13$next , \alu_op__invert_out$12$next , \alu_op__zero_a$11$next , \alu_op__invert_in$10$next , \alu_op__oe__ok$9$next , \alu_op__oe__oe$8$next , \alu_op__rc__ok$7$next , \alu_op__rc__rc$6$next , \alu_op__imm_data__ok$5$next , \alu_op__imm_data__data$4$next , \alu_op__fn_unit$3$next , \alu_op__insn_type$2$next } = { \alu_op__insn$80 , \alu_op__data_len$79 , \alu_op__is_signed$78 , \alu_op__is_32bit$77 , \alu_op__output_carry$76 , \alu_op__input_carry$75 , \alu_op__write_cr0$74 , \alu_op__invert_out$73 , \alu_op__zero_a$72 , \alu_op__invert_in$71 , \alu_op__oe__ok$70 , \alu_op__oe__oe$69 , \alu_op__rc__ok$68 , \alu_op__rc__rc$67 , \alu_op__imm_data__ok$66 , \alu_op__imm_data__data$65 , \alu_op__fn_unit$64 , \alu_op__insn_type$63 }; + { \alu_op__SV_Ptype$23$next , \alu_op__sv_saturate$22$next , \alu_op__sv_pred_dz$21$next , \alu_op__sv_pred_sz$20$next , \alu_op__insn$19$next , \alu_op__data_len$18$next , \alu_op__is_signed$17$next , \alu_op__is_32bit$16$next , \alu_op__output_carry$15$next , \alu_op__input_carry$14$next , \alu_op__write_cr0$13$next , \alu_op__invert_out$12$next , \alu_op__zero_a$11$next , \alu_op__invert_in$10$next , \alu_op__oe__ok$9$next , \alu_op__oe__oe$8$next , \alu_op__rc__ok$7$next , \alu_op__rc__rc$6$next , \alu_op__imm_data__ok$5$next , \alu_op__imm_data__data$4$next , \alu_op__fn_unit$3$next , \alu_op__insn_type$2$next } = { \alu_op__SV_Ptype$92 , \alu_op__sv_saturate$91 , \alu_op__sv_pred_dz$90 , \alu_op__sv_pred_sz$89 , \alu_op__insn$88 , \alu_op__data_len$87 , \alu_op__is_signed$86 , \alu_op__is_32bit$85 , \alu_op__output_carry$84 , \alu_op__input_carry$83 , \alu_op__write_cr0$82 , \alu_op__invert_out$81 , \alu_op__zero_a$80 , \alu_op__invert_in$79 , \alu_op__oe__ok$78 , \alu_op__oe__oe$77 , \alu_op__rc__ok$76 , \alu_op__rc__rc$75 , \alu_op__imm_data__ok$74 , \alu_op__imm_data__data$73 , \alu_op__fn_unit$72 , \alu_op__insn_type$71 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -170281,150 +182920,131 @@ module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_o end always @* begin if (\initial ) begin end - \o$20$next = \o$20 ; - \o_ok$21$next = \o_ok$21 ; + \o$24$next = \o$24 ; + \o_ok$25$next = \o_ok$25 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \o_ok$21$next , \o$20$next } = { \o_ok$82 , \o$81 }; + { \o_ok$25$next , \o$24$next } = { \o_ok$94 , \o$93 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \o_ok$21$next , \o$20$next } = { \o_ok$82 , \o$81 }; + { \o_ok$25$next , \o$24$next } = { \o_ok$94 , \o$93 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \o_ok$21$next = 1'h0; + \o_ok$25$next = 1'h0; endcase end always @* begin if (\initial ) begin end - \cr_a$22$next = \cr_a$22 ; - \cr_a_ok$23$next = \cr_a_ok$23 ; + \cr_a$26$next = \cr_a$26 ; + \cr_a_ok$27$next = \cr_a_ok$27 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \cr_a_ok$23$next , \cr_a$22$next } = { \cr_a_ok$84 , \cr_a$83 }; + { \cr_a_ok$27$next , \cr_a$26$next } = { \cr_a_ok$96 , \cr_a$95 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \cr_a_ok$23$next , \cr_a$22$next } = { \cr_a_ok$84 , \cr_a$83 }; + { \cr_a_ok$27$next , \cr_a$26$next } = { \cr_a_ok$96 , \cr_a$95 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \cr_a_ok$23$next = 1'h0; + \cr_a_ok$27$next = 1'h0; endcase end always @* begin if (\initial ) begin end - \xer_ca$24$next = \xer_ca$24 ; - \xer_ca_ok$25$next = \xer_ca_ok$25 ; + \xer_ca$28$next = \xer_ca$28 ; + \xer_ca_ok$29$next = \xer_ca_ok$29 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \xer_ca_ok$25$next , \xer_ca$24$next } = { \xer_ca_ok$86 , \xer_ca$85 }; + { \xer_ca_ok$29$next , \xer_ca$28$next } = { \xer_ca_ok$98 , \xer_ca$97 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \xer_ca_ok$25$next , \xer_ca$24$next } = { \xer_ca_ok$86 , \xer_ca$85 }; + { \xer_ca_ok$29$next , \xer_ca$28$next } = { \xer_ca_ok$98 , \xer_ca$97 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \xer_ca_ok$25$next = 1'h0; + \xer_ca_ok$29$next = 1'h0; endcase end always @* begin if (\initial ) begin end - \xer_ov$26$next = \xer_ov$26 ; - \xer_ov_ok$27$next = \xer_ov_ok$27 ; + \xer_ov$30$next = \xer_ov$30 ; + \xer_ov_ok$31$next = \xer_ov_ok$31 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \xer_ov_ok$27$next , \xer_ov$26$next } = { \xer_ov_ok$88 , \xer_ov$87 }; + { \xer_ov_ok$31$next , \xer_ov$30$next } = { \xer_ov_ok$100 , \xer_ov$99 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \xer_ov_ok$27$next , \xer_ov$26$next } = { \xer_ov_ok$88 , \xer_ov$87 }; + { \xer_ov_ok$31$next , \xer_ov$30$next } = { \xer_ov_ok$100 , \xer_ov$99 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \xer_ov_ok$27$next = 1'h0; - endcase - end - always @* begin - if (\initial ) begin end - \xer_so$28$next = \xer_so$28 ; - \xer_so_ok$29$next = \xer_so_ok$29 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) - casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) - /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ - 2'b?1: - { \xer_so_ok$29$next , \xer_so$28$next } = { \xer_so_ok$90 , \xer_so$89 }; - /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ - 2'b1?: - { \xer_so_ok$29$next , \xer_so$28$next } = { \xer_so_ok$90 , \xer_so$89 }; - endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) - casez (coresync_rst) - 1'h1: - \xer_so_ok$29$next = 1'h0; + \xer_ov_ok$31$next = 1'h0; endcase end assign p_ready_o = n_i_rdy_data; assign n_valid_o = r_busy; - assign { \xer_so_ok$90 , \xer_so$89 } = { output_xer_so_ok, \output_xer_so$54 }; - assign { \xer_ov_ok$88 , \xer_ov$87 } = { output_xer_ov_ok, \output_xer_ov$53 }; - assign { \xer_ca_ok$86 , \xer_ca$85 } = { output_xer_ca_ok, \output_xer_ca$52 }; - assign { \cr_a_ok$84 , \cr_a$83 } = { output_cr_a_ok, \output_cr_a$51 }; - assign { \o_ok$82 , \o$81 } = { \output_o_ok$50 , \output_o$49 }; - assign { \alu_op__insn$80 , \alu_op__data_len$79 , \alu_op__is_signed$78 , \alu_op__is_32bit$77 , \alu_op__output_carry$76 , \alu_op__input_carry$75 , \alu_op__write_cr0$74 , \alu_op__invert_out$73 , \alu_op__zero_a$72 , \alu_op__invert_in$71 , \alu_op__oe__ok$70 , \alu_op__oe__oe$69 , \alu_op__rc__ok$68 , \alu_op__rc__rc$67 , \alu_op__imm_data__ok$66 , \alu_op__imm_data__data$65 , \alu_op__fn_unit$64 , \alu_op__insn_type$63 } = { \output_alu_op__insn$48 , \output_alu_op__data_len$47 , \output_alu_op__is_signed$46 , \output_alu_op__is_32bit$45 , \output_alu_op__output_carry$44 , \output_alu_op__input_carry$43 , \output_alu_op__write_cr0$42 , \output_alu_op__invert_out$41 , \output_alu_op__zero_a$40 , \output_alu_op__invert_in$39 , \output_alu_op__oe__ok$38 , \output_alu_op__oe__oe$37 , \output_alu_op__rc__ok$36 , \output_alu_op__rc__rc$35 , \output_alu_op__imm_data__ok$34 , \output_alu_op__imm_data__data$33 , \output_alu_op__fn_unit$32 , \output_alu_op__insn_type$31 }; - assign \muxid$62 = \output_muxid$30 ; - assign p_valid_i_p_ready_o = \$60 ; + assign { \xer_so_ok$102 , \xer_so$101 } = { output_xer_so_ok, \output_xer_so$62 }; + assign { \xer_ov_ok$100 , \xer_ov$99 } = { output_xer_ov_ok, \output_xer_ov$61 }; + assign { \xer_ca_ok$98 , \xer_ca$97 } = { output_xer_ca_ok, \output_xer_ca$60 }; + assign { \cr_a_ok$96 , \cr_a$95 } = { output_cr_a_ok, \output_cr_a$59 }; + assign { \o_ok$94 , \o$93 } = { \output_o_ok$58 , \output_o$57 }; + assign { \alu_op__SV_Ptype$92 , \alu_op__sv_saturate$91 , \alu_op__sv_pred_dz$90 , \alu_op__sv_pred_sz$89 , \alu_op__insn$88 , \alu_op__data_len$87 , \alu_op__is_signed$86 , \alu_op__is_32bit$85 , \alu_op__output_carry$84 , \alu_op__input_carry$83 , \alu_op__write_cr0$82 , \alu_op__invert_out$81 , \alu_op__zero_a$80 , \alu_op__invert_in$79 , \alu_op__oe__ok$78 , \alu_op__oe__oe$77 , \alu_op__rc__ok$76 , \alu_op__rc__rc$75 , \alu_op__imm_data__ok$74 , \alu_op__imm_data__data$73 , \alu_op__fn_unit$72 , \alu_op__insn_type$71 } = { \output_alu_op__SV_Ptype$56 , \output_alu_op__sv_saturate$55 , \output_alu_op__sv_pred_dz$54 , \output_alu_op__sv_pred_sz$53 , \output_alu_op__insn$52 , \output_alu_op__data_len$51 , \output_alu_op__is_signed$50 , \output_alu_op__is_32bit$49 , \output_alu_op__output_carry$48 , \output_alu_op__input_carry$47 , \output_alu_op__write_cr0$46 , \output_alu_op__invert_out$45 , \output_alu_op__zero_a$44 , \output_alu_op__invert_in$43 , \output_alu_op__oe__ok$42 , \output_alu_op__oe__oe$41 , \output_alu_op__rc__ok$40 , \output_alu_op__rc__rc$39 , \output_alu_op__imm_data__ok$38 , \output_alu_op__imm_data__data$37 , \output_alu_op__fn_unit$36 , \output_alu_op__insn_type$35 }; + assign \muxid$70 = \output_muxid$34 ; + assign p_valid_i_p_ready_o = \$68 ; assign n_i_rdy_data = n_ready_i; - assign \p_valid_i$59 = p_valid_i; - assign { \xer_so_ok$58 , output_xer_so } = { xer_so_ok, xer_so }; - assign { \xer_ov_ok$57 , output_xer_ov } = { xer_ov_ok, xer_ov }; - assign { \xer_ca_ok$56 , output_xer_ca } = { xer_ca_ok, xer_ca }; - assign { \cr_a_ok$55 , output_cr_a } = { cr_a_ok, cr_a }; + assign \p_valid_i$67 = p_valid_i; + assign { \xer_so_ok$66 , output_xer_so } = { xer_so_ok, xer_so }; + assign { \xer_ov_ok$65 , output_xer_ov } = { xer_ov_ok, xer_ov }; + assign { \xer_ca_ok$64 , output_xer_ca } = { xer_ca_ok, xer_ca }; + assign { \cr_a_ok$63 , output_cr_a } = { cr_a_ok, cr_a }; assign { output_o_ok, output_o } = { o_ok, o }; - assign { output_alu_op__insn, output_alu_op__data_len, output_alu_op__is_signed, output_alu_op__is_32bit, output_alu_op__output_carry, output_alu_op__input_carry, output_alu_op__write_cr0, output_alu_op__invert_out, output_alu_op__zero_a, output_alu_op__invert_in, output_alu_op__oe__ok, output_alu_op__oe__oe, output_alu_op__rc__ok, output_alu_op__rc__rc, output_alu_op__imm_data__ok, output_alu_op__imm_data__data, output_alu_op__fn_unit, output_alu_op__insn_type } = { alu_op__insn, alu_op__data_len, alu_op__is_signed, alu_op__is_32bit, alu_op__output_carry, alu_op__input_carry, alu_op__write_cr0, alu_op__invert_out, alu_op__zero_a, alu_op__invert_in, alu_op__oe__ok, alu_op__oe__oe, alu_op__rc__ok, alu_op__rc__rc, alu_op__imm_data__ok, alu_op__imm_data__data, alu_op__fn_unit, alu_op__insn_type }; + assign { output_alu_op__SV_Ptype, output_alu_op__sv_saturate, output_alu_op__sv_pred_dz, output_alu_op__sv_pred_sz, output_alu_op__insn, output_alu_op__data_len, output_alu_op__is_signed, output_alu_op__is_32bit, output_alu_op__output_carry, output_alu_op__input_carry, output_alu_op__write_cr0, output_alu_op__invert_out, output_alu_op__zero_a, output_alu_op__invert_in, output_alu_op__oe__ok, output_alu_op__oe__oe, output_alu_op__rc__ok, output_alu_op__rc__rc, output_alu_op__imm_data__ok, output_alu_op__imm_data__data, output_alu_op__fn_unit, output_alu_op__insn_type } = { alu_op__SV_Ptype, alu_op__sv_saturate, alu_op__sv_pred_dz, alu_op__sv_pred_sz, alu_op__insn, alu_op__data_len, alu_op__is_signed, alu_op__is_32bit, alu_op__output_carry, alu_op__input_carry, alu_op__write_cr0, alu_op__invert_out, alu_op__zero_a, alu_op__invert_in, alu_op__oe__ok, alu_op__oe__oe, alu_op__rc__ok, alu_op__rc__rc, alu_op__imm_data__ok, alu_op__imm_data__data, alu_op__fn_unit, alu_op__insn_type }; assign output_muxid = muxid; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2" *) (* generator = "nMigen" *) -module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, o, o_ok, cr_a, cr_a_ok, xer_so, xer_so_ok, xer_ca, xer_ca_ok, n_valid_o, n_ready_i, \muxid$1 , \sr_op__insn_type$2 , \sr_op__fn_unit$3 , \sr_op__imm_data__data$4 , \sr_op__imm_data__ok$5 , \sr_op__rc__rc$6 , \sr_op__rc__ok$7 , \sr_op__oe__oe$8 , \sr_op__oe__ok$9 , \sr_op__write_cr0$10 , \sr_op__invert_in$11 , \sr_op__input_carry$12 , \sr_op__output_carry$13 , \sr_op__input_cr$14 , \sr_op__output_cr$15 , \sr_op__is_32bit$16 , \sr_op__is_signed$17 , \sr_op__insn$18 , \o$19 , \o_ok$20 , \cr_a$21 , \cr_a_ok$22 , \xer_ca$23 , \xer_ca_ok$24 , coresync_clk); +module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, sr_op__sv_pred_sz, sr_op__sv_pred_dz, sr_op__sv_saturate, sr_op__SV_Ptype, o, o_ok, cr_a, cr_a_ok, xer_so, xer_so_ok, xer_ca, xer_ca_ok, n_valid_o, n_ready_i, \muxid$1 , \sr_op__insn_type$2 , \sr_op__fn_unit$3 , \sr_op__imm_data__data$4 , \sr_op__imm_data__ok$5 , \sr_op__rc__rc$6 , \sr_op__rc__ok$7 , \sr_op__oe__oe$8 , \sr_op__oe__ok$9 , \sr_op__write_cr0$10 , \sr_op__invert_in$11 , \sr_op__input_carry$12 , \sr_op__output_carry$13 , \sr_op__input_cr$14 , \sr_op__output_cr$15 , \sr_op__is_32bit$16 , \sr_op__is_signed$17 , \sr_op__insn$18 , \sr_op__sv_pred_sz$19 , \sr_op__sv_pred_dz$20 , \sr_op__sv_saturate$21 , \sr_op__SV_Ptype$22 , \o$23 , \o_ok$24 , \cr_a$25 , \cr_a_ok$26 , \xer_ca$27 , \xer_ca_ok$28 , coresync_clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) - wire \$51 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + wire \$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [3:0] cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [3:0] \cr_a$21 ; - reg [3:0] \cr_a$21 = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg [3:0] \cr_a$21$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [3:0] \cr_a$73 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [3:0] \cr_a$25 ; + reg [3:0] \cr_a$25 = 4'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg [3:0] \cr_a$25$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [3:0] \cr_a$85 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input cr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \cr_a_ok$22 ; - reg \cr_a_ok$22 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg \cr_a_ok$22$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \cr_a_ok$47 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \cr_a_ok$74 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \cr_a_ok$26 ; + reg \cr_a_ok$26 = 1'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg \cr_a_ok$26$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \cr_a_ok$55 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \cr_a_ok$86 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) @@ -170433,111 +183053,125 @@ module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) reg [1:0] \muxid$1$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \muxid$53 ; + wire [1:0] \muxid$61 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *) wire n_i_rdy_data; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [63:0] \o$19 ; - reg [63:0] \o$19 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg [63:0] \o$19$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \o$71 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [63:0] \o$23 ; + reg [63:0] \o$23 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg [63:0] \o$23$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \o$83 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \o_ok$20 ; - reg \o_ok$20 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg \o_ok$20$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \o_ok$72 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \o_ok$24 ; + reg \o_ok$24 = 1'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg \o_ok$24$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \o_ok$84 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [3:0] output_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [3:0] \output_cr_a$45 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [3:0] \output_cr_a$53 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire output_cr_a_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] output_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \output_muxid$25 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \output_muxid$29 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] output_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \output_o$43 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \output_o$51 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire output_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \output_o_ok$44 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \output_o_ok$52 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] output_sr_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \output_sr_op__SV_Ptype$50 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] output_sr_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] output_sr_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \output_sr_op__fn_unit$27 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \output_sr_op__fn_unit$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] output_sr_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \output_sr_op__imm_data__data$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \output_sr_op__imm_data__data$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_sr_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_sr_op__imm_data__ok$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_sr_op__imm_data__ok$33 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [1:0] output_sr_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [1:0] \output_sr_op__input_carry$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \output_sr_op__input_carry$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_sr_op__input_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_sr_op__input_cr$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_sr_op__input_cr$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] output_sr_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \output_sr_op__insn$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \output_sr_op__insn$46 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -170613,7 +183247,9 @@ module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] output_sr_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -170690,179 +183326,225 @@ module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \output_sr_op__insn_type$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \output_sr_op__insn_type$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_sr_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_sr_op__invert_in$35 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_sr_op__invert_in$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_sr_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_sr_op__is_32bit$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_sr_op__is_32bit$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_sr_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_sr_op__is_signed$41 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_sr_op__is_signed$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_sr_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_sr_op__oe__oe$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_sr_op__oe__oe$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_sr_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_sr_op__oe__ok$33 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_sr_op__oe__ok$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_sr_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_sr_op__output_carry$37 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_sr_op__output_carry$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_sr_op__output_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_sr_op__output_cr$39 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_sr_op__output_cr$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_sr_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_sr_op__rc__ok$31 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_sr_op__rc__ok$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_sr_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_sr_op__rc__rc$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_sr_op__rc__rc$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire output_sr_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_sr_op__sv_pred_dz$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire output_sr_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_sr_op__sv_pred_sz$47 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] output_sr_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \output_sr_op__sv_saturate$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_sr_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_sr_op__write_cr0$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_sr_op__write_cr0$38 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [1:0] output_xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [1:0] \output_xer_ca$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [1:0] \output_xer_ca$54 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire output_xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire output_xer_so; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) input p_valid_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *) - wire \p_valid_i$50 ; + wire \p_valid_i$58 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *) wire p_valid_i_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg r_busy = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg \r_busy$next ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] sr_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \sr_op__SV_Ptype$22 ; + reg [1:0] \sr_op__SV_Ptype$22 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \sr_op__SV_Ptype$22$next ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \sr_op__SV_Ptype$82 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] sr_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] sr_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \sr_op__fn_unit$3 ; - reg [13:0] \sr_op__fn_unit$3 = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] \sr_op__fn_unit$3$next ; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \sr_op__fn_unit$3 ; + reg [14:0] \sr_op__fn_unit$3 = 15'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] \sr_op__fn_unit$3$next ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \sr_op__fn_unit$55 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \sr_op__fn_unit$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] sr_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \sr_op__imm_data__data$4 ; reg [63:0] \sr_op__imm_data__data$4 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] \sr_op__imm_data__data$4$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \sr_op__imm_data__data$56 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \sr_op__imm_data__data$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__imm_data__ok$5 ; reg \sr_op__imm_data__ok$5 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \sr_op__imm_data__ok$5$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__imm_data__ok$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__imm_data__ok$65 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] sr_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [1:0] \sr_op__input_carry$12 ; reg [1:0] \sr_op__input_carry$12 = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [1:0] \sr_op__input_carry$12$next ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [1:0] \sr_op__input_carry$64 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \sr_op__input_carry$72 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__input_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__input_cr$14 ; reg \sr_op__input_cr$14 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \sr_op__input_cr$14$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__input_cr$66 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__input_cr$74 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] sr_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \sr_op__insn$18 ; reg [31:0] \sr_op__insn$18 = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] \sr_op__insn$18$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \sr_op__insn$70 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \sr_op__insn$78 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -170938,7 +183620,9 @@ module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] sr_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -171015,10 +183699,12 @@ module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] \sr_op__insn_type$2 ; reg [6:0] \sr_op__insn_type$2 = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] \sr_op__insn_type$2$next ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -171095,137 +183781,178 @@ module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \sr_op__insn_type$54 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \sr_op__insn_type$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__invert_in$11 ; reg \sr_op__invert_in$11 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \sr_op__invert_in$11$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__invert_in$63 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__invert_in$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__is_32bit$16 ; reg \sr_op__is_32bit$16 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \sr_op__is_32bit$16$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__is_32bit$68 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__is_32bit$76 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__is_signed$17 ; reg \sr_op__is_signed$17 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \sr_op__is_signed$17$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__is_signed$69 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__is_signed$77 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__oe__oe$60 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__oe__oe$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__oe__oe$8 ; reg \sr_op__oe__oe$8 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \sr_op__oe__oe$8$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__oe__ok$61 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__oe__ok$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__oe__ok$9 ; reg \sr_op__oe__ok$9 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \sr_op__oe__ok$9$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__output_carry$13 ; reg \sr_op__output_carry$13 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \sr_op__output_carry$13$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__output_carry$65 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__output_carry$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__output_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__output_cr$15 ; reg \sr_op__output_cr$15 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \sr_op__output_cr$15$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__output_cr$67 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__output_cr$75 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__rc__ok$59 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__rc__ok$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__rc__ok$7 ; reg \sr_op__rc__ok$7 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \sr_op__rc__ok$7$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__rc__rc$58 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__rc__rc$6 ; reg \sr_op__rc__rc$6 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \sr_op__rc__rc$6$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__rc__rc$66 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input sr_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \sr_op__sv_pred_dz$20 ; + reg \sr_op__sv_pred_dz$20 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \sr_op__sv_pred_dz$20$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__sv_pred_dz$80 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input sr_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \sr_op__sv_pred_sz$19 ; + reg \sr_op__sv_pred_sz$19 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \sr_op__sv_pred_sz$19$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__sv_pred_sz$79 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] sr_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \sr_op__sv_saturate$21 ; + reg [1:0] \sr_op__sv_saturate$21 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \sr_op__sv_saturate$21$next ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \sr_op__sv_saturate$81 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input sr_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \sr_op__write_cr0$10 ; reg \sr_op__write_cr0$10 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \sr_op__write_cr0$10$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \sr_op__write_cr0$62 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \sr_op__write_cr0$70 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [1:0] xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [1:0] \xer_ca$23 ; - reg [1:0] \xer_ca$23 = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg [1:0] \xer_ca$23$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [1:0] \xer_ca$75 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [1:0] \xer_ca$27 ; + reg [1:0] \xer_ca$27 = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg [1:0] \xer_ca$27$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [1:0] \xer_ca$87 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \xer_ca_ok$24 ; - reg \xer_ca_ok$24 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg \xer_ca_ok$24$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_ca_ok$49 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_ca_ok$76 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \xer_ca_ok$28 ; + reg \xer_ca_ok$28 = 1'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg \xer_ca_ok$28$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_ca_ok$57 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_ca_ok$88 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input xer_so_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_so_ok$48 ; - assign \$51 = \p_valid_i$50 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_so_ok$56 ; + assign \$59 = \p_valid_i$58 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; always @(posedge coresync_clk) - \xer_ca$23 <= \xer_ca$23$next ; + \xer_ca$27 <= \xer_ca$27$next ; always @(posedge coresync_clk) - \xer_ca_ok$24 <= \xer_ca_ok$24$next ; + \xer_ca_ok$28 <= \xer_ca_ok$28$next ; always @(posedge coresync_clk) - \cr_a$21 <= \cr_a$21$next ; + \cr_a$25 <= \cr_a$25$next ; always @(posedge coresync_clk) - \cr_a_ok$22 <= \cr_a_ok$22$next ; + \cr_a_ok$26 <= \cr_a_ok$26$next ; always @(posedge coresync_clk) - \o$19 <= \o$19$next ; + \o$23 <= \o$23$next ; always @(posedge coresync_clk) - \o_ok$20 <= \o_ok$20$next ; + \o_ok$24 <= \o_ok$24$next ; always @(posedge coresync_clk) \sr_op__insn_type$2 <= \sr_op__insn_type$2$next ; always @(posedge coresync_clk) @@ -171260,6 +183987,14 @@ module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, \sr_op__is_signed$17 <= \sr_op__is_signed$17$next ; always @(posedge coresync_clk) \sr_op__insn$18 <= \sr_op__insn$18$next ; + always @(posedge coresync_clk) + \sr_op__sv_pred_sz$19 <= \sr_op__sv_pred_sz$19$next ; + always @(posedge coresync_clk) + \sr_op__sv_pred_dz$20 <= \sr_op__sv_pred_dz$20$next ; + always @(posedge coresync_clk) + \sr_op__sv_saturate$21 <= \sr_op__sv_saturate$21$next ; + always @(posedge coresync_clk) + \sr_op__SV_Ptype$22 <= \sr_op__SV_Ptype$22$next ; always @(posedge coresync_clk) \muxid$1 <= \muxid$1$next ; always @(posedge coresync_clk) @@ -171270,50 +184005,58 @@ module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, ); \output$118 \output ( .cr_a(output_cr_a), - .\cr_a$21 (\output_cr_a$45 ), + .\cr_a$25 (\output_cr_a$53 ), .cr_a_ok(output_cr_a_ok), .muxid(output_muxid), - .\muxid$1 (\output_muxid$25 ), + .\muxid$1 (\output_muxid$29 ), .o(output_o), - .\o$19 (\output_o$43 ), + .\o$23 (\output_o$51 ), .o_ok(output_o_ok), - .\o_ok$20 (\output_o_ok$44 ), + .\o_ok$24 (\output_o_ok$52 ), + .sr_op__SV_Ptype(output_sr_op__SV_Ptype), + .\sr_op__SV_Ptype$22 (\output_sr_op__SV_Ptype$50 ), .sr_op__fn_unit(output_sr_op__fn_unit), - .\sr_op__fn_unit$3 (\output_sr_op__fn_unit$27 ), + .\sr_op__fn_unit$3 (\output_sr_op__fn_unit$31 ), .sr_op__imm_data__data(output_sr_op__imm_data__data), - .\sr_op__imm_data__data$4 (\output_sr_op__imm_data__data$28 ), + .\sr_op__imm_data__data$4 (\output_sr_op__imm_data__data$32 ), .sr_op__imm_data__ok(output_sr_op__imm_data__ok), - .\sr_op__imm_data__ok$5 (\output_sr_op__imm_data__ok$29 ), + .\sr_op__imm_data__ok$5 (\output_sr_op__imm_data__ok$33 ), .sr_op__input_carry(output_sr_op__input_carry), - .\sr_op__input_carry$12 (\output_sr_op__input_carry$36 ), + .\sr_op__input_carry$12 (\output_sr_op__input_carry$40 ), .sr_op__input_cr(output_sr_op__input_cr), - .\sr_op__input_cr$14 (\output_sr_op__input_cr$38 ), + .\sr_op__input_cr$14 (\output_sr_op__input_cr$42 ), .sr_op__insn(output_sr_op__insn), - .\sr_op__insn$18 (\output_sr_op__insn$42 ), + .\sr_op__insn$18 (\output_sr_op__insn$46 ), .sr_op__insn_type(output_sr_op__insn_type), - .\sr_op__insn_type$2 (\output_sr_op__insn_type$26 ), + .\sr_op__insn_type$2 (\output_sr_op__insn_type$30 ), .sr_op__invert_in(output_sr_op__invert_in), - .\sr_op__invert_in$11 (\output_sr_op__invert_in$35 ), + .\sr_op__invert_in$11 (\output_sr_op__invert_in$39 ), .sr_op__is_32bit(output_sr_op__is_32bit), - .\sr_op__is_32bit$16 (\output_sr_op__is_32bit$40 ), + .\sr_op__is_32bit$16 (\output_sr_op__is_32bit$44 ), .sr_op__is_signed(output_sr_op__is_signed), - .\sr_op__is_signed$17 (\output_sr_op__is_signed$41 ), + .\sr_op__is_signed$17 (\output_sr_op__is_signed$45 ), .sr_op__oe__oe(output_sr_op__oe__oe), - .\sr_op__oe__oe$8 (\output_sr_op__oe__oe$32 ), + .\sr_op__oe__oe$8 (\output_sr_op__oe__oe$36 ), .sr_op__oe__ok(output_sr_op__oe__ok), - .\sr_op__oe__ok$9 (\output_sr_op__oe__ok$33 ), + .\sr_op__oe__ok$9 (\output_sr_op__oe__ok$37 ), .sr_op__output_carry(output_sr_op__output_carry), - .\sr_op__output_carry$13 (\output_sr_op__output_carry$37 ), + .\sr_op__output_carry$13 (\output_sr_op__output_carry$41 ), .sr_op__output_cr(output_sr_op__output_cr), - .\sr_op__output_cr$15 (\output_sr_op__output_cr$39 ), + .\sr_op__output_cr$15 (\output_sr_op__output_cr$43 ), .sr_op__rc__ok(output_sr_op__rc__ok), - .\sr_op__rc__ok$7 (\output_sr_op__rc__ok$31 ), + .\sr_op__rc__ok$7 (\output_sr_op__rc__ok$35 ), .sr_op__rc__rc(output_sr_op__rc__rc), - .\sr_op__rc__rc$6 (\output_sr_op__rc__rc$30 ), + .\sr_op__rc__rc$6 (\output_sr_op__rc__rc$34 ), + .sr_op__sv_pred_dz(output_sr_op__sv_pred_dz), + .\sr_op__sv_pred_dz$20 (\output_sr_op__sv_pred_dz$48 ), + .sr_op__sv_pred_sz(output_sr_op__sv_pred_sz), + .\sr_op__sv_pred_sz$19 (\output_sr_op__sv_pred_sz$47 ), + .sr_op__sv_saturate(output_sr_op__sv_saturate), + .\sr_op__sv_saturate$21 (\output_sr_op__sv_saturate$49 ), .sr_op__write_cr0(output_sr_op__write_cr0), - .\sr_op__write_cr0$10 (\output_sr_op__write_cr0$34 ), + .\sr_op__write_cr0$10 (\output_sr_op__write_cr0$38 ), .xer_ca(output_xer_ca), - .\xer_ca$22 (\output_xer_ca$46 ), + .\xer_ca$26 (\output_xer_ca$54 ), .xer_ca_ok(output_xer_ca_ok), .xer_so(output_xer_so) ); @@ -171333,7 +184076,7 @@ module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -171346,10 +184089,10 @@ module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \muxid$1$next = \muxid$53 ; + \muxid$1$next = \muxid$61 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \muxid$1$next = \muxid$53 ; + \muxid$1$next = \muxid$61 ; endcase end always @* begin @@ -171371,16 +184114,20 @@ module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, \sr_op__is_32bit$16$next = \sr_op__is_32bit$16 ; \sr_op__is_signed$17$next = \sr_op__is_signed$17 ; \sr_op__insn$18$next = \sr_op__insn$18 ; + \sr_op__sv_pred_sz$19$next = \sr_op__sv_pred_sz$19 ; + \sr_op__sv_pred_dz$20$next = \sr_op__sv_pred_dz$20 ; + \sr_op__sv_saturate$21$next = \sr_op__sv_saturate$21 ; + \sr_op__SV_Ptype$22$next = \sr_op__SV_Ptype$22 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \sr_op__insn$18$next , \sr_op__is_signed$17$next , \sr_op__is_32bit$16$next , \sr_op__output_cr$15$next , \sr_op__input_cr$14$next , \sr_op__output_carry$13$next , \sr_op__input_carry$12$next , \sr_op__invert_in$11$next , \sr_op__write_cr0$10$next , \sr_op__oe__ok$9$next , \sr_op__oe__oe$8$next , \sr_op__rc__ok$7$next , \sr_op__rc__rc$6$next , \sr_op__imm_data__ok$5$next , \sr_op__imm_data__data$4$next , \sr_op__fn_unit$3$next , \sr_op__insn_type$2$next } = { \sr_op__insn$70 , \sr_op__is_signed$69 , \sr_op__is_32bit$68 , \sr_op__output_cr$67 , \sr_op__input_cr$66 , \sr_op__output_carry$65 , \sr_op__input_carry$64 , \sr_op__invert_in$63 , \sr_op__write_cr0$62 , \sr_op__oe__ok$61 , \sr_op__oe__oe$60 , \sr_op__rc__ok$59 , \sr_op__rc__rc$58 , \sr_op__imm_data__ok$57 , \sr_op__imm_data__data$56 , \sr_op__fn_unit$55 , \sr_op__insn_type$54 }; + { \sr_op__SV_Ptype$22$next , \sr_op__sv_saturate$21$next , \sr_op__sv_pred_dz$20$next , \sr_op__sv_pred_sz$19$next , \sr_op__insn$18$next , \sr_op__is_signed$17$next , \sr_op__is_32bit$16$next , \sr_op__output_cr$15$next , \sr_op__input_cr$14$next , \sr_op__output_carry$13$next , \sr_op__input_carry$12$next , \sr_op__invert_in$11$next , \sr_op__write_cr0$10$next , \sr_op__oe__ok$9$next , \sr_op__oe__oe$8$next , \sr_op__rc__ok$7$next , \sr_op__rc__rc$6$next , \sr_op__imm_data__ok$5$next , \sr_op__imm_data__data$4$next , \sr_op__fn_unit$3$next , \sr_op__insn_type$2$next } = { \sr_op__SV_Ptype$82 , \sr_op__sv_saturate$81 , \sr_op__sv_pred_dz$80 , \sr_op__sv_pred_sz$79 , \sr_op__insn$78 , \sr_op__is_signed$77 , \sr_op__is_32bit$76 , \sr_op__output_cr$75 , \sr_op__input_cr$74 , \sr_op__output_carry$73 , \sr_op__input_carry$72 , \sr_op__invert_in$71 , \sr_op__write_cr0$70 , \sr_op__oe__ok$69 , \sr_op__oe__oe$68 , \sr_op__rc__ok$67 , \sr_op__rc__rc$66 , \sr_op__imm_data__ok$65 , \sr_op__imm_data__data$64 , \sr_op__fn_unit$63 , \sr_op__insn_type$62 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \sr_op__insn$18$next , \sr_op__is_signed$17$next , \sr_op__is_32bit$16$next , \sr_op__output_cr$15$next , \sr_op__input_cr$14$next , \sr_op__output_carry$13$next , \sr_op__input_carry$12$next , \sr_op__invert_in$11$next , \sr_op__write_cr0$10$next , \sr_op__oe__ok$9$next , \sr_op__oe__oe$8$next , \sr_op__rc__ok$7$next , \sr_op__rc__rc$6$next , \sr_op__imm_data__ok$5$next , \sr_op__imm_data__data$4$next , \sr_op__fn_unit$3$next , \sr_op__insn_type$2$next } = { \sr_op__insn$70 , \sr_op__is_signed$69 , \sr_op__is_32bit$68 , \sr_op__output_cr$67 , \sr_op__input_cr$66 , \sr_op__output_carry$65 , \sr_op__input_carry$64 , \sr_op__invert_in$63 , \sr_op__write_cr0$62 , \sr_op__oe__ok$61 , \sr_op__oe__oe$60 , \sr_op__rc__ok$59 , \sr_op__rc__rc$58 , \sr_op__imm_data__ok$57 , \sr_op__imm_data__data$56 , \sr_op__fn_unit$55 , \sr_op__insn_type$54 }; + { \sr_op__SV_Ptype$22$next , \sr_op__sv_saturate$21$next , \sr_op__sv_pred_dz$20$next , \sr_op__sv_pred_sz$19$next , \sr_op__insn$18$next , \sr_op__is_signed$17$next , \sr_op__is_32bit$16$next , \sr_op__output_cr$15$next , \sr_op__input_cr$14$next , \sr_op__output_carry$13$next , \sr_op__input_carry$12$next , \sr_op__invert_in$11$next , \sr_op__write_cr0$10$next , \sr_op__oe__ok$9$next , \sr_op__oe__oe$8$next , \sr_op__rc__ok$7$next , \sr_op__rc__rc$6$next , \sr_op__imm_data__ok$5$next , \sr_op__imm_data__data$4$next , \sr_op__fn_unit$3$next , \sr_op__insn_type$2$next } = { \sr_op__SV_Ptype$82 , \sr_op__sv_saturate$81 , \sr_op__sv_pred_dz$80 , \sr_op__sv_pred_sz$79 , \sr_op__insn$78 , \sr_op__is_signed$77 , \sr_op__is_32bit$76 , \sr_op__output_cr$75 , \sr_op__input_cr$74 , \sr_op__output_carry$73 , \sr_op__input_carry$72 , \sr_op__invert_in$71 , \sr_op__write_cr0$70 , \sr_op__oe__ok$69 , \sr_op__oe__oe$68 , \sr_op__rc__ok$67 , \sr_op__rc__rc$66 , \sr_op__imm_data__ok$65 , \sr_op__imm_data__data$64 , \sr_op__fn_unit$63 , \sr_op__insn_type$62 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -171395,195 +184142,235 @@ module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, end always @* begin if (\initial ) begin end - \o$19$next = \o$19 ; - \o_ok$20$next = \o_ok$20 ; + \o$23$next = \o$23 ; + \o_ok$24$next = \o_ok$24 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \o_ok$20$next , \o$19$next } = { \o_ok$72 , \o$71 }; + { \o_ok$24$next , \o$23$next } = { \o_ok$84 , \o$83 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \o_ok$20$next , \o$19$next } = { \o_ok$72 , \o$71 }; + { \o_ok$24$next , \o$23$next } = { \o_ok$84 , \o$83 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \o_ok$20$next = 1'h0; + \o_ok$24$next = 1'h0; endcase end always @* begin if (\initial ) begin end - \cr_a$21$next = \cr_a$21 ; - \cr_a_ok$22$next = \cr_a_ok$22 ; + \cr_a$25$next = \cr_a$25 ; + \cr_a_ok$26$next = \cr_a_ok$26 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \cr_a_ok$22$next , \cr_a$21$next } = { \cr_a_ok$74 , \cr_a$73 }; + { \cr_a_ok$26$next , \cr_a$25$next } = { \cr_a_ok$86 , \cr_a$85 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \cr_a_ok$22$next , \cr_a$21$next } = { \cr_a_ok$74 , \cr_a$73 }; + { \cr_a_ok$26$next , \cr_a$25$next } = { \cr_a_ok$86 , \cr_a$85 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \cr_a_ok$22$next = 1'h0; + \cr_a_ok$26$next = 1'h0; endcase end always @* begin if (\initial ) begin end - \xer_ca$23$next = \xer_ca$23 ; - \xer_ca_ok$24$next = \xer_ca_ok$24 ; + \xer_ca$27$next = \xer_ca$27 ; + \xer_ca_ok$28$next = \xer_ca_ok$28 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \xer_ca_ok$24$next , \xer_ca$23$next } = { \xer_ca_ok$76 , \xer_ca$75 }; + { \xer_ca_ok$28$next , \xer_ca$27$next } = { \xer_ca_ok$88 , \xer_ca$87 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \xer_ca_ok$24$next , \xer_ca$23$next } = { \xer_ca_ok$76 , \xer_ca$75 }; + { \xer_ca_ok$28$next , \xer_ca$27$next } = { \xer_ca_ok$88 , \xer_ca$87 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \xer_ca_ok$24$next = 1'h0; + \xer_ca_ok$28$next = 1'h0; endcase end assign p_ready_o = n_i_rdy_data; assign n_valid_o = r_busy; - assign { \xer_ca_ok$76 , \xer_ca$75 } = { output_xer_ca_ok, \output_xer_ca$46 }; - assign { \cr_a_ok$74 , \cr_a$73 } = { output_cr_a_ok, \output_cr_a$45 }; - assign { \o_ok$72 , \o$71 } = { \output_o_ok$44 , \output_o$43 }; - assign { \sr_op__insn$70 , \sr_op__is_signed$69 , \sr_op__is_32bit$68 , \sr_op__output_cr$67 , \sr_op__input_cr$66 , \sr_op__output_carry$65 , \sr_op__input_carry$64 , \sr_op__invert_in$63 , \sr_op__write_cr0$62 , \sr_op__oe__ok$61 , \sr_op__oe__oe$60 , \sr_op__rc__ok$59 , \sr_op__rc__rc$58 , \sr_op__imm_data__ok$57 , \sr_op__imm_data__data$56 , \sr_op__fn_unit$55 , \sr_op__insn_type$54 } = { \output_sr_op__insn$42 , \output_sr_op__is_signed$41 , \output_sr_op__is_32bit$40 , \output_sr_op__output_cr$39 , \output_sr_op__input_cr$38 , \output_sr_op__output_carry$37 , \output_sr_op__input_carry$36 , \output_sr_op__invert_in$35 , \output_sr_op__write_cr0$34 , \output_sr_op__oe__ok$33 , \output_sr_op__oe__oe$32 , \output_sr_op__rc__ok$31 , \output_sr_op__rc__rc$30 , \output_sr_op__imm_data__ok$29 , \output_sr_op__imm_data__data$28 , \output_sr_op__fn_unit$27 , \output_sr_op__insn_type$26 }; - assign \muxid$53 = \output_muxid$25 ; - assign p_valid_i_p_ready_o = \$51 ; + assign { \xer_ca_ok$88 , \xer_ca$87 } = { output_xer_ca_ok, \output_xer_ca$54 }; + assign { \cr_a_ok$86 , \cr_a$85 } = { output_cr_a_ok, \output_cr_a$53 }; + assign { \o_ok$84 , \o$83 } = { \output_o_ok$52 , \output_o$51 }; + assign { \sr_op__SV_Ptype$82 , \sr_op__sv_saturate$81 , \sr_op__sv_pred_dz$80 , \sr_op__sv_pred_sz$79 , \sr_op__insn$78 , \sr_op__is_signed$77 , \sr_op__is_32bit$76 , \sr_op__output_cr$75 , \sr_op__input_cr$74 , \sr_op__output_carry$73 , \sr_op__input_carry$72 , \sr_op__invert_in$71 , \sr_op__write_cr0$70 , \sr_op__oe__ok$69 , \sr_op__oe__oe$68 , \sr_op__rc__ok$67 , \sr_op__rc__rc$66 , \sr_op__imm_data__ok$65 , \sr_op__imm_data__data$64 , \sr_op__fn_unit$63 , \sr_op__insn_type$62 } = { \output_sr_op__SV_Ptype$50 , \output_sr_op__sv_saturate$49 , \output_sr_op__sv_pred_dz$48 , \output_sr_op__sv_pred_sz$47 , \output_sr_op__insn$46 , \output_sr_op__is_signed$45 , \output_sr_op__is_32bit$44 , \output_sr_op__output_cr$43 , \output_sr_op__input_cr$42 , \output_sr_op__output_carry$41 , \output_sr_op__input_carry$40 , \output_sr_op__invert_in$39 , \output_sr_op__write_cr0$38 , \output_sr_op__oe__ok$37 , \output_sr_op__oe__oe$36 , \output_sr_op__rc__ok$35 , \output_sr_op__rc__rc$34 , \output_sr_op__imm_data__ok$33 , \output_sr_op__imm_data__data$32 , \output_sr_op__fn_unit$31 , \output_sr_op__insn_type$30 }; + assign \muxid$61 = \output_muxid$29 ; + assign p_valid_i_p_ready_o = \$59 ; assign n_i_rdy_data = n_ready_i; - assign \p_valid_i$50 = p_valid_i; - assign { \xer_ca_ok$49 , output_xer_ca } = { xer_ca_ok, xer_ca }; - assign { \xer_so_ok$48 , output_xer_so } = { xer_so_ok, xer_so }; - assign { \cr_a_ok$47 , output_cr_a } = { cr_a_ok, cr_a }; + assign \p_valid_i$58 = p_valid_i; + assign { \xer_ca_ok$57 , output_xer_ca } = { xer_ca_ok, xer_ca }; + assign { \xer_so_ok$56 , output_xer_so } = { xer_so_ok, xer_so }; + assign { \cr_a_ok$55 , output_cr_a } = { cr_a_ok, cr_a }; assign { output_o_ok, output_o } = { o_ok, o }; - assign { output_sr_op__insn, output_sr_op__is_signed, output_sr_op__is_32bit, output_sr_op__output_cr, output_sr_op__input_cr, output_sr_op__output_carry, output_sr_op__input_carry, output_sr_op__invert_in, output_sr_op__write_cr0, output_sr_op__oe__ok, output_sr_op__oe__oe, output_sr_op__rc__ok, output_sr_op__rc__rc, output_sr_op__imm_data__ok, output_sr_op__imm_data__data, output_sr_op__fn_unit, output_sr_op__insn_type } = { sr_op__insn, sr_op__is_signed, sr_op__is_32bit, sr_op__output_cr, sr_op__input_cr, sr_op__output_carry, sr_op__input_carry, sr_op__invert_in, sr_op__write_cr0, sr_op__oe__ok, sr_op__oe__oe, sr_op__rc__ok, sr_op__rc__rc, sr_op__imm_data__ok, sr_op__imm_data__data, sr_op__fn_unit, sr_op__insn_type }; + assign { output_sr_op__SV_Ptype, output_sr_op__sv_saturate, output_sr_op__sv_pred_dz, output_sr_op__sv_pred_sz, output_sr_op__insn, output_sr_op__is_signed, output_sr_op__is_32bit, output_sr_op__output_cr, output_sr_op__input_cr, output_sr_op__output_carry, output_sr_op__input_carry, output_sr_op__invert_in, output_sr_op__write_cr0, output_sr_op__oe__ok, output_sr_op__oe__oe, output_sr_op__rc__ok, output_sr_op__rc__rc, output_sr_op__imm_data__ok, output_sr_op__imm_data__data, output_sr_op__fn_unit, output_sr_op__insn_type } = { sr_op__SV_Ptype, sr_op__sv_saturate, sr_op__sv_pred_dz, sr_op__sv_pred_sz, sr_op__insn, sr_op__is_signed, sr_op__is_32bit, sr_op__output_cr, sr_op__input_cr, sr_op__output_carry, sr_op__input_carry, sr_op__invert_in, sr_op__write_cr0, sr_op__oe__ok, sr_op__oe__oe, sr_op__rc__ok, sr_op__rc__rc, sr_op__imm_data__ok, sr_op__imm_data__data, sr_op__fn_unit, sr_op__insn_type }; assign output_muxid = muxid; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2" *) (* generator = "nMigen" *) -module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, ra, rb, fast1, fast2, n_valid_o, n_ready_i, \muxid$1 , \trap_op__insn_type$2 , \trap_op__fn_unit$3 , \trap_op__insn$4 , \trap_op__msr$5 , \trap_op__cia$6 , \trap_op__is_32bit$7 , \trap_op__traptype$8 , \trap_op__trapaddr$9 , \trap_op__ldst_exc$10 , o, o_ok, \fast1$11 , fast1_ok, \fast2$12 , fast2_ok, nia, nia_ok, msr, msr_ok, coresync_clk); +module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__svstate, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, trap_op__sv_pred_sz, trap_op__sv_pred_dz, trap_op__sv_saturate, trap_op__SV_Ptype, ra, rb, fast1, fast2, fast3, n_valid_o, n_ready_i, \muxid$1 , \trap_op__insn_type$2 , \trap_op__fn_unit$3 , \trap_op__insn$4 , \trap_op__msr$5 , \trap_op__cia$6 , \trap_op__svstate$7 , \trap_op__is_32bit$8 , \trap_op__traptype$9 , \trap_op__trapaddr$10 , \trap_op__ldst_exc$11 , \trap_op__sv_pred_sz$12 , \trap_op__sv_pred_dz$13 , \trap_op__sv_saturate$14 , \trap_op__SV_Ptype$15 , o, o_ok, \fast1$16 , fast1_ok, \fast2$17 , fast2_ok, \fast3$18 , fast3_ok, nia, nia_ok, msr, msr_ok, svstate, svstate_ok, coresync_clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) - wire \$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + wire \$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [63:0] \fast1$11 ; - reg [63:0] \fast1$11 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg [63:0] \fast1$11$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \fast1$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [63:0] \fast1$16 ; + reg [63:0] \fast1$16 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg [63:0] \fast1$16$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \fast1$57 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output fast1_ok; reg fast1_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \fast1_ok$41 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \fast1_ok$58 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \fast1_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] fast2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [63:0] \fast2$12 ; - reg [63:0] \fast2$12 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg [63:0] \fast2$12$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \fast2$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [63:0] \fast2$17 ; + reg [63:0] \fast2$17 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg [63:0] \fast2$17$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \fast2$59 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output fast2_ok; reg fast2_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \fast2_ok$43 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \fast2_ok$60 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \fast2_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + input [63:0] fast3; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [63:0] \fast3$18 ; + reg [63:0] \fast3$18 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg [63:0] \fast3$18$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \fast3$36 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \fast3$61 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output fast3_ok; + reg fast3_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \fast3_ok$62 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg \fast3_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] main_fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \main_fast1$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \main_fast1$34 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire main_fast1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] main_fast2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \main_fast2$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \main_fast2$35 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire main_fast2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] main_fast3; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire main_fast3_ok; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] main_msr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire main_msr_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] main_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \main_muxid$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \main_muxid$19 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] main_nia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire main_nia_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] main_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire main_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] main_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] main_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [31:0] main_svstate; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire main_svstate_ok; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] main_trap_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \main_trap_op__SV_Ptype$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] main_trap_op__cia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \main_trap_op__cia$18 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \main_trap_op__cia$24 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] main_trap_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] main_trap_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \main_trap_op__fn_unit$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \main_trap_op__fn_unit$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] main_trap_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \main_trap_op__insn$16 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \main_trap_op__insn$22 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -171659,7 +184446,9 @@ module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] main_trap_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -171736,41 +184525,67 @@ module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \main_trap_op__insn_type$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \main_trap_op__insn_type$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire main_trap_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \main_trap_op__is_32bit$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_trap_op__is_32bit$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [7:0] main_trap_op__ldst_exc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [7:0] \main_trap_op__ldst_exc$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [7:0] \main_trap_op__ldst_exc$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] main_trap_op__msr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \main_trap_op__msr$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \main_trap_op__msr$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire main_trap_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_trap_op__sv_pred_dz$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire main_trap_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \main_trap_op__sv_pred_sz$30 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] main_trap_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \main_trap_op__sv_saturate$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] main_trap_op__svstate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \main_trap_op__svstate$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [12:0] main_trap_op__trapaddr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [12:0] \main_trap_op__trapaddr$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [12:0] \main_trap_op__trapaddr$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [7:0] main_trap_op__traptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [7:0] \main_trap_op__traptype$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [7:0] \main_trap_op__traptype$27 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] msr; reg [63:0] msr = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \msr$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \msr$65 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [63:0] \msr$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output msr_ok; reg msr_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \msr_ok$47 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \msr_ok$66 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \msr_ok$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; @@ -171780,129 +184595,167 @@ module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) reg [1:0] \muxid$1$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \muxid$28 ; + wire [1:0] \muxid$40 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *) wire n_i_rdy_data; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] nia; reg [63:0] nia = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \nia$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \nia$63 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [63:0] \nia$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output nia_ok; reg nia_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \nia_ok$45 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \nia_ok$64 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \nia_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] o; reg [63:0] o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \o$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \o$55 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [63:0] \o$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output o_ok; reg o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \o_ok$39 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \o_ok$56 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \o_ok$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) input p_valid_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *) - wire \p_valid_i$25 ; + wire \p_valid_i$37 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *) wire p_valid_i_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg r_busy = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg \r_busy$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [31:0] svstate; + reg [31:0] svstate = 32'd0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [31:0] \svstate$67 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg [31:0] \svstate$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output svstate_ok; + reg svstate_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \svstate_ok$68 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg \svstate_ok$next ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] trap_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \trap_op__SV_Ptype$15 ; + reg [1:0] \trap_op__SV_Ptype$15 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \trap_op__SV_Ptype$15$next ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \trap_op__SV_Ptype$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] trap_op__cia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \trap_op__cia$33 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \trap_op__cia$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \trap_op__cia$6 ; reg [63:0] \trap_op__cia$6 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] \trap_op__cia$6$next ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] trap_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] trap_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \trap_op__fn_unit$3 ; - reg [13:0] \trap_op__fn_unit$3 = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] \trap_op__fn_unit$3$next ; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \trap_op__fn_unit$3 ; + reg [14:0] \trap_op__fn_unit$3 = 15'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] \trap_op__fn_unit$3$next ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \trap_op__fn_unit$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \trap_op__fn_unit$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] trap_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \trap_op__insn$31 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \trap_op__insn$4 ; reg [31:0] \trap_op__insn$4 = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] \trap_op__insn$4$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \trap_op__insn$43 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -171978,7 +184831,9 @@ module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] trap_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -172055,10 +184910,12 @@ module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] \trap_op__insn_type$2 ; reg [6:0] \trap_op__insn_type$2 = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] \trap_op__insn_type$2$next ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -172135,56 +184992,126 @@ module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \trap_op__insn_type$29 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \trap_op__insn_type$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input trap_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \trap_op__is_32bit$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output \trap_op__is_32bit$7 ; - reg \trap_op__is_32bit$7 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg \trap_op__is_32bit$7$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \trap_op__is_32bit$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \trap_op__is_32bit$8 ; + reg \trap_op__is_32bit$8 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \trap_op__is_32bit$8$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [7:0] trap_op__ldst_exc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [7:0] \trap_op__ldst_exc$10 ; - reg [7:0] \trap_op__ldst_exc$10 = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [7:0] \trap_op__ldst_exc$10$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [7:0] \trap_op__ldst_exc$37 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [7:0] \trap_op__ldst_exc$11 ; + reg [7:0] \trap_op__ldst_exc$11 = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [7:0] \trap_op__ldst_exc$11$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [7:0] \trap_op__ldst_exc$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] trap_op__msr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \trap_op__msr$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \trap_op__msr$44 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \trap_op__msr$5 ; reg [63:0] \trap_op__msr$5 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] \trap_op__msr$5$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input trap_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \trap_op__sv_pred_dz$13 ; + reg \trap_op__sv_pred_dz$13 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \trap_op__sv_pred_dz$13$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \trap_op__sv_pred_dz$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input trap_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \trap_op__sv_pred_sz$12 ; + reg \trap_op__sv_pred_sz$12 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \trap_op__sv_pred_sz$12$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \trap_op__sv_pred_sz$51 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] trap_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \trap_op__sv_saturate$14 ; + reg [1:0] \trap_op__sv_saturate$14 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \trap_op__sv_saturate$14$next ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \trap_op__sv_saturate$53 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [31:0] trap_op__svstate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \trap_op__svstate$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [31:0] \trap_op__svstate$7 ; + reg [31:0] \trap_op__svstate$7 = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [31:0] \trap_op__svstate$7$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [12:0] trap_op__trapaddr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [12:0] \trap_op__trapaddr$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [12:0] \trap_op__trapaddr$9 ; - reg [12:0] \trap_op__trapaddr$9 = 13'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [12:0] \trap_op__trapaddr$9$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [12:0] \trap_op__trapaddr$10 ; + reg [12:0] \trap_op__trapaddr$10 = 13'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [12:0] \trap_op__trapaddr$10$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [12:0] \trap_op__trapaddr$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [7:0] trap_op__traptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [7:0] \trap_op__traptype$35 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [7:0] \trap_op__traptype$8 ; - reg [7:0] \trap_op__traptype$8 = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [7:0] \trap_op__traptype$8$next ; - assign \$26 = \p_valid_i$25 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [7:0] \trap_op__traptype$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [7:0] \trap_op__traptype$9 ; + reg [7:0] \trap_op__traptype$9 = 8'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [7:0] \trap_op__traptype$9$next ; + assign \$38 = \p_valid_i$37 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; always @(posedge coresync_clk) - \fast1$11 <= \fast1$11$next ; + svstate <= \svstate$next ; + always @(posedge coresync_clk) + svstate_ok <= \svstate_ok$next ; + always @(posedge coresync_clk) + msr <= \msr$next ; + always @(posedge coresync_clk) + msr_ok <= \msr_ok$next ; + always @(posedge coresync_clk) + nia <= \nia$next ; + always @(posedge coresync_clk) + nia_ok <= \nia_ok$next ; + always @(posedge coresync_clk) + \fast3$18 <= \fast3$18$next ; + always @(posedge coresync_clk) + fast3_ok <= \fast3_ok$next ; + always @(posedge coresync_clk) + \fast2$17 <= \fast2$17$next ; + always @(posedge coresync_clk) + fast2_ok <= \fast2_ok$next ; + always @(posedge coresync_clk) + \fast1$16 <= \fast1$16$next ; always @(posedge coresync_clk) fast1_ok <= \fast1_ok$next ; always @(posedge coresync_clk) @@ -172202,64 +185129,76 @@ module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, always @(posedge coresync_clk) \trap_op__cia$6 <= \trap_op__cia$6$next ; always @(posedge coresync_clk) - \trap_op__is_32bit$7 <= \trap_op__is_32bit$7$next ; + \trap_op__svstate$7 <= \trap_op__svstate$7$next ; always @(posedge coresync_clk) - \trap_op__traptype$8 <= \trap_op__traptype$8$next ; + \trap_op__is_32bit$8 <= \trap_op__is_32bit$8$next ; always @(posedge coresync_clk) - \trap_op__trapaddr$9 <= \trap_op__trapaddr$9$next ; + \trap_op__traptype$9 <= \trap_op__traptype$9$next ; always @(posedge coresync_clk) - \trap_op__ldst_exc$10 <= \trap_op__ldst_exc$10$next ; + \trap_op__trapaddr$10 <= \trap_op__trapaddr$10$next ; always @(posedge coresync_clk) - \muxid$1 <= \muxid$1$next ; + \trap_op__ldst_exc$11 <= \trap_op__ldst_exc$11$next ; always @(posedge coresync_clk) - r_busy <= \r_busy$next ; + \trap_op__sv_pred_sz$12 <= \trap_op__sv_pred_sz$12$next ; always @(posedge coresync_clk) - msr <= \msr$next ; + \trap_op__sv_pred_dz$13 <= \trap_op__sv_pred_dz$13$next ; always @(posedge coresync_clk) - msr_ok <= \msr_ok$next ; - always @(posedge coresync_clk) - nia <= \nia$next ; + \trap_op__sv_saturate$14 <= \trap_op__sv_saturate$14$next ; always @(posedge coresync_clk) - nia_ok <= \nia_ok$next ; + \trap_op__SV_Ptype$15 <= \trap_op__SV_Ptype$15$next ; always @(posedge coresync_clk) - \fast2$12 <= \fast2$12$next ; + \muxid$1 <= \muxid$1$next ; always @(posedge coresync_clk) - fast2_ok <= \fast2_ok$next ; + r_busy <= \r_busy$next ; \main$38 main ( .fast1(main_fast1), - .\fast1$11 (\main_fast1$23 ), + .\fast1$16 (\main_fast1$34 ), .fast1_ok(main_fast1_ok), .fast2(main_fast2), - .\fast2$12 (\main_fast2$24 ), + .\fast2$17 (\main_fast2$35 ), .fast2_ok(main_fast2_ok), + .fast3(main_fast3), + .fast3_ok(main_fast3_ok), .msr(main_msr), .msr_ok(main_msr_ok), .muxid(main_muxid), - .\muxid$1 (\main_muxid$13 ), + .\muxid$1 (\main_muxid$19 ), .nia(main_nia), .nia_ok(main_nia_ok), .o(main_o), .o_ok(main_o_ok), .ra(main_ra), .rb(main_rb), + .svstate(main_svstate), + .svstate_ok(main_svstate_ok), + .trap_op__SV_Ptype(main_trap_op__SV_Ptype), + .\trap_op__SV_Ptype$15 (\main_trap_op__SV_Ptype$33 ), .trap_op__cia(main_trap_op__cia), - .\trap_op__cia$6 (\main_trap_op__cia$18 ), + .\trap_op__cia$6 (\main_trap_op__cia$24 ), .trap_op__fn_unit(main_trap_op__fn_unit), - .\trap_op__fn_unit$3 (\main_trap_op__fn_unit$15 ), + .\trap_op__fn_unit$3 (\main_trap_op__fn_unit$21 ), .trap_op__insn(main_trap_op__insn), - .\trap_op__insn$4 (\main_trap_op__insn$16 ), + .\trap_op__insn$4 (\main_trap_op__insn$22 ), .trap_op__insn_type(main_trap_op__insn_type), - .\trap_op__insn_type$2 (\main_trap_op__insn_type$14 ), + .\trap_op__insn_type$2 (\main_trap_op__insn_type$20 ), .trap_op__is_32bit(main_trap_op__is_32bit), - .\trap_op__is_32bit$7 (\main_trap_op__is_32bit$19 ), + .\trap_op__is_32bit$8 (\main_trap_op__is_32bit$26 ), .trap_op__ldst_exc(main_trap_op__ldst_exc), - .\trap_op__ldst_exc$10 (\main_trap_op__ldst_exc$22 ), + .\trap_op__ldst_exc$11 (\main_trap_op__ldst_exc$29 ), .trap_op__msr(main_trap_op__msr), - .\trap_op__msr$5 (\main_trap_op__msr$17 ), + .\trap_op__msr$5 (\main_trap_op__msr$23 ), + .trap_op__sv_pred_dz(main_trap_op__sv_pred_dz), + .\trap_op__sv_pred_dz$13 (\main_trap_op__sv_pred_dz$31 ), + .trap_op__sv_pred_sz(main_trap_op__sv_pred_sz), + .\trap_op__sv_pred_sz$12 (\main_trap_op__sv_pred_sz$30 ), + .trap_op__sv_saturate(main_trap_op__sv_saturate), + .\trap_op__sv_saturate$14 (\main_trap_op__sv_saturate$32 ), + .trap_op__svstate(main_trap_op__svstate), + .\trap_op__svstate$7 (\main_trap_op__svstate$25 ), .trap_op__trapaddr(main_trap_op__trapaddr), - .\trap_op__trapaddr$9 (\main_trap_op__trapaddr$21 ), + .\trap_op__trapaddr$10 (\main_trap_op__trapaddr$28 ), .trap_op__traptype(main_trap_op__traptype), - .\trap_op__traptype$8 (\main_trap_op__traptype$20 ) + .\trap_op__traptype$9 (\main_trap_op__traptype$27 ) ); \n$37 n ( .n_ready_i(n_ready_i), @@ -172281,7 +185220,7 @@ module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -172294,10 +185233,10 @@ module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \muxid$1$next = \muxid$28 ; + \muxid$1$next = \muxid$40 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \muxid$1$next = \muxid$28 ; + \muxid$1$next = \muxid$40 ; endcase end always @* begin @@ -172307,18 +185246,23 @@ module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, \trap_op__insn$4$next = \trap_op__insn$4 ; \trap_op__msr$5$next = \trap_op__msr$5 ; \trap_op__cia$6$next = \trap_op__cia$6 ; - \trap_op__is_32bit$7$next = \trap_op__is_32bit$7 ; - \trap_op__traptype$8$next = \trap_op__traptype$8 ; - \trap_op__trapaddr$9$next = \trap_op__trapaddr$9 ; - \trap_op__ldst_exc$10$next = \trap_op__ldst_exc$10 ; + \trap_op__svstate$7$next = \trap_op__svstate$7 ; + \trap_op__is_32bit$8$next = \trap_op__is_32bit$8 ; + \trap_op__traptype$9$next = \trap_op__traptype$9 ; + \trap_op__trapaddr$10$next = \trap_op__trapaddr$10 ; + \trap_op__ldst_exc$11$next = \trap_op__ldst_exc$11 ; + \trap_op__sv_pred_sz$12$next = \trap_op__sv_pred_sz$12 ; + \trap_op__sv_pred_dz$13$next = \trap_op__sv_pred_dz$13 ; + \trap_op__sv_saturate$14$next = \trap_op__sv_saturate$14 ; + \trap_op__SV_Ptype$15$next = \trap_op__SV_Ptype$15 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \trap_op__ldst_exc$10$next , \trap_op__trapaddr$9$next , \trap_op__traptype$8$next , \trap_op__is_32bit$7$next , \trap_op__cia$6$next , \trap_op__msr$5$next , \trap_op__insn$4$next , \trap_op__fn_unit$3$next , \trap_op__insn_type$2$next } = { \trap_op__ldst_exc$37 , \trap_op__trapaddr$36 , \trap_op__traptype$35 , \trap_op__is_32bit$34 , \trap_op__cia$33 , \trap_op__msr$32 , \trap_op__insn$31 , \trap_op__fn_unit$30 , \trap_op__insn_type$29 }; + { \trap_op__SV_Ptype$15$next , \trap_op__sv_saturate$14$next , \trap_op__sv_pred_dz$13$next , \trap_op__sv_pred_sz$12$next , \trap_op__ldst_exc$11$next , \trap_op__trapaddr$10$next , \trap_op__traptype$9$next , \trap_op__is_32bit$8$next , \trap_op__svstate$7$next , \trap_op__cia$6$next , \trap_op__msr$5$next , \trap_op__insn$4$next , \trap_op__fn_unit$3$next , \trap_op__insn_type$2$next } = { \trap_op__SV_Ptype$54 , \trap_op__sv_saturate$53 , \trap_op__sv_pred_dz$52 , \trap_op__sv_pred_sz$51 , \trap_op__ldst_exc$50 , \trap_op__trapaddr$49 , \trap_op__traptype$48 , \trap_op__is_32bit$47 , \trap_op__svstate$46 , \trap_op__cia$45 , \trap_op__msr$44 , \trap_op__insn$43 , \trap_op__fn_unit$42 , \trap_op__insn_type$41 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \trap_op__ldst_exc$10$next , \trap_op__trapaddr$9$next , \trap_op__traptype$8$next , \trap_op__is_32bit$7$next , \trap_op__cia$6$next , \trap_op__msr$5$next , \trap_op__insn$4$next , \trap_op__fn_unit$3$next , \trap_op__insn_type$2$next } = { \trap_op__ldst_exc$37 , \trap_op__trapaddr$36 , \trap_op__traptype$35 , \trap_op__is_32bit$34 , \trap_op__cia$33 , \trap_op__msr$32 , \trap_op__insn$31 , \trap_op__fn_unit$30 , \trap_op__insn_type$29 }; + { \trap_op__SV_Ptype$15$next , \trap_op__sv_saturate$14$next , \trap_op__sv_pred_dz$13$next , \trap_op__sv_pred_sz$12$next , \trap_op__ldst_exc$11$next , \trap_op__trapaddr$10$next , \trap_op__traptype$9$next , \trap_op__is_32bit$8$next , \trap_op__svstate$7$next , \trap_op__cia$6$next , \trap_op__msr$5$next , \trap_op__insn$4$next , \trap_op__fn_unit$3$next , \trap_op__insn_type$2$next } = { \trap_op__SV_Ptype$54 , \trap_op__sv_saturate$53 , \trap_op__sv_pred_dz$52 , \trap_op__sv_pred_sz$51 , \trap_op__ldst_exc$50 , \trap_op__trapaddr$49 , \trap_op__traptype$48 , \trap_op__is_32bit$47 , \trap_op__svstate$46 , \trap_op__cia$45 , \trap_op__msr$44 , \trap_op__insn$43 , \trap_op__fn_unit$42 , \trap_op__insn_type$41 }; endcase end always @* begin @@ -172329,12 +185273,12 @@ module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \o_ok$next , \o$next } = { \o_ok$39 , \o$38 }; + { \o_ok$next , \o$next } = { \o_ok$56 , \o$55 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \o_ok$next , \o$next } = { \o_ok$39 , \o$38 }; + { \o_ok$next , \o$next } = { \o_ok$56 , \o$55 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \o_ok$next = 1'h0; @@ -172342,18 +185286,18 @@ module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, end always @* begin if (\initial ) begin end - \fast1$11$next = \fast1$11 ; + \fast1$16$next = \fast1$16 ; \fast1_ok$next = fast1_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \fast1_ok$next , \fast1$11$next } = { \fast1_ok$41 , \fast1$40 }; + { \fast1_ok$next , \fast1$16$next } = { \fast1_ok$58 , \fast1$57 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \fast1_ok$next , \fast1$11$next } = { \fast1_ok$41 , \fast1$40 }; + { \fast1_ok$next , \fast1$16$next } = { \fast1_ok$58 , \fast1$57 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \fast1_ok$next = 1'h0; @@ -172361,23 +185305,42 @@ module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, end always @* begin if (\initial ) begin end - \fast2$12$next = \fast2$12 ; + \fast2$17$next = \fast2$17 ; \fast2_ok$next = fast2_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \fast2_ok$next , \fast2$12$next } = { \fast2_ok$43 , \fast2$42 }; + { \fast2_ok$next , \fast2$17$next } = { \fast2_ok$60 , \fast2$59 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \fast2_ok$next , \fast2$12$next } = { \fast2_ok$43 , \fast2$42 }; + { \fast2_ok$next , \fast2$17$next } = { \fast2_ok$60 , \fast2$59 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \fast2_ok$next = 1'h0; endcase end + always @* begin + if (\initial ) begin end + \fast3$18$next = \fast3$18 ; + \fast3_ok$next = fast3_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \fast3_ok$next , \fast3$18$next } = { \fast3_ok$62 , \fast3$61 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \fast3_ok$next , \fast3$18$next } = { \fast3_ok$62 , \fast3$61 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + casez (coresync_rst) + 1'h1: + \fast3_ok$next = 1'h0; + endcase + end always @* begin if (\initial ) begin end \nia$next = nia; @@ -172386,12 +185349,12 @@ module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \nia_ok$next , \nia$next } = { \nia_ok$45 , \nia$44 }; + { \nia_ok$next , \nia$next } = { \nia_ok$64 , \nia$63 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \nia_ok$next , \nia$next } = { \nia_ok$45 , \nia$44 }; + { \nia_ok$next , \nia$next } = { \nia_ok$64 , \nia$63 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \nia_ok$next = 1'h0; @@ -172405,66 +185368,88 @@ module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \msr_ok$next , \msr$next } = { \msr_ok$47 , \msr$46 }; + { \msr_ok$next , \msr$next } = { \msr_ok$66 , \msr$65 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \msr_ok$next , \msr$next } = { \msr_ok$47 , \msr$46 }; + { \msr_ok$next , \msr$next } = { \msr_ok$66 , \msr$65 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \msr_ok$next = 1'h0; endcase end + always @* begin + if (\initial ) begin end + \svstate$next = svstate; + \svstate_ok$next = svstate_ok; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \svstate_ok$next , \svstate$next } = { \svstate_ok$68 , \svstate$67 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \svstate_ok$next , \svstate$next } = { \svstate_ok$68 , \svstate$67 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + casez (coresync_rst) + 1'h1: + \svstate_ok$next = 1'h0; + endcase + end assign p_ready_o = n_i_rdy_data; assign n_valid_o = r_busy; - assign { \msr_ok$47 , \msr$46 } = { main_msr_ok, main_msr }; - assign { \nia_ok$45 , \nia$44 } = { main_nia_ok, main_nia }; - assign { \fast2_ok$43 , \fast2$42 } = { main_fast2_ok, \main_fast2$24 }; - assign { \fast1_ok$41 , \fast1$40 } = { main_fast1_ok, \main_fast1$23 }; - assign { \o_ok$39 , \o$38 } = { main_o_ok, main_o }; - assign { \trap_op__ldst_exc$37 , \trap_op__trapaddr$36 , \trap_op__traptype$35 , \trap_op__is_32bit$34 , \trap_op__cia$33 , \trap_op__msr$32 , \trap_op__insn$31 , \trap_op__fn_unit$30 , \trap_op__insn_type$29 } = { \main_trap_op__ldst_exc$22 , \main_trap_op__trapaddr$21 , \main_trap_op__traptype$20 , \main_trap_op__is_32bit$19 , \main_trap_op__cia$18 , \main_trap_op__msr$17 , \main_trap_op__insn$16 , \main_trap_op__fn_unit$15 , \main_trap_op__insn_type$14 }; - assign \muxid$28 = \main_muxid$13 ; - assign p_valid_i_p_ready_o = \$26 ; + assign { \svstate_ok$68 , \svstate$67 } = { main_svstate_ok, main_svstate }; + assign { \msr_ok$66 , \msr$65 } = { main_msr_ok, main_msr }; + assign { \nia_ok$64 , \nia$63 } = { main_nia_ok, main_nia }; + assign { \fast3_ok$62 , \fast3$61 } = { main_fast3_ok, main_fast3 }; + assign { \fast2_ok$60 , \fast2$59 } = { main_fast2_ok, \main_fast2$35 }; + assign { \fast1_ok$58 , \fast1$57 } = { main_fast1_ok, \main_fast1$34 }; + assign { \o_ok$56 , \o$55 } = { main_o_ok, main_o }; + assign { \trap_op__SV_Ptype$54 , \trap_op__sv_saturate$53 , \trap_op__sv_pred_dz$52 , \trap_op__sv_pred_sz$51 , \trap_op__ldst_exc$50 , \trap_op__trapaddr$49 , \trap_op__traptype$48 , \trap_op__is_32bit$47 , \trap_op__svstate$46 , \trap_op__cia$45 , \trap_op__msr$44 , \trap_op__insn$43 , \trap_op__fn_unit$42 , \trap_op__insn_type$41 } = { \main_trap_op__SV_Ptype$33 , \main_trap_op__sv_saturate$32 , \main_trap_op__sv_pred_dz$31 , \main_trap_op__sv_pred_sz$30 , \main_trap_op__ldst_exc$29 , \main_trap_op__trapaddr$28 , \main_trap_op__traptype$27 , \main_trap_op__is_32bit$26 , \main_trap_op__svstate$25 , \main_trap_op__cia$24 , \main_trap_op__msr$23 , \main_trap_op__insn$22 , \main_trap_op__fn_unit$21 , \main_trap_op__insn_type$20 }; + assign \muxid$40 = \main_muxid$19 ; + assign p_valid_i_p_ready_o = \$38 ; assign n_i_rdy_data = n_ready_i; - assign \p_valid_i$25 = p_valid_i; + assign \p_valid_i$37 = p_valid_i; + assign \fast3$36 = fast3; assign main_fast2 = fast2; assign main_fast1 = fast1; assign main_rb = rb; assign main_ra = ra; - assign { main_trap_op__ldst_exc, main_trap_op__trapaddr, main_trap_op__traptype, main_trap_op__is_32bit, main_trap_op__cia, main_trap_op__msr, main_trap_op__insn, main_trap_op__fn_unit, main_trap_op__insn_type } = { trap_op__ldst_exc, trap_op__trapaddr, trap_op__traptype, trap_op__is_32bit, trap_op__cia, trap_op__msr, trap_op__insn, trap_op__fn_unit, trap_op__insn_type }; + assign { main_trap_op__SV_Ptype, main_trap_op__sv_saturate, main_trap_op__sv_pred_dz, main_trap_op__sv_pred_sz, main_trap_op__ldst_exc, main_trap_op__trapaddr, main_trap_op__traptype, main_trap_op__is_32bit, main_trap_op__svstate, main_trap_op__cia, main_trap_op__msr, main_trap_op__insn, main_trap_op__fn_unit, main_trap_op__insn_type } = { trap_op__SV_Ptype, trap_op__sv_saturate, trap_op__sv_pred_dz, trap_op__sv_pred_sz, trap_op__ldst_exc, trap_op__trapaddr, trap_op__traptype, trap_op__is_32bit, trap_op__svstate, trap_op__cia, trap_op__msr, trap_op__insn, trap_op__fn_unit, trap_op__insn_type }; assign main_muxid = muxid; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0.pipe_end" *) (* generator = "nMigen" *) -module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, ra, rb, xer_so, divisor_neg, dividend_neg, dive_abs_ov32, dive_abs_ov64, div_by_zero, quotient_root, remainder, n_valid_o, n_ready_i, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , o, o_ok, cr_a, cr_a_ok, xer_ov, xer_ov_ok, \xer_so$20 , xer_so_ok, coresync_clk); +module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__SV_Ptype, ra, rb, xer_so, divisor_neg, dividend_neg, dive_abs_ov32, dive_abs_ov64, div_by_zero, quotient_root, remainder, n_valid_o, n_ready_i, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__SV_Ptype$23 , o, o_ok, cr_a, cr_a_ok, xer_ov, xer_ov_ok, \xer_so$24 , xer_so_ok, coresync_clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) - wire \$74 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + wire \$86 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [3:0] cr_a; reg [3:0] cr_a = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [3:0] \cr_a$68 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [3:0] \cr_a$97 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [3:0] \cr_a$113 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [3:0] \cr_a$80 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [3:0] \cr_a$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_a_ok; reg cr_a_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \cr_a_ok$67 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \cr_a_ok$69 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \cr_a_ok$98 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \cr_a_ok$114 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \cr_a_ok$79 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \cr_a_ok$81 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \cr_a_ok$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) input div_by_zero; @@ -172476,117 +185461,141 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type input dividend_neg; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *) input divisor_neg; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] logical_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \logical_op__SV_Ptype$110 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \logical_op__SV_Ptype$23 ; + reg [1:0] \logical_op__SV_Ptype$23 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \logical_op__SV_Ptype$23$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [3:0] logical_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [3:0] \logical_op__data_len$105 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [3:0] \logical_op__data_len$18 ; reg [3:0] \logical_op__data_len$18 = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [3:0] \logical_op__data_len$18$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [3:0] \logical_op__data_len$93 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] logical_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] logical_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \logical_op__fn_unit$3 ; - reg [13:0] \logical_op__fn_unit$3 = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] \logical_op__fn_unit$3$next ; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \logical_op__fn_unit$3 ; + reg [14:0] \logical_op__fn_unit$3 = 15'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] \logical_op__fn_unit$3$next ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \logical_op__fn_unit$78 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \logical_op__fn_unit$90 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] logical_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \logical_op__imm_data__data$4 ; reg [63:0] \logical_op__imm_data__data$4 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] \logical_op__imm_data__data$4$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \logical_op__imm_data__data$79 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \logical_op__imm_data__data$91 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__imm_data__ok$5 ; reg \logical_op__imm_data__ok$5 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__imm_data__ok$5$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__imm_data__ok$80 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__imm_data__ok$92 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] logical_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [1:0] \logical_op__input_carry$12 ; reg [1:0] \logical_op__input_carry$12 = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [1:0] \logical_op__input_carry$12$next ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [1:0] \logical_op__input_carry$87 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \logical_op__input_carry$99 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] logical_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \logical_op__insn$106 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \logical_op__insn$19 ; reg [31:0] \logical_op__insn$19 = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] \logical_op__insn$19$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \logical_op__insn$94 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -172662,7 +185671,9 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] logical_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -172739,10 +185750,12 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] \logical_op__insn_type$2 ; reg [6:0] \logical_op__insn_type$2 = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] \logical_op__insn_type$2$next ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -172819,107 +185832,148 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \logical_op__insn_type$77 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \logical_op__insn_type$89 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__invert_in$10 ; reg \logical_op__invert_in$10 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__invert_in$10$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__invert_in$85 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__invert_in$97 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__invert_out$100 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__invert_out$13 ; reg \logical_op__invert_out$13 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__invert_out$13$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__invert_out$88 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__is_32bit$103 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__is_32bit$16 ; reg \logical_op__is_32bit$16 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__is_32bit$16$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__is_32bit$91 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__is_signed$104 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__is_signed$17 ; reg \logical_op__is_signed$17 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__is_signed$17$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__is_signed$92 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__oe__oe$8 ; reg \logical_op__oe__oe$8 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__oe__oe$8$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__oe__oe$83 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__oe__oe$95 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__oe__ok$84 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__oe__ok$9 ; reg \logical_op__oe__ok$9 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__oe__ok$9$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__oe__ok$96 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__output_carry$102 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__output_carry$15 ; reg \logical_op__output_carry$15 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__output_carry$15$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__output_carry$90 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__rc__ok$7 ; reg \logical_op__rc__ok$7 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__rc__ok$7$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__rc__ok$82 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__rc__ok$94 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__rc__rc$6 ; reg \logical_op__rc__rc$6 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__rc__rc$6$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__rc__rc$81 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__rc__rc$93 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input logical_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__sv_pred_dz$108 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \logical_op__sv_pred_dz$21 ; + reg \logical_op__sv_pred_dz$21 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__sv_pred_dz$21$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input logical_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__sv_pred_sz$107 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \logical_op__sv_pred_sz$20 ; + reg \logical_op__sv_pred_sz$20 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__sv_pred_sz$20$next ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] logical_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \logical_op__sv_saturate$109 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \logical_op__sv_saturate$22 ; + reg [1:0] \logical_op__sv_saturate$22 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \logical_op__sv_saturate$22$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__write_cr0$101 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__write_cr0$14 ; reg \logical_op__write_cr0$14 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__write_cr0$14$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__write_cr0$89 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__zero_a$11 ; reg \logical_op__zero_a$11 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__zero_a$11$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__zero_a$86 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__zero_a$98 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) @@ -172928,95 +185982,109 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) reg [1:0] \muxid$1$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \muxid$76 ; + wire [1:0] \muxid$88 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *) wire n_i_rdy_data; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) output n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] o; reg [63:0] o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \o$95 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \o$111 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [63:0] \o$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output o_ok; reg o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \o_ok$96 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \o_ok$112 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \o_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [3:0] output_cr_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [3:0] \output_cr_a$62 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [3:0] \output_cr_a$74 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire output_cr_a_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] output_logical_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \output_logical_op__SV_Ptype$71 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [3:0] output_logical_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [3:0] \output_logical_op__data_len$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [3:0] \output_logical_op__data_len$66 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] output_logical_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] output_logical_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \output_logical_op__fn_unit$43 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \output_logical_op__fn_unit$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] output_logical_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \output_logical_op__imm_data__data$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \output_logical_op__imm_data__data$52 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_logical_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_logical_op__imm_data__ok$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_logical_op__imm_data__ok$53 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [1:0] output_logical_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [1:0] \output_logical_op__input_carry$52 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \output_logical_op__input_carry$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] output_logical_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \output_logical_op__insn$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \output_logical_op__insn$67 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -173092,7 +186160,9 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] output_logical_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -173169,64 +186239,86 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \output_logical_op__insn_type$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \output_logical_op__insn_type$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_logical_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_logical_op__invert_in$50 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_logical_op__invert_in$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_logical_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_logical_op__invert_out$53 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_logical_op__invert_out$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_logical_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_logical_op__is_32bit$56 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_logical_op__is_32bit$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_logical_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_logical_op__is_signed$57 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_logical_op__is_signed$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_logical_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_logical_op__oe__oe$48 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_logical_op__oe__oe$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_logical_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_logical_op__oe__ok$49 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_logical_op__oe__ok$57 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_logical_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_logical_op__output_carry$55 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_logical_op__output_carry$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_logical_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_logical_op__rc__ok$47 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_logical_op__rc__ok$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_logical_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_logical_op__rc__rc$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_logical_op__rc__rc$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire output_logical_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_logical_op__sv_pred_dz$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire output_logical_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_logical_op__sv_pred_sz$68 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] output_logical_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \output_logical_op__sv_saturate$70 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_logical_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_logical_op__write_cr0$54 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_logical_op__write_cr0$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_logical_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_logical_op__zero_a$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_logical_op__zero_a$59 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] output_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \output_muxid$41 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \output_muxid$49 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] output_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [63:0] \output_o$60 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] \output_o$72 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire output_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \output_o_ok$61 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \output_o_ok$73 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) wire output_stage_div_by_zero; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *) @@ -173237,68 +186329,82 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type wire output_stage_dividend_neg; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *) wire output_stage_divisor_neg; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] output_stage_logical_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \output_stage_logical_op__SV_Ptype$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [3:0] output_stage_logical_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [3:0] \output_stage_logical_op__data_len$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [3:0] \output_stage_logical_op__data_len$42 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] output_stage_logical_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] output_stage_logical_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \output_stage_logical_op__fn_unit$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \output_stage_logical_op__fn_unit$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] output_stage_logical_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \output_stage_logical_op__imm_data__data$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \output_stage_logical_op__imm_data__data$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_stage_logical_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_stage_logical_op__imm_data__ok$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_stage_logical_op__imm_data__ok$29 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [1:0] output_stage_logical_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [1:0] \output_stage_logical_op__input_carry$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \output_stage_logical_op__input_carry$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] output_stage_logical_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \output_stage_logical_op__insn$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \output_stage_logical_op__insn$43 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -173374,7 +186480,9 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] output_stage_logical_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -173451,90 +186559,112 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \output_stage_logical_op__insn_type$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \output_stage_logical_op__insn_type$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_stage_logical_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_stage_logical_op__invert_in$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_stage_logical_op__invert_in$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_stage_logical_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_stage_logical_op__invert_out$33 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_stage_logical_op__invert_out$37 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_stage_logical_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_stage_logical_op__is_32bit$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_stage_logical_op__is_32bit$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_stage_logical_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_stage_logical_op__is_signed$37 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_stage_logical_op__is_signed$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_stage_logical_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_stage_logical_op__oe__oe$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_stage_logical_op__oe__oe$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_stage_logical_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_stage_logical_op__oe__ok$29 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_stage_logical_op__oe__ok$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_stage_logical_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_stage_logical_op__output_carry$35 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_stage_logical_op__output_carry$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_stage_logical_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_stage_logical_op__rc__ok$27 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_stage_logical_op__rc__ok$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_stage_logical_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_stage_logical_op__rc__rc$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_stage_logical_op__rc__rc$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire output_stage_logical_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_stage_logical_op__sv_pred_dz$45 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire output_stage_logical_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_stage_logical_op__sv_pred_sz$44 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] output_stage_logical_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \output_stage_logical_op__sv_saturate$46 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_stage_logical_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_stage_logical_op__write_cr0$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_stage_logical_op__write_cr0$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire output_stage_logical_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \output_stage_logical_op__zero_a$31 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \output_stage_logical_op__zero_a$35 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] output_stage_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \output_stage_muxid$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [1:0] \output_stage_muxid$25 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] output_stage_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire output_stage_o_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" *) wire [63:0] output_stage_quotient_root; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" *) wire [191:0] output_stage_remainder; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [1:0] output_stage_xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire output_stage_xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire output_stage_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \output_stage_xer_so$40 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \output_stage_xer_so$48 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [1:0] output_xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [1:0] \output_xer_ov$63 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [1:0] \output_xer_ov$75 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire output_xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire output_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \output_xer_so$64 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \output_xer_so$76 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire output_xer_so_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) input p_valid_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *) - wire \p_valid_i$73 ; + wire \p_valid_i$85 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *) wire p_valid_i_p_ready_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" *) @@ -173543,55 +186673,55 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type reg r_busy = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg \r_busy$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \ra$65 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \ra$77 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \rb$66 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \rb$78 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" *) input [191:0] remainder; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [1:0] xer_ov; reg [1:0] xer_ov = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire [1:0] \xer_ov$99 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [1:0] \xer_ov$115 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [1:0] \xer_ov$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ov_ok; reg xer_ov_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_ov_ok$100 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_ov_ok$70 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_ov_ok$116 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_ov_ok$82 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \xer_ov_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_so$101 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \xer_so$20 ; - reg \xer_so$20 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - reg \xer_so$20$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_so$117 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \xer_so$24 ; + reg \xer_so$24 = 1'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg \xer_so$24$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_so_ok; reg xer_so_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_so_ok$102 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_so_ok$71 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - wire \xer_so_ok$72 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_so_ok$118 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_so_ok$83 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire \xer_so_ok$84 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \xer_so_ok$next ; - assign \$74 = \p_valid_i$73 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; + assign \$86 = \p_valid_i$85 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; always @(posedge coresync_clk) - \xer_so$20 <= \xer_so$20$next ; + \xer_so$24 <= \xer_so$24$next ; always @(posedge coresync_clk) xer_so_ok <= \xer_so_ok$next ; always @(posedge coresync_clk) @@ -173642,6 +186772,14 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type \logical_op__data_len$18 <= \logical_op__data_len$18$next ; always @(posedge coresync_clk) \logical_op__insn$19 <= \logical_op__insn$19$next ; + always @(posedge coresync_clk) + \logical_op__sv_pred_sz$20 <= \logical_op__sv_pred_sz$20$next ; + always @(posedge coresync_clk) + \logical_op__sv_pred_dz$21 <= \logical_op__sv_pred_dz$21$next ; + always @(posedge coresync_clk) + \logical_op__sv_saturate$22 <= \logical_op__sv_saturate$22$next ; + always @(posedge coresync_clk) + \logical_op__SV_Ptype$23 <= \logical_op__SV_Ptype$23$next ; always @(posedge coresync_clk) \muxid$1 <= \muxid$1$next ; always @(posedge coresync_clk) @@ -173652,55 +186790,63 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type ); \output$83 \output ( .cr_a(output_cr_a), - .\cr_a$22 (\output_cr_a$62 ), + .\cr_a$26 (\output_cr_a$74 ), .cr_a_ok(output_cr_a_ok), + .logical_op__SV_Ptype(output_logical_op__SV_Ptype), + .\logical_op__SV_Ptype$23 (\output_logical_op__SV_Ptype$71 ), .logical_op__data_len(output_logical_op__data_len), - .\logical_op__data_len$18 (\output_logical_op__data_len$58 ), + .\logical_op__data_len$18 (\output_logical_op__data_len$66 ), .logical_op__fn_unit(output_logical_op__fn_unit), - .\logical_op__fn_unit$3 (\output_logical_op__fn_unit$43 ), + .\logical_op__fn_unit$3 (\output_logical_op__fn_unit$51 ), .logical_op__imm_data__data(output_logical_op__imm_data__data), - .\logical_op__imm_data__data$4 (\output_logical_op__imm_data__data$44 ), + .\logical_op__imm_data__data$4 (\output_logical_op__imm_data__data$52 ), .logical_op__imm_data__ok(output_logical_op__imm_data__ok), - .\logical_op__imm_data__ok$5 (\output_logical_op__imm_data__ok$45 ), + .\logical_op__imm_data__ok$5 (\output_logical_op__imm_data__ok$53 ), .logical_op__input_carry(output_logical_op__input_carry), - .\logical_op__input_carry$12 (\output_logical_op__input_carry$52 ), + .\logical_op__input_carry$12 (\output_logical_op__input_carry$60 ), .logical_op__insn(output_logical_op__insn), - .\logical_op__insn$19 (\output_logical_op__insn$59 ), + .\logical_op__insn$19 (\output_logical_op__insn$67 ), .logical_op__insn_type(output_logical_op__insn_type), - .\logical_op__insn_type$2 (\output_logical_op__insn_type$42 ), + .\logical_op__insn_type$2 (\output_logical_op__insn_type$50 ), .logical_op__invert_in(output_logical_op__invert_in), - .\logical_op__invert_in$10 (\output_logical_op__invert_in$50 ), + .\logical_op__invert_in$10 (\output_logical_op__invert_in$58 ), .logical_op__invert_out(output_logical_op__invert_out), - .\logical_op__invert_out$13 (\output_logical_op__invert_out$53 ), + .\logical_op__invert_out$13 (\output_logical_op__invert_out$61 ), .logical_op__is_32bit(output_logical_op__is_32bit), - .\logical_op__is_32bit$16 (\output_logical_op__is_32bit$56 ), + .\logical_op__is_32bit$16 (\output_logical_op__is_32bit$64 ), .logical_op__is_signed(output_logical_op__is_signed), - .\logical_op__is_signed$17 (\output_logical_op__is_signed$57 ), + .\logical_op__is_signed$17 (\output_logical_op__is_signed$65 ), .logical_op__oe__oe(output_logical_op__oe__oe), - .\logical_op__oe__oe$8 (\output_logical_op__oe__oe$48 ), + .\logical_op__oe__oe$8 (\output_logical_op__oe__oe$56 ), .logical_op__oe__ok(output_logical_op__oe__ok), - .\logical_op__oe__ok$9 (\output_logical_op__oe__ok$49 ), + .\logical_op__oe__ok$9 (\output_logical_op__oe__ok$57 ), .logical_op__output_carry(output_logical_op__output_carry), - .\logical_op__output_carry$15 (\output_logical_op__output_carry$55 ), + .\logical_op__output_carry$15 (\output_logical_op__output_carry$63 ), .logical_op__rc__ok(output_logical_op__rc__ok), - .\logical_op__rc__ok$7 (\output_logical_op__rc__ok$47 ), + .\logical_op__rc__ok$7 (\output_logical_op__rc__ok$55 ), .logical_op__rc__rc(output_logical_op__rc__rc), - .\logical_op__rc__rc$6 (\output_logical_op__rc__rc$46 ), + .\logical_op__rc__rc$6 (\output_logical_op__rc__rc$54 ), + .logical_op__sv_pred_dz(output_logical_op__sv_pred_dz), + .\logical_op__sv_pred_dz$21 (\output_logical_op__sv_pred_dz$69 ), + .logical_op__sv_pred_sz(output_logical_op__sv_pred_sz), + .\logical_op__sv_pred_sz$20 (\output_logical_op__sv_pred_sz$68 ), + .logical_op__sv_saturate(output_logical_op__sv_saturate), + .\logical_op__sv_saturate$22 (\output_logical_op__sv_saturate$70 ), .logical_op__write_cr0(output_logical_op__write_cr0), - .\logical_op__write_cr0$14 (\output_logical_op__write_cr0$54 ), + .\logical_op__write_cr0$14 (\output_logical_op__write_cr0$62 ), .logical_op__zero_a(output_logical_op__zero_a), - .\logical_op__zero_a$11 (\output_logical_op__zero_a$51 ), + .\logical_op__zero_a$11 (\output_logical_op__zero_a$59 ), .muxid(output_muxid), - .\muxid$1 (\output_muxid$41 ), + .\muxid$1 (\output_muxid$49 ), .o(output_o), - .\o$20 (\output_o$60 ), + .\o$24 (\output_o$72 ), .o_ok(output_o_ok), - .\o_ok$21 (\output_o_ok$61 ), + .\o_ok$25 (\output_o_ok$73 ), .xer_ov(output_xer_ov), - .\xer_ov$23 (\output_xer_ov$63 ), + .\xer_ov$27 (\output_xer_ov$75 ), .xer_ov_ok(output_xer_ov_ok), .xer_so(output_xer_so), - .\xer_so$24 (\output_xer_so$64 ), + .\xer_so$28 (\output_xer_so$76 ), .xer_so_ok(output_xer_so_ok) ); output_stage output_stage ( @@ -173709,44 +186855,52 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type .dive_abs_ov64(output_stage_dive_abs_ov64), .dividend_neg(output_stage_dividend_neg), .divisor_neg(output_stage_divisor_neg), + .logical_op__SV_Ptype(output_stage_logical_op__SV_Ptype), + .\logical_op__SV_Ptype$23 (\output_stage_logical_op__SV_Ptype$47 ), .logical_op__data_len(output_stage_logical_op__data_len), - .\logical_op__data_len$18 (\output_stage_logical_op__data_len$38 ), + .\logical_op__data_len$18 (\output_stage_logical_op__data_len$42 ), .logical_op__fn_unit(output_stage_logical_op__fn_unit), - .\logical_op__fn_unit$3 (\output_stage_logical_op__fn_unit$23 ), + .\logical_op__fn_unit$3 (\output_stage_logical_op__fn_unit$27 ), .logical_op__imm_data__data(output_stage_logical_op__imm_data__data), - .\logical_op__imm_data__data$4 (\output_stage_logical_op__imm_data__data$24 ), + .\logical_op__imm_data__data$4 (\output_stage_logical_op__imm_data__data$28 ), .logical_op__imm_data__ok(output_stage_logical_op__imm_data__ok), - .\logical_op__imm_data__ok$5 (\output_stage_logical_op__imm_data__ok$25 ), + .\logical_op__imm_data__ok$5 (\output_stage_logical_op__imm_data__ok$29 ), .logical_op__input_carry(output_stage_logical_op__input_carry), - .\logical_op__input_carry$12 (\output_stage_logical_op__input_carry$32 ), + .\logical_op__input_carry$12 (\output_stage_logical_op__input_carry$36 ), .logical_op__insn(output_stage_logical_op__insn), - .\logical_op__insn$19 (\output_stage_logical_op__insn$39 ), + .\logical_op__insn$19 (\output_stage_logical_op__insn$43 ), .logical_op__insn_type(output_stage_logical_op__insn_type), - .\logical_op__insn_type$2 (\output_stage_logical_op__insn_type$22 ), + .\logical_op__insn_type$2 (\output_stage_logical_op__insn_type$26 ), .logical_op__invert_in(output_stage_logical_op__invert_in), - .\logical_op__invert_in$10 (\output_stage_logical_op__invert_in$30 ), + .\logical_op__invert_in$10 (\output_stage_logical_op__invert_in$34 ), .logical_op__invert_out(output_stage_logical_op__invert_out), - .\logical_op__invert_out$13 (\output_stage_logical_op__invert_out$33 ), + .\logical_op__invert_out$13 (\output_stage_logical_op__invert_out$37 ), .logical_op__is_32bit(output_stage_logical_op__is_32bit), - .\logical_op__is_32bit$16 (\output_stage_logical_op__is_32bit$36 ), + .\logical_op__is_32bit$16 (\output_stage_logical_op__is_32bit$40 ), .logical_op__is_signed(output_stage_logical_op__is_signed), - .\logical_op__is_signed$17 (\output_stage_logical_op__is_signed$37 ), + .\logical_op__is_signed$17 (\output_stage_logical_op__is_signed$41 ), .logical_op__oe__oe(output_stage_logical_op__oe__oe), - .\logical_op__oe__oe$8 (\output_stage_logical_op__oe__oe$28 ), + .\logical_op__oe__oe$8 (\output_stage_logical_op__oe__oe$32 ), .logical_op__oe__ok(output_stage_logical_op__oe__ok), - .\logical_op__oe__ok$9 (\output_stage_logical_op__oe__ok$29 ), + .\logical_op__oe__ok$9 (\output_stage_logical_op__oe__ok$33 ), .logical_op__output_carry(output_stage_logical_op__output_carry), - .\logical_op__output_carry$15 (\output_stage_logical_op__output_carry$35 ), + .\logical_op__output_carry$15 (\output_stage_logical_op__output_carry$39 ), .logical_op__rc__ok(output_stage_logical_op__rc__ok), - .\logical_op__rc__ok$7 (\output_stage_logical_op__rc__ok$27 ), + .\logical_op__rc__ok$7 (\output_stage_logical_op__rc__ok$31 ), .logical_op__rc__rc(output_stage_logical_op__rc__rc), - .\logical_op__rc__rc$6 (\output_stage_logical_op__rc__rc$26 ), + .\logical_op__rc__rc$6 (\output_stage_logical_op__rc__rc$30 ), + .logical_op__sv_pred_dz(output_stage_logical_op__sv_pred_dz), + .\logical_op__sv_pred_dz$21 (\output_stage_logical_op__sv_pred_dz$45 ), + .logical_op__sv_pred_sz(output_stage_logical_op__sv_pred_sz), + .\logical_op__sv_pred_sz$20 (\output_stage_logical_op__sv_pred_sz$44 ), + .logical_op__sv_saturate(output_stage_logical_op__sv_saturate), + .\logical_op__sv_saturate$22 (\output_stage_logical_op__sv_saturate$46 ), .logical_op__write_cr0(output_stage_logical_op__write_cr0), - .\logical_op__write_cr0$14 (\output_stage_logical_op__write_cr0$34 ), + .\logical_op__write_cr0$14 (\output_stage_logical_op__write_cr0$38 ), .logical_op__zero_a(output_stage_logical_op__zero_a), - .\logical_op__zero_a$11 (\output_stage_logical_op__zero_a$31 ), + .\logical_op__zero_a$11 (\output_stage_logical_op__zero_a$35 ), .muxid(output_stage_muxid), - .\muxid$1 (\output_stage_muxid$21 ), + .\muxid$1 (\output_stage_muxid$25 ), .o(output_stage_o), .o_ok(output_stage_o_ok), .quotient_root(output_stage_quotient_root), @@ -173754,12 +186908,58 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type .xer_ov(output_stage_xer_ov), .xer_ov_ok(output_stage_xer_ov_ok), .xer_so(output_stage_xer_so), - .\xer_so$20 (\output_stage_xer_so$40 ) + .\xer_so$24 (\output_stage_xer_so$48 ) ); \p$81 p ( .p_ready_o(p_ready_o), .p_valid_i(p_valid_i) ); + always @* begin + if (\initial ) begin end + \logical_op__insn_type$2$next = \logical_op__insn_type$2 ; + \logical_op__fn_unit$3$next = \logical_op__fn_unit$3 ; + \logical_op__imm_data__data$4$next = \logical_op__imm_data__data$4 ; + \logical_op__imm_data__ok$5$next = \logical_op__imm_data__ok$5 ; + \logical_op__rc__rc$6$next = \logical_op__rc__rc$6 ; + \logical_op__rc__ok$7$next = \logical_op__rc__ok$7 ; + \logical_op__oe__oe$8$next = \logical_op__oe__oe$8 ; + \logical_op__oe__ok$9$next = \logical_op__oe__ok$9 ; + \logical_op__invert_in$10$next = \logical_op__invert_in$10 ; + \logical_op__zero_a$11$next = \logical_op__zero_a$11 ; + \logical_op__input_carry$12$next = \logical_op__input_carry$12 ; + \logical_op__invert_out$13$next = \logical_op__invert_out$13 ; + \logical_op__write_cr0$14$next = \logical_op__write_cr0$14 ; + \logical_op__output_carry$15$next = \logical_op__output_carry$15 ; + \logical_op__is_32bit$16$next = \logical_op__is_32bit$16 ; + \logical_op__is_signed$17$next = \logical_op__is_signed$17 ; + \logical_op__data_len$18$next = \logical_op__data_len$18 ; + \logical_op__insn$19$next = \logical_op__insn$19 ; + \logical_op__sv_pred_sz$20$next = \logical_op__sv_pred_sz$20 ; + \logical_op__sv_pred_dz$21$next = \logical_op__sv_pred_dz$21 ; + \logical_op__sv_saturate$22$next = \logical_op__sv_saturate$22 ; + \logical_op__SV_Ptype$23$next = \logical_op__SV_Ptype$23 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + { \logical_op__SV_Ptype$23$next , \logical_op__sv_saturate$22$next , \logical_op__sv_pred_dz$21$next , \logical_op__sv_pred_sz$20$next , \logical_op__insn$19$next , \logical_op__data_len$18$next , \logical_op__is_signed$17$next , \logical_op__is_32bit$16$next , \logical_op__output_carry$15$next , \logical_op__write_cr0$14$next , \logical_op__invert_out$13$next , \logical_op__input_carry$12$next , \logical_op__zero_a$11$next , \logical_op__invert_in$10$next , \logical_op__oe__ok$9$next , \logical_op__oe__oe$8$next , \logical_op__rc__ok$7$next , \logical_op__rc__rc$6$next , \logical_op__imm_data__ok$5$next , \logical_op__imm_data__data$4$next , \logical_op__fn_unit$3$next , \logical_op__insn_type$2$next } = { \logical_op__SV_Ptype$110 , \logical_op__sv_saturate$109 , \logical_op__sv_pred_dz$108 , \logical_op__sv_pred_sz$107 , \logical_op__insn$106 , \logical_op__data_len$105 , \logical_op__is_signed$104 , \logical_op__is_32bit$103 , \logical_op__output_carry$102 , \logical_op__write_cr0$101 , \logical_op__invert_out$100 , \logical_op__input_carry$99 , \logical_op__zero_a$98 , \logical_op__invert_in$97 , \logical_op__oe__ok$96 , \logical_op__oe__oe$95 , \logical_op__rc__ok$94 , \logical_op__rc__rc$93 , \logical_op__imm_data__ok$92 , \logical_op__imm_data__data$91 , \logical_op__fn_unit$90 , \logical_op__insn_type$89 }; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + { \logical_op__SV_Ptype$23$next , \logical_op__sv_saturate$22$next , \logical_op__sv_pred_dz$21$next , \logical_op__sv_pred_sz$20$next , \logical_op__insn$19$next , \logical_op__data_len$18$next , \logical_op__is_signed$17$next , \logical_op__is_32bit$16$next , \logical_op__output_carry$15$next , \logical_op__write_cr0$14$next , \logical_op__invert_out$13$next , \logical_op__input_carry$12$next , \logical_op__zero_a$11$next , \logical_op__invert_in$10$next , \logical_op__oe__ok$9$next , \logical_op__oe__oe$8$next , \logical_op__rc__ok$7$next , \logical_op__rc__rc$6$next , \logical_op__imm_data__ok$5$next , \logical_op__imm_data__data$4$next , \logical_op__fn_unit$3$next , \logical_op__insn_type$2$next } = { \logical_op__SV_Ptype$110 , \logical_op__sv_saturate$109 , \logical_op__sv_pred_dz$108 , \logical_op__sv_pred_sz$107 , \logical_op__insn$106 , \logical_op__data_len$105 , \logical_op__is_signed$104 , \logical_op__is_32bit$103 , \logical_op__output_carry$102 , \logical_op__write_cr0$101 , \logical_op__invert_out$100 , \logical_op__input_carry$99 , \logical_op__zero_a$98 , \logical_op__invert_in$97 , \logical_op__oe__ok$96 , \logical_op__oe__oe$95 , \logical_op__rc__ok$94 , \logical_op__rc__rc$93 , \logical_op__imm_data__ok$92 , \logical_op__imm_data__data$91 , \logical_op__fn_unit$90 , \logical_op__insn_type$89 }; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + casez (coresync_rst) + 1'h1: + begin + \logical_op__imm_data__data$4$next = 64'h0000000000000000; + \logical_op__imm_data__ok$5$next = 1'h0; + \logical_op__rc__rc$6$next = 1'h0; + \logical_op__rc__ok$7$next = 1'h0; + \logical_op__oe__oe$8$next = 1'h0; + \logical_op__oe__ok$9$next = 1'h0; + end + endcase + end always @* begin if (\initial ) begin end \o$next = o; @@ -173768,12 +186968,12 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \o_ok$next , \o$next } = { \o_ok$96 , \o$95 }; + { \o_ok$next , \o$next } = { \o_ok$112 , \o$111 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \o_ok$next , \o$next } = { \o_ok$96 , \o$95 }; + { \o_ok$next , \o$next } = { \o_ok$112 , \o$111 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \o_ok$next = 1'h0; @@ -173787,12 +186987,12 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$98 , \cr_a$97 }; + { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$114 , \cr_a$113 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$98 , \cr_a$97 }; + { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$114 , \cr_a$113 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \cr_a_ok$next = 1'h0; @@ -173806,12 +187006,12 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$100 , \xer_ov$99 }; + { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$116 , \xer_ov$115 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$100 , \xer_ov$99 }; + { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$116 , \xer_ov$115 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \xer_ov_ok$next = 1'h0; @@ -173819,18 +187019,18 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type end always @* begin if (\initial ) begin end - \xer_so$20$next = \xer_so$20 ; + \xer_so$24$next = \xer_so$24 ; \xer_so_ok$next = xer_so_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \xer_so_ok$next , \xer_so$20$next } = { \xer_so_ok$102 , \xer_so$101 }; + { \xer_so_ok$next , \xer_so$24$next } = { \xer_so_ok$118 , \xer_so$117 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \xer_so_ok$next , \xer_so$20$next } = { \xer_so_ok$102 , \xer_so$101 }; + { \xer_so_ok$next , \xer_so$24$next } = { \xer_so_ok$118 , \xer_so$117 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \xer_so_ok$next = 1'h0; @@ -173848,7 +187048,7 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -173861,74 +187061,32 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \muxid$1$next = \muxid$76 ; + \muxid$1$next = \muxid$88 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \muxid$1$next = \muxid$76 ; + \muxid$1$next = \muxid$88 ; endcase end - always @* begin - if (\initial ) begin end - \logical_op__insn_type$2$next = \logical_op__insn_type$2 ; - \logical_op__fn_unit$3$next = \logical_op__fn_unit$3 ; - \logical_op__imm_data__data$4$next = \logical_op__imm_data__data$4 ; - \logical_op__imm_data__ok$5$next = \logical_op__imm_data__ok$5 ; - \logical_op__rc__rc$6$next = \logical_op__rc__rc$6 ; - \logical_op__rc__ok$7$next = \logical_op__rc__ok$7 ; - \logical_op__oe__oe$8$next = \logical_op__oe__oe$8 ; - \logical_op__oe__ok$9$next = \logical_op__oe__ok$9 ; - \logical_op__invert_in$10$next = \logical_op__invert_in$10 ; - \logical_op__zero_a$11$next = \logical_op__zero_a$11 ; - \logical_op__input_carry$12$next = \logical_op__input_carry$12 ; - \logical_op__invert_out$13$next = \logical_op__invert_out$13 ; - \logical_op__write_cr0$14$next = \logical_op__write_cr0$14 ; - \logical_op__output_carry$15$next = \logical_op__output_carry$15 ; - \logical_op__is_32bit$16$next = \logical_op__is_32bit$16 ; - \logical_op__is_signed$17$next = \logical_op__is_signed$17 ; - \logical_op__data_len$18$next = \logical_op__data_len$18 ; - \logical_op__insn$19$next = \logical_op__insn$19 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) - casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) - /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ - 2'b?1: - { \logical_op__insn$19$next , \logical_op__data_len$18$next , \logical_op__is_signed$17$next , \logical_op__is_32bit$16$next , \logical_op__output_carry$15$next , \logical_op__write_cr0$14$next , \logical_op__invert_out$13$next , \logical_op__input_carry$12$next , \logical_op__zero_a$11$next , \logical_op__invert_in$10$next , \logical_op__oe__ok$9$next , \logical_op__oe__oe$8$next , \logical_op__rc__ok$7$next , \logical_op__rc__rc$6$next , \logical_op__imm_data__ok$5$next , \logical_op__imm_data__data$4$next , \logical_op__fn_unit$3$next , \logical_op__insn_type$2$next } = { \logical_op__insn$94 , \logical_op__data_len$93 , \logical_op__is_signed$92 , \logical_op__is_32bit$91 , \logical_op__output_carry$90 , \logical_op__write_cr0$89 , \logical_op__invert_out$88 , \logical_op__input_carry$87 , \logical_op__zero_a$86 , \logical_op__invert_in$85 , \logical_op__oe__ok$84 , \logical_op__oe__oe$83 , \logical_op__rc__ok$82 , \logical_op__rc__rc$81 , \logical_op__imm_data__ok$80 , \logical_op__imm_data__data$79 , \logical_op__fn_unit$78 , \logical_op__insn_type$77 }; - /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ - 2'b1?: - { \logical_op__insn$19$next , \logical_op__data_len$18$next , \logical_op__is_signed$17$next , \logical_op__is_32bit$16$next , \logical_op__output_carry$15$next , \logical_op__write_cr0$14$next , \logical_op__invert_out$13$next , \logical_op__input_carry$12$next , \logical_op__zero_a$11$next , \logical_op__invert_in$10$next , \logical_op__oe__ok$9$next , \logical_op__oe__oe$8$next , \logical_op__rc__ok$7$next , \logical_op__rc__rc$6$next , \logical_op__imm_data__ok$5$next , \logical_op__imm_data__data$4$next , \logical_op__fn_unit$3$next , \logical_op__insn_type$2$next } = { \logical_op__insn$94 , \logical_op__data_len$93 , \logical_op__is_signed$92 , \logical_op__is_32bit$91 , \logical_op__output_carry$90 , \logical_op__write_cr0$89 , \logical_op__invert_out$88 , \logical_op__input_carry$87 , \logical_op__zero_a$86 , \logical_op__invert_in$85 , \logical_op__oe__ok$84 , \logical_op__oe__oe$83 , \logical_op__rc__ok$82 , \logical_op__rc__rc$81 , \logical_op__imm_data__ok$80 , \logical_op__imm_data__data$79 , \logical_op__fn_unit$78 , \logical_op__insn_type$77 }; - endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) - casez (coresync_rst) - 1'h1: - begin - \logical_op__imm_data__data$4$next = 64'h0000000000000000; - \logical_op__imm_data__ok$5$next = 1'h0; - \logical_op__rc__rc$6$next = 1'h0; - \logical_op__rc__ok$7$next = 1'h0; - \logical_op__oe__oe$8$next = 1'h0; - \logical_op__oe__ok$9$next = 1'h0; - end - endcase - end - assign \cr_a$68 = 4'h0; - assign \cr_a_ok$69 = 1'h0; - assign \xer_so_ok$72 = 1'h0; + assign \cr_a$80 = 4'h0; + assign \cr_a_ok$81 = 1'h0; + assign \xer_so_ok$84 = 1'h0; assign p_ready_o = n_i_rdy_data; assign n_valid_o = r_busy; - assign { \xer_so_ok$102 , \xer_so$101 } = { output_xer_so_ok, \output_xer_so$64 }; - assign { \xer_ov_ok$100 , \xer_ov$99 } = { output_xer_ov_ok, \output_xer_ov$63 }; - assign { \cr_a_ok$98 , \cr_a$97 } = { output_cr_a_ok, \output_cr_a$62 }; - assign { \o_ok$96 , \o$95 } = { \output_o_ok$61 , \output_o$60 }; - assign { \logical_op__insn$94 , \logical_op__data_len$93 , \logical_op__is_signed$92 , \logical_op__is_32bit$91 , \logical_op__output_carry$90 , \logical_op__write_cr0$89 , \logical_op__invert_out$88 , \logical_op__input_carry$87 , \logical_op__zero_a$86 , \logical_op__invert_in$85 , \logical_op__oe__ok$84 , \logical_op__oe__oe$83 , \logical_op__rc__ok$82 , \logical_op__rc__rc$81 , \logical_op__imm_data__ok$80 , \logical_op__imm_data__data$79 , \logical_op__fn_unit$78 , \logical_op__insn_type$77 } = { \output_logical_op__insn$59 , \output_logical_op__data_len$58 , \output_logical_op__is_signed$57 , \output_logical_op__is_32bit$56 , \output_logical_op__output_carry$55 , \output_logical_op__write_cr0$54 , \output_logical_op__invert_out$53 , \output_logical_op__input_carry$52 , \output_logical_op__zero_a$51 , \output_logical_op__invert_in$50 , \output_logical_op__oe__ok$49 , \output_logical_op__oe__oe$48 , \output_logical_op__rc__ok$47 , \output_logical_op__rc__rc$46 , \output_logical_op__imm_data__ok$45 , \output_logical_op__imm_data__data$44 , \output_logical_op__fn_unit$43 , \output_logical_op__insn_type$42 }; - assign \muxid$76 = \output_muxid$41 ; - assign p_valid_i_p_ready_o = \$74 ; + assign { \xer_so_ok$118 , \xer_so$117 } = { output_xer_so_ok, \output_xer_so$76 }; + assign { \xer_ov_ok$116 , \xer_ov$115 } = { output_xer_ov_ok, \output_xer_ov$75 }; + assign { \cr_a_ok$114 , \cr_a$113 } = { output_cr_a_ok, \output_cr_a$74 }; + assign { \o_ok$112 , \o$111 } = { \output_o_ok$73 , \output_o$72 }; + assign { \logical_op__SV_Ptype$110 , \logical_op__sv_saturate$109 , \logical_op__sv_pred_dz$108 , \logical_op__sv_pred_sz$107 , \logical_op__insn$106 , \logical_op__data_len$105 , \logical_op__is_signed$104 , \logical_op__is_32bit$103 , \logical_op__output_carry$102 , \logical_op__write_cr0$101 , \logical_op__invert_out$100 , \logical_op__input_carry$99 , \logical_op__zero_a$98 , \logical_op__invert_in$97 , \logical_op__oe__ok$96 , \logical_op__oe__oe$95 , \logical_op__rc__ok$94 , \logical_op__rc__rc$93 , \logical_op__imm_data__ok$92 , \logical_op__imm_data__data$91 , \logical_op__fn_unit$90 , \logical_op__insn_type$89 } = { \output_logical_op__SV_Ptype$71 , \output_logical_op__sv_saturate$70 , \output_logical_op__sv_pred_dz$69 , \output_logical_op__sv_pred_sz$68 , \output_logical_op__insn$67 , \output_logical_op__data_len$66 , \output_logical_op__is_signed$65 , \output_logical_op__is_32bit$64 , \output_logical_op__output_carry$63 , \output_logical_op__write_cr0$62 , \output_logical_op__invert_out$61 , \output_logical_op__input_carry$60 , \output_logical_op__zero_a$59 , \output_logical_op__invert_in$58 , \output_logical_op__oe__ok$57 , \output_logical_op__oe__oe$56 , \output_logical_op__rc__ok$55 , \output_logical_op__rc__rc$54 , \output_logical_op__imm_data__ok$53 , \output_logical_op__imm_data__data$52 , \output_logical_op__fn_unit$51 , \output_logical_op__insn_type$50 }; + assign \muxid$88 = \output_muxid$49 ; + assign p_valid_i_p_ready_o = \$86 ; assign n_i_rdy_data = n_ready_i; - assign \p_valid_i$73 = p_valid_i; - assign { \xer_so_ok$71 , output_xer_so } = { 1'h0, \output_stage_xer_so$40 }; - assign { \xer_ov_ok$70 , output_xer_ov } = { output_stage_xer_ov_ok, output_stage_xer_ov }; - assign { \cr_a_ok$67 , output_cr_a } = 5'h00; + assign \p_valid_i$85 = p_valid_i; + assign { \xer_so_ok$83 , output_xer_so } = { 1'h0, \output_stage_xer_so$48 }; + assign { \xer_ov_ok$82 , output_xer_ov } = { output_stage_xer_ov_ok, output_stage_xer_ov }; + assign { \cr_a_ok$79 , output_cr_a } = 5'h00; assign { output_o_ok, output_o } = { output_stage_o_ok, output_stage_o }; - assign { output_logical_op__insn, output_logical_op__data_len, output_logical_op__is_signed, output_logical_op__is_32bit, output_logical_op__output_carry, output_logical_op__write_cr0, output_logical_op__invert_out, output_logical_op__input_carry, output_logical_op__zero_a, output_logical_op__invert_in, output_logical_op__oe__ok, output_logical_op__oe__oe, output_logical_op__rc__ok, output_logical_op__rc__rc, output_logical_op__imm_data__ok, output_logical_op__imm_data__data, output_logical_op__fn_unit, output_logical_op__insn_type } = { \output_stage_logical_op__insn$39 , \output_stage_logical_op__data_len$38 , \output_stage_logical_op__is_signed$37 , \output_stage_logical_op__is_32bit$36 , \output_stage_logical_op__output_carry$35 , \output_stage_logical_op__write_cr0$34 , \output_stage_logical_op__invert_out$33 , \output_stage_logical_op__input_carry$32 , \output_stage_logical_op__zero_a$31 , \output_stage_logical_op__invert_in$30 , \output_stage_logical_op__oe__ok$29 , \output_stage_logical_op__oe__oe$28 , \output_stage_logical_op__rc__ok$27 , \output_stage_logical_op__rc__rc$26 , \output_stage_logical_op__imm_data__ok$25 , \output_stage_logical_op__imm_data__data$24 , \output_stage_logical_op__fn_unit$23 , \output_stage_logical_op__insn_type$22 }; - assign output_muxid = \output_stage_muxid$21 ; + assign { output_logical_op__SV_Ptype, output_logical_op__sv_saturate, output_logical_op__sv_pred_dz, output_logical_op__sv_pred_sz, output_logical_op__insn, output_logical_op__data_len, output_logical_op__is_signed, output_logical_op__is_32bit, output_logical_op__output_carry, output_logical_op__write_cr0, output_logical_op__invert_out, output_logical_op__input_carry, output_logical_op__zero_a, output_logical_op__invert_in, output_logical_op__oe__ok, output_logical_op__oe__oe, output_logical_op__rc__ok, output_logical_op__rc__rc, output_logical_op__imm_data__ok, output_logical_op__imm_data__data, output_logical_op__fn_unit, output_logical_op__insn_type } = { \output_stage_logical_op__SV_Ptype$47 , \output_stage_logical_op__sv_saturate$46 , \output_stage_logical_op__sv_pred_dz$45 , \output_stage_logical_op__sv_pred_sz$44 , \output_stage_logical_op__insn$43 , \output_stage_logical_op__data_len$42 , \output_stage_logical_op__is_signed$41 , \output_stage_logical_op__is_32bit$40 , \output_stage_logical_op__output_carry$39 , \output_stage_logical_op__write_cr0$38 , \output_stage_logical_op__invert_out$37 , \output_stage_logical_op__input_carry$36 , \output_stage_logical_op__zero_a$35 , \output_stage_logical_op__invert_in$34 , \output_stage_logical_op__oe__ok$33 , \output_stage_logical_op__oe__oe$32 , \output_stage_logical_op__rc__ok$31 , \output_stage_logical_op__rc__rc$30 , \output_stage_logical_op__imm_data__ok$29 , \output_stage_logical_op__imm_data__data$28 , \output_stage_logical_op__fn_unit$27 , \output_stage_logical_op__insn_type$26 }; + assign output_muxid = \output_stage_muxid$25 ; assign output_stage_remainder = remainder; assign output_stage_quotient_root = quotient_root; assign output_stage_div_by_zero = div_by_zero; @@ -173937,40 +187095,40 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type assign output_stage_dividend_neg = dividend_neg; assign output_stage_divisor_neg = divisor_neg; assign output_stage_xer_so = xer_so; - assign \rb$66 = rb; - assign \ra$65 = ra; - assign { output_stage_logical_op__insn, output_stage_logical_op__data_len, output_stage_logical_op__is_signed, output_stage_logical_op__is_32bit, output_stage_logical_op__output_carry, output_stage_logical_op__write_cr0, output_stage_logical_op__invert_out, output_stage_logical_op__input_carry, output_stage_logical_op__zero_a, output_stage_logical_op__invert_in, output_stage_logical_op__oe__ok, output_stage_logical_op__oe__oe, output_stage_logical_op__rc__ok, output_stage_logical_op__rc__rc, output_stage_logical_op__imm_data__ok, output_stage_logical_op__imm_data__data, output_stage_logical_op__fn_unit, output_stage_logical_op__insn_type } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; + assign \rb$78 = rb; + assign \ra$77 = ra; + assign { output_stage_logical_op__SV_Ptype, output_stage_logical_op__sv_saturate, output_stage_logical_op__sv_pred_dz, output_stage_logical_op__sv_pred_sz, output_stage_logical_op__insn, output_stage_logical_op__data_len, output_stage_logical_op__is_signed, output_stage_logical_op__is_32bit, output_stage_logical_op__output_carry, output_stage_logical_op__write_cr0, output_stage_logical_op__invert_out, output_stage_logical_op__input_carry, output_stage_logical_op__zero_a, output_stage_logical_op__invert_in, output_stage_logical_op__oe__ok, output_stage_logical_op__oe__oe, output_stage_logical_op__rc__ok, output_stage_logical_op__rc__rc, output_stage_logical_op__imm_data__ok, output_stage_logical_op__imm_data__data, output_stage_logical_op__fn_unit, output_stage_logical_op__insn_type } = { logical_op__SV_Ptype, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; assign output_stage_muxid = muxid; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0" *) (* generator = "nMigen" *) -module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, ra, rb, xer_so, divisor_neg, dividend_neg, dive_abs_ov32, dive_abs_ov64, div_by_zero, dividend, divisor_radicand, operation, n_valid_o, n_ready_i, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \ra$20 , \rb$21 , \xer_so$22 , \divisor_neg$23 , \dividend_neg$24 , \dive_abs_ov32$25 , \dive_abs_ov64$26 , \div_by_zero$27 , quotient_root, remainder, coresync_clk); +module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__SV_Ptype, ra, rb, xer_so, divisor_neg, dividend_neg, dive_abs_ov32, dive_abs_ov64, div_by_zero, dividend, divisor_radicand, operation, n_valid_o, n_ready_i, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__SV_Ptype$23 , \ra$24 , \rb$25 , \xer_so$26 , \divisor_neg$27 , \dividend_neg$28 , \dive_abs_ov32$29 , \dive_abs_ov64$30 , \div_by_zero$31 , quotient_root, remainder, coresync_clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" *) - wire [191:0] \$55 ; + wire [191:0] \$63 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" *) - wire [190:0] \$56 ; + wire [190:0] \$64 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" *) - wire \$59 ; + wire \$67 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" *) - wire \$61 ; + wire \$69 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" *) - wire \$63 ; + wire \$71 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" *) - wire \$66 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + wire \$74 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) input div_by_zero; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) - output \div_by_zero$27 ; + output \div_by_zero$31 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) - reg \div_by_zero$54 = 1'h0; + reg \div_by_zero$62 = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) - reg \div_by_zero$54$next ; + reg \div_by_zero$62$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:89" *) wire [127:0] div_state_init_dividend; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" *) @@ -173990,156 +187148,179 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *) input dive_abs_ov32; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *) - output \dive_abs_ov32$25 ; + output \dive_abs_ov32$29 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *) - reg \dive_abs_ov32$52 = 1'h0; + reg \dive_abs_ov32$60 = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *) - reg \dive_abs_ov32$52$next ; + reg \dive_abs_ov32$60$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *) input dive_abs_ov64; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *) - output \dive_abs_ov64$26 ; + output \dive_abs_ov64$30 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *) - reg \dive_abs_ov64$53 = 1'h0; + reg \dive_abs_ov64$61 = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *) - reg \dive_abs_ov64$53$next ; + reg \dive_abs_ov64$61$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *) input [127:0] dividend; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *) - reg [127:0] \dividend$68 = 128'h00000000000000000000000000000000; + reg [127:0] \dividend$76 = 128'h00000000000000000000000000000000; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *) - reg [127:0] \dividend$68$next ; + reg [127:0] \dividend$76$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *) input dividend_neg; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *) - output \dividend_neg$24 ; + output \dividend_neg$28 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *) - reg \dividend_neg$51 = 1'h0; + reg \dividend_neg$59 = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *) - reg \dividend_neg$51$next ; + reg \dividend_neg$59$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *) input divisor_neg; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *) - output \divisor_neg$23 ; + output \divisor_neg$27 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *) - reg \divisor_neg$50 = 1'h0; + reg \divisor_neg$58 = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *) - reg \divisor_neg$50$next ; + reg \divisor_neg$58$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *) input [63:0] divisor_radicand; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *) - reg [63:0] \divisor_radicand$65 = 64'h0000000000000000; + reg [63:0] \divisor_radicand$73 = 64'h0000000000000000; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *) - reg [63:0] \divisor_radicand$65$next ; + reg [63:0] \divisor_radicand$73$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" *) reg empty = 1'h1; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" *) reg \empty$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] logical_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \logical_op__SV_Ptype$23 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \logical_op__SV_Ptype$54 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \logical_op__SV_Ptype$54$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [3:0] logical_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [3:0] \logical_op__data_len$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [3:0] \logical_op__data_len$45 = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [3:0] \logical_op__data_len$45$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [3:0] \logical_op__data_len$49 = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [3:0] \logical_op__data_len$49$next ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] logical_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] logical_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \logical_op__fn_unit$3 ; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \logical_op__fn_unit$3 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] \logical_op__fn_unit$30 = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] \logical_op__fn_unit$30$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] \logical_op__fn_unit$34 = 15'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] \logical_op__fn_unit$34$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] logical_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [63:0] \logical_op__imm_data__data$31 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [63:0] \logical_op__imm_data__data$31$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [63:0] \logical_op__imm_data__data$35 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [63:0] \logical_op__imm_data__data$35$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \logical_op__imm_data__data$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg \logical_op__imm_data__ok$32 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg \logical_op__imm_data__ok$32$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__imm_data__ok$36 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__imm_data__ok$36$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__imm_data__ok$5 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] logical_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [1:0] \logical_op__input_carry$12 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [1:0] \logical_op__input_carry$39 = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [1:0] \logical_op__input_carry$39$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \logical_op__input_carry$43 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \logical_op__input_carry$43$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] logical_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \logical_op__insn$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [31:0] \logical_op__insn$46 = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [31:0] \logical_op__insn$46$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [31:0] \logical_op__insn$50 = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [31:0] \logical_op__insn$50$next ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -174215,7 +187396,9 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] logical_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -174292,7 +187475,9 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] \logical_op__insn_type$2 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -174369,106 +187554,144 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [6:0] \logical_op__insn_type$29 = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [6:0] \logical_op__insn_type$29$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [6:0] \logical_op__insn_type$33 = 7'h00; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [6:0] \logical_op__insn_type$33$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__invert_in$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg \logical_op__invert_in$37 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg \logical_op__invert_in$37$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__invert_in$41 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__invert_in$41$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__invert_out$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg \logical_op__invert_out$40 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg \logical_op__invert_out$40$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__invert_out$44 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__invert_out$44$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__is_32bit$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg \logical_op__is_32bit$43 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg \logical_op__is_32bit$43$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__is_32bit$47 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__is_32bit$47$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__is_signed$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg \logical_op__is_signed$44 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg \logical_op__is_signed$44$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__is_signed$48 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__is_signed$48$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg \logical_op__oe__oe$35 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg \logical_op__oe__oe$35$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__oe__oe$39 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__oe__oe$39$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__oe__oe$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg \logical_op__oe__ok$36 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg \logical_op__oe__ok$36$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__oe__ok$40 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__oe__ok$40$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__oe__ok$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__output_carry$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg \logical_op__output_carry$42 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg \logical_op__output_carry$42$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__output_carry$46 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__output_carry$46$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg \logical_op__rc__ok$34 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg \logical_op__rc__ok$34$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__rc__ok$38 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__rc__ok$38$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__rc__ok$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg \logical_op__rc__rc$33 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg \logical_op__rc__rc$33$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__rc__rc$37 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__rc__rc$37$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__rc__rc$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input logical_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \logical_op__sv_pred_dz$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__sv_pred_dz$52 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__sv_pred_dz$52$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input logical_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \logical_op__sv_pred_sz$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__sv_pred_sz$51 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__sv_pred_sz$51$next ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] logical_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \logical_op__sv_saturate$22 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \logical_op__sv_saturate$53 = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \logical_op__sv_saturate$53$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__write_cr0$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg \logical_op__write_cr0$41 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg \logical_op__write_cr0$41$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__write_cr0$45 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__write_cr0$45$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__zero_a$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg \logical_op__zero_a$38 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg \logical_op__zero_a$38$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__zero_a$42 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__zero_a$42$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] \muxid$1 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - reg [1:0] \muxid$28 = 2'h0; + reg [1:0] \muxid$32 = 2'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - reg [1:0] \muxid$28$next ; + reg [1:0] \muxid$32$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) input n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) @@ -174476,31 +187699,31 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" *) input [1:0] operation; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" *) - reg [1:0] \operation$69 = 2'h0; + reg [1:0] \operation$77 = 2'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" *) - reg [1:0] \operation$69$next ; + reg [1:0] \operation$77$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) output p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) input p_valid_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" *) output [63:0] quotient_root; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - output [63:0] \ra$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - reg [63:0] \ra$47 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - reg [63:0] \ra$47$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + output [63:0] \ra$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + reg [63:0] \ra$55 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + reg [63:0] \ra$55$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - output [63:0] \rb$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - reg [63:0] \rb$48 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - reg [63:0] \rb$48$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + output [63:0] \rb$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + reg [63:0] \rb$56 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + reg [63:0] \rb$56$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" *) output [191:0] remainder; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" *) @@ -174511,80 +187734,88 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn reg [6:0] saved_state_q_bits_known = 7'h00; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" *) reg [6:0] \saved_state_q_bits_known$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - output \xer_so$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - reg \xer_so$49 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - reg \xer_so$49$next ; - assign \$56 = div_state_next_o_dividend_quotient[127:64] <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" *) 7'h40; - assign \$55 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" *) \$56 ; - assign \$59 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" *) empty; - assign \$61 = saved_state_q_bits_known >= (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" *) 6'h3f; - assign \$63 = \$59 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" *) \$61 ; - assign \$66 = n_ready_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" *) n_valid_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + output \xer_so$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + reg \xer_so$57 = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + reg \xer_so$57$next ; + assign \$64 = div_state_next_o_dividend_quotient[127:64] <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" *) 7'h40; + assign \$63 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" *) \$64 ; + assign \$67 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" *) empty; + assign \$69 = saved_state_q_bits_known >= (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" *) 6'h3f; + assign \$71 = \$67 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" *) \$69 ; + assign \$74 = n_ready_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" *) n_valid_o; + always @(posedge coresync_clk) + \operation$77 <= \operation$77$next ; always @(posedge coresync_clk) - \operation$69 <= \operation$69$next ; + \divisor_radicand$73 <= \divisor_radicand$73$next ; always @(posedge coresync_clk) - \divisor_radicand$65 <= \divisor_radicand$65$next ; + \dividend$76 <= \dividend$76$next ; always @(posedge coresync_clk) - \dividend$68 <= \dividend$68$next ; + \div_by_zero$62 <= \div_by_zero$62$next ; always @(posedge coresync_clk) - \div_by_zero$54 <= \div_by_zero$54$next ; + \dive_abs_ov64$61 <= \dive_abs_ov64$61$next ; always @(posedge coresync_clk) - \dive_abs_ov64$53 <= \dive_abs_ov64$53$next ; + \dive_abs_ov32$60 <= \dive_abs_ov32$60$next ; always @(posedge coresync_clk) - \dive_abs_ov32$52 <= \dive_abs_ov32$52$next ; + \dividend_neg$59 <= \dividend_neg$59$next ; always @(posedge coresync_clk) - \dividend_neg$51 <= \dividend_neg$51$next ; + \divisor_neg$58 <= \divisor_neg$58$next ; always @(posedge coresync_clk) - \divisor_neg$50 <= \divisor_neg$50$next ; + \xer_so$57 <= \xer_so$57$next ; always @(posedge coresync_clk) - \xer_so$49 <= \xer_so$49$next ; + \rb$56 <= \rb$56$next ; always @(posedge coresync_clk) - \rb$48 <= \rb$48$next ; + \ra$55 <= \ra$55$next ; always @(posedge coresync_clk) - \ra$47 <= \ra$47$next ; + \logical_op__insn_type$33 <= \logical_op__insn_type$33$next ; always @(posedge coresync_clk) - \logical_op__insn_type$29 <= \logical_op__insn_type$29$next ; + \logical_op__fn_unit$34 <= \logical_op__fn_unit$34$next ; always @(posedge coresync_clk) - \logical_op__fn_unit$30 <= \logical_op__fn_unit$30$next ; + \logical_op__imm_data__data$35 <= \logical_op__imm_data__data$35$next ; always @(posedge coresync_clk) - \logical_op__imm_data__data$31 <= \logical_op__imm_data__data$31$next ; + \logical_op__imm_data__ok$36 <= \logical_op__imm_data__ok$36$next ; always @(posedge coresync_clk) - \logical_op__imm_data__ok$32 <= \logical_op__imm_data__ok$32$next ; + \logical_op__rc__rc$37 <= \logical_op__rc__rc$37$next ; always @(posedge coresync_clk) - \logical_op__rc__rc$33 <= \logical_op__rc__rc$33$next ; + \logical_op__rc__ok$38 <= \logical_op__rc__ok$38$next ; always @(posedge coresync_clk) - \logical_op__rc__ok$34 <= \logical_op__rc__ok$34$next ; + \logical_op__oe__oe$39 <= \logical_op__oe__oe$39$next ; always @(posedge coresync_clk) - \logical_op__oe__oe$35 <= \logical_op__oe__oe$35$next ; + \logical_op__oe__ok$40 <= \logical_op__oe__ok$40$next ; always @(posedge coresync_clk) - \logical_op__oe__ok$36 <= \logical_op__oe__ok$36$next ; + \logical_op__invert_in$41 <= \logical_op__invert_in$41$next ; always @(posedge coresync_clk) - \logical_op__invert_in$37 <= \logical_op__invert_in$37$next ; + \logical_op__zero_a$42 <= \logical_op__zero_a$42$next ; always @(posedge coresync_clk) - \logical_op__zero_a$38 <= \logical_op__zero_a$38$next ; + \logical_op__input_carry$43 <= \logical_op__input_carry$43$next ; always @(posedge coresync_clk) - \logical_op__input_carry$39 <= \logical_op__input_carry$39$next ; + \logical_op__invert_out$44 <= \logical_op__invert_out$44$next ; always @(posedge coresync_clk) - \logical_op__invert_out$40 <= \logical_op__invert_out$40$next ; + \logical_op__write_cr0$45 <= \logical_op__write_cr0$45$next ; always @(posedge coresync_clk) - \logical_op__write_cr0$41 <= \logical_op__write_cr0$41$next ; + \logical_op__output_carry$46 <= \logical_op__output_carry$46$next ; always @(posedge coresync_clk) - \logical_op__output_carry$42 <= \logical_op__output_carry$42$next ; + \logical_op__is_32bit$47 <= \logical_op__is_32bit$47$next ; always @(posedge coresync_clk) - \logical_op__is_32bit$43 <= \logical_op__is_32bit$43$next ; + \logical_op__is_signed$48 <= \logical_op__is_signed$48$next ; always @(posedge coresync_clk) - \logical_op__is_signed$44 <= \logical_op__is_signed$44$next ; + \logical_op__data_len$49 <= \logical_op__data_len$49$next ; always @(posedge coresync_clk) - \logical_op__data_len$45 <= \logical_op__data_len$45$next ; + \logical_op__insn$50 <= \logical_op__insn$50$next ; always @(posedge coresync_clk) - \logical_op__insn$46 <= \logical_op__insn$46$next ; + \logical_op__sv_pred_sz$51 <= \logical_op__sv_pred_sz$51$next ; always @(posedge coresync_clk) - \muxid$28 <= \muxid$28$next ; + \logical_op__sv_pred_dz$52 <= \logical_op__sv_pred_dz$52$next ; + always @(posedge coresync_clk) + \logical_op__sv_saturate$53 <= \logical_op__sv_saturate$53$next ; + always @(posedge coresync_clk) + \logical_op__SV_Ptype$54 <= \logical_op__SV_Ptype$54$next ; + always @(posedge coresync_clk) + \muxid$32 <= \muxid$32$next ; always @(posedge coresync_clk) empty <= \empty$next ; always @(posedge coresync_clk) @@ -174614,7 +187845,7 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn always @* begin if (\initial ) begin end \saved_state_q_bits_known$next = div_state_next_o_q_bits_known; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \saved_state_q_bits_known$next = 7'h00; @@ -174623,7 +187854,7 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn always @* begin if (\initial ) begin end \saved_state_dividend_quotient$next = div_state_next_o_dividend_quotient; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \saved_state_dividend_quotient$next = 128'h00000000000000000000000000000000; @@ -174665,7 +187896,7 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn div_state_next_divisor = divisor_radicand; /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:181" */ default: - div_state_next_divisor = \divisor_radicand$65 ; + div_state_next_divisor = \divisor_radicand$73 ; endcase end always @* begin @@ -174685,13 +187916,13 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:181" */ default: (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" *) - casez (\$66 ) + casez (\$74 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" */ 1'h1: \empty$next = 1'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \empty$next = 1'h1; @@ -174699,7 +187930,7 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn end always @* begin if (\initial ) begin end - \muxid$28$next = \muxid$28 ; + \muxid$32$next = \muxid$32 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) casez (empty) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ @@ -174708,30 +187939,34 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn casez (p_valid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */ 1'h1: - \muxid$28$next = muxid; - endcase - endcase - end - always @* begin - if (\initial ) begin end - \logical_op__insn_type$29$next = \logical_op__insn_type$29 ; - \logical_op__fn_unit$30$next = \logical_op__fn_unit$30 ; - \logical_op__imm_data__data$31$next = \logical_op__imm_data__data$31 ; - \logical_op__imm_data__ok$32$next = \logical_op__imm_data__ok$32 ; - \logical_op__rc__rc$33$next = \logical_op__rc__rc$33 ; - \logical_op__rc__ok$34$next = \logical_op__rc__ok$34 ; - \logical_op__oe__oe$35$next = \logical_op__oe__oe$35 ; - \logical_op__oe__ok$36$next = \logical_op__oe__ok$36 ; - \logical_op__invert_in$37$next = \logical_op__invert_in$37 ; - \logical_op__zero_a$38$next = \logical_op__zero_a$38 ; - \logical_op__input_carry$39$next = \logical_op__input_carry$39 ; - \logical_op__invert_out$40$next = \logical_op__invert_out$40 ; - \logical_op__write_cr0$41$next = \logical_op__write_cr0$41 ; - \logical_op__output_carry$42$next = \logical_op__output_carry$42 ; - \logical_op__is_32bit$43$next = \logical_op__is_32bit$43 ; - \logical_op__is_signed$44$next = \logical_op__is_signed$44 ; - \logical_op__data_len$45$next = \logical_op__data_len$45 ; - \logical_op__insn$46$next = \logical_op__insn$46 ; + \muxid$32$next = muxid; + endcase + endcase + end + always @* begin + if (\initial ) begin end + \logical_op__insn_type$33$next = \logical_op__insn_type$33 ; + \logical_op__fn_unit$34$next = \logical_op__fn_unit$34 ; + \logical_op__imm_data__data$35$next = \logical_op__imm_data__data$35 ; + \logical_op__imm_data__ok$36$next = \logical_op__imm_data__ok$36 ; + \logical_op__rc__rc$37$next = \logical_op__rc__rc$37 ; + \logical_op__rc__ok$38$next = \logical_op__rc__ok$38 ; + \logical_op__oe__oe$39$next = \logical_op__oe__oe$39 ; + \logical_op__oe__ok$40$next = \logical_op__oe__ok$40 ; + \logical_op__invert_in$41$next = \logical_op__invert_in$41 ; + \logical_op__zero_a$42$next = \logical_op__zero_a$42 ; + \logical_op__input_carry$43$next = \logical_op__input_carry$43 ; + \logical_op__invert_out$44$next = \logical_op__invert_out$44 ; + \logical_op__write_cr0$45$next = \logical_op__write_cr0$45 ; + \logical_op__output_carry$46$next = \logical_op__output_carry$46 ; + \logical_op__is_32bit$47$next = \logical_op__is_32bit$47 ; + \logical_op__is_signed$48$next = \logical_op__is_signed$48 ; + \logical_op__data_len$49$next = \logical_op__data_len$49 ; + \logical_op__insn$50$next = \logical_op__insn$50 ; + \logical_op__sv_pred_sz$51$next = \logical_op__sv_pred_sz$51 ; + \logical_op__sv_pred_dz$52$next = \logical_op__sv_pred_dz$52 ; + \logical_op__sv_saturate$53$next = \logical_op__sv_saturate$53 ; + \logical_op__SV_Ptype$54$next = \logical_op__SV_Ptype$54 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) casez (empty) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ @@ -174740,25 +187975,25 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn casez (p_valid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */ 1'h1: - { \logical_op__insn$46$next , \logical_op__data_len$45$next , \logical_op__is_signed$44$next , \logical_op__is_32bit$43$next , \logical_op__output_carry$42$next , \logical_op__write_cr0$41$next , \logical_op__invert_out$40$next , \logical_op__input_carry$39$next , \logical_op__zero_a$38$next , \logical_op__invert_in$37$next , \logical_op__oe__ok$36$next , \logical_op__oe__oe$35$next , \logical_op__rc__ok$34$next , \logical_op__rc__rc$33$next , \logical_op__imm_data__ok$32$next , \logical_op__imm_data__data$31$next , \logical_op__fn_unit$30$next , \logical_op__insn_type$29$next } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; + { \logical_op__SV_Ptype$54$next , \logical_op__sv_saturate$53$next , \logical_op__sv_pred_dz$52$next , \logical_op__sv_pred_sz$51$next , \logical_op__insn$50$next , \logical_op__data_len$49$next , \logical_op__is_signed$48$next , \logical_op__is_32bit$47$next , \logical_op__output_carry$46$next , \logical_op__write_cr0$45$next , \logical_op__invert_out$44$next , \logical_op__input_carry$43$next , \logical_op__zero_a$42$next , \logical_op__invert_in$41$next , \logical_op__oe__ok$40$next , \logical_op__oe__oe$39$next , \logical_op__rc__ok$38$next , \logical_op__rc__rc$37$next , \logical_op__imm_data__ok$36$next , \logical_op__imm_data__data$35$next , \logical_op__fn_unit$34$next , \logical_op__insn_type$33$next } = { logical_op__SV_Ptype, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin - \logical_op__imm_data__data$31$next = 64'h0000000000000000; - \logical_op__imm_data__ok$32$next = 1'h0; - \logical_op__rc__rc$33$next = 1'h0; - \logical_op__rc__ok$34$next = 1'h0; - \logical_op__oe__oe$35$next = 1'h0; - \logical_op__oe__ok$36$next = 1'h0; + \logical_op__imm_data__data$35$next = 64'h0000000000000000; + \logical_op__imm_data__ok$36$next = 1'h0; + \logical_op__rc__rc$37$next = 1'h0; + \logical_op__rc__ok$38$next = 1'h0; + \logical_op__oe__oe$39$next = 1'h0; + \logical_op__oe__ok$40$next = 1'h0; end endcase end always @* begin if (\initial ) begin end - \ra$47$next = \ra$47 ; + \ra$55$next = \ra$55 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) casez (empty) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ @@ -174767,13 +188002,13 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn casez (p_valid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */ 1'h1: - \ra$47$next = ra; + \ra$55$next = ra; endcase endcase end always @* begin if (\initial ) begin end - \rb$48$next = \rb$48 ; + \rb$56$next = \rb$56 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) casez (empty) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ @@ -174782,13 +188017,13 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn casez (p_valid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */ 1'h1: - \rb$48$next = rb; + \rb$56$next = rb; endcase endcase end always @* begin if (\initial ) begin end - \xer_so$49$next = \xer_so$49 ; + \xer_so$57$next = \xer_so$57 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) casez (empty) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ @@ -174797,13 +188032,13 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn casez (p_valid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */ 1'h1: - \xer_so$49$next = xer_so; + \xer_so$57$next = xer_so; endcase endcase end always @* begin if (\initial ) begin end - \divisor_neg$50$next = \divisor_neg$50 ; + \divisor_neg$58$next = \divisor_neg$58 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) casez (empty) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ @@ -174812,13 +188047,13 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn casez (p_valid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */ 1'h1: - \divisor_neg$50$next = divisor_neg; + \divisor_neg$58$next = divisor_neg; endcase endcase end always @* begin if (\initial ) begin end - \dividend_neg$51$next = \dividend_neg$51 ; + \dividend_neg$59$next = \dividend_neg$59 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) casez (empty) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ @@ -174827,13 +188062,13 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn casez (p_valid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */ 1'h1: - \dividend_neg$51$next = dividend_neg; + \dividend_neg$59$next = dividend_neg; endcase endcase end always @* begin if (\initial ) begin end - \dive_abs_ov32$52$next = \dive_abs_ov32$52 ; + \dive_abs_ov32$60$next = \dive_abs_ov32$60 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) casez (empty) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ @@ -174842,13 +188077,13 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn casez (p_valid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */ 1'h1: - \dive_abs_ov32$52$next = dive_abs_ov32; + \dive_abs_ov32$60$next = dive_abs_ov32; endcase endcase end always @* begin if (\initial ) begin end - \dive_abs_ov64$53$next = \dive_abs_ov64$53 ; + \dive_abs_ov64$61$next = \dive_abs_ov64$61 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) casez (empty) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ @@ -174857,13 +188092,13 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn casez (p_valid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */ 1'h1: - \dive_abs_ov64$53$next = dive_abs_ov64; + \dive_abs_ov64$61$next = dive_abs_ov64; endcase endcase end always @* begin if (\initial ) begin end - \div_by_zero$54$next = \div_by_zero$54 ; + \div_by_zero$62$next = \div_by_zero$62 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) casez (empty) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ @@ -174872,13 +188107,13 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn casez (p_valid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */ 1'h1: - \div_by_zero$54$next = div_by_zero; + \div_by_zero$62$next = div_by_zero; endcase endcase end always @* begin if (\initial ) begin end - \dividend$68$next = \dividend$68 ; + \dividend$76$next = \dividend$76 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) casez (empty) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ @@ -174887,13 +188122,13 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn casez (p_valid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */ 1'h1: - \dividend$68$next = dividend; + \dividend$76$next = dividend; endcase endcase end always @* begin if (\initial ) begin end - \divisor_radicand$65$next = \divisor_radicand$65 ; + \divisor_radicand$73$next = \divisor_radicand$73 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) casez (empty) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ @@ -174902,13 +188137,13 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn casez (p_valid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */ 1'h1: - \divisor_radicand$65$next = divisor_radicand; + \divisor_radicand$73$next = divisor_radicand; endcase endcase end always @* begin if (\initial ) begin end - \operation$69$next = \operation$69 ; + \operation$77$next = \operation$77 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) casez (empty) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ @@ -174917,148 +188152,162 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn casez (p_valid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" */ 1'h1: - \operation$69$next = operation; + \operation$77$next = operation; endcase endcase end assign p_ready_o = empty; - assign n_valid_o = \$63 ; - assign remainder = \$55 ; + assign n_valid_o = \$71 ; + assign remainder = \$63 ; assign quotient_root = div_state_next_o_dividend_quotient[63:0]; - assign \div_by_zero$27 = \div_by_zero$54 ; - assign \dive_abs_ov64$26 = \dive_abs_ov64$53 ; - assign \dive_abs_ov32$25 = \dive_abs_ov32$52 ; - assign \dividend_neg$24 = \dividend_neg$51 ; - assign \divisor_neg$23 = \divisor_neg$50 ; - assign \xer_so$22 = \xer_so$49 ; - assign \rb$21 = \rb$48 ; - assign \ra$20 = \ra$47 ; - assign { \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { \logical_op__insn$46 , \logical_op__data_len$45 , \logical_op__is_signed$44 , \logical_op__is_32bit$43 , \logical_op__output_carry$42 , \logical_op__write_cr0$41 , \logical_op__invert_out$40 , \logical_op__input_carry$39 , \logical_op__zero_a$38 , \logical_op__invert_in$37 , \logical_op__oe__ok$36 , \logical_op__oe__oe$35 , \logical_op__rc__ok$34 , \logical_op__rc__rc$33 , \logical_op__imm_data__ok$32 , \logical_op__imm_data__data$31 , \logical_op__fn_unit$30 , \logical_op__insn_type$29 }; - assign \muxid$1 = \muxid$28 ; + assign \div_by_zero$31 = \div_by_zero$62 ; + assign \dive_abs_ov64$30 = \dive_abs_ov64$61 ; + assign \dive_abs_ov32$29 = \dive_abs_ov32$60 ; + assign \dividend_neg$28 = \dividend_neg$59 ; + assign \divisor_neg$27 = \divisor_neg$58 ; + assign \xer_so$26 = \xer_so$57 ; + assign \rb$25 = \rb$56 ; + assign \ra$24 = \ra$55 ; + assign { \logical_op__SV_Ptype$23 , \logical_op__sv_saturate$22 , \logical_op__sv_pred_dz$21 , \logical_op__sv_pred_sz$20 , \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { \logical_op__SV_Ptype$54 , \logical_op__sv_saturate$53 , \logical_op__sv_pred_dz$52 , \logical_op__sv_pred_sz$51 , \logical_op__insn$50 , \logical_op__data_len$49 , \logical_op__is_signed$48 , \logical_op__is_32bit$47 , \logical_op__output_carry$46 , \logical_op__write_cr0$45 , \logical_op__invert_out$44 , \logical_op__input_carry$43 , \logical_op__zero_a$42 , \logical_op__invert_in$41 , \logical_op__oe__ok$40 , \logical_op__oe__oe$39 , \logical_op__rc__ok$38 , \logical_op__rc__rc$37 , \logical_op__imm_data__ok$36 , \logical_op__imm_data__data$35 , \logical_op__fn_unit$34 , \logical_op__insn_type$33 }; + assign \muxid$1 = \muxid$32 ; assign div_state_init_dividend = dividend; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0.pipe_start" *) (* generator = "nMigen" *) -module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, ra, rb, xer_so, divisor_neg, dividend_neg, dive_abs_ov32, dive_abs_ov64, div_by_zero, dividend, divisor_radicand, operation, p_valid_i, p_ready_o, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \ra$20 , \rb$21 , \xer_so$22 , coresync_clk); +module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__SV_Ptype, ra, rb, xer_so, divisor_neg, dividend_neg, dive_abs_ov32, dive_abs_ov64, div_by_zero, dividend, divisor_radicand, operation, p_valid_i, p_ready_o, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__SV_Ptype$23 , \ra$24 , \rb$25 , \xer_so$26 , coresync_clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) - wire \$66 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + wire \$78 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) output div_by_zero; reg div_by_zero = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) - wire \div_by_zero$96 ; + wire \div_by_zero$112 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) reg \div_by_zero$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *) output dive_abs_ov32; reg dive_abs_ov32 = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *) - wire \dive_abs_ov32$94 ; + wire \dive_abs_ov32$110 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *) reg \dive_abs_ov32$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *) output dive_abs_ov64; reg dive_abs_ov64 = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *) - wire \dive_abs_ov64$95 ; + wire \dive_abs_ov64$111 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *) reg \dive_abs_ov64$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *) output [127:0] dividend; reg [127:0] dividend = 128'h00000000000000000000000000000000; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *) - wire [127:0] \dividend$97 ; + wire [127:0] \dividend$113 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *) reg [127:0] \dividend$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *) output dividend_neg; reg dividend_neg = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *) - wire \dividend_neg$93 ; + wire \dividend_neg$109 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *) reg \dividend_neg$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *) output divisor_neg; reg divisor_neg = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *) - wire \divisor_neg$92 ; + wire \divisor_neg$108 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *) reg \divisor_neg$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *) output [63:0] divisor_radicand; reg [63:0] divisor_radicand = 64'h0000000000000000; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *) - wire [63:0] \divisor_radicand$98 ; + wire [63:0] \divisor_radicand$114 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *) reg [63:0] \divisor_radicand$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] input_logical_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \input_logical_op__SV_Ptype$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [3:0] input_logical_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [3:0] \input_logical_op__data_len$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [3:0] \input_logical_op__data_len$44 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] input_logical_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] input_logical_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \input_logical_op__fn_unit$25 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \input_logical_op__fn_unit$29 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] input_logical_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \input_logical_op__imm_data__data$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \input_logical_op__imm_data__data$30 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_logical_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_logical_op__imm_data__ok$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_logical_op__imm_data__ok$31 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [1:0] input_logical_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [1:0] \input_logical_op__input_carry$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \input_logical_op__input_carry$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] input_logical_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \input_logical_op__insn$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \input_logical_op__insn$45 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -175134,7 +188383,9 @@ module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_ty (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] input_logical_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -175211,178 +188462,224 @@ module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_ty (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \input_logical_op__insn_type$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \input_logical_op__insn_type$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_logical_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_logical_op__invert_in$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_logical_op__invert_in$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_logical_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_logical_op__invert_out$35 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_logical_op__invert_out$39 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_logical_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_logical_op__is_32bit$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_logical_op__is_32bit$42 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_logical_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_logical_op__is_signed$39 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_logical_op__is_signed$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_logical_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_logical_op__oe__oe$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_logical_op__oe__oe$34 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_logical_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_logical_op__oe__ok$31 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_logical_op__oe__ok$35 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_logical_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_logical_op__output_carry$37 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_logical_op__output_carry$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_logical_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_logical_op__rc__ok$29 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_logical_op__rc__ok$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_logical_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_logical_op__rc__rc$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_logical_op__rc__rc$32 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire input_logical_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_logical_op__sv_pred_dz$47 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire input_logical_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_logical_op__sv_pred_sz$46 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] input_logical_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \input_logical_op__sv_saturate$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_logical_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_logical_op__write_cr0$36 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_logical_op__write_cr0$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire input_logical_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \input_logical_op__zero_a$33 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \input_logical_op__zero_a$37 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] input_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \input_muxid$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + wire [1:0] \input_muxid$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] input_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \input_ra$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \input_ra$50 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] input_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \input_rb$43 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \input_rb$51 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire input_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire \input_xer_so$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire \input_xer_so$52 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] logical_op__SV_Ptype; + reg [1:0] logical_op__SV_Ptype = 2'h0; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \logical_op__SV_Ptype$102 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] \logical_op__SV_Ptype$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \logical_op__SV_Ptype$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [3:0] logical_op__data_len; reg [3:0] logical_op__data_len = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [3:0] \logical_op__data_len$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [3:0] \logical_op__data_len$85 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [3:0] \logical_op__data_len$97 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [3:0] \logical_op__data_len$next ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] logical_op__fn_unit; - reg [13:0] logical_op__fn_unit = 14'h0000; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] logical_op__fn_unit; + reg [14:0] logical_op__fn_unit = 15'h0000; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] \logical_op__fn_unit$3 ; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] \logical_op__fn_unit$3 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \logical_op__fn_unit$70 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] \logical_op__fn_unit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \logical_op__fn_unit$82 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] \logical_op__fn_unit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] logical_op__imm_data__data; reg [63:0] logical_op__imm_data__data = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] \logical_op__imm_data__data$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \logical_op__imm_data__data$71 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \logical_op__imm_data__data$83 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] \logical_op__imm_data__data$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output logical_op__imm_data__ok; reg logical_op__imm_data__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \logical_op__imm_data__ok$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__imm_data__ok$72 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__imm_data__ok$84 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__imm_data__ok$next ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [1:0] logical_op__input_carry; reg [1:0] logical_op__input_carry = 2'h0; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] \logical_op__input_carry$12 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [1:0] \logical_op__input_carry$79 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \logical_op__input_carry$91 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [1:0] \logical_op__input_carry$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] logical_op__insn; reg [31:0] logical_op__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] \logical_op__insn$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \logical_op__insn$86 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \logical_op__insn$98 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] \logical_op__insn$next ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -175459,7 +188756,9 @@ module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_ty (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] logical_op__insn_type; reg [6:0] logical_op__insn_type = 7'h00; (* enum_base_type = "MicrOp" *) @@ -175537,7 +188836,9 @@ module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_ty (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] \logical_op__insn_type$2 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -175614,108 +188915,149 @@ module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_ty (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \logical_op__insn_type$69 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \logical_op__insn_type$81 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] \logical_op__insn_type$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output logical_op__invert_in; reg logical_op__invert_in = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \logical_op__invert_in$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__invert_in$77 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__invert_in$89 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__invert_in$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output logical_op__invert_out; reg logical_op__invert_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \logical_op__invert_out$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__invert_out$80 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__invert_out$92 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__invert_out$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output logical_op__is_32bit; reg logical_op__is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \logical_op__is_32bit$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__is_32bit$83 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__is_32bit$95 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__is_32bit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output logical_op__is_signed; reg logical_op__is_signed = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \logical_op__is_signed$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__is_signed$84 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__is_signed$96 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__is_signed$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output logical_op__oe__oe; reg logical_op__oe__oe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__oe__oe$75 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \logical_op__oe__oe$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__oe__oe$87 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__oe__oe$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output logical_op__oe__ok; reg logical_op__oe__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__oe__ok$76 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__oe__ok$88 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \logical_op__oe__ok$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__oe__ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output logical_op__output_carry; reg logical_op__output_carry = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \logical_op__output_carry$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__output_carry$82 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__output_carry$94 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__output_carry$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output logical_op__rc__ok; reg logical_op__rc__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \logical_op__rc__ok$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__rc__ok$74 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__rc__ok$86 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__rc__ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output logical_op__rc__rc; reg logical_op__rc__rc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \logical_op__rc__rc$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__rc__rc$73 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__rc__rc$85 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__rc__rc$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output logical_op__sv_pred_dz; + reg logical_op__sv_pred_dz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__sv_pred_dz$100 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input \logical_op__sv_pred_dz$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__sv_pred_dz$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output logical_op__sv_pred_sz; + reg logical_op__sv_pred_sz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input \logical_op__sv_pred_sz$20 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__sv_pred_sz$99 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \logical_op__sv_pred_sz$next ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] logical_op__sv_saturate; + reg [1:0] logical_op__sv_saturate = 2'h0; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \logical_op__sv_saturate$101 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] \logical_op__sv_saturate$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \logical_op__sv_saturate$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output logical_op__write_cr0; reg logical_op__write_cr0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \logical_op__write_cr0$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__write_cr0$81 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__write_cr0$93 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__write_cr0$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output logical_op__zero_a; reg logical_op__zero_a = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input \logical_op__zero_a$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \logical_op__zero_a$78 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \logical_op__zero_a$90 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \logical_op__zero_a$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] muxid; @@ -175723,7 +189065,7 @@ module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_ty (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] \muxid$1 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \muxid$68 ; + wire [1:0] \muxid$80 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) reg [1:0] \muxid$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *) @@ -175736,7 +189078,7 @@ module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_ty output [1:0] operation; reg [1:0] operation = 2'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" *) - wire [1:0] \operation$99 ; + wire [1:0] \operation$115 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" *) reg [1:0] \operation$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) @@ -175744,34 +189086,34 @@ module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_ty (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) input p_valid_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *) - wire \p_valid_i$65 ; + wire \p_valid_i$77 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *) wire p_valid_i_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg r_busy = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *) reg \r_busy$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) output [63:0] ra; reg [63:0] ra = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - input [63:0] \ra$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \ra$87 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \ra$88 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \ra$103 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \ra$104 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + input [63:0] \ra$24 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) reg [63:0] \ra$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) output [63:0] rb; reg [63:0] rb = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - input [63:0] \rb$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \rb$89 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [63:0] \rb$90 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \rb$105 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \rb$106 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + input [63:0] \rb$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) reg [63:0] \rb$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) wire setup_stage_div_by_zero; @@ -175787,68 +189129,82 @@ module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_ty wire setup_stage_divisor_neg; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *) wire [63:0] setup_stage_divisor_radicand; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] setup_stage_logical_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \setup_stage_logical_op__SV_Ptype$75 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [3:0] setup_stage_logical_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [3:0] \setup_stage_logical_op__data_len$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [3:0] \setup_stage_logical_op__data_len$70 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] setup_stage_logical_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] setup_stage_logical_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [13:0] \setup_stage_logical_op__fn_unit$47 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [14:0] \setup_stage_logical_op__fn_unit$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [63:0] setup_stage_logical_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [63:0] \setup_stage_logical_op__imm_data__data$48 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [63:0] \setup_stage_logical_op__imm_data__data$56 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire setup_stage_logical_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \setup_stage_logical_op__imm_data__ok$49 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \setup_stage_logical_op__imm_data__ok$57 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [1:0] setup_stage_logical_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [1:0] \setup_stage_logical_op__input_carry$56 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \setup_stage_logical_op__input_carry$64 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [31:0] setup_stage_logical_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [31:0] \setup_stage_logical_op__insn$63 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [31:0] \setup_stage_logical_op__insn$71 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) (* enum_value_0000001 = "OP_NOP" *) @@ -175924,7 +189280,9 @@ module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_ty (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [6:0] setup_stage_logical_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -176001,76 +189359,98 @@ module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_ty (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire [6:0] \setup_stage_logical_op__insn_type$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [6:0] \setup_stage_logical_op__insn_type$54 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire setup_stage_logical_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \setup_stage_logical_op__invert_in$54 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \setup_stage_logical_op__invert_in$62 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire setup_stage_logical_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \setup_stage_logical_op__invert_out$57 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \setup_stage_logical_op__invert_out$65 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire setup_stage_logical_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \setup_stage_logical_op__is_32bit$60 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \setup_stage_logical_op__is_32bit$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire setup_stage_logical_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \setup_stage_logical_op__is_signed$61 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \setup_stage_logical_op__is_signed$69 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire setup_stage_logical_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \setup_stage_logical_op__oe__oe$52 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \setup_stage_logical_op__oe__oe$60 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire setup_stage_logical_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \setup_stage_logical_op__oe__ok$53 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \setup_stage_logical_op__oe__ok$61 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire setup_stage_logical_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \setup_stage_logical_op__output_carry$59 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \setup_stage_logical_op__output_carry$67 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire setup_stage_logical_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \setup_stage_logical_op__rc__ok$51 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \setup_stage_logical_op__rc__ok$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire setup_stage_logical_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \setup_stage_logical_op__rc__rc$50 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \setup_stage_logical_op__rc__rc$58 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire setup_stage_logical_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \setup_stage_logical_op__sv_pred_dz$73 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire setup_stage_logical_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \setup_stage_logical_op__sv_pred_sz$72 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] setup_stage_logical_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire [1:0] \setup_stage_logical_op__sv_saturate$74 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire setup_stage_logical_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \setup_stage_logical_op__write_cr0$58 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \setup_stage_logical_op__write_cr0$66 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire setup_stage_logical_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - wire \setup_stage_logical_op__zero_a$55 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + wire \setup_stage_logical_op__zero_a$63 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) wire [1:0] setup_stage_muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) - wire [1:0] \setup_stage_muxid$45 ; + wire [1:0] \setup_stage_muxid$53 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" *) wire [1:0] setup_stage_operation; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] setup_stage_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] setup_stage_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire setup_stage_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire \setup_stage_xer_so$64 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire \setup_stage_xer_so$76 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) output xer_so; reg xer_so = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - input \xer_so$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire \xer_so$91 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire \xer_so$107 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + input \xer_so$26 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) reg \xer_so$next ; - assign \$66 = \p_valid_i$65 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; + assign \$78 = \p_valid_i$77 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o; always @(posedge coresync_clk) operation <= \operation$next ; always @(posedge coresync_clk) @@ -176129,55 +189509,71 @@ module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_ty logical_op__data_len <= \logical_op__data_len$next ; always @(posedge coresync_clk) logical_op__insn <= \logical_op__insn$next ; + always @(posedge coresync_clk) + logical_op__sv_pred_sz <= \logical_op__sv_pred_sz$next ; + always @(posedge coresync_clk) + logical_op__sv_pred_dz <= \logical_op__sv_pred_dz$next ; + always @(posedge coresync_clk) + logical_op__sv_saturate <= \logical_op__sv_saturate$next ; + always @(posedge coresync_clk) + logical_op__SV_Ptype <= \logical_op__SV_Ptype$next ; always @(posedge coresync_clk) muxid <= \muxid$next ; always @(posedge coresync_clk) r_busy <= \r_busy$next ; \input$78 \input ( + .logical_op__SV_Ptype(input_logical_op__SV_Ptype), + .\logical_op__SV_Ptype$23 (\input_logical_op__SV_Ptype$49 ), .logical_op__data_len(input_logical_op__data_len), - .\logical_op__data_len$18 (\input_logical_op__data_len$40 ), + .\logical_op__data_len$18 (\input_logical_op__data_len$44 ), .logical_op__fn_unit(input_logical_op__fn_unit), - .\logical_op__fn_unit$3 (\input_logical_op__fn_unit$25 ), + .\logical_op__fn_unit$3 (\input_logical_op__fn_unit$29 ), .logical_op__imm_data__data(input_logical_op__imm_data__data), - .\logical_op__imm_data__data$4 (\input_logical_op__imm_data__data$26 ), + .\logical_op__imm_data__data$4 (\input_logical_op__imm_data__data$30 ), .logical_op__imm_data__ok(input_logical_op__imm_data__ok), - .\logical_op__imm_data__ok$5 (\input_logical_op__imm_data__ok$27 ), + .\logical_op__imm_data__ok$5 (\input_logical_op__imm_data__ok$31 ), .logical_op__input_carry(input_logical_op__input_carry), - .\logical_op__input_carry$12 (\input_logical_op__input_carry$34 ), + .\logical_op__input_carry$12 (\input_logical_op__input_carry$38 ), .logical_op__insn(input_logical_op__insn), - .\logical_op__insn$19 (\input_logical_op__insn$41 ), + .\logical_op__insn$19 (\input_logical_op__insn$45 ), .logical_op__insn_type(input_logical_op__insn_type), - .\logical_op__insn_type$2 (\input_logical_op__insn_type$24 ), + .\logical_op__insn_type$2 (\input_logical_op__insn_type$28 ), .logical_op__invert_in(input_logical_op__invert_in), - .\logical_op__invert_in$10 (\input_logical_op__invert_in$32 ), + .\logical_op__invert_in$10 (\input_logical_op__invert_in$36 ), .logical_op__invert_out(input_logical_op__invert_out), - .\logical_op__invert_out$13 (\input_logical_op__invert_out$35 ), + .\logical_op__invert_out$13 (\input_logical_op__invert_out$39 ), .logical_op__is_32bit(input_logical_op__is_32bit), - .\logical_op__is_32bit$16 (\input_logical_op__is_32bit$38 ), + .\logical_op__is_32bit$16 (\input_logical_op__is_32bit$42 ), .logical_op__is_signed(input_logical_op__is_signed), - .\logical_op__is_signed$17 (\input_logical_op__is_signed$39 ), + .\logical_op__is_signed$17 (\input_logical_op__is_signed$43 ), .logical_op__oe__oe(input_logical_op__oe__oe), - .\logical_op__oe__oe$8 (\input_logical_op__oe__oe$30 ), + .\logical_op__oe__oe$8 (\input_logical_op__oe__oe$34 ), .logical_op__oe__ok(input_logical_op__oe__ok), - .\logical_op__oe__ok$9 (\input_logical_op__oe__ok$31 ), + .\logical_op__oe__ok$9 (\input_logical_op__oe__ok$35 ), .logical_op__output_carry(input_logical_op__output_carry), - .\logical_op__output_carry$15 (\input_logical_op__output_carry$37 ), + .\logical_op__output_carry$15 (\input_logical_op__output_carry$41 ), .logical_op__rc__ok(input_logical_op__rc__ok), - .\logical_op__rc__ok$7 (\input_logical_op__rc__ok$29 ), + .\logical_op__rc__ok$7 (\input_logical_op__rc__ok$33 ), .logical_op__rc__rc(input_logical_op__rc__rc), - .\logical_op__rc__rc$6 (\input_logical_op__rc__rc$28 ), + .\logical_op__rc__rc$6 (\input_logical_op__rc__rc$32 ), + .logical_op__sv_pred_dz(input_logical_op__sv_pred_dz), + .\logical_op__sv_pred_dz$21 (\input_logical_op__sv_pred_dz$47 ), + .logical_op__sv_pred_sz(input_logical_op__sv_pred_sz), + .\logical_op__sv_pred_sz$20 (\input_logical_op__sv_pred_sz$46 ), + .logical_op__sv_saturate(input_logical_op__sv_saturate), + .\logical_op__sv_saturate$22 (\input_logical_op__sv_saturate$48 ), .logical_op__write_cr0(input_logical_op__write_cr0), - .\logical_op__write_cr0$14 (\input_logical_op__write_cr0$36 ), + .\logical_op__write_cr0$14 (\input_logical_op__write_cr0$40 ), .logical_op__zero_a(input_logical_op__zero_a), - .\logical_op__zero_a$11 (\input_logical_op__zero_a$33 ), + .\logical_op__zero_a$11 (\input_logical_op__zero_a$37 ), .muxid(input_muxid), - .\muxid$1 (\input_muxid$23 ), + .\muxid$1 (\input_muxid$27 ), .ra(input_ra), - .\ra$20 (\input_ra$42 ), + .\ra$24 (\input_ra$50 ), .rb(input_rb), - .\rb$21 (\input_rb$43 ), + .\rb$25 (\input_rb$51 ), .xer_so(input_xer_so), - .\xer_so$22 (\input_xer_so$44 ) + .\xer_so$26 (\input_xer_so$52 ) ); \n$77 n ( .n_ready_i(n_ready_i), @@ -176195,50 +189591,97 @@ module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_ty .dividend_neg(setup_stage_dividend_neg), .divisor_neg(setup_stage_divisor_neg), .divisor_radicand(setup_stage_divisor_radicand), + .logical_op__SV_Ptype(setup_stage_logical_op__SV_Ptype), + .\logical_op__SV_Ptype$23 (\setup_stage_logical_op__SV_Ptype$75 ), .logical_op__data_len(setup_stage_logical_op__data_len), - .\logical_op__data_len$18 (\setup_stage_logical_op__data_len$62 ), + .\logical_op__data_len$18 (\setup_stage_logical_op__data_len$70 ), .logical_op__fn_unit(setup_stage_logical_op__fn_unit), - .\logical_op__fn_unit$3 (\setup_stage_logical_op__fn_unit$47 ), + .\logical_op__fn_unit$3 (\setup_stage_logical_op__fn_unit$55 ), .logical_op__imm_data__data(setup_stage_logical_op__imm_data__data), - .\logical_op__imm_data__data$4 (\setup_stage_logical_op__imm_data__data$48 ), + .\logical_op__imm_data__data$4 (\setup_stage_logical_op__imm_data__data$56 ), .logical_op__imm_data__ok(setup_stage_logical_op__imm_data__ok), - .\logical_op__imm_data__ok$5 (\setup_stage_logical_op__imm_data__ok$49 ), + .\logical_op__imm_data__ok$5 (\setup_stage_logical_op__imm_data__ok$57 ), .logical_op__input_carry(setup_stage_logical_op__input_carry), - .\logical_op__input_carry$12 (\setup_stage_logical_op__input_carry$56 ), + .\logical_op__input_carry$12 (\setup_stage_logical_op__input_carry$64 ), .logical_op__insn(setup_stage_logical_op__insn), - .\logical_op__insn$19 (\setup_stage_logical_op__insn$63 ), + .\logical_op__insn$19 (\setup_stage_logical_op__insn$71 ), .logical_op__insn_type(setup_stage_logical_op__insn_type), - .\logical_op__insn_type$2 (\setup_stage_logical_op__insn_type$46 ), + .\logical_op__insn_type$2 (\setup_stage_logical_op__insn_type$54 ), .logical_op__invert_in(setup_stage_logical_op__invert_in), - .\logical_op__invert_in$10 (\setup_stage_logical_op__invert_in$54 ), + .\logical_op__invert_in$10 (\setup_stage_logical_op__invert_in$62 ), .logical_op__invert_out(setup_stage_logical_op__invert_out), - .\logical_op__invert_out$13 (\setup_stage_logical_op__invert_out$57 ), + .\logical_op__invert_out$13 (\setup_stage_logical_op__invert_out$65 ), .logical_op__is_32bit(setup_stage_logical_op__is_32bit), - .\logical_op__is_32bit$16 (\setup_stage_logical_op__is_32bit$60 ), + .\logical_op__is_32bit$16 (\setup_stage_logical_op__is_32bit$68 ), .logical_op__is_signed(setup_stage_logical_op__is_signed), - .\logical_op__is_signed$17 (\setup_stage_logical_op__is_signed$61 ), + .\logical_op__is_signed$17 (\setup_stage_logical_op__is_signed$69 ), .logical_op__oe__oe(setup_stage_logical_op__oe__oe), - .\logical_op__oe__oe$8 (\setup_stage_logical_op__oe__oe$52 ), + .\logical_op__oe__oe$8 (\setup_stage_logical_op__oe__oe$60 ), .logical_op__oe__ok(setup_stage_logical_op__oe__ok), - .\logical_op__oe__ok$9 (\setup_stage_logical_op__oe__ok$53 ), + .\logical_op__oe__ok$9 (\setup_stage_logical_op__oe__ok$61 ), .logical_op__output_carry(setup_stage_logical_op__output_carry), - .\logical_op__output_carry$15 (\setup_stage_logical_op__output_carry$59 ), + .\logical_op__output_carry$15 (\setup_stage_logical_op__output_carry$67 ), .logical_op__rc__ok(setup_stage_logical_op__rc__ok), - .\logical_op__rc__ok$7 (\setup_stage_logical_op__rc__ok$51 ), + .\logical_op__rc__ok$7 (\setup_stage_logical_op__rc__ok$59 ), .logical_op__rc__rc(setup_stage_logical_op__rc__rc), - .\logical_op__rc__rc$6 (\setup_stage_logical_op__rc__rc$50 ), + .\logical_op__rc__rc$6 (\setup_stage_logical_op__rc__rc$58 ), + .logical_op__sv_pred_dz(setup_stage_logical_op__sv_pred_dz), + .\logical_op__sv_pred_dz$21 (\setup_stage_logical_op__sv_pred_dz$73 ), + .logical_op__sv_pred_sz(setup_stage_logical_op__sv_pred_sz), + .\logical_op__sv_pred_sz$20 (\setup_stage_logical_op__sv_pred_sz$72 ), + .logical_op__sv_saturate(setup_stage_logical_op__sv_saturate), + .\logical_op__sv_saturate$22 (\setup_stage_logical_op__sv_saturate$74 ), .logical_op__write_cr0(setup_stage_logical_op__write_cr0), - .\logical_op__write_cr0$14 (\setup_stage_logical_op__write_cr0$58 ), + .\logical_op__write_cr0$14 (\setup_stage_logical_op__write_cr0$66 ), .logical_op__zero_a(setup_stage_logical_op__zero_a), - .\logical_op__zero_a$11 (\setup_stage_logical_op__zero_a$55 ), + .\logical_op__zero_a$11 (\setup_stage_logical_op__zero_a$63 ), .muxid(setup_stage_muxid), - .\muxid$1 (\setup_stage_muxid$45 ), + .\muxid$1 (\setup_stage_muxid$53 ), .operation(setup_stage_operation), .ra(setup_stage_ra), .rb(setup_stage_rb), .xer_so(setup_stage_xer_so), - .\xer_so$20 (\setup_stage_xer_so$64 ) + .\xer_so$24 (\setup_stage_xer_so$76 ) ); + always @* begin + if (\initial ) begin end + \ra$next = ra; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \ra$next = \ra$103 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \ra$next = \ra$103 ; + endcase + end + always @* begin + if (\initial ) begin end + \rb$next = rb; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \rb$next = \rb$105 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \rb$next = \rb$105 ; + endcase + end + always @* begin + if (\initial ) begin end + \xer_so$next = xer_so; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) + casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ + 2'b?1: + \xer_so$next = \xer_so$107 ; + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ + 2'b1?: + \xer_so$next = \xer_so$107 ; + endcase + end always @* begin if (\initial ) begin end \divisor_neg$next = divisor_neg; @@ -176246,10 +189689,10 @@ module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_ty casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \divisor_neg$next = \divisor_neg$92 ; + \divisor_neg$next = \divisor_neg$108 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \divisor_neg$next = \divisor_neg$92 ; + \divisor_neg$next = \divisor_neg$108 ; endcase end always @* begin @@ -176259,10 +189702,10 @@ module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_ty casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \dividend_neg$next = \dividend_neg$93 ; + \dividend_neg$next = \dividend_neg$109 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \dividend_neg$next = \dividend_neg$93 ; + \dividend_neg$next = \dividend_neg$109 ; endcase end always @* begin @@ -176272,10 +189715,10 @@ module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_ty casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \dive_abs_ov32$next = \dive_abs_ov32$94 ; + \dive_abs_ov32$next = \dive_abs_ov32$110 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \dive_abs_ov32$next = \dive_abs_ov32$94 ; + \dive_abs_ov32$next = \dive_abs_ov32$110 ; endcase end always @* begin @@ -176285,10 +189728,10 @@ module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_ty casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \dive_abs_ov64$next = \dive_abs_ov64$95 ; + \dive_abs_ov64$next = \dive_abs_ov64$111 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \dive_abs_ov64$next = \dive_abs_ov64$95 ; + \dive_abs_ov64$next = \dive_abs_ov64$111 ; endcase end always @* begin @@ -176298,10 +189741,10 @@ module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_ty casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \div_by_zero$next = \div_by_zero$96 ; + \div_by_zero$next = \div_by_zero$112 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \div_by_zero$next = \div_by_zero$96 ; + \div_by_zero$next = \div_by_zero$112 ; endcase end always @* begin @@ -176311,10 +189754,10 @@ module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_ty casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \dividend$next = \dividend$97 ; + \dividend$next = \dividend$113 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \dividend$next = \dividend$97 ; + \dividend$next = \dividend$113 ; endcase end always @* begin @@ -176324,10 +189767,10 @@ module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_ty casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \divisor_radicand$next = \divisor_radicand$98 ; + \divisor_radicand$next = \divisor_radicand$114 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \divisor_radicand$next = \divisor_radicand$98 ; + \divisor_radicand$next = \divisor_radicand$114 ; endcase end always @* begin @@ -176337,10 +189780,10 @@ module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_ty casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \operation$next = \operation$99 ; + \operation$next = \operation$115 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \operation$next = \operation$99 ; + \operation$next = \operation$115 ; endcase end always @* begin @@ -176355,7 +189798,7 @@ module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_ty 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -176368,10 +189811,10 @@ module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_ty casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - \muxid$next = \muxid$68 ; + \muxid$next = \muxid$80 ; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - \muxid$next = \muxid$68 ; + \muxid$next = \muxid$80 ; endcase end always @* begin @@ -176394,16 +189837,20 @@ module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_ty \logical_op__is_signed$next = logical_op__is_signed; \logical_op__data_len$next = logical_op__data_len; \logical_op__insn$next = logical_op__insn; + \logical_op__sv_pred_sz$next = logical_op__sv_pred_sz; + \logical_op__sv_pred_dz$next = logical_op__sv_pred_dz; + \logical_op__sv_saturate$next = logical_op__sv_saturate; + \logical_op__SV_Ptype$next = logical_op__SV_Ptype; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ 2'b?1: - { \logical_op__insn$next , \logical_op__data_len$next , \logical_op__is_signed$next , \logical_op__is_32bit$next , \logical_op__output_carry$next , \logical_op__write_cr0$next , \logical_op__invert_out$next , \logical_op__input_carry$next , \logical_op__zero_a$next , \logical_op__invert_in$next , \logical_op__oe__ok$next , \logical_op__oe__oe$next , \logical_op__rc__ok$next , \logical_op__rc__rc$next , \logical_op__imm_data__ok$next , \logical_op__imm_data__data$next , \logical_op__fn_unit$next , \logical_op__insn_type$next } = { \logical_op__insn$86 , \logical_op__data_len$85 , \logical_op__is_signed$84 , \logical_op__is_32bit$83 , \logical_op__output_carry$82 , \logical_op__write_cr0$81 , \logical_op__invert_out$80 , \logical_op__input_carry$79 , \logical_op__zero_a$78 , \logical_op__invert_in$77 , \logical_op__oe__ok$76 , \logical_op__oe__oe$75 , \logical_op__rc__ok$74 , \logical_op__rc__rc$73 , \logical_op__imm_data__ok$72 , \logical_op__imm_data__data$71 , \logical_op__fn_unit$70 , \logical_op__insn_type$69 }; + { \logical_op__SV_Ptype$next , \logical_op__sv_saturate$next , \logical_op__sv_pred_dz$next , \logical_op__sv_pred_sz$next , \logical_op__insn$next , \logical_op__data_len$next , \logical_op__is_signed$next , \logical_op__is_32bit$next , \logical_op__output_carry$next , \logical_op__write_cr0$next , \logical_op__invert_out$next , \logical_op__input_carry$next , \logical_op__zero_a$next , \logical_op__invert_in$next , \logical_op__oe__ok$next , \logical_op__oe__oe$next , \logical_op__rc__ok$next , \logical_op__rc__rc$next , \logical_op__imm_data__ok$next , \logical_op__imm_data__data$next , \logical_op__fn_unit$next , \logical_op__insn_type$next } = { \logical_op__SV_Ptype$102 , \logical_op__sv_saturate$101 , \logical_op__sv_pred_dz$100 , \logical_op__sv_pred_sz$99 , \logical_op__insn$98 , \logical_op__data_len$97 , \logical_op__is_signed$96 , \logical_op__is_32bit$95 , \logical_op__output_carry$94 , \logical_op__write_cr0$93 , \logical_op__invert_out$92 , \logical_op__input_carry$91 , \logical_op__zero_a$90 , \logical_op__invert_in$89 , \logical_op__oe__ok$88 , \logical_op__oe__oe$87 , \logical_op__rc__ok$86 , \logical_op__rc__rc$85 , \logical_op__imm_data__ok$84 , \logical_op__imm_data__data$83 , \logical_op__fn_unit$82 , \logical_op__insn_type$81 }; /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ 2'b1?: - { \logical_op__insn$next , \logical_op__data_len$next , \logical_op__is_signed$next , \logical_op__is_32bit$next , \logical_op__output_carry$next , \logical_op__write_cr0$next , \logical_op__invert_out$next , \logical_op__input_carry$next , \logical_op__zero_a$next , \logical_op__invert_in$next , \logical_op__oe__ok$next , \logical_op__oe__oe$next , \logical_op__rc__ok$next , \logical_op__rc__rc$next , \logical_op__imm_data__ok$next , \logical_op__imm_data__data$next , \logical_op__fn_unit$next , \logical_op__insn_type$next } = { \logical_op__insn$86 , \logical_op__data_len$85 , \logical_op__is_signed$84 , \logical_op__is_32bit$83 , \logical_op__output_carry$82 , \logical_op__write_cr0$81 , \logical_op__invert_out$80 , \logical_op__input_carry$79 , \logical_op__zero_a$78 , \logical_op__invert_in$77 , \logical_op__oe__ok$76 , \logical_op__oe__oe$75 , \logical_op__rc__ok$74 , \logical_op__rc__rc$73 , \logical_op__imm_data__ok$72 , \logical_op__imm_data__data$71 , \logical_op__fn_unit$70 , \logical_op__insn_type$69 }; + { \logical_op__SV_Ptype$next , \logical_op__sv_saturate$next , \logical_op__sv_pred_dz$next , \logical_op__sv_pred_sz$next , \logical_op__insn$next , \logical_op__data_len$next , \logical_op__is_signed$next , \logical_op__is_32bit$next , \logical_op__output_carry$next , \logical_op__write_cr0$next , \logical_op__invert_out$next , \logical_op__input_carry$next , \logical_op__zero_a$next , \logical_op__invert_in$next , \logical_op__oe__ok$next , \logical_op__oe__oe$next , \logical_op__rc__ok$next , \logical_op__rc__rc$next , \logical_op__imm_data__ok$next , \logical_op__imm_data__data$next , \logical_op__fn_unit$next , \logical_op__insn_type$next } = { \logical_op__SV_Ptype$102 , \logical_op__sv_saturate$101 , \logical_op__sv_pred_dz$100 , \logical_op__sv_pred_sz$99 , \logical_op__insn$98 , \logical_op__data_len$97 , \logical_op__is_signed$96 , \logical_op__is_32bit$95 , \logical_op__output_carry$94 , \logical_op__write_cr0$93 , \logical_op__invert_out$92 , \logical_op__input_carry$91 , \logical_op__zero_a$90 , \logical_op__invert_in$89 , \logical_op__oe__ok$88 , \logical_op__oe__oe$87 , \logical_op__rc__ok$86 , \logical_op__rc__rc$85 , \logical_op__imm_data__ok$84 , \logical_op__imm_data__data$83 , \logical_op__fn_unit$82 , \logical_op__insn_type$81 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -176416,139 +189863,38 @@ module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_ty end endcase end - always @* begin - if (\initial ) begin end - \ra$next = ra; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) - casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) - /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ - 2'b?1: - \ra$next = \ra$87 ; - /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ - 2'b1?: - \ra$next = \ra$87 ; - endcase - end - always @* begin - if (\initial ) begin end - \rb$next = rb; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) - casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) - /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ - 2'b?1: - \rb$next = \rb$89 ; - /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ - 2'b1?: - \rb$next = \rb$89 ; - endcase - end - always @* begin - if (\initial ) begin end - \xer_so$next = xer_so; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *) - casez ({ n_i_rdy_data, p_valid_i_p_ready_o }) - /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" */ - 2'b?1: - \xer_so$next = \xer_so$91 ; - /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:642" */ - 2'b1?: - \xer_so$next = \xer_so$91 ; - endcase - end - assign \ra$88 = 64'h0000000000000000; - assign \rb$90 = 64'h0000000000000000; + assign \ra$104 = 64'h0000000000000000; + assign \rb$106 = 64'h0000000000000000; assign p_ready_o = n_i_rdy_data; assign n_valid_o = r_busy; - assign \operation$99 = setup_stage_operation; - assign \divisor_radicand$98 = setup_stage_divisor_radicand; - assign \dividend$97 = setup_stage_dividend; - assign \div_by_zero$96 = setup_stage_div_by_zero; - assign \dive_abs_ov64$95 = setup_stage_dive_abs_ov64; - assign \dive_abs_ov32$94 = setup_stage_dive_abs_ov32; - assign \dividend_neg$93 = setup_stage_dividend_neg; - assign \divisor_neg$92 = setup_stage_divisor_neg; - assign \xer_so$91 = \setup_stage_xer_so$64 ; - assign \rb$89 = 64'h0000000000000000; - assign \ra$87 = 64'h0000000000000000; - assign { \logical_op__insn$86 , \logical_op__data_len$85 , \logical_op__is_signed$84 , \logical_op__is_32bit$83 , \logical_op__output_carry$82 , \logical_op__write_cr0$81 , \logical_op__invert_out$80 , \logical_op__input_carry$79 , \logical_op__zero_a$78 , \logical_op__invert_in$77 , \logical_op__oe__ok$76 , \logical_op__oe__oe$75 , \logical_op__rc__ok$74 , \logical_op__rc__rc$73 , \logical_op__imm_data__ok$72 , \logical_op__imm_data__data$71 , \logical_op__fn_unit$70 , \logical_op__insn_type$69 } = { \setup_stage_logical_op__insn$63 , \setup_stage_logical_op__data_len$62 , \setup_stage_logical_op__is_signed$61 , \setup_stage_logical_op__is_32bit$60 , \setup_stage_logical_op__output_carry$59 , \setup_stage_logical_op__write_cr0$58 , \setup_stage_logical_op__invert_out$57 , \setup_stage_logical_op__input_carry$56 , \setup_stage_logical_op__zero_a$55 , \setup_stage_logical_op__invert_in$54 , \setup_stage_logical_op__oe__ok$53 , \setup_stage_logical_op__oe__oe$52 , \setup_stage_logical_op__rc__ok$51 , \setup_stage_logical_op__rc__rc$50 , \setup_stage_logical_op__imm_data__ok$49 , \setup_stage_logical_op__imm_data__data$48 , \setup_stage_logical_op__fn_unit$47 , \setup_stage_logical_op__insn_type$46 }; - assign \muxid$68 = \setup_stage_muxid$45 ; - assign p_valid_i_p_ready_o = \$66 ; + assign \operation$115 = setup_stage_operation; + assign \divisor_radicand$114 = setup_stage_divisor_radicand; + assign \dividend$113 = setup_stage_dividend; + assign \div_by_zero$112 = setup_stage_div_by_zero; + assign \dive_abs_ov64$111 = setup_stage_dive_abs_ov64; + assign \dive_abs_ov32$110 = setup_stage_dive_abs_ov32; + assign \dividend_neg$109 = setup_stage_dividend_neg; + assign \divisor_neg$108 = setup_stage_divisor_neg; + assign \xer_so$107 = \setup_stage_xer_so$76 ; + assign \rb$105 = 64'h0000000000000000; + assign \ra$103 = 64'h0000000000000000; + assign { \logical_op__SV_Ptype$102 , \logical_op__sv_saturate$101 , \logical_op__sv_pred_dz$100 , \logical_op__sv_pred_sz$99 , \logical_op__insn$98 , \logical_op__data_len$97 , \logical_op__is_signed$96 , \logical_op__is_32bit$95 , \logical_op__output_carry$94 , \logical_op__write_cr0$93 , \logical_op__invert_out$92 , \logical_op__input_carry$91 , \logical_op__zero_a$90 , \logical_op__invert_in$89 , \logical_op__oe__ok$88 , \logical_op__oe__oe$87 , \logical_op__rc__ok$86 , \logical_op__rc__rc$85 , \logical_op__imm_data__ok$84 , \logical_op__imm_data__data$83 , \logical_op__fn_unit$82 , \logical_op__insn_type$81 } = { \setup_stage_logical_op__SV_Ptype$75 , \setup_stage_logical_op__sv_saturate$74 , \setup_stage_logical_op__sv_pred_dz$73 , \setup_stage_logical_op__sv_pred_sz$72 , \setup_stage_logical_op__insn$71 , \setup_stage_logical_op__data_len$70 , \setup_stage_logical_op__is_signed$69 , \setup_stage_logical_op__is_32bit$68 , \setup_stage_logical_op__output_carry$67 , \setup_stage_logical_op__write_cr0$66 , \setup_stage_logical_op__invert_out$65 , \setup_stage_logical_op__input_carry$64 , \setup_stage_logical_op__zero_a$63 , \setup_stage_logical_op__invert_in$62 , \setup_stage_logical_op__oe__ok$61 , \setup_stage_logical_op__oe__oe$60 , \setup_stage_logical_op__rc__ok$59 , \setup_stage_logical_op__rc__rc$58 , \setup_stage_logical_op__imm_data__ok$57 , \setup_stage_logical_op__imm_data__data$56 , \setup_stage_logical_op__fn_unit$55 , \setup_stage_logical_op__insn_type$54 }; + assign \muxid$80 = \setup_stage_muxid$53 ; + assign p_valid_i_p_ready_o = \$78 ; assign n_i_rdy_data = n_ready_i; - assign \p_valid_i$65 = p_valid_i; - assign setup_stage_xer_so = \input_xer_so$44 ; - assign setup_stage_rb = \input_rb$43 ; - assign setup_stage_ra = \input_ra$42 ; - assign { setup_stage_logical_op__insn, setup_stage_logical_op__data_len, setup_stage_logical_op__is_signed, setup_stage_logical_op__is_32bit, setup_stage_logical_op__output_carry, setup_stage_logical_op__write_cr0, setup_stage_logical_op__invert_out, setup_stage_logical_op__input_carry, setup_stage_logical_op__zero_a, setup_stage_logical_op__invert_in, setup_stage_logical_op__oe__ok, setup_stage_logical_op__oe__oe, setup_stage_logical_op__rc__ok, setup_stage_logical_op__rc__rc, setup_stage_logical_op__imm_data__ok, setup_stage_logical_op__imm_data__data, setup_stage_logical_op__fn_unit, setup_stage_logical_op__insn_type } = { \input_logical_op__insn$41 , \input_logical_op__data_len$40 , \input_logical_op__is_signed$39 , \input_logical_op__is_32bit$38 , \input_logical_op__output_carry$37 , \input_logical_op__write_cr0$36 , \input_logical_op__invert_out$35 , \input_logical_op__input_carry$34 , \input_logical_op__zero_a$33 , \input_logical_op__invert_in$32 , \input_logical_op__oe__ok$31 , \input_logical_op__oe__oe$30 , \input_logical_op__rc__ok$29 , \input_logical_op__rc__rc$28 , \input_logical_op__imm_data__ok$27 , \input_logical_op__imm_data__data$26 , \input_logical_op__fn_unit$25 , \input_logical_op__insn_type$24 }; - assign setup_stage_muxid = \input_muxid$23 ; - assign input_xer_so = \xer_so$22 ; - assign input_rb = \rb$21 ; - assign input_ra = \ra$20 ; - assign { input_logical_op__insn, input_logical_op__data_len, input_logical_op__is_signed, input_logical_op__is_32bit, input_logical_op__output_carry, input_logical_op__write_cr0, input_logical_op__invert_out, input_logical_op__input_carry, input_logical_op__zero_a, input_logical_op__invert_in, input_logical_op__oe__ok, input_logical_op__oe__oe, input_logical_op__rc__ok, input_logical_op__rc__rc, input_logical_op__imm_data__ok, input_logical_op__imm_data__data, input_logical_op__fn_unit, input_logical_op__insn_type } = { \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 }; + assign \p_valid_i$77 = p_valid_i; + assign setup_stage_xer_so = \input_xer_so$52 ; + assign setup_stage_rb = \input_rb$51 ; + assign setup_stage_ra = \input_ra$50 ; + assign { setup_stage_logical_op__SV_Ptype, setup_stage_logical_op__sv_saturate, setup_stage_logical_op__sv_pred_dz, setup_stage_logical_op__sv_pred_sz, setup_stage_logical_op__insn, setup_stage_logical_op__data_len, setup_stage_logical_op__is_signed, setup_stage_logical_op__is_32bit, setup_stage_logical_op__output_carry, setup_stage_logical_op__write_cr0, setup_stage_logical_op__invert_out, setup_stage_logical_op__input_carry, setup_stage_logical_op__zero_a, setup_stage_logical_op__invert_in, setup_stage_logical_op__oe__ok, setup_stage_logical_op__oe__oe, setup_stage_logical_op__rc__ok, setup_stage_logical_op__rc__rc, setup_stage_logical_op__imm_data__ok, setup_stage_logical_op__imm_data__data, setup_stage_logical_op__fn_unit, setup_stage_logical_op__insn_type } = { \input_logical_op__SV_Ptype$49 , \input_logical_op__sv_saturate$48 , \input_logical_op__sv_pred_dz$47 , \input_logical_op__sv_pred_sz$46 , \input_logical_op__insn$45 , \input_logical_op__data_len$44 , \input_logical_op__is_signed$43 , \input_logical_op__is_32bit$42 , \input_logical_op__output_carry$41 , \input_logical_op__write_cr0$40 , \input_logical_op__invert_out$39 , \input_logical_op__input_carry$38 , \input_logical_op__zero_a$37 , \input_logical_op__invert_in$36 , \input_logical_op__oe__ok$35 , \input_logical_op__oe__oe$34 , \input_logical_op__rc__ok$33 , \input_logical_op__rc__rc$32 , \input_logical_op__imm_data__ok$31 , \input_logical_op__imm_data__data$30 , \input_logical_op__fn_unit$29 , \input_logical_op__insn_type$28 }; + assign setup_stage_muxid = \input_muxid$27 ; + assign input_xer_so = \xer_so$26 ; + assign input_rb = \rb$25 ; + assign input_ra = \ra$24 ; + assign { input_logical_op__SV_Ptype, input_logical_op__sv_saturate, input_logical_op__sv_pred_dz, input_logical_op__sv_pred_sz, input_logical_op__insn, input_logical_op__data_len, input_logical_op__is_signed, input_logical_op__is_32bit, input_logical_op__output_carry, input_logical_op__write_cr0, input_logical_op__invert_out, input_logical_op__input_carry, input_logical_op__zero_a, input_logical_op__invert_in, input_logical_op__oe__ok, input_logical_op__oe__oe, input_logical_op__rc__ok, input_logical_op__rc__rc, input_logical_op__imm_data__ok, input_logical_op__imm_data__data, input_logical_op__fn_unit, input_logical_op__insn_type } = { \logical_op__SV_Ptype$23 , \logical_op__sv_saturate$22 , \logical_op__sv_pred_dz$21 , \logical_op__sv_pred_sz$20 , \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 }; assign input_muxid = \muxid$1 ; endmodule -(* \nmigen.hierarchy = "test_issuer.pll" *) -(* generator = "nMigen" *) -module pll(\ref , div_out_test, a0, a1, vco_test_ana, out); - reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" *) - wire \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" *) - wire \$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:22" *) - wire \$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" *) - wire \$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" *) - wire \$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" *) - wire \$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" *) - wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" *) - input a0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" *) - input a1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" *) - output div_out_test; - reg div_out_test; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" *) - output out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" *) - input \ref ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:14" *) - output vco_test_ana; - reg vco_test_ana; - assign \$9 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" *) a1; - assign \$11 = \$7 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" *) \$9 ; - assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:22" *) \ref ; - assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" *) a0; - assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" *) a1; - assign \$5 = \$1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" *) \$3 ; - assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" *) a0; - always @* begin - if (\initial ) begin end - vco_test_ana = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" *) - casez (\$5 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" */ - 1'h1: - vco_test_ana = \ref ; - endcase - end - always @* begin - if (\initial ) begin end - div_out_test = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" *) - casez (\$11 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" */ - 1'h1: - div_out_test = \$13 ; - endcase - end - assign out = \ref ; -endmodule - (* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.popcount" *) (* generator = "nMigen" *) module popcount(data_len, o, a); @@ -177485,7 +190831,7 @@ endmodule (* generator = "nMigen" *) module rdpick_FAST_fast1(o, en_o, i); (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) - wire [4:0] \$1 ; + wire [5:0] \$1 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) wire \$11 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) @@ -177494,9 +190840,13 @@ module rdpick_FAST_fast1(o, en_o, i); wire \$15 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) wire \$16 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) wire \$19 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$20 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) + wire \$23 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) wire \$3 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) wire \$4 ; @@ -177507,11 +190857,11 @@ module rdpick_FAST_fast1(o, en_o, i); (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) output en_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) - input [4:0] i; + input [5:0] i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *) - wire [4:0] ni; + wire [5:0] ni; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) - output [4:0] o; + output [5:0] o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) wire t0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) @@ -177522,18 +190872,23 @@ module rdpick_FAST_fast1(o, en_o, i); wire t3; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) wire t4; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t5; assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$8 ; assign \$12 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[2:0], ni[3] }; assign \$11 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$12 ; assign \$16 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[3:0], ni[4] }; assign \$15 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$16 ; assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i; - assign \$19 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o; + assign \$20 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[4:0], ni[5] }; + assign \$19 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$20 ; + assign \$23 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o; assign \$4 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[0], ni[1] }; assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$4 ; assign \$8 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[1:0], ni[2] }; - assign en_o = \$19 ; - assign o = { t4, t3, t2, t1, t0 }; + assign en_o = \$23 ; + assign o = { t5, t4, t3, t2, t1, t0 }; + assign t5 = \$19 ; assign t4 = \$15 ; assign t3 = \$11 ; assign t2 = \$7 ; @@ -177906,9 +191261,9 @@ module reg_0(coresync_rst, src10__ren, src10__data_o, src20__ren, src20__data_o, wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] dest10__data_i; @@ -178022,7 +191377,7 @@ module reg_0(coresync_rst, src10__ren, src10__data_o, src20__ren, src20__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src10__data_o$next = 4'h0; @@ -178079,7 +191434,7 @@ module reg_0(coresync_rst, src10__ren, src10__data_o, src20__ren, src20__data_o, 1'h1: \reg$next = w0__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \reg$next = 4'h0; @@ -178119,7 +191474,7 @@ module reg_0(coresync_rst, src10__ren, src10__data_o, src20__ren, src20__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src20__data_o$next = 4'h0; @@ -178189,7 +191544,7 @@ module reg_0(coresync_rst, src10__ren, src10__data_o, src20__ren, src20__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src30__data_o$next = 4'h0; @@ -178259,7 +191614,7 @@ module reg_0(coresync_rst, src10__ren, src10__data_o, src20__ren, src20__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r0__data_o$next = 4'h0; @@ -178329,7 +191684,7 @@ module reg_0(coresync_rst, src10__ren, src10__data_o, src20__ren, src20__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r20__data_o$next = 4'h0; @@ -178379,9 +191734,9 @@ module \reg_0$132 (coresync_rst, src10__ren, src10__data_o, src20__ren, src20__d wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [1:0] dest10__data_i; @@ -178493,7 +191848,7 @@ module \reg_0$132 (coresync_rst, src10__ren, src10__data_o, src20__ren, src20__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src10__data_o$next = 2'h0; @@ -178575,7 +191930,7 @@ module \reg_0$132 (coresync_rst, src10__ren, src10__data_o, src20__ren, src20__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src20__data_o$next = 2'h0; @@ -178657,7 +192012,7 @@ module \reg_0$132 (coresync_rst, src10__ren, src10__data_o, src20__ren, src20__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src30__data_o$next = 2'h0; @@ -178739,7 +192094,7 @@ module \reg_0$132 (coresync_rst, src10__ren, src10__data_o, src20__ren, src20__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r0__data_o$next = 2'h0; @@ -178808,7 +192163,7 @@ module \reg_0$132 (coresync_rst, src10__ren, src10__data_o, src20__ren, src20__d 1'h1: \reg$next = w0__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \reg$next = 2'h0; @@ -178818,7 +192173,7 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.state.reg_0" *) (* generator = "nMigen" *) -module \reg_0$135 (coresync_rst, cia0__ren, cia0__data_o, msr0__ren, msr0__data_o, sv0__ren, sv0__data_o, nia0__wen, nia0__data_i, msr0__wen, msr0__data_i, sv0__wen, sv0__data_i, d_wr10__wen, d_wr10__data_i, coresync_clk); +module \reg_0$135 (coresync_rst, cia0__ren, cia0__data_o, msr0__ren, msr0__data_o, sv0__ren, sv0__data_o, nia0__wen, nia0__data_i, msr0__wen, msr0__data_i, svstate0__wen, svstate0__data_i, sv0__wen, sv0__data_i, d_wr10__wen, d_wr10__data_i, coresync_clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$1 ; @@ -178833,9 +192188,9 @@ module \reg_0$135 (coresync_rst, cia0__ren, cia0__data_o, msr0__ren, msr0__data_ reg [63:0] \cia0__data_o$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input cia0__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [63:0] d_wr10__data_i; @@ -178871,6 +192226,10 @@ module \reg_0$135 (coresync_rst, cia0__ren, cia0__data_o, msr0__ren, msr0__data_ input sv0__ren; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input sv0__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [63:0] svstate0__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input svstate0__wen; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) reg wr_detect; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) @@ -178909,6 +192268,12 @@ module \reg_0$135 (coresync_rst, cia0__ren, cia0__data_o, msr0__ren, msr0__data_ \cia0__data_o$next = msr0__data_i; endcase (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (svstate0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \cia0__data_o$next = svstate0__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) casez (sv0__wen) /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ 1'h1: @@ -178928,7 +192293,7 @@ module \reg_0$135 (coresync_rst, cia0__ren, cia0__data_o, msr0__ren, msr0__data_ endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \cia0__data_o$next = 64'h0000000000000000; @@ -178956,6 +192321,12 @@ module \reg_0$135 (coresync_rst, cia0__ren, cia0__data_o, msr0__ren, msr0__data_ wr_detect = 1'h1; endcase (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (svstate0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) casez (sv0__wen) /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ 1'h1: @@ -178991,6 +192362,12 @@ module \reg_0$135 (coresync_rst, cia0__ren, cia0__data_o, msr0__ren, msr0__data_ \msr0__data_o$next = msr0__data_i; endcase (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (svstate0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \msr0__data_o$next = svstate0__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) casez (sv0__wen) /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ 1'h1: @@ -179010,7 +192387,7 @@ module \reg_0$135 (coresync_rst, cia0__ren, cia0__data_o, msr0__ren, msr0__data_ endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \msr0__data_o$next = 64'h0000000000000000; @@ -179038,6 +192415,12 @@ module \reg_0$135 (coresync_rst, cia0__ren, cia0__data_o, msr0__ren, msr0__data_ \wr_detect$4 = 1'h1; endcase (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (svstate0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) casez (sv0__wen) /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ 1'h1: @@ -179073,6 +192456,12 @@ module \reg_0$135 (coresync_rst, cia0__ren, cia0__data_o, msr0__ren, msr0__data_ \sv0__data_o$next = msr0__data_i; endcase (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (svstate0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \sv0__data_o$next = svstate0__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) casez (sv0__wen) /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ 1'h1: @@ -179092,7 +192481,7 @@ module \reg_0$135 (coresync_rst, cia0__ren, cia0__data_o, msr0__ren, msr0__data_ endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \sv0__data_o$next = 64'h0000000000000000; @@ -179120,6 +192509,12 @@ module \reg_0$135 (coresync_rst, cia0__ren, cia0__data_o, msr0__ren, msr0__data_ \wr_detect$7 = 1'h1; endcase (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (svstate0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) casez (sv0__wen) /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ 1'h1: @@ -179150,6 +192545,12 @@ module \reg_0$135 (coresync_rst, cia0__ren, cia0__data_o, msr0__ren, msr0__data_ \reg$next = msr0__data_i; endcase (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (svstate0__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = svstate0__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) casez (sv0__wen) /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ 1'h1: @@ -179161,7 +192562,7 @@ module \reg_0$135 (coresync_rst, cia0__ren, cia0__data_o, msr0__ren, msr0__data_ 1'h1: \reg$next = d_wr10__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \reg$next = 64'h0000000000000000; @@ -179183,9 +192584,9 @@ module reg_1(coresync_rst, src11__ren, src11__data_o, src21__ren, src21__data_o, wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] dest11__data_i; @@ -179299,7 +192700,7 @@ module reg_1(coresync_rst, src11__ren, src11__data_o, src21__ren, src21__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src11__data_o$next = 4'h0; @@ -179356,7 +192757,7 @@ module reg_1(coresync_rst, src11__ren, src11__data_o, src21__ren, src21__data_o, 1'h1: \reg$next = w1__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \reg$next = 4'h0; @@ -179396,7 +192797,7 @@ module reg_1(coresync_rst, src11__ren, src11__data_o, src21__ren, src21__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src21__data_o$next = 4'h0; @@ -179466,7 +192867,7 @@ module reg_1(coresync_rst, src11__ren, src11__data_o, src21__ren, src21__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src31__data_o$next = 4'h0; @@ -179536,7 +192937,7 @@ module reg_1(coresync_rst, src11__ren, src11__data_o, src21__ren, src21__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r1__data_o$next = 4'h0; @@ -179606,7 +193007,7 @@ module reg_1(coresync_rst, src11__ren, src11__data_o, src21__ren, src21__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r21__data_o$next = 4'h0; @@ -179656,9 +193057,9 @@ module \reg_1$133 (coresync_rst, src11__ren, src11__data_o, src21__ren, src21__d wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [1:0] dest11__data_i; @@ -179770,7 +193171,7 @@ module \reg_1$133 (coresync_rst, src11__ren, src11__data_o, src21__ren, src21__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src11__data_o$next = 2'h0; @@ -179852,7 +193253,7 @@ module \reg_1$133 (coresync_rst, src11__ren, src11__data_o, src21__ren, src21__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src21__data_o$next = 2'h0; @@ -179934,7 +193335,7 @@ module \reg_1$133 (coresync_rst, src11__ren, src11__data_o, src21__ren, src21__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src31__data_o$next = 2'h0; @@ -180016,7 +193417,7 @@ module \reg_1$133 (coresync_rst, src11__ren, src11__data_o, src21__ren, src21__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r1__data_o$next = 2'h0; @@ -180085,7 +193486,7 @@ module \reg_1$133 (coresync_rst, src11__ren, src11__data_o, src21__ren, src21__d 1'h1: \reg$next = w1__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \reg$next = 2'h0; @@ -180095,7 +193496,7 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.state.reg_1" *) (* generator = "nMigen" *) -module \reg_1$136 (coresync_rst, cia1__ren, cia1__data_o, msr1__ren, msr1__data_o, sv1__ren, sv1__data_o, nia1__wen, nia1__data_i, msr1__wen, msr1__data_i, sv1__wen, sv1__data_i, d_wr11__wen, d_wr11__data_i, coresync_clk); +module \reg_1$136 (coresync_rst, cia1__ren, cia1__data_o, msr1__ren, msr1__data_o, sv1__ren, sv1__data_o, nia1__wen, nia1__data_i, msr1__wen, msr1__data_i, svstate1__wen, svstate1__data_i, sv1__wen, sv1__data_i, d_wr11__wen, d_wr11__data_i, coresync_clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$1 ; @@ -180110,9 +193511,9 @@ module \reg_1$136 (coresync_rst, cia1__ren, cia1__data_o, msr1__ren, msr1__data_ reg [63:0] \cia1__data_o$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input cia1__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [63:0] d_wr11__data_i; @@ -180148,6 +193549,10 @@ module \reg_1$136 (coresync_rst, cia1__ren, cia1__data_o, msr1__ren, msr1__data_ input sv1__ren; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input sv1__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [63:0] svstate1__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input svstate1__wen; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) reg wr_detect; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) @@ -180186,6 +193591,12 @@ module \reg_1$136 (coresync_rst, cia1__ren, cia1__data_o, msr1__ren, msr1__data_ \cia1__data_o$next = msr1__data_i; endcase (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (svstate1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \cia1__data_o$next = svstate1__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) casez (sv1__wen) /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ 1'h1: @@ -180205,7 +193616,7 @@ module \reg_1$136 (coresync_rst, cia1__ren, cia1__data_o, msr1__ren, msr1__data_ endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \cia1__data_o$next = 64'h0000000000000000; @@ -180233,6 +193644,12 @@ module \reg_1$136 (coresync_rst, cia1__ren, cia1__data_o, msr1__ren, msr1__data_ wr_detect = 1'h1; endcase (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (svstate1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) casez (sv1__wen) /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ 1'h1: @@ -180268,6 +193685,12 @@ module \reg_1$136 (coresync_rst, cia1__ren, cia1__data_o, msr1__ren, msr1__data_ \msr1__data_o$next = msr1__data_i; endcase (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (svstate1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \msr1__data_o$next = svstate1__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) casez (sv1__wen) /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ 1'h1: @@ -180287,7 +193710,7 @@ module \reg_1$136 (coresync_rst, cia1__ren, cia1__data_o, msr1__ren, msr1__data_ endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \msr1__data_o$next = 64'h0000000000000000; @@ -180315,6 +193738,12 @@ module \reg_1$136 (coresync_rst, cia1__ren, cia1__data_o, msr1__ren, msr1__data_ \wr_detect$4 = 1'h1; endcase (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (svstate1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) casez (sv1__wen) /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ 1'h1: @@ -180350,6 +193779,12 @@ module \reg_1$136 (coresync_rst, cia1__ren, cia1__data_o, msr1__ren, msr1__data_ \sv1__data_o$next = msr1__data_i; endcase (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (svstate1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \sv1__data_o$next = svstate1__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) casez (sv1__wen) /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ 1'h1: @@ -180369,7 +193804,7 @@ module \reg_1$136 (coresync_rst, cia1__ren, cia1__data_o, msr1__ren, msr1__data_ endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \sv1__data_o$next = 64'h0000000000000000; @@ -180397,6 +193832,12 @@ module \reg_1$136 (coresync_rst, cia1__ren, cia1__data_o, msr1__ren, msr1__data_ \wr_detect$7 = 1'h1; endcase (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (svstate1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) casez (sv1__wen) /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ 1'h1: @@ -180427,6 +193868,12 @@ module \reg_1$136 (coresync_rst, cia1__ren, cia1__data_o, msr1__ren, msr1__data_ \reg$next = msr1__data_i; endcase (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (svstate1__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = svstate1__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) casez (sv1__wen) /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ 1'h1: @@ -180438,7 +193885,7 @@ module \reg_1$136 (coresync_rst, cia1__ren, cia1__data_o, msr1__ren, msr1__data_ 1'h1: \reg$next = d_wr11__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \reg$next = 64'h0000000000000000; @@ -180460,9 +193907,9 @@ module reg_2(coresync_rst, src12__ren, src12__data_o, src22__ren, src22__data_o, wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] dest12__data_i; @@ -180576,7 +194023,7 @@ module reg_2(coresync_rst, src12__ren, src12__data_o, src22__ren, src22__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src12__data_o$next = 4'h0; @@ -180633,7 +194080,7 @@ module reg_2(coresync_rst, src12__ren, src12__data_o, src22__ren, src22__data_o, 1'h1: \reg$next = w2__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \reg$next = 4'h0; @@ -180673,7 +194120,7 @@ module reg_2(coresync_rst, src12__ren, src12__data_o, src22__ren, src22__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src22__data_o$next = 4'h0; @@ -180743,7 +194190,7 @@ module reg_2(coresync_rst, src12__ren, src12__data_o, src22__ren, src22__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src32__data_o$next = 4'h0; @@ -180813,7 +194260,7 @@ module reg_2(coresync_rst, src12__ren, src12__data_o, src22__ren, src22__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r2__data_o$next = 4'h0; @@ -180883,7 +194330,7 @@ module reg_2(coresync_rst, src12__ren, src12__data_o, src22__ren, src22__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r22__data_o$next = 4'h0; @@ -180933,9 +194380,9 @@ module \reg_2$134 (coresync_rst, src12__ren, src12__data_o, src22__ren, src22__d wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [1:0] dest12__data_i; @@ -181047,7 +194494,7 @@ module \reg_2$134 (coresync_rst, src12__ren, src12__data_o, src22__ren, src22__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src12__data_o$next = 2'h0; @@ -181129,7 +194576,7 @@ module \reg_2$134 (coresync_rst, src12__ren, src12__data_o, src22__ren, src22__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src22__data_o$next = 2'h0; @@ -181211,7 +194658,7 @@ module \reg_2$134 (coresync_rst, src12__ren, src12__data_o, src22__ren, src22__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src32__data_o$next = 2'h0; @@ -181293,7 +194740,7 @@ module \reg_2$134 (coresync_rst, src12__ren, src12__data_o, src22__ren, src22__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r2__data_o$next = 2'h0; @@ -181362,7 +194809,7 @@ module \reg_2$134 (coresync_rst, src12__ren, src12__data_o, src22__ren, src22__d 1'h1: \reg$next = w2__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \reg$next = 2'h0; @@ -181372,7 +194819,7 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.state.reg_2" *) (* generator = "nMigen" *) -module \reg_2$137 (coresync_rst, cia2__ren, cia2__data_o, msr2__ren, msr2__data_o, sv2__ren, sv2__data_o, nia2__wen, nia2__data_i, msr2__wen, msr2__data_i, sv2__wen, sv2__data_i, d_wr12__wen, d_wr12__data_i, coresync_clk); +module \reg_2$137 (coresync_rst, cia2__ren, cia2__data_o, msr2__ren, msr2__data_o, sv2__ren, sv2__data_o, nia2__wen, nia2__data_i, msr2__wen, msr2__data_i, svstate2__wen, svstate2__data_i, sv2__wen, sv2__data_i, d_wr12__wen, d_wr12__data_i, coresync_clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$1 ; @@ -181387,9 +194834,9 @@ module \reg_2$137 (coresync_rst, cia2__ren, cia2__data_o, msr2__ren, msr2__data_ reg [63:0] \cia2__data_o$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input cia2__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [63:0] d_wr12__data_i; @@ -181425,6 +194872,10 @@ module \reg_2$137 (coresync_rst, cia2__ren, cia2__data_o, msr2__ren, msr2__data_ input sv2__ren; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input sv2__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [63:0] svstate2__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input svstate2__wen; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) reg wr_detect; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *) @@ -181463,6 +194914,12 @@ module \reg_2$137 (coresync_rst, cia2__ren, cia2__data_o, msr2__ren, msr2__data_ \cia2__data_o$next = msr2__data_i; endcase (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (svstate2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \cia2__data_o$next = svstate2__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) casez (sv2__wen) /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ 1'h1: @@ -181482,7 +194939,7 @@ module \reg_2$137 (coresync_rst, cia2__ren, cia2__data_o, msr2__ren, msr2__data_ endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \cia2__data_o$next = 64'h0000000000000000; @@ -181510,6 +194967,12 @@ module \reg_2$137 (coresync_rst, cia2__ren, cia2__data_o, msr2__ren, msr2__data_ wr_detect = 1'h1; endcase (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (svstate2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + wr_detect = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) casez (sv2__wen) /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ 1'h1: @@ -181545,6 +195008,12 @@ module \reg_2$137 (coresync_rst, cia2__ren, cia2__data_o, msr2__ren, msr2__data_ \msr2__data_o$next = msr2__data_i; endcase (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (svstate2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \msr2__data_o$next = svstate2__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) casez (sv2__wen) /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ 1'h1: @@ -181564,7 +195033,7 @@ module \reg_2$137 (coresync_rst, cia2__ren, cia2__data_o, msr2__ren, msr2__data_ endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \msr2__data_o$next = 64'h0000000000000000; @@ -181592,6 +195061,12 @@ module \reg_2$137 (coresync_rst, cia2__ren, cia2__data_o, msr2__ren, msr2__data_ \wr_detect$4 = 1'h1; endcase (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (svstate2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$4 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) casez (sv2__wen) /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ 1'h1: @@ -181627,6 +195102,12 @@ module \reg_2$137 (coresync_rst, cia2__ren, cia2__data_o, msr2__ren, msr2__data_ \sv2__data_o$next = msr2__data_i; endcase (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (svstate2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \sv2__data_o$next = svstate2__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) casez (sv2__wen) /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ 1'h1: @@ -181646,7 +195127,7 @@ module \reg_2$137 (coresync_rst, cia2__ren, cia2__data_o, msr2__ren, msr2__data_ endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \sv2__data_o$next = 64'h0000000000000000; @@ -181674,6 +195155,12 @@ module \reg_2$137 (coresync_rst, cia2__ren, cia2__data_o, msr2__ren, msr2__data_ \wr_detect$7 = 1'h1; endcase (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) + casez (svstate2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ + 1'h1: + \wr_detect$7 = 1'h1; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *) casez (sv2__wen) /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" */ 1'h1: @@ -181704,6 +195191,12 @@ module \reg_2$137 (coresync_rst, cia2__ren, cia2__data_o, msr2__ren, msr2__data_ \reg$next = msr2__data_i; endcase (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) + casez (svstate2__wen) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ + 1'h1: + \reg$next = svstate2__data_i; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *) casez (sv2__wen) /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" */ 1'h1: @@ -181715,7 +195208,7 @@ module \reg_2$137 (coresync_rst, cia2__ren, cia2__data_o, msr2__ren, msr2__data_ 1'h1: \reg$next = d_wr12__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \reg$next = 64'h0000000000000000; @@ -181737,9 +195230,9 @@ module reg_3(coresync_rst, src13__ren, src13__data_o, src23__ren, src23__data_o, wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] dest13__data_i; @@ -181853,7 +195346,7 @@ module reg_3(coresync_rst, src13__ren, src13__data_o, src23__ren, src23__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src13__data_o$next = 4'h0; @@ -181910,7 +195403,7 @@ module reg_3(coresync_rst, src13__ren, src13__data_o, src23__ren, src23__data_o, 1'h1: \reg$next = w3__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \reg$next = 4'h0; @@ -181950,7 +195443,7 @@ module reg_3(coresync_rst, src13__ren, src13__data_o, src23__ren, src23__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src23__data_o$next = 4'h0; @@ -182020,7 +195513,7 @@ module reg_3(coresync_rst, src13__ren, src13__data_o, src23__ren, src23__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src33__data_o$next = 4'h0; @@ -182090,7 +195583,7 @@ module reg_3(coresync_rst, src13__ren, src13__data_o, src23__ren, src23__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r3__data_o$next = 4'h0; @@ -182160,7 +195653,7 @@ module reg_3(coresync_rst, src13__ren, src13__data_o, src23__ren, src23__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r23__data_o$next = 4'h0; @@ -182212,9 +195705,9 @@ module reg_4(coresync_rst, src14__ren, src14__data_o, src24__ren, src24__data_o, wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] dest14__data_i; @@ -182328,7 +195821,7 @@ module reg_4(coresync_rst, src14__ren, src14__data_o, src24__ren, src24__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src14__data_o$next = 4'h0; @@ -182385,7 +195878,7 @@ module reg_4(coresync_rst, src14__ren, src14__data_o, src24__ren, src24__data_o, 1'h1: \reg$next = w4__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \reg$next = 4'h0; @@ -182425,7 +195918,7 @@ module reg_4(coresync_rst, src14__ren, src14__data_o, src24__ren, src24__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src24__data_o$next = 4'h0; @@ -182495,7 +195988,7 @@ module reg_4(coresync_rst, src14__ren, src14__data_o, src24__ren, src24__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src34__data_o$next = 4'h0; @@ -182565,7 +196058,7 @@ module reg_4(coresync_rst, src14__ren, src14__data_o, src24__ren, src24__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r4__data_o$next = 4'h0; @@ -182635,7 +196128,7 @@ module reg_4(coresync_rst, src14__ren, src14__data_o, src24__ren, src24__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r24__data_o$next = 4'h0; @@ -182687,9 +196180,9 @@ module reg_5(coresync_rst, src15__ren, src15__data_o, src25__ren, src25__data_o, wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] dest15__data_i; @@ -182803,7 +196296,7 @@ module reg_5(coresync_rst, src15__ren, src15__data_o, src25__ren, src25__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src15__data_o$next = 4'h0; @@ -182860,7 +196353,7 @@ module reg_5(coresync_rst, src15__ren, src15__data_o, src25__ren, src25__data_o, 1'h1: \reg$next = w5__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \reg$next = 4'h0; @@ -182900,7 +196393,7 @@ module reg_5(coresync_rst, src15__ren, src15__data_o, src25__ren, src25__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src25__data_o$next = 4'h0; @@ -182970,7 +196463,7 @@ module reg_5(coresync_rst, src15__ren, src15__data_o, src25__ren, src25__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src35__data_o$next = 4'h0; @@ -183040,7 +196533,7 @@ module reg_5(coresync_rst, src15__ren, src15__data_o, src25__ren, src25__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r5__data_o$next = 4'h0; @@ -183110,7 +196603,7 @@ module reg_5(coresync_rst, src15__ren, src15__data_o, src25__ren, src25__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r25__data_o$next = 4'h0; @@ -183162,9 +196655,9 @@ module reg_6(coresync_rst, src16__ren, src16__data_o, src26__ren, src26__data_o, wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] dest16__data_i; @@ -183278,7 +196771,7 @@ module reg_6(coresync_rst, src16__ren, src16__data_o, src26__ren, src26__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src16__data_o$next = 4'h0; @@ -183335,7 +196828,7 @@ module reg_6(coresync_rst, src16__ren, src16__data_o, src26__ren, src26__data_o, 1'h1: \reg$next = w6__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \reg$next = 4'h0; @@ -183375,7 +196868,7 @@ module reg_6(coresync_rst, src16__ren, src16__data_o, src26__ren, src26__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src26__data_o$next = 4'h0; @@ -183445,7 +196938,7 @@ module reg_6(coresync_rst, src16__ren, src16__data_o, src26__ren, src26__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src36__data_o$next = 4'h0; @@ -183515,7 +197008,7 @@ module reg_6(coresync_rst, src16__ren, src16__data_o, src26__ren, src26__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r6__data_o$next = 4'h0; @@ -183585,7 +197078,7 @@ module reg_6(coresync_rst, src16__ren, src16__data_o, src26__ren, src26__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r26__data_o$next = 4'h0; @@ -183637,9 +197130,9 @@ module reg_7(coresync_rst, src17__ren, src17__data_o, src27__ren, src27__data_o, wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] dest17__data_i; @@ -183753,7 +197246,7 @@ module reg_7(coresync_rst, src17__ren, src17__data_o, src27__ren, src27__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src17__data_o$next = 4'h0; @@ -183810,7 +197303,7 @@ module reg_7(coresync_rst, src17__ren, src17__data_o, src27__ren, src27__data_o, 1'h1: \reg$next = w7__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \reg$next = 4'h0; @@ -183850,7 +197343,7 @@ module reg_7(coresync_rst, src17__ren, src17__data_o, src27__ren, src27__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src27__data_o$next = 4'h0; @@ -183920,7 +197413,7 @@ module reg_7(coresync_rst, src17__ren, src17__data_o, src27__ren, src27__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src37__data_o$next = 4'h0; @@ -183990,7 +197483,7 @@ module reg_7(coresync_rst, src17__ren, src17__data_o, src27__ren, src27__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r7__data_o$next = 4'h0; @@ -184060,7 +197553,7 @@ module reg_7(coresync_rst, src17__ren, src17__data_o, src27__ren, src27__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \r27__data_o$next = 4'h0; @@ -184118,9 +197611,9 @@ module req_l(coresync_rst, q_req, s_req, r_req, coresync_clk); wire [4:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [4:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [4:0] q_int = 5'h00; @@ -184149,7 +197642,7 @@ module req_l(coresync_rst, q_req, s_req, r_req, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 5'h00; @@ -184180,9 +197673,9 @@ module \req_l$103 (coresync_rst, q_req, s_req, r_req, coresync_clk); wire [3:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [3:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [3:0] q_int = 4'h0; @@ -184211,7 +197704,7 @@ module \req_l$103 (coresync_rst, q_req, s_req, r_req, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 4'h0; @@ -184242,9 +197735,9 @@ module \req_l$12 (coresync_rst, q_req, s_req, r_req, coresync_clk); wire [2:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [2:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [2:0] q_int = 3'h0; @@ -184273,7 +197766,7 @@ module \req_l$12 (coresync_rst, q_req, s_req, r_req, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 3'h0; @@ -184304,9 +197797,9 @@ module \req_l$121 (coresync_rst, q_req, s_req, r_req, coresync_clk); wire [2:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [2:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [2:0] q_int = 3'h0; @@ -184335,7 +197828,7 @@ module \req_l$121 (coresync_rst, q_req, s_req, r_req, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 3'h0; @@ -184366,9 +197859,9 @@ module \req_l$25 (coresync_rst, q_req, s_req, r_req, coresync_clk); wire [2:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [2:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [2:0] q_int = 3'h0; @@ -184397,7 +197890,7 @@ module \req_l$25 (coresync_rst, q_req, s_req, r_req, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 3'h0; @@ -184413,39 +197906,39 @@ endmodule module \req_l$41 (coresync_rst, q_req, s_req, r_req, coresync_clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) - wire [4:0] \$1 ; + wire [6:0] \$1 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) - wire [4:0] \$11 ; + wire [6:0] \$11 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) - wire [4:0] \$13 ; + wire [6:0] \$13 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) - wire [4:0] \$15 ; + wire [6:0] \$15 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) - wire [4:0] \$3 ; + wire [6:0] \$3 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) - wire [4:0] \$5 ; + wire [6:0] \$5 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) - wire [4:0] \$7 ; + wire [6:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) - wire [4:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + wire [6:0] \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) - reg [4:0] q_int = 5'h00; + reg [6:0] q_int = 7'h00; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) - reg [4:0] \q_int$next ; + reg [6:0] \q_int$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) - output [4:0] q_req; + output [6:0] q_req; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) - wire [4:0] qlq_req; + wire [6:0] qlq_req; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) - wire [4:0] qn_req; + wire [6:0] qn_req; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) - input [4:0] r_req; + input [6:0] r_req; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) - input [4:0] s_req; + input [6:0] s_req; assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_req; assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_req; @@ -184459,10 +197952,10 @@ module \req_l$41 (coresync_rst, q_req, s_req, r_req, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \q_int$next = 5'h00; + \q_int$next = 7'h00; endcase end assign qlq_req = \$15 ; @@ -184490,9 +197983,9 @@ module \req_l$57 (coresync_rst, q_req, s_req, r_req, coresync_clk); wire [1:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [1:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [1:0] q_int = 2'h0; @@ -184521,7 +198014,7 @@ module \req_l$57 (coresync_rst, q_req, s_req, r_req, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 2'h0; @@ -184552,9 +198045,9 @@ module \req_l$69 (coresync_rst, q_req, s_req, r_req, coresync_clk); wire [5:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [5:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [5:0] q_int = 6'h00; @@ -184583,7 +198076,7 @@ module \req_l$69 (coresync_rst, q_req, s_req, r_req, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 6'h00; @@ -184614,9 +198107,9 @@ module \req_l$86 (coresync_rst, q_req, s_req, r_req, coresync_clk); wire [3:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [3:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [3:0] q_int = 4'h0; @@ -184645,7 +198138,7 @@ module \req_l$86 (coresync_rst, q_req, s_req, r_req, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 4'h0; @@ -184670,9 +198163,9 @@ module reset_l(coresync_rst, s_reset, r_reset, q_reset, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -184698,7 +198191,7 @@ module reset_l(coresync_rst, s_reset, r_reset, q_reset, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -184723,9 +198216,9 @@ module \reset_l$131 (coresync_rst, s_reset, r_reset, q_reset, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -184751,7 +198244,7 @@ module \reset_l$131 (coresync_rst, s_reset, r_reset, q_reset, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -185373,9 +198866,9 @@ module rok_l(coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -185404,7 +198897,7 @@ module rok_l(coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -185435,9 +198928,9 @@ module \rok_l$105 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -185466,7 +198959,7 @@ module \rok_l$105 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -185497,9 +198990,9 @@ module \rok_l$123 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -185528,7 +199021,7 @@ module \rok_l$123 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -185559,9 +199052,9 @@ module \rok_l$14 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -185590,7 +199083,7 @@ module \rok_l$14 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -185621,9 +199114,9 @@ module \rok_l$27 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -185652,7 +199145,7 @@ module \rok_l$27 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -185683,9 +199176,9 @@ module \rok_l$43 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -185714,7 +199207,7 @@ module \rok_l$43 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -185745,9 +199238,9 @@ module \rok_l$59 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -185776,7 +199269,7 @@ module \rok_l$59 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -185807,9 +199300,9 @@ module \rok_l$71 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -185838,7 +199331,7 @@ module \rok_l$71 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -185869,9 +199362,9 @@ module \rok_l$88 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -185900,7 +199393,7 @@ module \rok_l$88 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -186321,9 +199814,9 @@ module rst_l(coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -186352,7 +199845,7 @@ module rst_l(coresync_rst, s_rst, r_rst, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -186383,9 +199876,9 @@ module \rst_l$104 (coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -186414,7 +199907,7 @@ module \rst_l$104 (coresync_rst, s_rst, r_rst, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -186445,9 +199938,9 @@ module \rst_l$122 (coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -186476,7 +199969,7 @@ module \rst_l$122 (coresync_rst, s_rst, r_rst, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -186507,9 +200000,9 @@ module \rst_l$129 (coresync_rst, s_rst, r_rst, q_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -186538,7 +200031,7 @@ module \rst_l$129 (coresync_rst, s_rst, r_rst, q_rst, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -186569,9 +200062,9 @@ module \rst_l$13 (coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -186600,7 +200093,7 @@ module \rst_l$13 (coresync_rst, s_rst, r_rst, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -186631,9 +200124,9 @@ module \rst_l$26 (coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -186662,7 +200155,7 @@ module \rst_l$26 (coresync_rst, s_rst, r_rst, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -186693,9 +200186,9 @@ module \rst_l$42 (coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -186724,7 +200217,7 @@ module \rst_l$42 (coresync_rst, s_rst, r_rst, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -186755,9 +200248,9 @@ module \rst_l$58 (coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -186786,7 +200279,7 @@ module \rst_l$58 (coresync_rst, s_rst, r_rst, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -186817,9 +200310,9 @@ module \rst_l$70 (coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -186848,7 +200341,7 @@ module \rst_l$70 (coresync_rst, s_rst, r_rst, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -186879,9 +200372,9 @@ module \rst_l$87 (coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -186910,7 +200403,7 @@ module \rst_l$87 (coresync_rst, s_rst, r_rst, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -186923,58 +200416,58 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.setup_stage" *) (* generator = "nMigen" *) -module setup_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, ra, rb, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \xer_so$20 , divisor_neg, dividend_neg, dive_abs_ov32, dive_abs_ov64, div_by_zero, dividend, divisor_radicand, operation, muxid); +module setup_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__SV_Ptype, ra, rb, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \logical_op__sv_pred_sz$20 , \logical_op__sv_pred_dz$21 , \logical_op__sv_saturate$22 , \logical_op__SV_Ptype$23 , \xer_so$24 , divisor_neg, dividend_neg, dive_abs_ov32, dive_abs_ov64, div_by_zero, dividend, divisor_radicand, operation, muxid); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" *) - wire \$21 ; + wire \$25 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" *) - wire \$23 ; + wire \$27 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" *) - wire \$25 ; + wire \$29 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" *) - wire \$27 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" *) - wire [64:0] \$29 ; + wire \$31 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" *) - wire [64:0] \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [64:0] \$32 ; + wire [64:0] \$33 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" *) wire [64:0] \$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [64:0] \$36 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" *) + wire [64:0] \$38 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" *) - wire [64:0] \$37 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - wire [64:0] \$39 ; + wire [64:0] \$40 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" *) wire [64:0] \$41 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [64:0] \$43 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" *) + wire [64:0] \$45 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" *) - wire \$43 ; + wire \$47 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" *) - wire \$45 ; + wire \$49 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" *) - wire \$47 ; + wire \$51 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" *) - wire \$49 ; + wire \$53 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" *) - wire \$51 ; + wire \$55 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" *) - wire \$53 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *) - wire [31:0] \$55 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" *) wire \$57 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *) wire [31:0] \$59 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" *) + wire \$61 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *) + wire [31:0] \$63 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" *) - wire [127:0] \$61 ; + wire [127:0] \$65 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" *) - wire [94:0] \$62 ; + wire [94:0] \$66 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" *) - wire [190:0] \$65 ; + wire [190:0] \$69 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" *) - wire [190:0] \$66 ; + wire [190:0] \$70 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:52" *) wire [63:0] abs_dend; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:51" *) @@ -186994,67 +200487,81 @@ module setup_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_d output divisor_neg; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *) output [63:0] divisor_radicand; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] logical_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \logical_op__SV_Ptype$23 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [3:0] logical_op__data_len; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [3:0] \logical_op__data_len$18 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] logical_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] logical_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \logical_op__fn_unit$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \logical_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] logical_op__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [63:0] \logical_op__imm_data__data$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__imm_data__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__imm_data__ok$5 ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] logical_op__input_carry; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [1:0] \logical_op__input_carry$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] logical_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \logical_op__insn$19 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -187131,7 +200638,9 @@ module setup_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_d (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] logical_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -187208,51 +200717,73 @@ module setup_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_d (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] \logical_op__insn_type$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__invert_in$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__invert_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__invert_out$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__is_32bit$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__is_signed$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__oe__oe$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__oe__ok$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__output_carry$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__rc__ok$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__rc__rc$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input logical_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \logical_op__sv_pred_dz$21 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input logical_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \logical_op__sv_pred_sz$20 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] logical_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \logical_op__sv_saturate$22 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__write_cr0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__write_cr0$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input logical_op__zero_a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \logical_op__zero_a$11 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; @@ -187260,36 +200791,36 @@ module setup_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_d output [1:0] \muxid$1 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" *) output [1:0] operation; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) - output \xer_so$20 ; - assign \$21 = logical_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" *) ra[31] : ra[63]; - assign \$23 = \$21 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" *) logical_op__is_signed; - assign \$25 = logical_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" *) rb[31] : rb[63]; - assign \$27 = \$25 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" *) logical_op__is_signed; - assign \$30 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" *) rb; - assign \$32 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) rb; - assign \$34 = divisor_neg ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" *) \$30 : \$32 ; - assign \$37 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" *) ra; - assign \$39 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) ra; - assign \$41 = dividend_neg ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" *) \$37 : \$39 ; - assign \$43 = abs_dend >= (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" *) abs_dor; - assign \$45 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" *) 7'h1e; - assign \$47 = \$43 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" *) \$45 ; - assign \$49 = abs_dend[31:0] >= (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" *) abs_dor[31:0]; - assign \$51 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" *) 7'h1e; - assign \$53 = \$49 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" *) \$51 ; - assign \$55 = logical_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *) 32'd0 : abs_dor[63:32]; - assign \$57 = divisor_radicand == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" *) 1'h0; - assign \$59 = logical_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *) 32'd0 : abs_dend[63:32]; - assign \$62 = abs_dend[31:0] <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" *) 6'h20; - assign \$61 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" *) \$62 ; - assign \$66 = abs_dend <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" *) 7'h40; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + output \xer_so$24 ; + assign \$25 = logical_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" *) ra[31] : ra[63]; + assign \$27 = \$25 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" *) logical_op__is_signed; + assign \$29 = logical_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" *) rb[31] : rb[63]; + assign \$31 = \$29 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" *) logical_op__is_signed; + assign \$34 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" *) rb; + assign \$36 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) rb; + assign \$38 = divisor_neg ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" *) \$34 : \$36 ; + assign \$41 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" *) ra; + assign \$43 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) ra; + assign \$45 = dividend_neg ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" *) \$41 : \$43 ; + assign \$47 = abs_dend >= (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" *) abs_dor; + assign \$49 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" *) 7'h1e; + assign \$51 = \$47 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" *) \$49 ; + assign \$53 = abs_dend[31:0] >= (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" *) abs_dor[31:0]; + assign \$55 = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" *) 7'h1e; + assign \$57 = \$53 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" *) \$55 ; + assign \$59 = logical_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *) 32'd0 : abs_dor[63:32]; + assign \$61 = divisor_radicand == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" *) 1'h0; + assign \$63 = logical_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *) 32'd0 : abs_dend[63:32]; + assign \$66 = abs_dend[31:0] <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" *) 6'h20; + assign \$65 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" *) \$66 ; + assign \$70 = abs_dend <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" *) 7'h40; always @* begin if (\initial ) begin end dividend = 128'h00000000000000000000000000000000; @@ -187300,7 +200831,7 @@ module setup_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_d 7'h1d, 7'h2f: begin dividend[31:0] = abs_dend[31:0]; - dividend[63:32] = \$59 ; + dividend[63:32] = \$63 ; end /* \nmigen.decoding = "OP_DIVE/30" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:77" */ @@ -187310,34 +200841,34 @@ module setup_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_d casez (logical_op__is_32bit) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:78" */ 1'h1: - dividend = \$61 ; + dividend = \$65 ; /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:80" */ default: - dividend = \$65 [127:0]; + dividend = \$69 [127:0]; endcase endcase end - assign \$29 = \$34 ; - assign \$36 = \$41 ; - assign \$65 = \$66 ; - assign { \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; + assign \$33 = \$38 ; + assign \$40 = \$45 ; + assign \$69 = \$70 ; + assign { \logical_op__SV_Ptype$23 , \logical_op__sv_saturate$22 , \logical_op__sv_pred_dz$21 , \logical_op__sv_pred_sz$20 , \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2 } = { logical_op__SV_Ptype, logical_op__sv_saturate, logical_op__sv_pred_dz, logical_op__sv_pred_sz, logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; assign \muxid$1 = muxid; - assign \xer_so$20 = xer_so; - assign div_by_zero = \$57 ; - assign divisor_radicand[63:32] = \$55 ; + assign \xer_so$24 = xer_so; + assign div_by_zero = \$61 ; + assign divisor_radicand[63:32] = \$59 ; assign divisor_radicand[31:0] = abs_dor[31:0]; - assign dive_abs_ov32 = \$53 ; - assign dive_abs_ov64 = \$47 ; - assign abs_dend = \$41 [63:0]; - assign abs_dor = \$34 [63:0]; - assign divisor_neg = \$27 ; - assign dividend_neg = \$23 ; + assign dive_abs_ov32 = \$57 ; + assign dive_abs_ov64 = \$51 ; + assign abs_dend = \$45 [63:0]; + assign abs_dor = \$38 [63:0]; + assign divisor_neg = \$31 ; + assign dividend_neg = \$27 ; assign operation = 2'h1; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0" *) (* generator = "nMigen" *) -module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shift_rot0__fn_unit, oper_i_alu_shift_rot0__imm_data__data, oper_i_alu_shift_rot0__imm_data__ok, oper_i_alu_shift_rot0__rc__rc, oper_i_alu_shift_rot0__rc__ok, oper_i_alu_shift_rot0__oe__oe, oper_i_alu_shift_rot0__oe__ok, oper_i_alu_shift_rot0__write_cr0, oper_i_alu_shift_rot0__invert_in, oper_i_alu_shift_rot0__input_carry, oper_i_alu_shift_rot0__output_carry, oper_i_alu_shift_rot0__input_cr, oper_i_alu_shift_rot0__output_cr, oper_i_alu_shift_rot0__is_32bit, oper_i_alu_shift_rot0__is_signed, oper_i_alu_shift_rot0__insn, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src3_i, src1_i, src4_i, src5_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, cr_a_ok, dest2_o, xer_ca_ok, dest3_o, coresync_clk); +module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shift_rot0__fn_unit, oper_i_alu_shift_rot0__imm_data__data, oper_i_alu_shift_rot0__imm_data__ok, oper_i_alu_shift_rot0__rc__rc, oper_i_alu_shift_rot0__rc__ok, oper_i_alu_shift_rot0__oe__oe, oper_i_alu_shift_rot0__oe__ok, oper_i_alu_shift_rot0__write_cr0, oper_i_alu_shift_rot0__invert_in, oper_i_alu_shift_rot0__input_carry, oper_i_alu_shift_rot0__output_carry, oper_i_alu_shift_rot0__input_cr, oper_i_alu_shift_rot0__output_cr, oper_i_alu_shift_rot0__is_32bit, oper_i_alu_shift_rot0__is_signed, oper_i_alu_shift_rot0__insn, oper_i_alu_shift_rot0__sv_pred_sz, oper_i_alu_shift_rot0__sv_pred_dz, oper_i_alu_shift_rot0__sv_saturate, oper_i_alu_shift_rot0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src3_i, src1_i, src4_i, src5_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, cr_a_ok, dest2_o, xer_ca_ok, dest3_o, coresync_clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) wire \$10 ; @@ -187487,66 +201018,75 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif wire alu_pulse; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" *) wire [2:0] alu_pulsem; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [3:0] alu_shift_rot0_cr_a; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) wire alu_shift_rot0_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire alu_shift_rot0_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] alu_shift_rot0_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire alu_shift_rot0_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) wire alu_shift_rot0_p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] alu_shift_rot0_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] alu_shift_rot0_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] alu_shift_rot0_rc; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] alu_shift_rot0_sr_op__SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \alu_shift_rot0_sr_op__SV_Ptype$next ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] alu_shift_rot0_sr_op__fn_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] \alu_shift_rot0_sr_op__fn_unit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] alu_shift_rot0_sr_op__fn_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] \alu_shift_rot0_sr_op__fn_unit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] alu_shift_rot0_sr_op__imm_data__data = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] \alu_shift_rot0_sr_op__imm_data__data$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_shift_rot0_sr_op__imm_data__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_shift_rot0_sr_op__imm_data__ok$next ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [1:0] alu_shift_rot0_sr_op__input_carry = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [1:0] \alu_shift_rot0_sr_op__input_carry$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_shift_rot0_sr_op__input_cr = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_shift_rot0_sr_op__input_cr$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] alu_shift_rot0_sr_op__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] \alu_shift_rot0_sr_op__insn$next ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -187623,55 +201163,73 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] alu_shift_rot0_sr_op__insn_type = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] \alu_shift_rot0_sr_op__insn_type$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_shift_rot0_sr_op__invert_in = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_shift_rot0_sr_op__invert_in$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_shift_rot0_sr_op__is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_shift_rot0_sr_op__is_32bit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_shift_rot0_sr_op__is_signed = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_shift_rot0_sr_op__is_signed$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_shift_rot0_sr_op__oe__oe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_shift_rot0_sr_op__oe__oe$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_shift_rot0_sr_op__oe__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_shift_rot0_sr_op__oe__ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_shift_rot0_sr_op__output_carry = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_shift_rot0_sr_op__output_carry$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_shift_rot0_sr_op__output_cr = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_shift_rot0_sr_op__output_cr$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_shift_rot0_sr_op__rc__ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_shift_rot0_sr_op__rc__ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_shift_rot0_sr_op__rc__rc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_shift_rot0_sr_op__rc__rc$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg alu_shift_rot0_sr_op__sv_pred_dz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \alu_shift_rot0_sr_op__sv_pred_dz$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg alu_shift_rot0_sr_op__sv_pred_sz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \alu_shift_rot0_sr_op__sv_pred_sz$next ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] alu_shift_rot0_sr_op__sv_saturate = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \alu_shift_rot0_sr_op__sv_saturate$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_shift_rot0_sr_op__write_cr0 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_shift_rot0_sr_op__write_cr0$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [1:0] alu_shift_rot0_xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [1:0] \alu_shift_rot0_xer_ca$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire alu_shift_rot0_xer_so; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire alui_l_q_alui; @@ -187681,11 +201239,11 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_a_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) output cu_busy_o; @@ -187742,7 +201300,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) output [1:0] dest3_o; reg [1:0] dest3_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire opc_l_q_opc; @@ -187754,36 +201312,43 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif reg opc_l_s_opc = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) reg \opc_l_s_opc$next ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_shift_rot0__SV_Ptype; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] oper_i_alu_shift_rot0__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] oper_i_alu_shift_rot0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] oper_i_alu_shift_rot0__imm_data__data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_shift_rot0__imm_data__ok; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [1:0] oper_i_alu_shift_rot0__input_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_shift_rot0__input_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] oper_i_alu_shift_rot0__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -187860,27 +201425,39 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] oper_i_alu_shift_rot0__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_shift_rot0__invert_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_shift_rot0__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_shift_rot0__is_signed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_shift_rot0__oe__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_shift_rot0__oe__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_shift_rot0__output_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_shift_rot0__output_cr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_shift_rot0__rc__ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_shift_rot0__rc__rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_shift_rot0__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_shift_rot0__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_shift_rot0__sv_saturate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_shift_rot0__write_cr0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *) reg [2:0] prev_wr_go = 3'h0; @@ -187970,7 +201547,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif wire src_sel; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" *) wire wr_any; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ca_ok; assign \$100 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) cu_rdmaskn_i; assign \$102 = \$98 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) \$100 ; @@ -188091,6 +201668,14 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif alu_shift_rot0_sr_op__is_signed <= \alu_shift_rot0_sr_op__is_signed$next ; always @(posedge coresync_clk) alu_shift_rot0_sr_op__insn <= \alu_shift_rot0_sr_op__insn$next ; + always @(posedge coresync_clk) + alu_shift_rot0_sr_op__sv_pred_sz <= \alu_shift_rot0_sr_op__sv_pred_sz$next ; + always @(posedge coresync_clk) + alu_shift_rot0_sr_op__sv_pred_dz <= \alu_shift_rot0_sr_op__sv_pred_dz$next ; + always @(posedge coresync_clk) + alu_shift_rot0_sr_op__sv_saturate <= \alu_shift_rot0_sr_op__sv_saturate$next ; + always @(posedge coresync_clk) + alu_shift_rot0_sr_op__SV_Ptype <= \alu_shift_rot0_sr_op__SV_Ptype$next ; always @(posedge coresync_clk) req_l_r_req <= \req_l_r_req$next ; always @(posedge coresync_clk) @@ -188138,6 +201723,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif .ra(alu_shift_rot0_ra), .rb(alu_shift_rot0_rb), .rc(alu_shift_rot0_rc), + .sr_op__SV_Ptype(alu_shift_rot0_sr_op__SV_Ptype), .sr_op__fn_unit(alu_shift_rot0_sr_op__fn_unit), .sr_op__imm_data__data(alu_shift_rot0_sr_op__imm_data__data), .sr_op__imm_data__ok(alu_shift_rot0_sr_op__imm_data__ok), @@ -188154,6 +201740,9 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif .sr_op__output_cr(alu_shift_rot0_sr_op__output_cr), .sr_op__rc__ok(alu_shift_rot0_sr_op__rc__ok), .sr_op__rc__rc(alu_shift_rot0_sr_op__rc__rc), + .sr_op__sv_pred_dz(alu_shift_rot0_sr_op__sv_pred_dz), + .sr_op__sv_pred_sz(alu_shift_rot0_sr_op__sv_pred_sz), + .sr_op__sv_saturate(alu_shift_rot0_sr_op__sv_saturate), .sr_op__write_cr0(alu_shift_rot0_sr_op__write_cr0), .xer_ca(alu_shift_rot0_xer_ca), .\xer_ca$1 (\alu_shift_rot0_xer_ca$1 ), @@ -188214,7 +201803,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \rok_l_s_rdok$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_s_rdok$next = 1'h0; @@ -188223,7 +201812,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \rok_l_r_rdok$next = \$64 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_r_rdok$next = 1'h1; @@ -188232,7 +201821,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \rst_l_s_rst$next = all_rd; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_s_rst$next = 1'h0; @@ -188241,7 +201830,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \rst_l_r_rst$next = rst_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_r_rst$next = 1'h1; @@ -188250,7 +201839,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \opc_l_s_opc$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_s_opc$next = 1'h0; @@ -188259,7 +201848,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \opc_l_r_opc$next = req_done; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_r_opc$next = 1'h1; @@ -188268,7 +201857,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_s_src$next = 5'h00; @@ -188277,7 +201866,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \src_l_r_src$next = reset_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_r_src$next = 5'h1f; @@ -188286,7 +201875,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \req_l_s_req$next = \$66 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_s_req$next = 3'h0; @@ -188295,7 +201884,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \req_l_r_req$next = \$68 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_r_req$next = 3'h7; @@ -188320,13 +201909,17 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif \alu_shift_rot0_sr_op__is_32bit$next = alu_shift_rot0_sr_op__is_32bit; \alu_shift_rot0_sr_op__is_signed$next = alu_shift_rot0_sr_op__is_signed; \alu_shift_rot0_sr_op__insn$next = alu_shift_rot0_sr_op__insn; + \alu_shift_rot0_sr_op__sv_pred_sz$next = alu_shift_rot0_sr_op__sv_pred_sz; + \alu_shift_rot0_sr_op__sv_pred_dz$next = alu_shift_rot0_sr_op__sv_pred_dz; + \alu_shift_rot0_sr_op__sv_saturate$next = alu_shift_rot0_sr_op__sv_saturate; + \alu_shift_rot0_sr_op__SV_Ptype$next = alu_shift_rot0_sr_op__SV_Ptype; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *) casez (cu_issue_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" */ 1'h1: - { \alu_shift_rot0_sr_op__insn$next , \alu_shift_rot0_sr_op__is_signed$next , \alu_shift_rot0_sr_op__is_32bit$next , \alu_shift_rot0_sr_op__output_cr$next , \alu_shift_rot0_sr_op__input_cr$next , \alu_shift_rot0_sr_op__output_carry$next , \alu_shift_rot0_sr_op__input_carry$next , \alu_shift_rot0_sr_op__invert_in$next , \alu_shift_rot0_sr_op__write_cr0$next , \alu_shift_rot0_sr_op__oe__ok$next , \alu_shift_rot0_sr_op__oe__oe$next , \alu_shift_rot0_sr_op__rc__ok$next , \alu_shift_rot0_sr_op__rc__rc$next , \alu_shift_rot0_sr_op__imm_data__ok$next , \alu_shift_rot0_sr_op__imm_data__data$next , \alu_shift_rot0_sr_op__fn_unit$next , \alu_shift_rot0_sr_op__insn_type$next } = { oper_i_alu_shift_rot0__insn, oper_i_alu_shift_rot0__is_signed, oper_i_alu_shift_rot0__is_32bit, oper_i_alu_shift_rot0__output_cr, oper_i_alu_shift_rot0__input_cr, oper_i_alu_shift_rot0__output_carry, oper_i_alu_shift_rot0__input_carry, oper_i_alu_shift_rot0__invert_in, oper_i_alu_shift_rot0__write_cr0, oper_i_alu_shift_rot0__oe__ok, oper_i_alu_shift_rot0__oe__oe, oper_i_alu_shift_rot0__rc__ok, oper_i_alu_shift_rot0__rc__rc, oper_i_alu_shift_rot0__imm_data__ok, oper_i_alu_shift_rot0__imm_data__data, oper_i_alu_shift_rot0__fn_unit, oper_i_alu_shift_rot0__insn_type }; + { \alu_shift_rot0_sr_op__SV_Ptype$next , \alu_shift_rot0_sr_op__sv_saturate$next , \alu_shift_rot0_sr_op__sv_pred_dz$next , \alu_shift_rot0_sr_op__sv_pred_sz$next , \alu_shift_rot0_sr_op__insn$next , \alu_shift_rot0_sr_op__is_signed$next , \alu_shift_rot0_sr_op__is_32bit$next , \alu_shift_rot0_sr_op__output_cr$next , \alu_shift_rot0_sr_op__input_cr$next , \alu_shift_rot0_sr_op__output_carry$next , \alu_shift_rot0_sr_op__input_carry$next , \alu_shift_rot0_sr_op__invert_in$next , \alu_shift_rot0_sr_op__write_cr0$next , \alu_shift_rot0_sr_op__oe__ok$next , \alu_shift_rot0_sr_op__oe__oe$next , \alu_shift_rot0_sr_op__rc__ok$next , \alu_shift_rot0_sr_op__rc__rc$next , \alu_shift_rot0_sr_op__imm_data__ok$next , \alu_shift_rot0_sr_op__imm_data__data$next , \alu_shift_rot0_sr_op__fn_unit$next , \alu_shift_rot0_sr_op__insn_type$next } = { oper_i_alu_shift_rot0__SV_Ptype, oper_i_alu_shift_rot0__sv_saturate, oper_i_alu_shift_rot0__sv_pred_dz, oper_i_alu_shift_rot0__sv_pred_sz, oper_i_alu_shift_rot0__insn, oper_i_alu_shift_rot0__is_signed, oper_i_alu_shift_rot0__is_32bit, oper_i_alu_shift_rot0__output_cr, oper_i_alu_shift_rot0__input_cr, oper_i_alu_shift_rot0__output_carry, oper_i_alu_shift_rot0__input_carry, oper_i_alu_shift_rot0__invert_in, oper_i_alu_shift_rot0__write_cr0, oper_i_alu_shift_rot0__oe__ok, oper_i_alu_shift_rot0__oe__oe, oper_i_alu_shift_rot0__rc__ok, oper_i_alu_shift_rot0__rc__rc, oper_i_alu_shift_rot0__imm_data__ok, oper_i_alu_shift_rot0__imm_data__data, oper_i_alu_shift_rot0__fn_unit, oper_i_alu_shift_rot0__insn_type }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: begin @@ -188355,7 +201948,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif 1'h1: { \data_r0__o_ok$next , \data_r0__o$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r0__o_ok$next = 1'h0; @@ -188377,7 +201970,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif 1'h1: { \data_r1__cr_a_ok$next , \data_r1__cr_a$next } = 5'h00; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r1__cr_a_ok$next = 1'h0; @@ -188399,7 +201992,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif 1'h1: { \data_r2__xer_ca_ok$next , \data_r2__xer_ca$next } = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r2__xer_ca_ok$next = 1'h0; @@ -188458,7 +202051,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \alui_l_r_alui$next = \$90 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alui_l_r_alui$next = 1'h1; @@ -188467,7 +202060,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \alu_l_r_alu$next = \$92 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alu_l_r_alu$next = 1'h1; @@ -188506,7 +202099,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \prev_wr_go$next = \$20 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \prev_wr_go$next = 3'h0; @@ -188550,23 +202143,23 @@ endmodule (* generator = "nMigen" *) module spr(coresync_rst, spr1__data_o, spr1__addr, spr1__ren, spr1__data_i, \spr1__addr$1 , spr1__wen, coresync_clk); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:211" *) wire [3:0] memory_r_addr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:211" *) wire [63:0] memory_r_data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:219" *) wire [3:0] memory_w_addr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:219" *) wire [63:0] memory_w_data; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:219" *) wire memory_w_en; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" *) reg ren_delay = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" *) reg \ren_delay$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] spr1__addr; @@ -188606,7 +202199,7 @@ module spr(coresync_rst, spr1__data_o, spr1__addr, spr1__ren, spr1__data_i, \spr always @* begin if (\initial ) begin end \ren_delay$next = spr1__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \ren_delay$next = 1'h0; @@ -188615,9 +202208,9 @@ module spr(coresync_rst, spr1__data_o, spr1__addr, spr1__ren, spr1__data_i, \spr always @* begin if (\initial ) begin end spr1__data_o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:246" *) casez (ren_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:246" */ 1'h1: spr1__data_o = memory_r_data; endcase @@ -188630,7 +202223,7 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.spr0" *) (* generator = "nMigen" *) -module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, oper_i_alu_spr0__insn, oper_i_alu_spr0__is_32bit, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src1_i, src4_i, src6_i, src5_i, src3_i, src2_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, xer_ca_ok, dest6_o, xer_ov_ok, dest5_o, xer_so_ok, dest4_o, fast1_ok, dest3_o, spr1_ok, dest2_o, coresync_clk); +module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, oper_i_alu_spr0__insn, oper_i_alu_spr0__is_32bit, oper_i_alu_spr0__sv_pred_sz, oper_i_alu_spr0__sv_pred_dz, oper_i_alu_spr0__sv_saturate, oper_i_alu_spr0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src1_i, src4_i, src6_i, src5_i, src3_i, src2_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, xer_ca_ok, dest6_o, xer_ov_ok, dest5_o, xer_so_ok, dest4_o, fast1_ok, dest3_o, spr1_ok, dest2_o, coresync_clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) wire \$100 ; @@ -188794,48 +202387,57 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, wire alu_pulse; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" *) wire [5:0] alu_pulsem; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] alu_spr0_fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] \alu_spr0_fast1$2 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) wire alu_spr0_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire alu_spr0_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] alu_spr0_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire alu_spr0_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) wire alu_spr0_p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] alu_spr0_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] alu_spr0_spr1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] \alu_spr0_spr1$1 ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] alu_spr0_spr_op__SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \alu_spr0_spr_op__SV_Ptype$next ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] alu_spr0_spr_op__fn_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] \alu_spr0_spr_op__fn_unit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] alu_spr0_spr_op__fn_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] \alu_spr0_spr_op__fn_unit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] alu_spr0_spr_op__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] \alu_spr0_spr_op__insn$next ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -188912,25 +202514,43 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] alu_spr0_spr_op__insn_type = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] \alu_spr0_spr_op__insn_type$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_spr0_spr_op__is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_spr0_spr_op__is_32bit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg alu_spr0_spr_op__sv_pred_dz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \alu_spr0_spr_op__sv_pred_dz$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg alu_spr0_spr_op__sv_pred_sz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \alu_spr0_spr_op__sv_pred_sz$next ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] alu_spr0_spr_op__sv_saturate = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \alu_spr0_spr_op__sv_saturate$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [1:0] alu_spr0_xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [1:0] \alu_spr0_xer_ca$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [1:0] alu_spr0_xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [1:0] \alu_spr0_xer_ov$4 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire alu_spr0_xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire \alu_spr0_xer_so$3 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire alui_l_q_alui; @@ -188940,9 +202560,9 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) output cu_busy_o; @@ -189032,9 +202652,9 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) output [1:0] dest6_o; reg [1:0] dest6_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output fast1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire opc_l_q_opc; @@ -189046,24 +202666,31 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, reg opc_l_s_opc = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) reg \opc_l_s_opc$next ; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_spr0__SV_Ptype; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] oper_i_alu_spr0__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] oper_i_alu_spr0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] oper_i_alu_spr0__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -189140,10 +202767,22 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] oper_i_alu_spr0__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_spr0__is_32bit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_spr0__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_spr0__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_spr0__sv_saturate; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *) reg [5:0] prev_wr_go = 6'h00; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *) @@ -189186,7 +202825,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, reg \rst_l_s_rst$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" *) wire rst_r; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output spr1_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) input [63:0] src1_i; @@ -189236,11 +202875,11 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, reg [1:0] \src_r5$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" *) wire wr_any; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_so_ok; assign \$9 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__rel_o; assign \$100 = alu_spr0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) alu_l_q_alu; @@ -189356,6 +202995,14 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, alu_spr0_spr_op__insn <= \alu_spr0_spr_op__insn$next ; always @(posedge coresync_clk) alu_spr0_spr_op__is_32bit <= \alu_spr0_spr_op__is_32bit$next ; + always @(posedge coresync_clk) + alu_spr0_spr_op__sv_pred_sz <= \alu_spr0_spr_op__sv_pred_sz$next ; + always @(posedge coresync_clk) + alu_spr0_spr_op__sv_pred_dz <= \alu_spr0_spr_op__sv_pred_dz$next ; + always @(posedge coresync_clk) + alu_spr0_spr_op__sv_saturate <= \alu_spr0_spr_op__sv_saturate$next ; + always @(posedge coresync_clk) + alu_spr0_spr_op__SV_Ptype <= \alu_spr0_spr_op__SV_Ptype$next ; always @(posedge coresync_clk) req_l_r_req <= \req_l_r_req$next ; always @(posedge coresync_clk) @@ -189405,10 +203052,14 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, .spr1(alu_spr0_spr1), .\spr1$1 (\alu_spr0_spr1$1 ), .spr1_ok(spr1_ok), + .spr_op__SV_Ptype(alu_spr0_spr_op__SV_Ptype), .spr_op__fn_unit(alu_spr0_spr_op__fn_unit), .spr_op__insn(alu_spr0_spr_op__insn), .spr_op__insn_type(alu_spr0_spr_op__insn_type), .spr_op__is_32bit(alu_spr0_spr_op__is_32bit), + .spr_op__sv_pred_dz(alu_spr0_spr_op__sv_pred_dz), + .spr_op__sv_pred_sz(alu_spr0_spr_op__sv_pred_sz), + .spr_op__sv_saturate(alu_spr0_spr_op__sv_saturate), .xer_ca(alu_spr0_xer_ca), .\xer_ca$5 (\alu_spr0_xer_ca$5 ), .xer_ca_ok(xer_ca_ok), @@ -189473,7 +203124,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \rok_l_s_rdok$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_s_rdok$next = 1'h0; @@ -189482,7 +203133,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \rok_l_r_rdok$next = \$68 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_r_rdok$next = 1'h1; @@ -189491,7 +203142,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \rst_l_s_rst$next = all_rd; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_s_rst$next = 1'h0; @@ -189500,7 +203151,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \rst_l_r_rst$next = rst_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_r_rst$next = 1'h1; @@ -189509,7 +203160,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \opc_l_s_opc$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_s_opc$next = 1'h0; @@ -189518,7 +203169,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \opc_l_r_opc$next = req_done; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_r_opc$next = 1'h1; @@ -189527,7 +203178,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_s_src$next = 6'h00; @@ -189536,7 +203187,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \src_l_r_src$next = reset_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \src_l_r_src$next = 6'h3f; @@ -189545,7 +203196,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \req_l_s_req$next = \$70 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_s_req$next = 6'h00; @@ -189554,7 +203205,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \req_l_r_req$next = \$72 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \req_l_r_req$next = 6'h3f; @@ -189566,11 +203217,15 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, \alu_spr0_spr_op__fn_unit$next = alu_spr0_spr_op__fn_unit; \alu_spr0_spr_op__insn$next = alu_spr0_spr_op__insn; \alu_spr0_spr_op__is_32bit$next = alu_spr0_spr_op__is_32bit; + \alu_spr0_spr_op__sv_pred_sz$next = alu_spr0_spr_op__sv_pred_sz; + \alu_spr0_spr_op__sv_pred_dz$next = alu_spr0_spr_op__sv_pred_dz; + \alu_spr0_spr_op__sv_saturate$next = alu_spr0_spr_op__sv_saturate; + \alu_spr0_spr_op__SV_Ptype$next = alu_spr0_spr_op__SV_Ptype; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *) casez (cu_issue_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" */ 1'h1: - { \alu_spr0_spr_op__is_32bit$next , \alu_spr0_spr_op__insn$next , \alu_spr0_spr_op__fn_unit$next , \alu_spr0_spr_op__insn_type$next } = { oper_i_alu_spr0__is_32bit, oper_i_alu_spr0__insn, oper_i_alu_spr0__fn_unit, oper_i_alu_spr0__insn_type }; + { \alu_spr0_spr_op__SV_Ptype$next , \alu_spr0_spr_op__sv_saturate$next , \alu_spr0_spr_op__sv_pred_dz$next , \alu_spr0_spr_op__sv_pred_sz$next , \alu_spr0_spr_op__is_32bit$next , \alu_spr0_spr_op__insn$next , \alu_spr0_spr_op__fn_unit$next , \alu_spr0_spr_op__insn_type$next } = { oper_i_alu_spr0__SV_Ptype, oper_i_alu_spr0__sv_saturate, oper_i_alu_spr0__sv_pred_dz, oper_i_alu_spr0__sv_pred_sz, oper_i_alu_spr0__is_32bit, oper_i_alu_spr0__insn, oper_i_alu_spr0__fn_unit, oper_i_alu_spr0__insn_type }; endcase end always @* begin @@ -189589,7 +203244,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, 1'h1: { \data_r0__o_ok$next , \data_r0__o$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r0__o_ok$next = 1'h0; @@ -189611,7 +203266,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, 1'h1: { \data_r1__spr1_ok$next , \data_r1__spr1$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r1__spr1_ok$next = 1'h0; @@ -189633,7 +203288,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, 1'h1: { \data_r2__fast1_ok$next , \data_r2__fast1$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r2__fast1_ok$next = 1'h0; @@ -189655,7 +203310,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, 1'h1: { \data_r3__xer_so_ok$next , \data_r3__xer_so$next } = 2'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r3__xer_so_ok$next = 1'h0; @@ -189677,7 +203332,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, 1'h1: { \data_r4__xer_ov_ok$next , \data_r4__xer_ov$next } = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r4__xer_ov_ok$next = 1'h0; @@ -189699,7 +203354,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, 1'h1: { \data_r5__xer_ca_ok$next , \data_r5__xer_ca$next } = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r5__xer_ca_ok$next = 1'h0; @@ -189768,7 +203423,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \alui_l_r_alui$next = \$98 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alui_l_r_alui$next = 1'h1; @@ -189777,7 +203432,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \alu_l_r_alu$next = \$100 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alu_l_r_alu$next = 1'h1; @@ -189846,7 +203501,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \prev_wr_go$next = \$24 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \prev_wr_go$next = 6'h00; @@ -189887,13 +203542,9 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.spr_main" *) (* generator = "nMigen" *) -module spr_main(spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32bit, ra, spr1, fast1, xer_so, xer_ov, xer_ca, \muxid$1 , \spr_op__insn_type$2 , \spr_op__fn_unit$3 , \spr_op__insn$4 , \spr_op__is_32bit$5 , o, o_ok, \spr1$6 , spr1_ok, \fast1$7 , fast1_ok, \xer_so$8 , xer_so_ok, \xer_ov$9 , xer_ov_ok, \xer_ca$10 , xer_ca_ok, muxid); +module spr_main(spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32bit, spr_op__sv_pred_sz, spr_op__sv_pred_dz, spr_op__sv_saturate, spr_op__SV_Ptype, ra, spr1, fast1, xer_so, xer_ov, xer_ca, \muxid$1 , \spr_op__insn_type$2 , \spr_op__fn_unit$3 , \spr_op__insn$4 , \spr_op__is_32bit$5 , \spr_op__sv_pred_sz$6 , \spr_op__sv_pred_dz$7 , \spr_op__sv_saturate$8 , \spr_op__SV_Ptype$9 , o, o_ok, \spr1$10 , spr1_ok, \fast1$11 , fast1_ok, \xer_so$12 , xer_so_ok, \xer_ov$13 , xer_ov_ok, \xer_ca$14 , xer_ca_ok, muxid); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) - wire \$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) - wire \$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) wire \$15 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) wire \$17 ; @@ -189901,75 +203552,93 @@ module spr_main(spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32b wire \$19 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) wire \$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:90" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) wire \$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) + wire \$25 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:90" *) + wire \$27 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [63:0] \fast1$7 ; - reg [63:0] \fast1$7 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [63:0] \fast1$11 ; + reg [63:0] \fast1$11 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output fast1_ok; reg fast1_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) input [1:0] muxid; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *) output [1:0] \muxid$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] o; reg [63:0] o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output o_ok; reg o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] ra; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:50" *) wire [9:0] spr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] spr1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [63:0] \spr1$6 ; - reg [63:0] \spr1$6 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [63:0] \spr1$10 ; + reg [63:0] \spr1$10 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output spr1_ok; reg spr1_ok; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] spr_op__SV_Ptype; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \spr_op__SV_Ptype$9 ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] spr_op__fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] spr_op__fn_unit; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - output [13:0] \spr_op__fn_unit$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [14:0] \spr_op__fn_unit$3 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] spr_op__insn; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [31:0] \spr_op__insn$4 ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -190046,7 +203715,9 @@ module spr_main(spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32b (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] spr_op__insn_type; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -190123,46 +203794,68 @@ module spr_main(spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32b (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output [6:0] \spr_op__insn_type$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input spr_op__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) output \spr_op__is_32bit$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input spr_op__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \spr_op__sv_pred_dz$7 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input spr_op__sv_pred_sz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output \spr_op__sv_pred_sz$6 ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] spr_op__sv_saturate; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + output [1:0] \spr_op__sv_saturate$8 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [1:0] xer_ca; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [1:0] \xer_ca$10 ; - reg [1:0] \xer_ca$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [1:0] \xer_ca$14 ; + reg [1:0] \xer_ca$14 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ca_ok; reg xer_ca_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [1:0] xer_ov; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output [1:0] \xer_ov$9 ; - reg [1:0] \xer_ov$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output [1:0] \xer_ov$13 ; + reg [1:0] \xer_ov$13 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_ov_ok; reg xer_ov_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input xer_so; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) - output \xer_so$8 ; - reg \xer_so$8 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output \xer_so$12 ; + reg \xer_so$12 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output xer_so_ok; reg xer_so_ok; - assign \$11 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) 10'h001; - assign \$13 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) 10'h001; assign \$15 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) 10'h001; assign \$17 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) 10'h001; assign \$19 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) 10'h001; assign \$21 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) 10'h001; - assign \$23 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:90" *) 10'h001; + assign \$23 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) 10'h001; + assign \$25 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) 10'h001; + assign \$27 = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:90" *) 10'h001; always @* begin if (\initial ) begin end - \fast1$7 = 64'h0000000000000000; + \fast1$11 = 64'h0000000000000000; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" *) casez (spr_op__insn_type) /* \nmigen.decoding = "OP_MTSPR/49" */ @@ -190172,7 +203865,7 @@ module spr_main(spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32b casez (spr) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:60" */ 10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016: - \fast1$7 = ra; + \fast1$11 = ra; endcase endcase end @@ -190219,7 +203912,7 @@ module spr_main(spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32b begin o = fast1; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:90" *) - casez (\$23 ) + casez (\$27 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:90" */ 1'h1: begin @@ -190261,7 +203954,7 @@ module spr_main(spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32b end always @* begin if (\initial ) begin end - \xer_so$8 = 1'h0; + \xer_so$12 = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" *) casez (spr_op__insn_type) /* \nmigen.decoding = "OP_MTSPR/49" */ @@ -190272,10 +203965,10 @@ module spr_main(spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32b /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:60" */ 10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016: (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) - casez (\$11 ) + casez (\$15 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" */ 1'h1: - \xer_so$8 = ra[31]; + \xer_so$12 = ra[31]; endcase endcase endcase @@ -190293,7 +203986,7 @@ module spr_main(spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32b /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:60" */ 10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016: (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) - casez (\$13 ) + casez (\$17 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" */ 1'h1: xer_so_ok = 1'h1; @@ -190303,7 +203996,7 @@ module spr_main(spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32b end always @* begin if (\initial ) begin end - \xer_ov$9 = 2'h0; + \xer_ov$13 = 2'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" *) casez (spr_op__insn_type) /* \nmigen.decoding = "OP_MTSPR/49" */ @@ -190314,12 +204007,12 @@ module spr_main(spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32b /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:60" */ 10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016: (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) - casez (\$15 ) + casez (\$19 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" */ 1'h1: begin - \xer_ov$9 [0] = ra[30]; - \xer_ov$9 [1] = ra[19]; + \xer_ov$13 [0] = ra[30]; + \xer_ov$13 [1] = ra[19]; end endcase endcase @@ -190338,7 +204031,7 @@ module spr_main(spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32b /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:60" */ 10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016: (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) - casez (\$17 ) + casez (\$21 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" */ 1'h1: xer_ov_ok = 1'h1; @@ -190348,7 +204041,7 @@ module spr_main(spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32b end always @* begin if (\initial ) begin end - \xer_ca$10 = 2'h0; + \xer_ca$14 = 2'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" *) casez (spr_op__insn_type) /* \nmigen.decoding = "OP_MTSPR/49" */ @@ -190359,12 +204052,12 @@ module spr_main(spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32b /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:60" */ 10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016: (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) - casez (\$19 ) + casez (\$23 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" */ 1'h1: begin - \xer_ca$10 [0] = ra[29]; - \xer_ca$10 [1] = ra[18]; + \xer_ca$14 [0] = ra[29]; + \xer_ca$14 [1] = ra[18]; end endcase endcase @@ -190383,7 +204076,7 @@ module spr_main(spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32b /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:60" */ 10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016: (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) - casez (\$21 ) + casez (\$25 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" */ 1'h1: xer_ca_ok = 1'h1; @@ -190393,7 +204086,7 @@ module spr_main(spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32b end always @* begin if (\initial ) begin end - \spr1$6 = 64'h0000000000000000; + \spr1$10 = 64'h0000000000000000; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" *) casez (spr_op__insn_type) /* \nmigen.decoding = "OP_MTSPR/49" */ @@ -190407,11 +204100,11 @@ module spr_main(spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32b /* empty */; /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:78" */ default: - \spr1$6 = ra; + \spr1$10 = ra; endcase endcase end - assign { \spr_op__is_32bit$5 , \spr_op__insn$4 , \spr_op__fn_unit$3 , \spr_op__insn_type$2 } = { spr_op__is_32bit, spr_op__insn, spr_op__fn_unit, spr_op__insn_type }; + assign { \spr_op__SV_Ptype$9 , \spr_op__sv_saturate$8 , \spr_op__sv_pred_dz$7 , \spr_op__sv_pred_sz$6 , \spr_op__is_32bit$5 , \spr_op__insn$4 , \spr_op__fn_unit$3 , \spr_op__insn_type$2 } = { spr_op__SV_Ptype, spr_op__sv_saturate, spr_op__sv_pred_dz, spr_op__sv_pred_sz, spr_op__is_32bit, spr_op__insn, spr_op__fn_unit, spr_op__insn_type }; assign \muxid$1 = muxid; assign spr = { spr_op__insn[15:11], spr_op__insn[20:16] }; endmodule @@ -190420,13 +204113,13 @@ endmodule (* generator = "nMigen" *) module sprmap(spr_o, spr_o_ok, fast_o, fast_o_ok, spr_i); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [2:0] fast_o; reg [2:0] fast_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output fast_o_ok; reg fast_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:75" *) input [9:0] spr_i; (* enum_base_type = "SPR" *) (* enum_value_0000000001 = "XER" *) @@ -190542,330 +204235,330 @@ module sprmap(spr_o, spr_o_ok, fast_o, fast_o_ok, spr_i); (* enum_value_1110000000 = "PPR" *) (* enum_value_1110000010 = "PPR32" *) (* enum_value_1111111111 = "PIR" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [9:0] spr_o; reg [9:0] spr_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output spr_o_ok; reg spr_o_ok; always @* begin if (\initial ) begin end fast_o = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:85" *) casez (spr_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h001: fast_o = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h003: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h008: fast_o = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h009: fast_o = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h00d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h011: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h012: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h013: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h016: fast_o = 3'h6; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h01a: fast_o = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h01b: fast_o = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h01c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h01d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h030: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h03d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h080: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h081: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h082: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h083: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h088: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h090: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h098: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h099: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0b0: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0b4: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0ba: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0bb: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0bc: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0be: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h100: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h103: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h10c: fast_o = 3'h7; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h10d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h110: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h111: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h112: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h113: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h130: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h131: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h132: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h133: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h134: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h135: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h136: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h139: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13a: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h150: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h151: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h152: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h153: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h15d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h1be: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h1d0: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2c0: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2d0: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h2d1: - /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + fast_o = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h300: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h301: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h302: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h303: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h304: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h305: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h306: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h307: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h308: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h310: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h311: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h312: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h313: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h314: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h315: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h316: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h317: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h318: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h320: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h321: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h322: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h323: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h324: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h325: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h326: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h328: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h329: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h32a: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h32b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h32f: fast_o = 3'h2; endcase @@ -190873,321 +204566,321 @@ module sprmap(spr_o, spr_o_ok, fast_o, fast_o_ok, spr_i); always @* begin if (\initial ) begin end fast_o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:85" *) casez (spr_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h001: fast_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h003: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h008: fast_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h009: fast_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h00d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h011: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h012: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h013: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h016: fast_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h01a: fast_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h01b: fast_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h01c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h01d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h030: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h03d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h080: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h081: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h082: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h083: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h088: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h090: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h098: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h099: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0b0: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0b4: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0ba: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0bb: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0bc: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0be: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h100: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h103: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h10c: fast_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h10d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h110: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h111: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h112: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h113: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h130: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h131: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h132: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h133: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h134: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h135: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h136: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h139: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13a: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h150: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h151: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h152: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h153: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h15d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h1be: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h1d0: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2c0: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2d0: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h2d1: - /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + fast_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h300: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h301: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h302: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h303: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h304: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h305: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h306: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h307: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h308: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h310: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h311: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h312: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h313: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h314: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h315: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h316: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h317: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h318: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h320: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h321: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h322: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h323: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h324: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h325: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h326: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h328: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h329: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h32a: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h32b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h32f: fast_o_ok = 1'h1; endcase @@ -191195,345 +204888,345 @@ module sprmap(spr_o, spr_o_ok, fast_o, fast_o_ok, spr_i); always @* begin if (\initial ) begin end spr_o = 10'h000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:85" *) casez (spr_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h001: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h003: spr_o = 10'h001; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h008: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h009: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h00d: spr_o = 10'h004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h011: spr_o = 10'h005; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h012: spr_o = 10'h006; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h013: spr_o = 10'h007; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h016: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h01a: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h01b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h01c: spr_o = 10'h00b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h01d: spr_o = 10'h00c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h030: spr_o = 10'h00d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h03d: spr_o = 10'h00e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h080: spr_o = 10'h00f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h081: spr_o = 10'h010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h082: spr_o = 10'h011; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h083: spr_o = 10'h012; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h088: spr_o = 10'h013; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h090: spr_o = 10'h014; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h098: spr_o = 10'h015; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h099: spr_o = 10'h016; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09d: spr_o = 10'h017; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09e: spr_o = 10'h018; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09f: spr_o = 10'h019; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0b0: spr_o = 10'h01a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0b4: spr_o = 10'h01b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0ba: spr_o = 10'h01c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0bb: spr_o = 10'h01d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0bc: spr_o = 10'h01e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0be: spr_o = 10'h01f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h100: spr_o = 10'h020; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h103: spr_o = 10'h021; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h10c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h10d: spr_o = 10'h023; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h110: spr_o = 10'h024; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h111: spr_o = 10'h025; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h112: spr_o = 10'h026; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h113: spr_o = 10'h027; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11b: spr_o = 10'h028; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11c: spr_o = 10'h029; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11d: spr_o = 10'h02a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11e: spr_o = 10'h02b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11f: spr_o = 10'h02c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h130: spr_o = 10'h02d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h131: spr_o = 10'h02e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h132: spr_o = 10'h02f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h133: spr_o = 10'h030; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h134: spr_o = 10'h031; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h135: spr_o = 10'h032; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h136: spr_o = 10'h033; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h139: spr_o = 10'h034; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13a: spr_o = 10'h035; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13b: spr_o = 10'h036; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13e: spr_o = 10'h037; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13f: spr_o = 10'h038; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h150: spr_o = 10'h039; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h151: spr_o = 10'h03a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h152: spr_o = 10'h03b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h153: spr_o = 10'h03c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h15d: spr_o = 10'h03d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h1be: spr_o = 10'h03e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h1d0: spr_o = 10'h03f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2c0: spr_o = 10'h040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2d0: spr_o = 10'h041; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h2d1: - spr_o = 10'h042; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* empty */; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h300: spr_o = 10'h043; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h301: spr_o = 10'h044; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h302: spr_o = 10'h045; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h303: spr_o = 10'h046; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h304: spr_o = 10'h047; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h305: spr_o = 10'h048; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h306: spr_o = 10'h049; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h307: spr_o = 10'h04a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h308: spr_o = 10'h04b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30b: spr_o = 10'h04c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30c: spr_o = 10'h04d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30d: spr_o = 10'h04e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30e: spr_o = 10'h04f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h310: spr_o = 10'h050; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h311: spr_o = 10'h051; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h312: spr_o = 10'h052; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h313: spr_o = 10'h053; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h314: spr_o = 10'h054; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h315: spr_o = 10'h055; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h316: spr_o = 10'h056; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h317: spr_o = 10'h057; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h318: spr_o = 10'h058; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31b: spr_o = 10'h059; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31c: spr_o = 10'h05a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31d: spr_o = 10'h05b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31e: spr_o = 10'h05c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h320: spr_o = 10'h05d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h321: spr_o = 10'h05e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h322: spr_o = 10'h05f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h323: spr_o = 10'h060; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h324: spr_o = 10'h061; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h325: spr_o = 10'h062; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h326: spr_o = 10'h063; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h328: spr_o = 10'h064; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h329: spr_o = 10'h065; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h32a: spr_o = 10'h066; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h32b: spr_o = 10'h067; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h32f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h330: spr_o = 10'h069; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h337: spr_o = 10'h06a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h350: spr_o = 10'h06b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h351: spr_o = 10'h06c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h357: spr_o = 10'h06d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h380: spr_o = 10'h06e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h382: spr_o = 10'h06f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h3ff: spr_o = 10'h070; endcase @@ -191541,345 +205234,345 @@ module sprmap(spr_o, spr_o_ok, fast_o, fast_o_ok, spr_i); always @* begin if (\initial ) begin end spr_o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:85" *) casez (spr_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h001: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h003: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h008: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h009: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h00d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h011: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h012: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h013: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h016: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h01a: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h01b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h01c: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h01d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h030: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h03d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h080: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h081: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h082: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h083: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h088: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h090: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h098: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h099: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09e: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09f: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0b0: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0b4: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0ba: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0bb: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0bc: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0be: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h100: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h103: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h10c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h10d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h110: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h111: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h112: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h113: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11b: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11c: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11e: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11f: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h130: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h131: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h132: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h133: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h134: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h135: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h136: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h139: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13a: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13b: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13e: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13f: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h150: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h151: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h152: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h153: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h15d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h1be: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h1d0: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2c0: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2d0: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h2d1: - spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* empty */; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h300: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h301: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h302: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h303: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h304: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h305: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h306: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h307: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h308: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30b: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30c: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30e: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h310: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h311: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h312: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h313: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h314: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h315: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h316: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h317: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h318: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31b: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31c: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31e: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h320: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h321: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h322: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h323: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h324: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h325: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h326: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h328: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h329: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h32a: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h32b: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h32f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h330: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h337: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h350: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h351: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h357: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h380: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h382: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h3ff: spr_o_ok = 1'h1; endcase @@ -191890,13 +205583,13 @@ endmodule (* generator = "nMigen" *) module \sprmap$174 (spr_o, spr_o_ok, fast_o, fast_o_ok, spr_i); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [2:0] fast_o; reg [2:0] fast_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output fast_o_ok; reg fast_o_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:75" *) input [9:0] spr_i; (* enum_base_type = "SPR" *) (* enum_value_0000000001 = "XER" *) @@ -192012,330 +205705,330 @@ module \sprmap$174 (spr_o, spr_o_ok, fast_o, fast_o_ok, spr_i); (* enum_value_1110000000 = "PPR" *) (* enum_value_1110000010 = "PPR32" *) (* enum_value_1111111111 = "PIR" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [9:0] spr_o; reg [9:0] spr_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output spr_o_ok; reg spr_o_ok; always @* begin if (\initial ) begin end fast_o = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:85" *) casez (spr_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h001: fast_o = 3'h5; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h003: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h008: fast_o = 3'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h009: fast_o = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h00d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h011: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h012: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h013: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h016: fast_o = 3'h6; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h01a: fast_o = 3'h3; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h01b: fast_o = 3'h4; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h01c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h01d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h030: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h03d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h080: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h081: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h082: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h083: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h088: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h090: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h098: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h099: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0b0: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0b4: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0ba: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0bb: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0bc: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0be: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h100: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h103: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h10c: fast_o = 3'h7; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h10d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h110: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h111: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h112: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h113: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h130: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h131: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h132: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h133: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h134: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h135: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h136: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h139: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13a: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h150: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h151: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h152: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h153: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h15d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h1be: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h1d0: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2c0: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2d0: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h2d1: - /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + fast_o = 3'h0; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h300: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h301: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h302: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h303: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h304: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h305: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h306: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h307: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h308: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h310: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h311: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h312: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h313: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h314: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h315: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h316: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h317: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h318: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h320: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h321: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h322: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h323: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h324: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h325: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h326: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h328: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h329: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h32a: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h32b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h32f: fast_o = 3'h2; endcase @@ -192343,321 +206036,321 @@ module \sprmap$174 (spr_o, spr_o_ok, fast_o, fast_o_ok, spr_i); always @* begin if (\initial ) begin end fast_o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:85" *) casez (spr_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h001: fast_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h003: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h008: fast_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h009: fast_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h00d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h011: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h012: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h013: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h016: fast_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h01a: fast_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h01b: fast_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h01c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h01d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h030: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h03d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h080: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h081: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h082: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h083: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h088: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h090: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h098: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h099: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0b0: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0b4: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0ba: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0bb: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0bc: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0be: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h100: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h103: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h10c: fast_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h10d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h110: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h111: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h112: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h113: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h130: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h131: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h132: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h133: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h134: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h135: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h136: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h139: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13a: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h150: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h151: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h152: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h153: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h15d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h1be: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h1d0: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2c0: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2d0: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h2d1: - /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + fast_o_ok = 1'h1; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h300: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h301: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h302: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h303: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h304: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h305: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h306: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h307: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h308: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h310: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h311: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h312: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h313: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h314: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h315: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h316: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h317: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h318: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31d: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31e: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h320: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h321: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h322: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h323: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h324: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h325: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h326: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h328: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h329: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h32a: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h32b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h32f: fast_o_ok = 1'h1; endcase @@ -192665,345 +206358,345 @@ module \sprmap$174 (spr_o, spr_o_ok, fast_o, fast_o_ok, spr_i); always @* begin if (\initial ) begin end spr_o = 10'h000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:85" *) casez (spr_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h001: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h003: spr_o = 10'h001; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h008: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h009: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h00d: spr_o = 10'h004; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h011: spr_o = 10'h005; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h012: spr_o = 10'h006; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h013: spr_o = 10'h007; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h016: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h01a: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h01b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h01c: spr_o = 10'h00b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h01d: spr_o = 10'h00c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h030: spr_o = 10'h00d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h03d: spr_o = 10'h00e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h080: spr_o = 10'h00f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h081: spr_o = 10'h010; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h082: spr_o = 10'h011; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h083: spr_o = 10'h012; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h088: spr_o = 10'h013; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h090: spr_o = 10'h014; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h098: spr_o = 10'h015; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h099: spr_o = 10'h016; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09d: spr_o = 10'h017; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09e: spr_o = 10'h018; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09f: spr_o = 10'h019; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0b0: spr_o = 10'h01a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0b4: spr_o = 10'h01b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0ba: spr_o = 10'h01c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0bb: spr_o = 10'h01d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0bc: spr_o = 10'h01e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0be: spr_o = 10'h01f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h100: spr_o = 10'h020; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h103: spr_o = 10'h021; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h10c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h10d: spr_o = 10'h023; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h110: spr_o = 10'h024; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h111: spr_o = 10'h025; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h112: spr_o = 10'h026; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h113: spr_o = 10'h027; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11b: spr_o = 10'h028; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11c: spr_o = 10'h029; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11d: spr_o = 10'h02a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11e: spr_o = 10'h02b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11f: spr_o = 10'h02c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h130: spr_o = 10'h02d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h131: spr_o = 10'h02e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h132: spr_o = 10'h02f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h133: spr_o = 10'h030; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h134: spr_o = 10'h031; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h135: spr_o = 10'h032; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h136: spr_o = 10'h033; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h139: spr_o = 10'h034; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13a: spr_o = 10'h035; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13b: spr_o = 10'h036; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13e: spr_o = 10'h037; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13f: spr_o = 10'h038; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h150: spr_o = 10'h039; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h151: spr_o = 10'h03a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h152: spr_o = 10'h03b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h153: spr_o = 10'h03c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h15d: spr_o = 10'h03d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h1be: spr_o = 10'h03e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h1d0: spr_o = 10'h03f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2c0: spr_o = 10'h040; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2d0: spr_o = 10'h041; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h2d1: - spr_o = 10'h042; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* empty */; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h300: spr_o = 10'h043; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h301: spr_o = 10'h044; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h302: spr_o = 10'h045; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h303: spr_o = 10'h046; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h304: spr_o = 10'h047; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h305: spr_o = 10'h048; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h306: spr_o = 10'h049; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h307: spr_o = 10'h04a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h308: spr_o = 10'h04b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30b: spr_o = 10'h04c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30c: spr_o = 10'h04d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30d: spr_o = 10'h04e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30e: spr_o = 10'h04f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h310: spr_o = 10'h050; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h311: spr_o = 10'h051; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h312: spr_o = 10'h052; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h313: spr_o = 10'h053; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h314: spr_o = 10'h054; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h315: spr_o = 10'h055; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h316: spr_o = 10'h056; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h317: spr_o = 10'h057; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h318: spr_o = 10'h058; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31b: spr_o = 10'h059; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31c: spr_o = 10'h05a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31d: spr_o = 10'h05b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31e: spr_o = 10'h05c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h320: spr_o = 10'h05d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h321: spr_o = 10'h05e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h322: spr_o = 10'h05f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h323: spr_o = 10'h060; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h324: spr_o = 10'h061; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h325: spr_o = 10'h062; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h326: spr_o = 10'h063; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h328: spr_o = 10'h064; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h329: spr_o = 10'h065; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h32a: spr_o = 10'h066; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h32b: spr_o = 10'h067; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h32f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h330: spr_o = 10'h069; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h337: spr_o = 10'h06a; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h350: spr_o = 10'h06b; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h351: spr_o = 10'h06c; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h357: spr_o = 10'h06d; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h380: spr_o = 10'h06e; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h382: spr_o = 10'h06f; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h3ff: spr_o = 10'h070; endcase @@ -193011,927 +206704,351 @@ module \sprmap$174 (spr_o, spr_o_ok, fast_o, fast_o_ok, spr_i); always @* begin if (\initial ) begin end spr_o_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:85" *) casez (spr_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h001: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h003: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h008: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h009: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h00d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h011: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h012: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h013: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h016: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h01a: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h01b: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h01c: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h01d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h030: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h03d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h080: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h081: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h082: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h083: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h088: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h090: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h098: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h099: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09e: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h09f: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0b0: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0b4: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0ba: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0bb: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0bc: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h0be: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h100: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h103: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h10c: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h10d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h110: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h111: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h112: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h113: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11b: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11c: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11e: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h11f: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h130: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h131: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h132: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h133: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h134: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h135: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h136: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h139: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13a: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13b: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13e: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h13f: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h150: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h151: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h152: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h153: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h15d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h1be: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h1d0: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2c0: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h2d0: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h2d1: - spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* empty */; + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h300: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h301: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h302: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h303: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h304: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h305: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h306: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h307: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h308: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30b: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30c: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h30e: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h310: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h311: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h312: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h313: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h314: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h315: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h316: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h317: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h318: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31b: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31c: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31d: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h31e: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h320: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h321: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h322: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h323: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h324: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h325: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h326: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h328: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h329: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h32a: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h32b: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:91" */ 10'h32f: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h330: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h337: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h350: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h351: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h357: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h380: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h382: spr_o_ok = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" */ + /* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder2.py:87" */ 10'h3ff: spr_o_ok = 1'h1; endcase end endmodule -(* \nmigen.hierarchy = "test_issuer.ti.sram4k_0" *) -(* generator = "nMigen" *) -module sram4k_0(rst, enable, sram4k_0_wb__cyc, sram4k_0_wb__stb, sram4k_0_wb__ack, sram4k_0_wb__adr, sram4k_0_wb__dat_r, sram4k_0_wb__dat_w, sram4k_0_wb__we, sram4k_0_wb__sel, clk); - reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) - wire \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" *) - reg [8:0] a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *) - input clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" *) - reg [63:0] d; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" *) - input enable; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" *) - wire [63:0] q; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *) - input rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - output sram4k_0_wb__ack; - reg sram4k_0_wb__ack = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - reg \sram4k_0_wb__ack$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [8:0] sram4k_0_wb__adr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_0_wb__cyc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - output [63:0] sram4k_0_wb__dat_r; - reg [63:0] sram4k_0_wb__dat_r; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [63:0] sram4k_0_wb__dat_w; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [7:0] sram4k_0_wb__sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_0_wb__stb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_0_wb__we; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55" *) - reg wb_active; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" *) - reg [7:0] we; - assign \$1 = sram4k_0_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_0_wb__stb; - always @(posedge clk) - sram4k_0_wb__ack <= \sram4k_0_wb__ack$next ; - spblock_512w64b8w spblock_512w64b8w_3 ( - .a(a), - .clk(clk), - .d(d), - .q(q), - .we(we) - ); - always @* begin - if (\initial ) begin end - wb_active = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) - casez (enable) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ - 1'h1: - wb_active = \$1 ; - endcase - end - always @* begin - if (\initial ) begin end - \sram4k_0_wb__ack$next = sram4k_0_wb__ack; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) - casez (enable) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ - 1'h1: - \sram4k_0_wb__ack$next = wb_active; - endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) - casez (rst) - 1'h1: - \sram4k_0_wb__ack$next = 1'h0; - endcase - end - always @* begin - if (\initial ) begin end - a = 9'h000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) - casez (enable) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ - 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) - casez (wb_active) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" */ - 1'h1: - a = sram4k_0_wb__adr; - endcase - endcase - end - always @* begin - if (\initial ) begin end - sram4k_0_wb__dat_r = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) - casez (enable) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ - 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) - casez (wb_active) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" */ - 1'h1: - sram4k_0_wb__dat_r = q; - endcase - endcase - end - always @* begin - if (\initial ) begin end - d = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) - casez (enable) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ - 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) - casez (wb_active) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" */ - 1'h1: - d = sram4k_0_wb__dat_w; - endcase - endcase - end - always @* begin - if (\initial ) begin end - we = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) - casez (enable) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ - 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) - casez (wb_active) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" */ - 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:71" *) - casez (sram4k_0_wb__we) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:71" */ - 1'h1: - we = sram4k_0_wb__sel; - endcase - endcase - endcase - end -endmodule - -(* \nmigen.hierarchy = "test_issuer.ti.sram4k_1" *) -(* generator = "nMigen" *) -module sram4k_1(rst, enable, sram4k_1_wb__cyc, sram4k_1_wb__stb, sram4k_1_wb__ack, sram4k_1_wb__adr, sram4k_1_wb__dat_r, sram4k_1_wb__dat_w, sram4k_1_wb__we, sram4k_1_wb__sel, clk); - reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) - wire \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" *) - reg [8:0] a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *) - input clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" *) - reg [63:0] d; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" *) - input enable; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" *) - wire [63:0] q; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *) - input rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - output sram4k_1_wb__ack; - reg sram4k_1_wb__ack = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - reg \sram4k_1_wb__ack$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [8:0] sram4k_1_wb__adr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_1_wb__cyc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - output [63:0] sram4k_1_wb__dat_r; - reg [63:0] sram4k_1_wb__dat_r; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [63:0] sram4k_1_wb__dat_w; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [7:0] sram4k_1_wb__sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_1_wb__stb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_1_wb__we; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55" *) - reg wb_active; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" *) - reg [7:0] we; - assign \$1 = sram4k_1_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_1_wb__stb; - always @(posedge clk) - sram4k_1_wb__ack <= \sram4k_1_wb__ack$next ; - spblock_512w64b8w spblock_512w64b8w_0 ( - .a(a), - .clk(clk), - .d(d), - .q(q), - .we(we) - ); - always @* begin - if (\initial ) begin end - wb_active = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) - casez (enable) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ - 1'h1: - wb_active = \$1 ; - endcase - end - always @* begin - if (\initial ) begin end - \sram4k_1_wb__ack$next = sram4k_1_wb__ack; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) - casez (enable) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ - 1'h1: - \sram4k_1_wb__ack$next = wb_active; - endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) - casez (rst) - 1'h1: - \sram4k_1_wb__ack$next = 1'h0; - endcase - end - always @* begin - if (\initial ) begin end - a = 9'h000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) - casez (enable) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ - 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) - casez (wb_active) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" */ - 1'h1: - a = sram4k_1_wb__adr; - endcase - endcase - end - always @* begin - if (\initial ) begin end - sram4k_1_wb__dat_r = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) - casez (enable) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ - 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) - casez (wb_active) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" */ - 1'h1: - sram4k_1_wb__dat_r = q; - endcase - endcase - end - always @* begin - if (\initial ) begin end - d = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) - casez (enable) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ - 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) - casez (wb_active) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" */ - 1'h1: - d = sram4k_1_wb__dat_w; - endcase - endcase - end - always @* begin - if (\initial ) begin end - we = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) - casez (enable) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ - 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) - casez (wb_active) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" */ - 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:71" *) - casez (sram4k_1_wb__we) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:71" */ - 1'h1: - we = sram4k_1_wb__sel; - endcase - endcase - endcase - end -endmodule - -(* \nmigen.hierarchy = "test_issuer.ti.sram4k_2" *) -(* generator = "nMigen" *) -module sram4k_2(rst, enable, sram4k_2_wb__cyc, sram4k_2_wb__stb, sram4k_2_wb__ack, sram4k_2_wb__adr, sram4k_2_wb__dat_r, sram4k_2_wb__dat_w, sram4k_2_wb__we, sram4k_2_wb__sel, clk); - reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) - wire \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" *) - reg [8:0] a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *) - input clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" *) - reg [63:0] d; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" *) - input enable; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" *) - wire [63:0] q; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *) - input rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - output sram4k_2_wb__ack; - reg sram4k_2_wb__ack = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - reg \sram4k_2_wb__ack$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [8:0] sram4k_2_wb__adr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_2_wb__cyc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - output [63:0] sram4k_2_wb__dat_r; - reg [63:0] sram4k_2_wb__dat_r; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [63:0] sram4k_2_wb__dat_w; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [7:0] sram4k_2_wb__sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_2_wb__stb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_2_wb__we; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55" *) - reg wb_active; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" *) - reg [7:0] we; - assign \$1 = sram4k_2_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_2_wb__stb; - always @(posedge clk) - sram4k_2_wb__ack <= \sram4k_2_wb__ack$next ; - spblock_512w64b8w spblock_512w64b8w_1 ( - .a(a), - .clk(clk), - .d(d), - .q(q), - .we(we) - ); - always @* begin - if (\initial ) begin end - wb_active = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) - casez (enable) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ - 1'h1: - wb_active = \$1 ; - endcase - end - always @* begin - if (\initial ) begin end - \sram4k_2_wb__ack$next = sram4k_2_wb__ack; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) - casez (enable) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ - 1'h1: - \sram4k_2_wb__ack$next = wb_active; - endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) - casez (rst) - 1'h1: - \sram4k_2_wb__ack$next = 1'h0; - endcase - end - always @* begin - if (\initial ) begin end - a = 9'h000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) - casez (enable) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ - 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) - casez (wb_active) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" */ - 1'h1: - a = sram4k_2_wb__adr; - endcase - endcase - end - always @* begin - if (\initial ) begin end - sram4k_2_wb__dat_r = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) - casez (enable) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ - 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) - casez (wb_active) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" */ - 1'h1: - sram4k_2_wb__dat_r = q; - endcase - endcase - end - always @* begin - if (\initial ) begin end - d = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) - casez (enable) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ - 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) - casez (wb_active) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" */ - 1'h1: - d = sram4k_2_wb__dat_w; - endcase - endcase - end - always @* begin - if (\initial ) begin end - we = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) - casez (enable) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ - 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) - casez (wb_active) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" */ - 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:71" *) - casez (sram4k_2_wb__we) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:71" */ - 1'h1: - we = sram4k_2_wb__sel; - endcase - endcase - endcase - end -endmodule - -(* \nmigen.hierarchy = "test_issuer.ti.sram4k_3" *) -(* generator = "nMigen" *) -module sram4k_3(rst, enable, sram4k_3_wb__cyc, sram4k_3_wb__stb, sram4k_3_wb__ack, sram4k_3_wb__adr, sram4k_3_wb__dat_r, sram4k_3_wb__dat_w, sram4k_3_wb__we, sram4k_3_wb__sel, clk); - reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) - wire \$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" *) - reg [8:0] a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *) - input clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" *) - reg [63:0] d; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" *) - input enable; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" *) - wire [63:0] q; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *) - input rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - output sram4k_3_wb__ack; - reg sram4k_3_wb__ack = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - reg \sram4k_3_wb__ack$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [8:0] sram4k_3_wb__adr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_3_wb__cyc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - output [63:0] sram4k_3_wb__dat_r; - reg [63:0] sram4k_3_wb__dat_r; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [63:0] sram4k_3_wb__dat_w; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [7:0] sram4k_3_wb__sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_3_wb__stb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_3_wb__we; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55" *) - reg wb_active; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" *) - reg [7:0] we; - assign \$1 = sram4k_3_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_3_wb__stb; - always @(posedge clk) - sram4k_3_wb__ack <= \sram4k_3_wb__ack$next ; - spblock_512w64b8w spblock_512w64b8w_2 ( - .a(a), - .clk(clk), - .d(d), - .q(q), - .we(we) - ); - always @* begin - if (\initial ) begin end - wb_active = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) - casez (enable) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ - 1'h1: - wb_active = \$1 ; - endcase - end - always @* begin - if (\initial ) begin end - \sram4k_3_wb__ack$next = sram4k_3_wb__ack; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) - casez (enable) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ - 1'h1: - \sram4k_3_wb__ack$next = wb_active; - endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) - casez (rst) - 1'h1: - \sram4k_3_wb__ack$next = 1'h0; - endcase - end - always @* begin - if (\initial ) begin end - a = 9'h000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) - casez (enable) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ - 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) - casez (wb_active) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" */ - 1'h1: - a = sram4k_3_wb__adr; - endcase - endcase - end - always @* begin - if (\initial ) begin end - sram4k_3_wb__dat_r = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) - casez (enable) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ - 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) - casez (wb_active) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" */ - 1'h1: - sram4k_3_wb__dat_r = q; - endcase - endcase - end - always @* begin - if (\initial ) begin end - d = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) - casez (enable) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ - 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) - casez (wb_active) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" */ - 1'h1: - d = sram4k_3_wb__dat_w; - endcase - endcase - end - always @* begin - if (\initial ) begin end - we = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" *) - casez (enable) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" */ - 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" *) - casez (wb_active) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" */ - 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:71" *) - casez (sram4k_3_wb__we) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:71" */ - 1'h1: - we = sram4k_3_wb__sel; - endcase - endcase - endcase - end -endmodule - (* \nmigen.hierarchy = "test_issuer.ti.core.fus.alu0.src_l" *) (* generator = "nMigen" *) module src_l(coresync_rst, s_src, r_src, q_src, coresync_clk); @@ -193952,9 +207069,9 @@ module src_l(coresync_rst, s_src, r_src, q_src, coresync_clk); wire [3:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [3:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [3:0] q_int = 4'h0; @@ -193983,7 +207100,7 @@ module src_l(coresync_rst, s_src, r_src, q_src, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 4'h0; @@ -194014,9 +207131,9 @@ module \src_l$10 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [5:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [5:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [5:0] q_int = 6'h00; @@ -194045,7 +207162,7 @@ module \src_l$10 (coresync_rst, s_src, r_src, q_src, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 6'h00; @@ -194076,9 +207193,9 @@ module \src_l$101 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [2:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [2:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [2:0] q_int = 3'h0; @@ -194107,7 +207224,7 @@ module \src_l$101 (coresync_rst, s_src, r_src, q_src, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 3'h0; @@ -194138,9 +207255,9 @@ module \src_l$119 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [4:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [4:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [4:0] q_int = 5'h00; @@ -194169,7 +207286,7 @@ module \src_l$119 (coresync_rst, s_src, r_src, q_src, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 5'h00; @@ -194200,9 +207317,9 @@ module \src_l$127 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [2:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [2:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [2:0] q_int = 3'h0; @@ -194231,7 +207348,7 @@ module \src_l$127 (coresync_rst, s_src, r_src, q_src, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 3'h0; @@ -194262,9 +207379,9 @@ module \src_l$23 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [2:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [2:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [2:0] q_int = 3'h0; @@ -194293,7 +207410,7 @@ module \src_l$23 (coresync_rst, s_src, r_src, q_src, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 3'h0; @@ -194309,39 +207426,39 @@ endmodule module \src_l$39 (coresync_rst, s_src, r_src, q_src, coresync_clk); reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) - wire [3:0] \$1 ; + wire [4:0] \$1 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) - wire [3:0] \$11 ; + wire [4:0] \$11 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) - wire [3:0] \$13 ; + wire [4:0] \$13 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) - wire [3:0] \$15 ; + wire [4:0] \$15 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) - wire [3:0] \$3 ; + wire [4:0] \$3 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) - wire [3:0] \$5 ; + wire [4:0] \$5 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) - wire [3:0] \$7 ; + wire [4:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) - wire [3:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + wire [4:0] \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) - reg [3:0] q_int = 4'h0; + reg [4:0] q_int = 5'h00; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) - reg [3:0] \q_int$next ; + reg [4:0] \q_int$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) - output [3:0] q_src; + output [4:0] q_src; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *) - wire [3:0] qlq_src; + wire [4:0] qlq_src; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *) - wire [3:0] qn_src; + wire [4:0] qn_src; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) - input [3:0] r_src; + input [4:0] r_src; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) - input [3:0] s_src; + input [4:0] s_src; assign \$9 = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ; assign \$11 = \$9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_src; assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_src; @@ -194355,10 +207472,10 @@ module \src_l$39 (coresync_rst, s_src, r_src, q_src, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \q_int$next = 4'h0; + \q_int$next = 5'h00; endcase end assign qlq_src = \$15 ; @@ -194386,9 +207503,9 @@ module \src_l$55 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [2:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [2:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [2:0] q_int = 3'h0; @@ -194417,7 +207534,7 @@ module \src_l$55 (coresync_rst, s_src, r_src, q_src, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 3'h0; @@ -194448,9 +207565,9 @@ module \src_l$67 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [5:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [5:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [5:0] q_int = 6'h00; @@ -194479,7 +207596,7 @@ module \src_l$67 (coresync_rst, s_src, r_src, q_src, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 6'h00; @@ -194510,9 +207627,9 @@ module \src_l$84 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [2:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [2:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [2:0] q_int = 3'h0; @@ -194541,7 +207658,7 @@ module \src_l$84 (coresync_rst, s_src, r_src, q_src, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 3'h0; @@ -194572,9 +207689,9 @@ module st_active(coresync_rst, r_st_active, s_st_active, q_st_active, coresync_c wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -194603,7 +207720,7 @@ module st_active(coresync_rst, r_st_active, s_st_active, q_st_active, coresync_c always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -194634,9 +207751,9 @@ module st_done(coresync_rst, s_st_done, r_st_done, q_st_done, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -194665,7 +207782,7 @@ module st_done(coresync_rst, s_st_done, r_st_done, q_st_done, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -194678,34 +207795,34 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.state" *) (* generator = "nMigen" *) -module state(coresync_rst, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data_i, msr__ren, msr__data_o, \wen$1 , \data_i$2 , state_nia_wen, \data_i$3 , \data_i$4 , \wen$5 , coresync_clk); +module state(coresync_rst, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data_i, msr__ren, msr__data_o, \wen$1 , \data_i$2 , state_nia_wen, \data_i$3 , \data_i$4 , \wen$5 , \data_i$6 , \wen$7 , coresync_clk); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) wire [63:0] \$10 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [63:0] \$12 ; (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) - wire \$13 ; + wire \$15 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [63:0] \$15 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) wire [63:0] \$17 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [63:0] \$19 ; (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) - wire \$20 ; + wire \$22 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [63:0] \$22 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) wire [63:0] \$24 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) + wire [63:0] \$26 ; (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) - wire \$6 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) - wire [63:0] \$8 ; + wire \$8 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) output [63:0] cia__data_o; reg [63:0] cia__data_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [2:0] cia__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [63:0] data_i; @@ -194716,6 +207833,8 @@ module state(coresync_rst, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [63:0] \data_i$4 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [63:0] \data_i$6 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) output [63:0] msr__data_o; reg [63:0] msr__data_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) @@ -194749,6 +207868,10 @@ module state(coresync_rst, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire reg_0_sv0__wen; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] reg_0_svstate0__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_0_svstate0__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [63:0] reg_1_cia1__data_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire reg_1_cia1__ren; @@ -194777,6 +207900,10 @@ module state(coresync_rst, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire reg_1_sv1__wen; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] reg_1_svstate1__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_1_svstate1__wen; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [63:0] reg_2_cia2__data_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire reg_2_cia2__ren; @@ -194804,17 +207931,21 @@ module state(coresync_rst, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data wire reg_2_sv2__ren; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire reg_2_sv2__wen; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] reg_2_svstate2__data_i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire reg_2_svstate2__wen; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) reg [2:0] ren_delay = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) - reg [2:0] \ren_delay$12 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) - reg [2:0] \ren_delay$12$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) - reg [2:0] \ren_delay$19 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) - reg [2:0] \ren_delay$19$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) + reg [2:0] \ren_delay$14 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) + reg [2:0] \ren_delay$14$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) + reg [2:0] \ren_delay$21 = 3'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) + reg [2:0] \ren_delay$21$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) reg [2:0] \ren_delay$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [2:0] state_nia_wen; @@ -194829,19 +207960,21 @@ module state(coresync_rst, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data input [2:0] \wen$1 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [2:0] \wen$5 ; - assign \$10 = reg_0_cia0__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$8 ; - assign \$13 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \ren_delay$12 ; - assign \$15 = reg_1_msr1__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_2_msr2__data_o; - assign \$17 = reg_0_msr0__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$15 ; - assign \$20 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \ren_delay$19 ; - assign \$22 = reg_1_sv1__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_2_sv2__data_o; - assign \$24 = reg_0_sv0__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$22 ; - assign \$6 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) ren_delay; - assign \$8 = reg_1_cia1__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_2_cia2__data_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + input [2:0] \wen$7 ; + assign \$10 = reg_1_cia1__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_2_cia2__data_o; + assign \$12 = reg_0_cia0__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$10 ; + assign \$15 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \ren_delay$14 ; + assign \$17 = reg_1_msr1__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_2_msr2__data_o; + assign \$19 = reg_0_msr0__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$17 ; + assign \$22 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \ren_delay$21 ; + assign \$24 = reg_1_sv1__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_2_sv2__data_o; + assign \$26 = reg_0_sv0__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$24 ; + assign \$8 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) ren_delay; always @(posedge coresync_clk) - \ren_delay$19 <= \ren_delay$19$next ; + \ren_delay$21 <= \ren_delay$21$next ; always @(posedge coresync_clk) - \ren_delay$12 <= \ren_delay$12$next ; + \ren_delay$14 <= \ren_delay$14$next ; always @(posedge coresync_clk) ren_delay <= \ren_delay$next ; \reg_0$135 reg_0 ( @@ -194860,7 +207993,9 @@ module state(coresync_rst, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data .sv0__data_i(reg_0_sv0__data_i), .sv0__data_o(reg_0_sv0__data_o), .sv0__ren(reg_0_sv0__ren), - .sv0__wen(reg_0_sv0__wen) + .sv0__wen(reg_0_sv0__wen), + .svstate0__data_i(reg_0_svstate0__data_i), + .svstate0__wen(reg_0_svstate0__wen) ); \reg_1$136 reg_1 ( .cia1__data_o(reg_1_cia1__data_o), @@ -194878,7 +208013,9 @@ module state(coresync_rst, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data .sv1__data_i(reg_1_sv1__data_i), .sv1__data_o(reg_1_sv1__data_o), .sv1__ren(reg_1_sv1__ren), - .sv1__wen(reg_1_sv1__wen) + .sv1__wen(reg_1_sv1__wen), + .svstate1__data_i(reg_1_svstate1__data_i), + .svstate1__wen(reg_1_svstate1__wen) ); \reg_2$137 reg_2 ( .cia2__data_o(reg_2_cia2__data_o), @@ -194896,31 +208033,33 @@ module state(coresync_rst, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data .sv2__data_i(reg_2_sv2__data_i), .sv2__data_o(reg_2_sv2__data_o), .sv2__ren(reg_2_sv2__ren), - .sv2__wen(reg_2_sv2__wen) + .sv2__wen(reg_2_sv2__wen), + .svstate2__data_i(reg_2_svstate2__data_i), + .svstate2__wen(reg_2_svstate2__wen) ); always @* begin if (\initial ) begin end - \ren_delay$19$next = sv__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \ren_delay$21$next = sv__ren; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \ren_delay$19$next = 3'h0; + \ren_delay$21$next = 3'h0; endcase end always @* begin if (\initial ) begin end sv__data_o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *) - casez (\$20 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" *) + casez (\$22 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" */ 1'h1: - sv__data_o = \$24 ; + sv__data_o = \$26 ; endcase end always @* begin if (\initial ) begin end \ren_delay$next = cia__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \ren_delay$next = 3'h0; @@ -194929,30 +208068,30 @@ module state(coresync_rst, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data always @* begin if (\initial ) begin end cia__data_o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *) - casez (\$6 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" *) + casez (\$8 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" */ 1'h1: - cia__data_o = \$10 ; + cia__data_o = \$12 ; endcase end always @* begin if (\initial ) begin end - \ren_delay$12$next = msr__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \ren_delay$14$next = msr__ren; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \ren_delay$12$next = 3'h0; + \ren_delay$14$next = 3'h0; endcase end always @* begin if (\initial ) begin end msr__data_o = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *) - casez (\$13 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" *) + casez (\$15 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" */ 1'h1: - msr__data_o = \$17 ; + msr__data_o = \$19 ; endcase end assign reg_2_d_wr12__data_i = data_i; @@ -194963,6 +208102,10 @@ module state(coresync_rst, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data assign reg_1_sv1__data_i = \data_i$2 ; assign reg_0_sv0__data_i = \data_i$2 ; assign { reg_2_sv2__wen, reg_1_sv1__wen, reg_0_sv0__wen } = \wen$1 ; + assign reg_2_svstate2__data_i = \data_i$6 ; + assign reg_1_svstate1__data_i = \data_i$6 ; + assign reg_0_svstate0__data_i = \data_i$6 ; + assign { reg_2_svstate2__wen, reg_1_svstate1__wen, reg_0_svstate0__wen } = \wen$7 ; assign reg_2_msr2__data_i = \data_i$4 ; assign reg_1_msr1__data_i = \data_i$4 ; assign reg_0_msr0__data_i = \data_i$4 ; @@ -194996,9 +208139,9 @@ module sto_l(coresync_rst, s_sto, r_sto, q_sto, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -195027,7 +208170,7 @@ module sto_l(coresync_rst, s_sto, r_sto, q_sto, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -195041,8 +208184,8 @@ endmodule (* \nmigen.hierarchy = "test_issuer" *) (* top = 1 *) (* generator = "nMigen" *) -module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__tdo, TAP_bus__tdi, TAP_bus__tms, TAP_bus__tck, jtag_wb__adr, jtag_wb__dat_w, jtag_wb__dat_r, jtag_wb__sel, jtag_wb__cyc, jtag_wb__stb, jtag_wb__we, jtag_wb__ack, jtag_wb__err, mspi0_clk__core__o, mspi0_clk__pad__o, mspi0_cs_n__core__o, mspi0_cs_n__pad__o, mspi0_mosi__core__o, mspi0_mosi__pad__o, mspi0_miso__core__i, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_0__pad__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_1__pad__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_2__pad__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_3__pad__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_4__pad__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_5__pad__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_6__pad__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_dq_7__pad__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__core__o, sdr_a_0__pad__o, sdr_a_1__core__o, sdr_a_1__pad__o, sdr_a_2__core__o, sdr_a_2__pad__o, sdr_a_3__core__o, sdr_a_3__pad__o, sdr_a_4__core__o, sdr_a_4__pad__o, sdr_a_5__core__o, sdr_a_5__pad__o, sdr_a_6__core__o, sdr_a_6__pad__o, sdr_a_7__core__o, sdr_a_7__pad__o, sdr_a_8__core__o, sdr_a_8__pad__o, sdr_a_9__core__o, sdr_a_9__pad__o, sdr_ba_0__core__o, sdr_ba_0__pad__o, sdr_ba_1__core__o, sdr_ba_1__pad__o, sdr_clock__core__o, sdr_clock__pad__o, sdr_cke__core__o, sdr_cke__pad__o, sdr_ras_n__core__o, sdr_ras_n__pad__o, sdr_cas_n__core__o, sdr_cas_n__pad__o, sdr_we_n__core__o, sdr_we_n__pad__o, sdr_cs_n__core__o, sdr_cs_n__pad__o, sdr_a_10__core__o, sdr_a_10__pad__o, sdr_a_11__core__o, sdr_a_11__pad__o, sdr_a_12__core__o, sdr_a_12__pad__o, sdr_dm_1__core__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_8__pad__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_9__pad__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_10__pad__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_11__pad__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_12__pad__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_13__pad__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_14__pad__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, sdr_dq_15__pad__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e8__pad__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e9__pad__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e10__pad__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e11__pad__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e12__pad__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e13__pad__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e14__pad__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_e15__pad__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s0__pad__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s1__pad__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s2__pad__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s3__pad__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s4__pad__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s5__pad__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s6__pad__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__core__o, gpio_s7__core__oe, gpio_s7__pad__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_sda__pad__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__core__o, mtwi_scl__pad__o, eint_0__core__i, eint_0__pad__i, eint_1__core__i, eint_1__pad__i, eint_2__core__i, eint_2__pad__i, ibus__adr, ibus__dat_w, ibus__dat_r, ibus__sel, ibus__cyc, ibus__stb, ibus__ack, ibus__we, ibus__err, ibus__cti, ibus__bte, dbus__adr, dbus__dat_w, dbus__dat_r, dbus__sel, dbus__cyc, dbus__stb, dbus__ack, dbus__we, dbus__err, dbus__cti, dbus__bte, sram4k_0_wb__adr, sram4k_0_wb__dat_w, sram4k_0_wb__dat_r, sram4k_0_wb__sel, sram4k_0_wb__cyc, sram4k_0_wb__stb, sram4k_0_wb__we, sram4k_0_wb__ack, sram4k_0_wb__err, sram4k_1_wb__adr, sram4k_1_wb__dat_w, sram4k_1_wb__dat_r, sram4k_1_wb__sel, sram4k_1_wb__cyc, sram4k_1_wb__stb, sram4k_1_wb__we, sram4k_1_wb__ack, sram4k_1_wb__err, sram4k_2_wb__adr, sram4k_2_wb__dat_w, sram4k_2_wb__dat_r, sram4k_2_wb__sel, sram4k_2_wb__cyc, sram4k_2_wb__stb, sram4k_2_wb__we, sram4k_2_wb__ack, sram4k_2_wb__err, sram4k_3_wb__adr, sram4k_3_wb__dat_w, sram4k_3_wb__dat_r, sram4k_3_wb__sel, sram4k_3_wb__cyc, sram4k_3_wb__stb, sram4k_3_wb__we, sram4k_3_wb__ack, sram4k_3_wb__err, icp_wb__adr, icp_wb__dat_w, icp_wb__dat_r, icp_wb__sel, icp_wb__cyc, icp_wb__stb, icp_wb__ack, icp_wb__we, icp_wb__err, ics_wb__adr, ics_wb__dat_w, ics_wb__dat_r, ics_wb__sel, ics_wb__cyc, ics_wb__stb, ics_wb__ack, ics_wb__we, ics_wb__err, int_level_i, clk, rst, clk_sel_i, pll_18_o, vco_test_ana, pc_i); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1158" *) +module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__tdo, TAP_bus__tdi, TAP_bus__tms, TAP_bus__tck, jtag_wb__adr, jtag_wb__dat_w, jtag_wb__dat_r, jtag_wb__sel, jtag_wb__cyc, jtag_wb__stb, jtag_wb__we, jtag_wb__ack, jtag_wb__err, mspi0_clk__core__o, mspi0_clk__pad__o, mspi0_cs_n__core__o, mspi0_cs_n__pad__o, mspi0_mosi__core__o, mspi0_mosi__pad__o, mspi0_miso__core__i, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_0__pad__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_1__pad__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_2__pad__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_3__pad__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_4__pad__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_5__pad__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_6__pad__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_dq_7__pad__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__core__o, sdr_a_0__pad__o, sdr_a_1__core__o, sdr_a_1__pad__o, sdr_a_2__core__o, sdr_a_2__pad__o, sdr_a_3__core__o, sdr_a_3__pad__o, sdr_a_4__core__o, sdr_a_4__pad__o, sdr_a_5__core__o, sdr_a_5__pad__o, sdr_a_6__core__o, sdr_a_6__pad__o, sdr_a_7__core__o, sdr_a_7__pad__o, sdr_a_8__core__o, sdr_a_8__pad__o, sdr_a_9__core__o, sdr_a_9__pad__o, sdr_ba_0__core__o, sdr_ba_0__pad__o, sdr_ba_1__core__o, sdr_ba_1__pad__o, sdr_clock__core__o, sdr_clock__pad__o, sdr_cke__core__o, sdr_cke__pad__o, sdr_ras_n__core__o, sdr_ras_n__pad__o, sdr_cas_n__core__o, sdr_cas_n__pad__o, sdr_we_n__core__o, sdr_we_n__pad__o, sdr_cs_n__core__o, sdr_cs_n__pad__o, sdr_a_10__core__o, sdr_a_10__pad__o, sdr_a_11__core__o, sdr_a_11__pad__o, sdr_a_12__core__o, sdr_a_12__pad__o, sdr_dm_1__core__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_8__pad__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_9__pad__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_10__pad__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_11__pad__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_12__pad__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_13__pad__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_14__pad__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, sdr_dq_15__pad__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e8__pad__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e9__pad__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e10__pad__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e11__pad__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e12__pad__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e13__pad__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e14__pad__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_e15__pad__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s0__pad__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s1__pad__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s2__pad__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s3__pad__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s4__pad__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s5__pad__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s6__pad__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__core__o, gpio_s7__core__oe, gpio_s7__pad__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_sda__pad__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__core__o, mtwi_scl__pad__o, eint_0__core__i, eint_0__pad__i, eint_1__core__i, eint_1__pad__i, eint_2__core__i, eint_2__pad__i, ibus__adr, ibus__dat_w, ibus__dat_r, ibus__sel, ibus__cyc, ibus__stb, ibus__ack, ibus__we, ibus__err, ibus__cti, ibus__bte, dbus__adr, dbus__dat_w, dbus__dat_r, dbus__sel, dbus__cyc, dbus__stb, dbus__ack, dbus__we, dbus__err, dbus__cti, dbus__bte, icp_wb__adr, icp_wb__dat_w, icp_wb__dat_r, icp_wb__sel, icp_wb__cyc, icp_wb__stb, icp_wb__ack, icp_wb__we, icp_wb__err, ics_wb__adr, ics_wb__dat_w, ics_wb__dat_r, ics_wb__sel, ics_wb__cyc, ics_wb__stb, ics_wb__ack, ics_wb__we, ics_wb__err, int_level_i, clk, rst, clk_sel_i, pll_18_o, pll_ana_o, pc_i); + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1236" *) wire [1:0] \$1 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) input TAP_bus__tck; @@ -195052,13 +208195,13 @@ module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__t output TAP_bus__tdo; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) input TAP_bus__tms; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:239" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:240" *) output busy_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) input clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1158" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1236" *) input clk_sel_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:238" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:239" *) input core_bigendian_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) input dbus__ack; @@ -195364,7 +208507,7 @@ module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__t output jtag_wb__stb; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) output jtag_wb__we; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:240" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:241" *) input memerr_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) input mspi0_clk__core__o; @@ -195398,29 +208541,21 @@ module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__t output mtwi_sda__pad__o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) output mtwi_sda__pad__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [63:0] pc_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input pc_i_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:236" *) output [63:0] pc_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1157" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1235" *) output pll_18_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" *) - wire pll_a0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" *) - wire pll_a1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" *) - wire pll_div_out_test; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" *) - wire pll_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" *) - wire pll_ref; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1173" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:15" *) + output pll_ana_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1251" *) wire pllclk_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1173" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1251" *) wire pllclk_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) input rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) input sdr_a_0__core__o; @@ -195706,91 +208841,17 @@ module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__t input sdr_we_n__core__o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) output sdr_we_n__pad__o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - output sram4k_0_wb__ack; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [8:0] sram4k_0_wb__adr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_0_wb__cyc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - output [63:0] sram4k_0_wb__dat_r; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [63:0] sram4k_0_wb__dat_w; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_0_wb__err; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [7:0] sram4k_0_wb__sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_0_wb__stb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_0_wb__we; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - output sram4k_1_wb__ack; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [8:0] sram4k_1_wb__adr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_1_wb__cyc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - output [63:0] sram4k_1_wb__dat_r; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [63:0] sram4k_1_wb__dat_w; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_1_wb__err; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [7:0] sram4k_1_wb__sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_1_wb__stb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_1_wb__we; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - output sram4k_2_wb__ack; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [8:0] sram4k_2_wb__adr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_2_wb__cyc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - output [63:0] sram4k_2_wb__dat_r; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [63:0] sram4k_2_wb__dat_w; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_2_wb__err; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [7:0] sram4k_2_wb__sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_2_wb__stb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_2_wb__we; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - output sram4k_3_wb__ack; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [8:0] sram4k_3_wb__adr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_3_wb__cyc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - output [63:0] sram4k_3_wb__dat_r; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [63:0] sram4k_3_wb__dat_w; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_3_wb__err; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [7:0] sram4k_3_wb__sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_3_wb__stb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_3_wb__we; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) wire ti_coresync_clk; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" *) + wire wrappll_clk_24_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" *) + wire wrappll_clk_pll_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" *) + wire [1:0] wrappll_clk_sel_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:14" *) - output vco_test_ana; - assign \$1 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1158" *) clk_sel_i; - pll pll ( - .a0(pll_a0), - .a1(pll_a1), - .div_out_test(pll_div_out_test), - .out(pll_out), - .\ref (pll_ref), - .vco_test_ana(vco_test_ana) - ); + wire wrappll_pll_18_o; + assign \$1 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1236" *) clk_sel_i; ti ti ( .TAP_bus__tck(TAP_bus__tck), .TAP_bus__tdi(TAP_bus__tdi), @@ -196103,307 +209164,284 @@ module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__t .sdr_ras_n__core__o(sdr_ras_n__core__o), .sdr_ras_n__pad__o(sdr_ras_n__pad__o), .sdr_we_n__core__o(sdr_we_n__core__o), - .sdr_we_n__pad__o(sdr_we_n__pad__o), - .sram4k_0_wb__ack(sram4k_0_wb__ack), - .sram4k_0_wb__adr(sram4k_0_wb__adr), - .sram4k_0_wb__cyc(sram4k_0_wb__cyc), - .sram4k_0_wb__dat_r(sram4k_0_wb__dat_r), - .sram4k_0_wb__dat_w(sram4k_0_wb__dat_w), - .sram4k_0_wb__sel(sram4k_0_wb__sel), - .sram4k_0_wb__stb(sram4k_0_wb__stb), - .sram4k_0_wb__we(sram4k_0_wb__we), - .sram4k_1_wb__ack(sram4k_1_wb__ack), - .sram4k_1_wb__adr(sram4k_1_wb__adr), - .sram4k_1_wb__cyc(sram4k_1_wb__cyc), - .sram4k_1_wb__dat_r(sram4k_1_wb__dat_r), - .sram4k_1_wb__dat_w(sram4k_1_wb__dat_w), - .sram4k_1_wb__sel(sram4k_1_wb__sel), - .sram4k_1_wb__stb(sram4k_1_wb__stb), - .sram4k_1_wb__we(sram4k_1_wb__we), - .sram4k_2_wb__ack(sram4k_2_wb__ack), - .sram4k_2_wb__adr(sram4k_2_wb__adr), - .sram4k_2_wb__cyc(sram4k_2_wb__cyc), - .sram4k_2_wb__dat_r(sram4k_2_wb__dat_r), - .sram4k_2_wb__dat_w(sram4k_2_wb__dat_w), - .sram4k_2_wb__sel(sram4k_2_wb__sel), - .sram4k_2_wb__stb(sram4k_2_wb__stb), - .sram4k_2_wb__we(sram4k_2_wb__we), - .sram4k_3_wb__ack(sram4k_3_wb__ack), - .sram4k_3_wb__adr(sram4k_3_wb__adr), - .sram4k_3_wb__cyc(sram4k_3_wb__cyc), - .sram4k_3_wb__dat_r(sram4k_3_wb__dat_r), - .sram4k_3_wb__dat_w(sram4k_3_wb__dat_w), - .sram4k_3_wb__sel(sram4k_3_wb__sel), - .sram4k_3_wb__stb(sram4k_3_wb__stb), - .sram4k_3_wb__we(sram4k_3_wb__we) + .sdr_we_n__pad__o(sdr_we_n__pad__o) ); - assign ti_coresync_clk = pll_out; + wrappll wrappll ( + .clk_24_i(wrappll_clk_24_i), + .clk_pll_o(wrappll_clk_pll_o), + .clk_sel_i(wrappll_clk_sel_i), + .pll_18_o(wrappll_pll_18_o), + .pll_ana_o(pll_ana_o) + ); + assign ti_coresync_clk = wrappll_clk_pll_o; assign pllclk_rst = rst; - assign { pll_a1, pll_a0 } = \$1 ; - assign pll_18_o = pll_div_out_test; - assign pll_ref = clk; - assign pllclk_clk = pll_out; + assign wrappll_clk_sel_i = \$1 ; + assign pll_18_o = wrappll_pll_18_o; + assign wrappll_clk_24_i = clk; + assign pllclk_clk = wrappll_clk_pll_o; endmodule (* \nmigen.hierarchy = "test_issuer.ti" *) (* generator = "nMigen" *) -module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, ibus__cyc, ibus__ack, ibus__err, ibus__stb, ibus__sel, ibus__dat_r, ibus__adr, mspi0_clk__core__o, mspi0_cs_n__core__o, mspi0_mosi__core__o, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dq_0__pad__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_1__pad__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_2__pad__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_3__pad__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_4__pad__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_5__pad__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_6__pad__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_7__pad__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_a_0__core__o, sdr_a_1__core__o, sdr_a_2__core__o, sdr_a_3__core__o, sdr_a_4__core__o, sdr_a_5__core__o, sdr_a_6__core__o, sdr_a_7__core__o, sdr_a_8__core__o, sdr_a_9__core__o, sdr_ba_0__core__o, sdr_ba_1__core__o, sdr_clock__core__o, sdr_cke__core__o, sdr_ras_n__core__o, sdr_cas_n__core__o, sdr_we_n__core__o, sdr_cs_n__core__o, sdr_a_10__core__o, sdr_a_11__core__o, sdr_a_12__core__o, sdr_dm_1__core__o, sdr_dq_8__pad__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_9__pad__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_10__pad__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_11__pad__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_12__pad__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_13__pad__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_14__pad__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_15__pad__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, gpio_e8__pad__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e9__pad__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e10__pad__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e11__pad__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e12__pad__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e13__pad__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e14__pad__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e15__pad__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_s0__pad__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s1__pad__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s2__pad__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s3__pad__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s4__pad__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s5__pad__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s6__pad__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s7__pad__i, gpio_s7__core__o, gpio_s7__core__oe, mtwi_sda__pad__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_scl__core__o, eint_0__pad__i, eint_1__pad__i, eint_2__pad__i, TAP_bus__tdi, mspi0_clk__pad__o, mspi0_cs_n__pad__o, mspi0_mosi__pad__o, mspi0_miso__core__i, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__pad__o, sdr_a_1__pad__o, sdr_a_2__pad__o, sdr_a_3__pad__o, sdr_a_4__pad__o, sdr_a_5__pad__o, sdr_a_6__pad__o, sdr_a_7__pad__o, sdr_a_8__pad__o, sdr_a_9__pad__o, sdr_ba_0__pad__o, sdr_ba_1__pad__o, sdr_clock__pad__o, sdr_cke__pad__o, sdr_ras_n__pad__o, sdr_cas_n__pad__o, sdr_we_n__pad__o, sdr_cs_n__pad__o, sdr_a_10__pad__o, sdr_a_11__pad__o, sdr_a_12__pad__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__pad__o, eint_0__core__i, eint_1__core__i, eint_2__core__i, TAP_bus__tdo, jtag_wb__adr, jtag_wb__sel, jtag_wb__stb, jtag_wb__we, jtag_wb__cyc, jtag_wb__dat_w, jtag_wb__ack, jtag_wb__dat_r, TAP_bus__tck, TAP_bus__tms, sram4k_0_wb__cyc, sram4k_0_wb__stb, sram4k_0_wb__ack, sram4k_0_wb__adr, sram4k_0_wb__dat_r, sram4k_0_wb__dat_w, sram4k_0_wb__we, sram4k_0_wb__sel, sram4k_1_wb__cyc, sram4k_1_wb__stb, sram4k_1_wb__ack, sram4k_1_wb__adr, sram4k_1_wb__dat_r, sram4k_1_wb__dat_w, sram4k_1_wb__we, sram4k_1_wb__sel, sram4k_2_wb__cyc, sram4k_2_wb__stb, sram4k_2_wb__ack, sram4k_2_wb__adr, sram4k_2_wb__dat_r, sram4k_2_wb__dat_w, sram4k_2_wb__we, sram4k_2_wb__sel, sram4k_3_wb__cyc, sram4k_3_wb__stb, sram4k_3_wb__ack, sram4k_3_wb__adr, sram4k_3_wb__dat_r, sram4k_3_wb__dat_w, sram4k_3_wb__we, sram4k_3_wb__sel, icp_wb__ack, icp_wb__cyc, icp_wb__dat_r, icp_wb__dat_w, icp_wb__stb, icp_wb__we, icp_wb__adr, icp_wb__sel, ics_wb__adr, int_level_i, ics_wb__cyc, ics_wb__stb, ics_wb__dat_r, ics_wb__ack, ics_wb__dat_w, ics_wb__we, clk); +module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, ibus__cyc, ibus__ack, ibus__err, ibus__stb, ibus__sel, ibus__dat_r, ibus__adr, mspi0_clk__core__o, mspi0_cs_n__core__o, mspi0_mosi__core__o, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dq_0__pad__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_1__pad__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_2__pad__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_3__pad__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_4__pad__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_5__pad__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_6__pad__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_7__pad__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_a_0__core__o, sdr_a_1__core__o, sdr_a_2__core__o, sdr_a_3__core__o, sdr_a_4__core__o, sdr_a_5__core__o, sdr_a_6__core__o, sdr_a_7__core__o, sdr_a_8__core__o, sdr_a_9__core__o, sdr_ba_0__core__o, sdr_ba_1__core__o, sdr_clock__core__o, sdr_cke__core__o, sdr_ras_n__core__o, sdr_cas_n__core__o, sdr_we_n__core__o, sdr_cs_n__core__o, sdr_a_10__core__o, sdr_a_11__core__o, sdr_a_12__core__o, sdr_dm_1__core__o, sdr_dq_8__pad__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_9__pad__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_10__pad__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_11__pad__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_12__pad__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_13__pad__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_14__pad__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_15__pad__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, gpio_e8__pad__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e9__pad__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e10__pad__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e11__pad__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e12__pad__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e13__pad__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e14__pad__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e15__pad__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_s0__pad__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s1__pad__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s2__pad__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s3__pad__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s4__pad__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s5__pad__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s6__pad__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s7__pad__i, gpio_s7__core__o, gpio_s7__core__oe, mtwi_sda__pad__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_scl__core__o, eint_0__pad__i, eint_1__pad__i, eint_2__pad__i, TAP_bus__tdi, mspi0_clk__pad__o, mspi0_cs_n__pad__o, mspi0_mosi__pad__o, mspi0_miso__core__i, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__pad__o, sdr_a_1__pad__o, sdr_a_2__pad__o, sdr_a_3__pad__o, sdr_a_4__pad__o, sdr_a_5__pad__o, sdr_a_6__pad__o, sdr_a_7__pad__o, sdr_a_8__pad__o, sdr_a_9__pad__o, sdr_ba_0__pad__o, sdr_ba_1__pad__o, sdr_clock__pad__o, sdr_cke__pad__o, sdr_ras_n__pad__o, sdr_cas_n__pad__o, sdr_we_n__pad__o, sdr_cs_n__pad__o, sdr_a_10__pad__o, sdr_a_11__pad__o, sdr_a_12__pad__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__pad__o, eint_0__core__i, eint_1__core__i, eint_2__core__i, TAP_bus__tdo, jtag_wb__adr, jtag_wb__sel, jtag_wb__stb, jtag_wb__we, jtag_wb__cyc, jtag_wb__dat_w, jtag_wb__ack, jtag_wb__dat_r, TAP_bus__tck, TAP_bus__tms, icp_wb__ack, icp_wb__cyc, icp_wb__dat_r, icp_wb__dat_w, icp_wb__stb, icp_wb__we, icp_wb__adr, icp_wb__sel, ics_wb__adr, int_level_i, ics_wb__cyc, ics_wb__stb, ics_wb__dat_r, ics_wb__ack, ics_wb__dat_w, ics_wb__we, clk); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) wire \$100 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *) wire \$102 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:353" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:354" *) wire [64:0] \$104 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:353" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:354" *) wire [64:0] \$105 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:56" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:57" *) wire [31:0] \$107 ; (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:605" *) wire [6:0] \$108 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:56" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:57" *) wire [31:0] \$111 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:364" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:365" *) wire [64:0] \$112 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:364" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:365" *) wire [64:0] \$113 ; (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:605" *) wire [6:0] \$115 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) wire \$118 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) wire \$120 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) wire \$122 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) wire \$124 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) wire \$126 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) wire \$128 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) wire \$130 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) wire \$132 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) wire \$134 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:548" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:594" *) wire [7:0] \$136 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:548" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:594" *) wire [7:0] \$137 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:549" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:595" *) wire [7:0] \$139 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:549" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:595" *) wire [7:0] \$140 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" *) wire \$142 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) wire \$144 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) wire \$146 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) wire \$148 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) wire \$150 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) wire \$152 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) wire \$154 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) wire \$156 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) wire \$158 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" *) wire \$160 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) wire \$162 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) wire \$164 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) wire \$166 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) wire \$168 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) wire \$170 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) wire \$172 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) wire \$174 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) wire \$176 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) wire \$178 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) wire \$180 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) wire \$182 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) wire \$184 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) wire \$186 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) wire \$188 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) wire \$190 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) wire \$192 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) wire \$194 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) wire \$196 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:796" *) - wire [2:0] \$197 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) - wire \$200 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) + wire \$198 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:873" *) + wire [2:0] \$199 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) wire \$202 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) wire \$204 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) wire \$206 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) wire \$208 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) wire \$210 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) wire \$212 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) wire \$214 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) wire \$216 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) wire \$218 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) wire \$220 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) wire \$222 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) wire \$224 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) wire \$226 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) wire \$228 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *) wire \$23 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) wire \$230 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794" *) - wire [2:0] \$231 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *) - wire \$234 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) + wire \$232 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:871" *) + wire [2:0] \$233 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) wire \$236 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) wire \$238 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *) wire \$240 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) wire \$242 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) wire \$244 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) wire \$246 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) wire \$248 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:936" *) wire \$25 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) wire \$250 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) wire \$252 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:776" *) + wire \$254 ; (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:178" *) - wire [63:0] \$254 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791" *) - wire \$256 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" *) + wire [63:0] \$256 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" *) wire \$258 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *) wire \$260 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) - wire [63:0] \$262 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *) + wire \$262 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [63:0] \$264 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1079" *) - wire [64:0] \$266 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1079" *) - wire [64:0] \$267 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [63:0] \$266 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1157" *) + wire [64:0] \$268 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1157" *) wire [64:0] \$269 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:937" *) wire [2:0] \$27 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" *) - wire [64:0] \$270 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1173" *) + wire [64:0] \$271 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1173" *) + wire [64:0] \$272 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:937" *) wire [2:0] \$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:865" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *) wire \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:865" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *) wire \$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:865" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *) wire \$34 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$36 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) - wire \$40 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) + wire \$40 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *) wire \$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) wire \$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) wire \$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) - wire \$48 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) + wire \$48 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *) wire \$50 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) wire \$52 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] \$54 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) wire \$56 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) wire \$58 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) wire \$60 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) wire \$62 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) wire \$64 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) wire \$66 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) wire \$68 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) wire \$70 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) wire \$72 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) wire \$74 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) wire \$76 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) wire \$78 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) wire \$80 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) wire \$82 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) wire \$84 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) wire \$86 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) wire \$88 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) wire \$90 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) wire \$92 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) wire \$94 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) wire \$96 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) wire \$98 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) input TAP_bus__tck; @@ -196413,102 +209451,127 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus output TAP_bus__tdo; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) input TAP_bus__tms; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:239" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:240" *) output busy_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) input clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:104" *) reg [7:0] core_asmcode = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:104" *) reg [7:0] \core_asmcode$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:238" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:239" *) input core_bigendian_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" *) reg \core_bigendian_i$10 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" *) reg \core_bigendian_i$10$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [63:0] core_cia__data_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) reg [2:0] core_cia__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [1:0] core_core_core__SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [1:0] \core_core_core__SV_Ptype$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg core_core_core__sv_pred_dz = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg \core_core_core__sv_pred_dz$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg core_core_core__sv_pred_sz = 1'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg \core_core_core__sv_pred_sz$next ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [1:0] core_core_core__sv_saturate = 2'h0; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + reg [1:0] \core_core_core__sv_saturate$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:46" *) reg [63:0] core_core_core_cia = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:46" *) reg [63:0] \core_core_core_cia$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [7:0] core_core_core_cr_rd = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [7:0] \core_core_core_cr_rd$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg core_core_core_cr_rd_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \core_core_core_cr_rd_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [7:0] core_core_core_cr_wr = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [7:0] \core_core_core_cr_wr$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) reg \core_core_core_exc_$signal = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) reg \core_core_core_exc_$signal$3 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) reg \core_core_core_exc_$signal$3$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) reg \core_core_core_exc_$signal$4 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) reg \core_core_core_exc_$signal$4$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) reg \core_core_core_exc_$signal$5 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) reg \core_core_core_exc_$signal$5$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) reg \core_core_core_exc_$signal$6 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) reg \core_core_core_exc_$signal$6$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) reg \core_core_core_exc_$signal$7 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) reg \core_core_core_exc_$signal$7$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) reg \core_core_core_exc_$signal$8 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) reg \core_core_core_exc_$signal$8$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) reg \core_core_core_exc_$signal$9 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) reg \core_core_core_exc_$signal$9$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) reg \core_core_core_exc_$signal$next ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" *) - reg [13:0] core_core_core_fn_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" *) - reg [13:0] \core_core_core_fn_unit$next ; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:52" *) + reg [14:0] core_core_core_fn_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:52" *) + reg [14:0] \core_core_core_fn_unit$next ; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:56" *) reg [1:0] core_core_core_input_carry = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:56" *) reg [1:0] \core_core_core_input_carry$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:50" *) reg [31:0] core_core_core_insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:50" *) reg [31:0] \core_core_core_insn$next ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -196585,145 +209648,167 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:51" *) reg [6:0] core_core_core_insn_type = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:51" *) reg [6:0] \core_core_core_insn_type$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:62" *) reg core_core_core_is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:62" *) reg \core_core_core_is_32bit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:45" *) reg [63:0] core_core_core_msr = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:45" *) reg [63:0] \core_core_core_msr$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg core_core_core_oe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \core_core_core_oe$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg core_core_core_oe_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \core_core_core_oe_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg core_core_core_rc = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \core_core_core_rc$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg core_core_core_rc_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \core_core_core_rc_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:47" *) + reg [31:0] core_core_core_svstate = 32'd0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:47" *) + reg [31:0] \core_core_core_svstate$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:59" *) reg [12:0] core_core_core_trapaddr = 13'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:59" *) reg [12:0] \core_core_core_trapaddr$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:57" *) reg [7:0] core_core_core_traptype = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:57" *) reg [7:0] \core_core_core_traptype$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [6:0] core_core_cr_in1 = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [6:0] \core_core_cr_in1$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg core_core_cr_in1_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \core_core_cr_in1_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [6:0] core_core_cr_in2 = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [6:0] \core_core_cr_in2$1 = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [6:0] \core_core_cr_in2$1$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [6:0] \core_core_cr_in2$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg core_core_cr_in2_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \core_core_cr_in2_ok$2 = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \core_core_cr_in2_ok$2$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \core_core_cr_in2_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [6:0] core_core_cr_out = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [6:0] \core_core_cr_out$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg core_core_cr_wr_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \core_core_cr_wr_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:28" *) reg [6:0] core_core_dststep = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:28" *) reg [6:0] \core_core_dststep$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [6:0] core_core_ea = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [6:0] \core_core_ea$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [2:0] core_core_fast1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [2:0] \core_core_fast1$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg core_core_fast1_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \core_core_fast1_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [2:0] core_core_fast2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [2:0] \core_core_fast2$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg core_core_fast2_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \core_core_fast2_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg [2:0] core_core_fast3 = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg [2:0] \core_core_fast3$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg core_core_fast3_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg \core_core_fast3_ok$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [2:0] core_core_fasto1 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [2:0] \core_core_fasto1$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [2:0] core_core_fasto2 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [2:0] \core_core_fasto2$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg [2:0] core_core_fasto3 = 3'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg [2:0] \core_core_fasto3$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:53" *) reg core_core_lk = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:53" *) reg \core_core_lk$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:31" *) reg [6:0] core_core_maxvl = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:31" *) reg [6:0] \core_core_maxvl$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:17" *) + reg [63:0] core_core_msr = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:17" *) + reg [63:0] \core_core_msr$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:16" *) reg [63:0] core_core_pc = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:16" *) reg [63:0] \core_core_pc$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [6:0] core_core_reg1 = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [6:0] \core_core_reg1$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg core_core_reg1_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \core_core_reg1_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [6:0] core_core_reg2 = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [6:0] \core_core_reg2$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg core_core_reg2_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \core_core_reg2_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [6:0] core_core_reg3 = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [6:0] \core_core_reg3$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg core_core_reg3_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \core_core_reg3_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [6:0] core_core_rego = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [6:0] \core_core_rego$next ; (* enum_base_type = "SPR" *) (* enum_value_0000010010 = "DSISR" *) @@ -196737,13 +209822,13 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus (* enum_value_1011000000 = "SVSTATE" *) (* enum_value_1011010000 = "PRTBL" *) (* enum_value_1011010001 = "SVSRR0" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [9:0] core_core_spr1 = 10'h000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [9:0] \core_core_spr1$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg core_core_spr1_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \core_core_spr1_ok$next ; (* enum_base_type = "SPR" *) (* enum_value_0000010010 = "DSISR" *) @@ -196757,39 +209842,39 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus (* enum_value_1011000000 = "SVSTATE" *) (* enum_value_1011010000 = "PRTBL" *) (* enum_value_1011010001 = "SVSRR0" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [9:0] core_core_spro = 10'h000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg [9:0] \core_core_spro$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:29" *) reg [6:0] core_core_srcstep = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:29" *) reg [6:0] \core_core_srcstep$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:27" *) reg [1:0] core_core_subvl = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:27" *) reg [1:0] \core_core_subvl$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:26" *) reg [1:0] core_core_svstep = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:26" *) reg [1:0] \core_core_svstep$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:110" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:123" *) wire core_core_terminate_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:30" *) reg [6:0] core_core_vl = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:30" *) reg [6:0] \core_core_vl$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:114" *) reg [2:0] core_core_xer_in = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:114" *) reg [2:0] \core_core_xer_in$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:107" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:120" *) wire core_corebusy_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) wire core_coresync_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg core_cr_out_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \core_cr_out_ok$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) wire core_cu_ad__go_i; @@ -196803,9 +209888,9 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus reg [63:0] core_data_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) reg [63:0] \core_data_i$12 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:19" *) reg [63:0] core_dec = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:19" *) reg [63:0] \core_dec$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) reg [4:0] core_dmi__addr; @@ -196813,22 +209898,28 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus wire [63:0] core_dmi__data_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) reg core_dmi__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg core_ea_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \core_ea_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:18" *) reg core_eint = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:18" *) reg \core_eint$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) + wire \core_exc_o_$signal ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg core_fasto1_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \core_fasto1_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg core_fasto2_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \core_fasto2_ok$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg core_fasto3_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + reg \core_fasto3_ok$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [31:0] core_full_rd2__data_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) @@ -196838,9 +209929,9 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) reg [2:0] core_full_rd__ren; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) - reg [2:0] core_issue__addr; + reg [3:0] core_issue__addr; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) - reg [2:0] \core_issue__addr$13 ; + reg [3:0] \core_issue__addr$13 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) reg [63:0] core_issue__data_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) @@ -196849,29 +209940,25 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus reg core_issue__ren; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) reg core_issue__wen; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:106" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119" *) reg core_issue_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:105" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118" *) reg core_ivalid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" *) - reg [63:0] core_msr = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" *) - reg [63:0] \core_msr$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [63:0] core_msr__data_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) reg [2:0] core_msr__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:101" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:110" *) reg [31:0] core_raw_insn_i = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:101" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:110" *) reg [31:0] \core_raw_insn_i$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg core_rego_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \core_rego_ok$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg core_spro_ok = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg \core_spro_ok$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [2:0] core_state_nia_wen; @@ -196879,21 +209966,17 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus wire [63:0] core_sv__data_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) reg [2:0] core_sv__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" *) - reg core_sv_a_nz = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" *) - reg \core_sv_a_nz$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" *) wire core_wb_dcache_en; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) reg [2:0] core_wen; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) reg [2:0] \core_wen$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:115" *) reg core_xer_out = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:115" *) reg \core_xer_out$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) reg cu_st__rel_o_dly = 1'h0; @@ -196901,57 +209984,33 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus wire \cu_st__rel_o_dly$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) wire cu_st__rel_o_rise; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *) - reg [6:0] cur_cur_dststep = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *) - reg [6:0] \cur_cur_dststep$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" *) - reg [6:0] cur_cur_maxvl = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" *) - reg [6:0] \cur_cur_maxvl$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" *) - reg [6:0] cur_cur_srcstep = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" *) - reg [6:0] \cur_cur_srcstep$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" *) - reg [1:0] cur_cur_subvl = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" *) - reg [1:0] \cur_cur_subvl$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" *) - reg [1:0] cur_cur_svstep = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" *) - reg [1:0] \cur_cur_svstep$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" *) - reg [6:0] cur_cur_vl = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" *) - reg [6:0] \cur_cur_vl$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1034" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1112" *) reg d_cr_delay = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1034" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1112" *) reg \d_cr_delay$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1024" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1102" *) reg d_reg_delay = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1024" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1102" *) reg \d_reg_delay$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1044" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1122" *) reg d_xer_delay = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1044" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1122" *) reg \d_xer_delay$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:28" *) wire [6:0] dbg_core_dbg_core_dbg_dststep; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:31" *) wire [6:0] dbg_core_dbg_core_dbg_maxvl; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:29" *) wire [6:0] dbg_core_dbg_core_dbg_srcstep; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:27" *) wire [1:0] dbg_core_dbg_core_dbg_subvl; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:26" *) wire [1:0] dbg_core_dbg_core_dbg_svstep; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:30" *) wire [6:0] dbg_core_dbg_core_dbg_vl; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:17" *) wire [63:0] dbg_core_dbg_msr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:16" *) wire [63:0] dbg_core_dbg_pc; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:99" *) wire dbg_core_rst_o; @@ -197019,112 +210078,151 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus output dbus__stb; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) output dbus__we; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] dec2_SV_Ptype; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:104" *) wire [7:0] dec2_asmcode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:479" *) wire dec2_bigendian; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:46" *) wire [63:0] dec2_cia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [6:0] dec2_cr_in1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec2_cr_in1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [6:0] dec2_cr_in2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [6:0] \dec2_cr_in2$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec2_cr_in2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire \dec2_cr_in2_ok$15 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [6:0] dec2_cr_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec2_cr_out_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [7:0] dec2_cr_rd; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec2_cr_rd_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [7:0] dec2_cr_wr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec2_cr_wr_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:28" *) + reg [6:0] dec2_cur_cur_dststep = 7'h00; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:28" *) + reg [6:0] \dec2_cur_cur_dststep$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:31" *) + reg [6:0] dec2_cur_cur_maxvl = 7'h00; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:31" *) + reg [6:0] \dec2_cur_cur_maxvl$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:29" *) + reg [6:0] dec2_cur_cur_srcstep = 7'h00; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:29" *) + reg [6:0] \dec2_cur_cur_srcstep$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:27" *) + reg [1:0] dec2_cur_cur_subvl = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:27" *) + reg [1:0] \dec2_cur_cur_subvl$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:26" *) + reg [1:0] dec2_cur_cur_svstep = 2'h0; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:26" *) + reg [1:0] \dec2_cur_cur_svstep$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:30" *) + reg [6:0] dec2_cur_cur_vl = 7'h00; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:30" *) + reg [6:0] \dec2_cur_cur_vl$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:19" *) reg [63:0] dec2_cur_dec = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:19" *) reg [63:0] \dec2_cur_dec$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:18" *) reg dec2_cur_eint = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:18" *) reg \dec2_cur_eint$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:17" *) reg [63:0] dec2_cur_msr = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:17" *) reg [63:0] \dec2_cur_msr$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:16" *) reg [63:0] dec2_cur_pc = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/state.py:16" *) reg [63:0] \dec2_cur_pc$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [6:0] dec2_ea; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec2_ea_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \dec2_exc_$signal ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \dec2_exc_$signal$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \dec2_exc_$signal$17 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \dec2_exc_$signal$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \dec2_exc_$signal$19 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \dec2_exc_$signal$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \dec2_exc_$signal$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/exceptions.py:14" *) wire \dec2_exc_$signal$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [2:0] dec2_fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec2_fast1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [2:0] dec2_fast2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec2_fast2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [2:0] dec2_fast3; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire dec2_fast3_ok; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [2:0] dec2_fasto1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec2_fasto1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [2:0] dec2_fasto2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec2_fasto2_ok; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [2:0] dec2_fasto3; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire dec2_fasto3_ok; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" *) - wire [13:0] dec2_fn_unit; + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:52" *) + wire [14:0] dec2_fn_unit; (* enum_base_type = "CryIn" *) (* enum_value_00 = "ZERO" *) (* enum_value_01 = "ONE" *) (* enum_value_10 = "CA" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:56" *) wire [1:0] dec2_input_carry; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:50" *) wire [31:0] dec2_insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -197201,41 +210299,43 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:51" *) wire [6:0] dec2_insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:62" *) wire dec2_is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:53" *) wire dec2_lk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:45" *) wire [63:0] dec2_msr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec2_oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec2_oe_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:478" *) reg [31:0] dec2_raw_opcode_in = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/power_decoder.py:478" *) reg [31:0] \dec2_raw_opcode_in$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec2_rc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec2_rc_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [6:0] dec2_reg1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec2_reg1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [6:0] dec2_reg2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec2_reg2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [6:0] dec2_reg3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec2_reg3_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [6:0] dec2_rego; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec2_rego_ok; (* enum_base_type = "SPR" *) (* enum_value_0000000001 = "XER" *) @@ -197351,9 +210451,9 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus (* enum_value_1110000000 = "PPR" *) (* enum_value_1110000010 = "PPR32" *) (* enum_value_1111111111 = "PIR" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [9:0] dec2_spr1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec2_spr1_ok; (* enum_base_type = "SPR" *) (* enum_value_0000000001 = "XER" *) @@ -197469,23 +210569,33 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus (* enum_value_1110000000 = "PPR" *) (* enum_value_1110000010 = "PPR32" *) (* enum_value_1111111111 = "PIR" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [9:0] dec2_spro; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire dec2_spro_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) - wire dec2_sv_a_nz; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire dec2_sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire dec2_sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + wire [1:0] dec2_sv_saturate; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:47" *) + wire [31:0] dec2_svstate; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:59" *) wire [12:0] dec2_trapaddr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:57" *) wire [7:0] dec2_traptype; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:114" *) wire [2:0] dec2_xer_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:115" *) wire dec2_xer_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:858" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:935" *) reg [1:0] delay = 2'h3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:858" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:935" *) reg [1:0] \delay$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) output eint_0__core__i; @@ -197499,33 +210609,35 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus output eint_2__core__i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) input eint_2__pad__i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:777" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:602" *) + wire exc_happened; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) reg exec_fsm_state = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:777" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) reg \exec_fsm_state$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:954" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1032" *) reg exec_insn_ready_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:953" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1031" *) reg exec_insn_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:958" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1036" *) reg exec_pc_ready_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:957" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1035" *) reg exec_pc_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) reg [1:0] fetch_fsm_state = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) reg [1:0] \fetch_fsm_state$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1020" *) reg fetch_insn_ready_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:941" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1019" *) reg fetch_insn_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:938" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1016" *) reg fetch_pc_ready_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:937" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1015" *) reg fetch_pc_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1067" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *) reg [1:0] fsm_state = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1067" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *) reg [1:0] \fsm_state$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) output gpio_e10__core__i; @@ -197775,17 +210887,17 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus reg imem_f_valid_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" *) wire imem_wb_icache_en; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:268" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:269" *) reg insn_done; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" *) input [15:0] int_level_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:697" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:774" *) reg is_last; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1008" *) wire is_svp64_mode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) reg [2:0] issue_fsm_state = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) reg [2:0] \issue_fsm_state$next ; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) reg jtag_dmi0__ack_o = 1'h0; @@ -197819,8 +210931,6 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus output jtag_wb__stb; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) output jtag_wb__we; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:96" *) - wire jtag_wb_sram_en; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) input mspi0_clk__core__o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) @@ -197837,9 +210947,9 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus input mspi0_mosi__core__o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) output mspi0_mosi__pad__o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" *) reg msr_read = 1'h1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" *) reg \msr_read$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) input mtwi_scl__core__o; @@ -197857,57 +210967,57 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus output mtwi_sda__pad__o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) output mtwi_sda__pad__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1077" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1155" *) reg [63:0] new_dec; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:28" *) reg [6:0] new_svstate_dststep; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:31" *) reg [6:0] new_svstate_maxvl; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:29" *) reg [6:0] new_svstate_srcstep; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:27" *) reg [1:0] new_svstate_subvl; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:26" *) reg [1:0] new_svstate_svstep; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:30" *) reg [6:0] new_svstate_vl; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1094" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1172" *) reg [63:0] new_tb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:593" *) wire [6:0] next_dststep; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:546" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:592" *) wire [6:0] next_srcstep; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:920" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:997" *) reg [63:0] nia = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:920" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:997" *) reg [63:0] \nia$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" *) reg [63:0] pc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:899" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:976" *) reg pc_changed = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:899" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:976" *) reg \pc_changed$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [63:0] pc_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input pc_i_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:236" *) output [63:0] pc_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) reg pc_ok_delay = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) reg \pc_ok_delay$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:852" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:929" *) wire por_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:946" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1024" *) wire pred_insn_ready_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:945" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1023" *) reg pred_insn_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:950" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" *) reg pred_mask_ready_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:949" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1027" *) wire pred_mask_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) input rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) input sdr_a_0__core__o; @@ -198193,95 +211303,23 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus input sdr_we_n__core__o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) output sdr_we_n__pad__o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" *) - wire sram4k_0_enable; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - output sram4k_0_wb__ack; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [8:0] sram4k_0_wb__adr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_0_wb__cyc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - output [63:0] sram4k_0_wb__dat_r; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [63:0] sram4k_0_wb__dat_w; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [7:0] sram4k_0_wb__sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_0_wb__stb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_0_wb__we; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" *) - wire sram4k_1_enable; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - output sram4k_1_wb__ack; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [8:0] sram4k_1_wb__adr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_1_wb__cyc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - output [63:0] sram4k_1_wb__dat_r; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [63:0] sram4k_1_wb__dat_w; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [7:0] sram4k_1_wb__sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_1_wb__stb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_1_wb__we; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" *) - wire sram4k_2_enable; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - output sram4k_2_wb__ack; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [8:0] sram4k_2_wb__adr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_2_wb__cyc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - output [63:0] sram4k_2_wb__dat_r; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [63:0] sram4k_2_wb__dat_w; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [7:0] sram4k_2_wb__sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_2_wb__stb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_2_wb__we; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" *) - wire sram4k_3_enable; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - output sram4k_3_wb__ack; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [8:0] sram4k_3_wb__adr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_3_wb__cyc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - output [63:0] sram4k_3_wb__dat_r; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [63:0] sram4k_3_wb__dat_w; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input [7:0] sram4k_3_wb__sel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_3_wb__stb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *) - input sram4k_3_wb__we; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:977" *) reg sv_changed = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:977" *) reg \sv_changed$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" *) reg [63:0] svstate; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [31:0] svstate_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire svstate_i_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) reg svstate_ok_delay = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) reg \svstate_ok_delay$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:857" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:934" *) wire ti_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) reg update_svstate; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" *) wire xics_icp_core_irq_o; @@ -198293,145 +211331,160 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus wire [7:0] xics_ics_icp_o_pri; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" *) wire [3:0] xics_ics_icp_o_src; - assign \$100 = \$98 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *) is_last; - assign \$102 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *) msr_read; - assign \$105 = dec2_cur_pc + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:353" *) 3'h4; + assign \$100 = \$98 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) is_last; + assign \$102 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *) msr_read; + assign \$105 = dec2_cur_pc + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:354" *) 3'h4; assign \$108 = dec2_cur_pc[2] * (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:605" *) 6'h20; assign \$107 = imem_f_instr_o >> \$108 ; - assign \$113 = dec2_cur_pc + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:364" *) 3'h4; + assign \$113 = dec2_cur_pc + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:365" *) 3'h4; assign \$115 = \$112 [2] * (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:605" *) 6'h20; assign \$111 = imem_f_instr_o >> \$115 ; - assign \$118 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; - assign \$120 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; - assign \$122 = \$118 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$120 ; - assign \$124 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) dbg_core_stop_o; - assign \$126 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) core_coresync_rst; - assign \$128 = \$124 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) \$126 ; - assign \$130 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" *) sv_changed; - assign \$132 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *) 1'h0; - assign \$134 = \$132 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *) is_last; - assign \$137 = cur_cur_srcstep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:548" *) 1'h1; - assign \$140 = cur_cur_dststep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:549" *) 1'h1; - assign \$142 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; - assign \$144 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; - assign \$146 = \$142 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$144 ; - assign \$148 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; - assign \$150 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; - assign \$152 = \$148 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$150 ; - assign \$154 = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *) 1'h0; - assign \$156 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *) \$154 ; - assign \$158 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" *) is_svp64_mode; - assign \$160 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) dbg_core_stop_o; - assign \$162 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) core_coresync_rst; - assign \$164 = \$160 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) \$162 ; - assign \$166 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" *) sv_changed; - assign \$168 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *) 1'h0; - assign \$170 = \$168 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *) is_last; - assign \$172 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; - assign \$174 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; - assign \$176 = \$172 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$174 ; - assign \$178 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) dbg_core_stop_o; - assign \$180 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) core_coresync_rst; - assign \$182 = \$178 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) \$180 ; - assign \$184 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; - assign \$186 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; - assign \$188 = \$184 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$186 ; - assign \$190 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) dbg_core_stop_o; - assign \$192 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) core_coresync_rst; - assign \$194 = \$190 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) \$192 ; - assign \$197 = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:796" *) 1'h1; - assign \$196 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$197 ; - assign \$200 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; - assign \$202 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; - assign \$204 = \$200 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$202 ; - assign \$206 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) dbg_core_stop_o; - assign \$208 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) core_coresync_rst; - assign \$210 = \$206 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) \$208 ; - assign \$212 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" *) sv_changed; - assign \$214 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *) 1'h0; - assign \$216 = \$214 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *) is_last; - assign \$218 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; - assign \$220 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; - assign \$222 = \$218 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$220 ; - assign \$224 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) dbg_core_stop_o; - assign \$226 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) core_coresync_rst; - assign \$228 = \$224 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) \$226 ; - assign \$231 = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794" *) 3'h4; - assign \$230 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$231 ; - assign \$234 = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *) 1'h0; - assign \$236 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *) \$234 ; - assign \$238 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" *) core_corebusy_o; - assign \$23 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *) msr_read; - assign \$240 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) dbg_core_stop_o; - assign \$242 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) core_coresync_rst; - assign \$244 = \$240 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) \$242 ; - assign \$246 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) dbg_core_stop_o; - assign \$248 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) core_coresync_rst; - assign \$250 = \$246 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) \$248 ; - assign \$252 = next_srcstep == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *) cur_cur_vl; - assign \$254 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:178" *) { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep }; - assign \$256 = core_core_core_insn_type != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791" *) 7'h01; - assign \$258 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" *) core_corebusy_o; - assign \$25 = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *) 1'h0; - assign \$260 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" *) core_corebusy_o; - assign \$262 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) core_full_rd2__data_o; - assign \$264 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) core_full_rd__data_o; - assign \$267 = core_issue__data_o - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1079" *) 1'h1; - assign \$270 = core_issue__data_o + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" *) 1'h1; - assign \$28 = delay - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" *) 1'h1; - assign \$30 = 1'h0 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:865" *) dbg_core_rst_o; - assign \$32 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:865" *) rst; - assign \$34 = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:865" *) \$32 ; + assign \$118 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o; + assign \$120 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst; + assign \$122 = \$118 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$120 ; + assign \$124 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o; + assign \$126 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst; + assign \$128 = \$124 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$126 ; + assign \$130 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) sv_changed; + assign \$132 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) 1'h0; + assign \$134 = \$132 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) is_last; + assign \$137 = dec2_cur_cur_srcstep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:594" *) 1'h1; + assign \$140 = dec2_cur_cur_dststep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:595" *) 1'h1; + assign \$142 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" *) \core_exc_o_$signal ; + assign \$144 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o; + assign \$146 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst; + assign \$148 = \$144 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$146 ; + assign \$150 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o; + assign \$152 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst; + assign \$154 = \$150 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$152 ; + assign \$156 = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) 1'h0; + assign \$158 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) \$156 ; + assign \$160 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" *) is_svp64_mode; + assign \$162 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o; + assign \$164 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst; + assign \$166 = \$162 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$164 ; + assign \$168 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) sv_changed; + assign \$170 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) 1'h0; + assign \$172 = \$170 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) is_last; + assign \$174 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o; + assign \$176 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst; + assign \$178 = \$174 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$176 ; + assign \$180 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o; + assign \$182 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst; + assign \$184 = \$180 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$182 ; + assign \$186 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o; + assign \$188 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst; + assign \$190 = \$186 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$188 ; + assign \$192 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o; + assign \$194 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst; + assign \$196 = \$192 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$194 ; + assign \$199 = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:873" *) 1'h1; + assign \$198 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$199 ; + assign \$202 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o; + assign \$204 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst; + assign \$206 = \$202 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$204 ; + assign \$208 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o; + assign \$210 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst; + assign \$212 = \$208 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$210 ; + assign \$214 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) sv_changed; + assign \$216 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) 1'h0; + assign \$218 = \$216 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) is_last; + assign \$220 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o; + assign \$222 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst; + assign \$224 = \$220 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$222 ; + assign \$226 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o; + assign \$228 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst; + assign \$230 = \$226 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$228 ; + assign \$233 = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:871" *) 3'h4; + assign \$232 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$233 ; + assign \$236 = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) 1'h0; + assign \$238 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) \$236 ; + assign \$23 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *) msr_read; + assign \$240 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *) core_corebusy_o; + assign \$242 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o; + assign \$244 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst; + assign \$246 = \$242 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$244 ; + assign \$248 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o; + assign \$250 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst; + assign \$252 = \$248 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$250 ; + assign \$254 = next_srcstep == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:776" *) dec2_cur_cur_vl; + assign \$256 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:178" *) { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep }; + assign \$258 = core_core_core_insn_type != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" *) 7'h01; + assign \$25 = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:936" *) 1'h0; + assign \$260 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *) core_corebusy_o; + assign \$262 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *) core_corebusy_o; + assign \$264 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) core_full_rd2__data_o; + assign \$266 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) core_full_rd__data_o; + assign \$269 = core_issue__data_o - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1157" *) 1'h1; + assign \$272 = core_issue__data_o + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1173" *) 1'h1; + assign \$28 = delay - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:937" *) 1'h1; + assign \$30 = 1'h0 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *) dbg_core_rst_o; + assign \$32 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *) rst; + assign \$34 = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *) \$32 ; assign \$36 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) cu_st__rel_o_dly; assign \$38 = core_cu_st__rel_o & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$36 ; - assign \$40 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) core_coresync_rst; - assign \$42 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) pc_i_ok; - assign \$44 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) core_coresync_rst; - assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) core_coresync_rst; - assign \$48 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) core_coresync_rst; - assign \$50 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) svstate_i_ok; - assign \$52 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) core_coresync_rst; - assign \$54 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) svstate_i; - assign \$56 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) core_coresync_rst; - assign \$58 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; - assign \$60 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; - assign \$62 = \$58 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$60 ; - assign \$64 = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *) 1'h0; - assign \$66 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *) \$64 ; - assign \$68 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) dbg_core_stop_o; - assign \$70 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) core_coresync_rst; - assign \$72 = \$68 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) \$70 ; - assign \$74 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" *) sv_changed; - assign \$76 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *) 1'h0; - assign \$78 = \$76 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *) is_last; - assign \$80 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; - assign \$82 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; - assign \$84 = \$80 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$82 ; - assign \$86 = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *) 1'h0; - assign \$88 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *) \$86 ; - assign \$90 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) dbg_core_stop_o; - assign \$92 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) core_coresync_rst; - assign \$94 = \$90 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) \$92 ; - assign \$96 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" *) sv_changed; - assign \$98 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *) 1'h0; + assign \$40 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst; + assign \$42 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *) pc_i_ok; + assign \$44 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst; + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst; + assign \$48 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst; + assign \$50 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *) svstate_i_ok; + assign \$52 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst; + assign \$54 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) svstate_i; + assign \$56 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst; + assign \$58 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o; + assign \$60 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst; + assign \$62 = \$58 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$60 ; + assign \$64 = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) 1'h0; + assign \$66 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) \$64 ; + assign \$68 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o; + assign \$70 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst; + assign \$72 = \$68 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$70 ; + assign \$74 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) sv_changed; + assign \$76 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) 1'h0; + assign \$78 = \$76 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) is_last; + assign \$80 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o; + assign \$82 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst; + assign \$84 = \$80 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$82 ; + assign \$86 = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) 1'h0; + assign \$88 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) \$86 ; + assign \$90 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o; + assign \$92 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst; + assign \$94 = \$90 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$92 ; + assign \$96 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) sv_changed; + assign \$98 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) 1'h0; always @(posedge clk) fsm_state <= \fsm_state$next ; always @(posedge clk) - core_msr <= \core_msr$next ; + core_eint <= \core_eint$next ; + always @(posedge clk) + dec2_cur_dec <= \dec2_cur_dec$next ; + always @(posedge clk) + dec2_cur_cur_svstep <= \dec2_cur_cur_svstep$next ; + always @(posedge clk) + dec2_cur_cur_subvl <= \dec2_cur_cur_subvl$next ; + always @(posedge clk) + dec2_cur_cur_dststep <= \dec2_cur_cur_dststep$next ; + always @(posedge clk) + dec2_cur_cur_srcstep <= \dec2_cur_cur_srcstep$next ; + always @(posedge clk) + dec2_cur_cur_vl <= \dec2_cur_cur_vl$next ; + always @(posedge clk) + dec2_cur_cur_maxvl <= \dec2_cur_cur_maxvl$next ; + always @(posedge clk) + jtag_dmi0__dout <= \jtag_dmi0__dout$next ; always @(posedge clk) jtag_dmi0__ack_o <= \jtag_dmi0__ack_o$next ; always @(posedge clk) dbg_dmi_din <= \dbg_dmi_din$next ; + always @(posedge clk) + core_dec <= \core_dec$next ; always @(posedge clk) dbg_dmi_we_i <= \dbg_dmi_we_i$next ; always @(posedge clk) dbg_dmi_req_i <= \dbg_dmi_req_i$next ; always @(posedge clk) dbg_dmi_addr_i <= \dbg_dmi_addr_i$next ; - always @(posedge clk) - core_eint <= \core_eint$next ; - always @(posedge clk) - core_dec <= \core_dec$next ; always @(posedge clk) core_core_svstep <= \core_core_svstep$next ; always @(posedge clk) @@ -198446,10 +211499,10 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus core_core_maxvl <= \core_core_maxvl$next ; always @(posedge clk) core_asmcode <= \core_asmcode$next ; - always @(posedge clk) - d_xer_delay <= \d_xer_delay$next ; always @(posedge clk) core_core_rego <= \core_core_rego$next ; + always @(posedge clk) + d_xer_delay <= \d_xer_delay$next ; always @(posedge clk) core_rego_ok <= \core_rego_ok$next ; always @(posedge clk) @@ -198468,10 +211521,10 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus core_core_reg3 <= \core_core_reg3$next ; always @(posedge clk) core_core_reg3_ok <= \core_core_reg3_ok$next ; - always @(posedge clk) - d_cr_delay <= \d_cr_delay$next ; always @(posedge clk) core_core_spro <= \core_core_spro$next ; + always @(posedge clk) + d_cr_delay <= \d_cr_delay$next ; always @(posedge clk) core_spro_ok <= \core_spro_ok$next ; always @(posedge clk) @@ -198490,8 +211543,12 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus core_core_fast2 <= \core_core_fast2$next ; always @(posedge clk) core_core_fast2_ok <= \core_core_fast2_ok$next ; + always @(posedge clk) + core_core_fast3 <= \core_core_fast3$next ; always @(posedge clk) d_reg_delay <= \d_reg_delay$next ; + always @(posedge clk) + core_core_fast3_ok <= \core_core_fast3_ok$next ; always @(posedge clk) core_core_fasto1 <= \core_core_fasto1$next ; always @(posedge clk) @@ -198500,28 +211557,44 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus core_core_fasto2 <= \core_core_fasto2$next ; always @(posedge clk) core_fasto2_ok <= \core_fasto2_ok$next ; + always @(posedge clk) + core_core_fasto3 <= \core_core_fasto3$next ; + always @(posedge clk) + core_fasto3_ok <= \core_fasto3_ok$next ; always @(posedge clk) core_core_cr_in1 <= \core_core_cr_in1$next ; always @(posedge clk) core_core_cr_in1_ok <= \core_core_cr_in1_ok$next ; always @(posedge clk) core_core_cr_in2 <= \core_core_cr_in2$next ; + always @(posedge clk) + exec_fsm_state <= \exec_fsm_state$next ; always @(posedge clk) core_core_cr_in2_ok <= \core_core_cr_in2_ok$next ; always @(posedge clk) \core_core_cr_in2$1 <= \core_core_cr_in2$1$next ; always @(posedge clk) \core_core_cr_in2_ok$2 <= \core_core_cr_in2_ok$2$next ; - always @(posedge clk) - exec_fsm_state <= \exec_fsm_state$next ; always @(posedge clk) core_core_cr_out <= \core_core_cr_out$next ; always @(posedge clk) core_cr_out_ok <= \core_cr_out_ok$next ; + always @(posedge clk) + core_core_core__sv_pred_sz <= \core_core_core__sv_pred_sz$next ; + always @(posedge clk) + core_core_core__sv_pred_dz <= \core_core_core__sv_pred_dz$next ; + always @(posedge clk) + core_core_core__sv_saturate <= \core_core_core__sv_saturate$next ; + always @(posedge clk) + core_core_core__SV_Ptype <= \core_core_core__SV_Ptype$next ; always @(posedge clk) core_core_core_msr <= \core_core_core_msr$next ; + always @(posedge clk) + \core_bigendian_i$10 <= \core_bigendian_i$10$next ; always @(posedge clk) core_core_core_cia <= \core_core_core_cia$next ; + always @(posedge clk) + core_core_core_svstate <= \core_core_core_svstate$next ; always @(posedge clk) core_core_core_insn <= \core_core_core_insn$next ; always @(posedge clk) @@ -198534,12 +211607,12 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus core_core_core_rc <= \core_core_core_rc$next ; always @(posedge clk) core_core_core_rc_ok <= \core_core_core_rc_ok$next ; - always @(posedge clk) - core_sv_a_nz <= \core_sv_a_nz$next ; always @(posedge clk) core_core_core_oe <= \core_core_core_oe$next ; always @(posedge clk) core_core_core_oe_ok <= \core_core_core_oe_ok$next ; + always @(posedge clk) + core_raw_insn_i <= \core_raw_insn_i$next ; always @(posedge clk) core_core_core_input_carry <= \core_core_core_input_carry$next ; always @(posedge clk) @@ -198556,12 +211629,12 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus \core_core_core_exc_$signal$6 <= \core_core_core_exc_$signal$6$next ; always @(posedge clk) \core_core_core_exc_$signal$7 <= \core_core_core_exc_$signal$7$next ; - always @(posedge clk) - \core_bigendian_i$10 <= \core_bigendian_i$10$next ; always @(posedge clk) \core_core_core_exc_$signal$8 <= \core_core_core_exc_$signal$8$next ; always @(posedge clk) \core_core_core_exc_$signal$9 <= \core_core_core_exc_$signal$9$next ; + always @(posedge clk) + core_core_pc <= \core_core_pc$next ; always @(posedge clk) core_core_core_trapaddr <= \core_core_core_trapaddr$next ; always @(posedge clk) @@ -198578,12 +211651,12 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus sv_changed <= \sv_changed$next ; always @(posedge clk) pc_changed <= \pc_changed$next ; - always @(posedge clk) - core_raw_insn_i <= \core_raw_insn_i$next ; always @(posedge clk) issue_fsm_state <= \issue_fsm_state$next ; always @(posedge clk) dec2_raw_opcode_in <= \dec2_raw_opcode_in$next ; + always @(posedge clk) + core_core_msr <= \core_core_msr$next ; always @(posedge clk) nia <= \nia$next ; always @(posedge clk) @@ -198600,32 +211673,18 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus delay <= \delay$next ; always @(posedge clk) dec2_cur_eint <= \dec2_cur_eint$next ; - always @(posedge clk) - core_core_pc <= \core_core_pc$next ; always @(posedge clk) dec2_cur_pc <= \dec2_cur_pc$next ; always @(posedge clk) dec2_cur_msr <= \dec2_cur_msr$next ; - always @(posedge clk) - dec2_cur_dec <= \dec2_cur_dec$next ; - always @(posedge clk) - cur_cur_svstep <= \cur_cur_svstep$next ; - always @(posedge clk) - cur_cur_subvl <= \cur_cur_subvl$next ; - always @(posedge clk) - cur_cur_dststep <= \cur_cur_dststep$next ; - always @(posedge clk) - cur_cur_srcstep <= \cur_cur_srcstep$next ; - always @(posedge clk) - cur_cur_vl <= \cur_cur_vl$next ; - always @(posedge clk) - cur_cur_maxvl <= \cur_cur_maxvl$next ; - always @(posedge clk) - jtag_dmi0__dout <= \jtag_dmi0__dout$next ; core core ( .bigendian_i(\core_bigendian_i$10 ), .cia__data_o(core_cia__data_o), .cia__ren(core_cia__ren), + .core_core__SV_Ptype(core_core_core__SV_Ptype), + .core_core__sv_pred_dz(core_core_core__sv_pred_dz), + .core_core__sv_pred_sz(core_core_core__sv_pred_sz), + .core_core__sv_saturate(core_core_core__sv_saturate), .core_core_cia(core_core_core_cia), .core_core_cr_rd(core_core_core_cr_rd), .core_core_cr_rd_ok(core_core_core_cr_rd_ok), @@ -198648,6 +211707,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus .core_core_oe_ok(core_core_core_oe_ok), .core_core_rc(core_core_core_rc), .core_core_rc_ok(core_core_core_rc_ok), + .core_core_svstate(core_core_core_svstate), .core_core_trapaddr(core_core_core_trapaddr), .core_core_traptype(core_core_core_traptype), .core_cr_in1(core_core_cr_in1), @@ -198662,8 +211722,12 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus .core_fast1_ok(core_core_fast1_ok), .core_fast2(core_core_fast2), .core_fast2_ok(core_core_fast2_ok), + .core_fast3(core_core_fast3), + .core_fast3_ok(core_core_fast3_ok), .core_fasto1(core_core_fasto1), .core_fasto2(core_core_fasto2), + .core_fasto3(core_core_fasto3), + .core_msr(core_core_msr), .core_pc(core_core_pc), .core_reg1(core_core_reg1), .core_reg1_ok(core_core_reg1_ok), @@ -198698,6 +211762,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus .dmi__addr(core_dmi__addr), .dmi__data_o(core_dmi__data_o), .dmi__ren(core_dmi__ren), + .\exc_o_$signal (\core_exc_o_$signal ), .full_rd2__data_o(core_full_rd2__data_o), .full_rd2__ren(core_full_rd2__ren), .full_rd__data_o(core_full_rd__data_o), @@ -198716,7 +211781,6 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus .state_nia_wen(core_state_nia_wen), .sv__data_o(core_sv__data_o), .sv__ren(core_sv__ren), - .sv_a_nz(core_sv_a_nz), .wb_dcache_en(core_wb_dcache_en), .wen(core_wen), .\wen$10 (\core_wen$11 ) @@ -198754,6 +211818,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus .terminate_i(dbg_terminate_i) ); dec2 dec2 ( + .SV_Ptype(dec2_SV_Ptype), .asmcode(dec2_asmcode), .bigendian(dec2_bigendian), .cia(dec2_cia), @@ -198769,6 +211834,12 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus .cr_rd_ok(dec2_cr_rd_ok), .cr_wr(dec2_cr_wr), .cr_wr_ok(dec2_cr_wr_ok), + .cur_cur_dststep(dec2_cur_cur_dststep), + .cur_cur_maxvl(dec2_cur_cur_maxvl), + .cur_cur_srcstep(dec2_cur_cur_srcstep), + .cur_cur_subvl(dec2_cur_cur_subvl), + .cur_cur_svstep(dec2_cur_cur_svstep), + .cur_cur_vl(dec2_cur_cur_vl), .cur_dec(dec2_cur_dec), .cur_eint(dec2_cur_eint), .cur_msr(dec2_cur_msr), @@ -198787,10 +211858,14 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus .fast1_ok(dec2_fast1_ok), .fast2(dec2_fast2), .fast2_ok(dec2_fast2_ok), + .fast3(dec2_fast3), + .fast3_ok(dec2_fast3_ok), .fasto1(dec2_fasto1), .fasto1_ok(dec2_fasto1_ok), .fasto2(dec2_fasto2), .fasto2_ok(dec2_fasto2_ok), + .fasto3(dec2_fasto3), + .fasto3_ok(dec2_fasto3_ok), .fn_unit(dec2_fn_unit), .input_carry(dec2_input_carry), .insn(dec2_insn), @@ -198815,7 +211890,10 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus .spr1_ok(dec2_spr1_ok), .spro(dec2_spro), .spro_ok(dec2_spro_ok), - .sv_a_nz(dec2_sv_a_nz), + .sv_pred_dz(dec2_sv_pred_dz), + .sv_pred_sz(dec2_sv_pred_sz), + .sv_saturate(dec2_sv_saturate), + .svstate(dec2_svstate), .trapaddr(dec2_trapaddr), .traptype(dec2_traptype), .xer_in(dec2_xer_in), @@ -199120,60 +212198,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus .sdr_we_n__core__o(sdr_we_n__core__o), .sdr_we_n__pad__o(sdr_we_n__pad__o), .wb_dcache_en(core_wb_dcache_en), - .wb_icache_en(imem_wb_icache_en), - .wb_sram_en(jtag_wb_sram_en) - ); - sram4k_0 sram4k_0 ( - .clk(clk), - .enable(sram4k_0_enable), - .rst(rst), - .sram4k_0_wb__ack(sram4k_0_wb__ack), - .sram4k_0_wb__adr(sram4k_0_wb__adr), - .sram4k_0_wb__cyc(sram4k_0_wb__cyc), - .sram4k_0_wb__dat_r(sram4k_0_wb__dat_r), - .sram4k_0_wb__dat_w(sram4k_0_wb__dat_w), - .sram4k_0_wb__sel(sram4k_0_wb__sel), - .sram4k_0_wb__stb(sram4k_0_wb__stb), - .sram4k_0_wb__we(sram4k_0_wb__we) - ); - sram4k_1 sram4k_1 ( - .clk(clk), - .enable(sram4k_1_enable), - .rst(rst), - .sram4k_1_wb__ack(sram4k_1_wb__ack), - .sram4k_1_wb__adr(sram4k_1_wb__adr), - .sram4k_1_wb__cyc(sram4k_1_wb__cyc), - .sram4k_1_wb__dat_r(sram4k_1_wb__dat_r), - .sram4k_1_wb__dat_w(sram4k_1_wb__dat_w), - .sram4k_1_wb__sel(sram4k_1_wb__sel), - .sram4k_1_wb__stb(sram4k_1_wb__stb), - .sram4k_1_wb__we(sram4k_1_wb__we) - ); - sram4k_2 sram4k_2 ( - .clk(clk), - .enable(sram4k_2_enable), - .rst(rst), - .sram4k_2_wb__ack(sram4k_2_wb__ack), - .sram4k_2_wb__adr(sram4k_2_wb__adr), - .sram4k_2_wb__cyc(sram4k_2_wb__cyc), - .sram4k_2_wb__dat_r(sram4k_2_wb__dat_r), - .sram4k_2_wb__dat_w(sram4k_2_wb__dat_w), - .sram4k_2_wb__sel(sram4k_2_wb__sel), - .sram4k_2_wb__stb(sram4k_2_wb__stb), - .sram4k_2_wb__we(sram4k_2_wb__we) - ); - sram4k_3 sram4k_3 ( - .clk(clk), - .enable(sram4k_3_enable), - .rst(rst), - .sram4k_3_wb__ack(sram4k_3_wb__ack), - .sram4k_3_wb__adr(sram4k_3_wb__adr), - .sram4k_3_wb__cyc(sram4k_3_wb__cyc), - .sram4k_3_wb__dat_r(sram4k_3_wb__dat_r), - .sram4k_3_wb__dat_w(sram4k_3_wb__dat_w), - .sram4k_3_wb__sel(sram4k_3_wb__sel), - .sram4k_3_wb__stb(sram4k_3_wb__stb), - .sram4k_3_wb__we(sram4k_3_wb__we) + .wb_icache_en(imem_wb_icache_en) ); xics_icp xics_icp ( .clk(clk), @@ -199207,7 +212232,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end \dbg_dmi_addr_i$next = jtag_dmi0__addr_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \dbg_dmi_addr_i$next = 4'h0; @@ -199216,26 +212241,16 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end \dbg_dmi_req_i$next = jtag_dmi0__req_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \dbg_dmi_req_i$next = 1'h0; endcase end - always @* begin - if (\initial ) begin end - \delay$next = delay; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *) - casez (\$25 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" */ - 1'h1: - \delay$next = \$27 [1:0]; - endcase - end always @* begin if (\initial ) begin end \core_core_pc$next = core_core_pc; - \core_msr$next = core_msr; + \core_core_msr$next = core_core_msr; \core_eint$next = core_eint; \core_dec$next = core_dec; \core_core_svstep$next = core_core_svstep; @@ -199244,39 +212259,39 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus \core_core_srcstep$next = core_core_srcstep; \core_core_vl$next = core_core_vl; \core_core_maxvl$next = core_core_maxvl; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */ 3'h2: - { \core_core_maxvl$next , \core_core_vl$next , \core_core_srcstep$next , \core_core_dststep$next , \core_core_subvl$next , \core_core_svstep$next , \core_dec$next , \core_eint$next , \core_msr$next , \core_core_pc$next } = { cur_cur_maxvl, cur_cur_vl, cur_cur_srcstep, cur_cur_dststep, cur_cur_subvl, cur_cur_svstep, dec2_cur_dec, dec2_cur_eint, dec2_cur_msr, dec2_cur_pc }; + { \core_core_maxvl$next , \core_core_vl$next , \core_core_srcstep$next , \core_core_dststep$next , \core_core_subvl$next , \core_core_svstep$next , \core_dec$next , \core_eint$next , \core_core_msr$next , \core_core_pc$next } = { dec2_cur_cur_maxvl, dec2_cur_cur_vl, dec2_cur_cur_srcstep, dec2_cur_cur_dststep, dec2_cur_cur_subvl, dec2_cur_cur_svstep, dec2_cur_dec, dec2_cur_eint, dec2_cur_msr, dec2_cur_pc }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: begin \core_core_pc$next = 64'h0000000000000000; - \core_msr$next = 64'h0000000000000000; + \core_core_msr$next = 64'h0000000000000000; \core_eint$next = 1'h0; \core_dec$next = 64'h0000000000000000; \core_core_svstep$next = 2'h0; @@ -199291,34 +212306,34 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end \core_raw_insn_i$next = core_raw_insn_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */ 3'h2: \core_raw_insn_i$next = dec2_raw_opcode_in; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \core_raw_insn_i$next = 32'd0; @@ -199327,106 +212342,70 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end \core_bigendian_i$10$next = \core_bigendian_i$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */ 3'h2: \core_bigendian_i$10$next = core_bigendian_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \core_bigendian_i$10$next = 1'h0; endcase end - always @* begin - if (\initial ) begin end - \core_sv_a_nz$next = core_sv_a_nz; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) - casez (issue_fsm_state) - /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ - 3'h0: - /* empty */; - /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */ - 3'h1: - /* empty */; - /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ - 3'h3: - /* empty */; - /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */ - 3'h4: - /* empty */; - /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */ - 3'h5: - /* empty */; - /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */ - 3'h2: - \core_sv_a_nz$next = dec2_sv_a_nz; - endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) - casez (rst) - 1'h1: - \core_sv_a_nz$next = 1'h0; - endcase - end always @* begin if (\initial ) begin end exec_insn_valid_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */ 3'h6: exec_insn_valid_i = 1'h1; endcase @@ -199435,42 +212414,42 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end exec_pc_ready_i = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:689" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */ 3'h7: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) - casez (\$244 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + casez (\$246 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */ 1'h1: exec_pc_ready_i = 1'h1; endcase @@ -199480,48 +212459,48 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end is_last = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:689" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */ 3'h7: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) - casez (\$250 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + casez (\$252 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:694" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" *) casez (exec_pc_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:694" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" */ 1'h1: - is_last = \$252 ; + is_last = \$254 ; endcase endcase endcase @@ -199529,9 +212508,9 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end \core_wen$11 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:751" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" *) casez (update_svstate) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:751" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" */ 1'h1: \core_wen$11 = 3'h4; endcase @@ -199539,20 +212518,20 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end \core_data_i$12 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:751" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" *) casez (update_svstate) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:751" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" */ 1'h1: - \core_data_i$12 = \$254 ; + \core_data_i$12 = \$256 ; endcase end always @* begin if (\initial ) begin end exec_insn_ready_o = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:777" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) casez (exec_fsm_state) /* \nmigen.decoding = "INSN_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:780" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:857" */ 1'h0: exec_insn_ready_o = 1'h1; endcase @@ -199561,23 +212540,23 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end core_ivalid_i = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:777" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) casez (exec_fsm_state) /* \nmigen.decoding = "INSN_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:780" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:857" */ 1'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *) casez (exec_insn_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" */ 1'h1: core_ivalid_i = 1'h1; endcase /* \nmigen.decoding = "INSN_ACTIVE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791" *) - casez (\$256 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" *) + casez (\$258 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" */ 1'h1: core_ivalid_i = 1'h1; endcase @@ -199586,14 +212565,14 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end core_issue_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:777" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) casez (exec_fsm_state) /* \nmigen.decoding = "INSN_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:780" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:857" */ 1'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *) casez (exec_insn_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" */ 1'h1: core_issue_i = 1'h1; endcase @@ -199603,33 +212582,33 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end \exec_fsm_state$next = exec_fsm_state; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:777" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) casez (exec_fsm_state) /* \nmigen.decoding = "INSN_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:780" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:857" */ 1'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *) casez (exec_insn_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" */ 1'h1: \exec_fsm_state$next = 1'h1; endcase /* \nmigen.decoding = "INSN_ACTIVE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" *) - casez (\$258 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *) + casez (\$260 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:877" *) casez (exec_pc_ready_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:877" */ 1'h1: \exec_fsm_state$next = 1'h0; endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \exec_fsm_state$next = 1'h0; @@ -199639,18 +212618,18 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end exec_pc_valid_o = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:777" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) casez (exec_fsm_state) /* \nmigen.decoding = "INSN_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:780" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:857" */ 1'h0: /* empty */; /* \nmigen.decoding = "INSN_ACTIVE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" *) - casez (\$260 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *) + casez (\$262 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" */ 1'h1: exec_pc_valid_o = 1'h1; endcase @@ -199659,9 +212638,9 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end core_dmi__addr = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1016" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1094" *) casez (dbg_d_gpr_req) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1016" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1094" */ 1'h1: core_dmi__addr = dbg_d_gpr_addr[4:0]; endcase @@ -199669,9 +212648,9 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end core_dmi__ren = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1016" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1094" *) casez (dbg_d_gpr_req) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1016" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1094" */ 1'h1: core_dmi__ren = 1'h1; endcase @@ -199679,7 +212658,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end \d_reg_delay$next = dbg_d_gpr_req; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \d_reg_delay$next = 1'h0; @@ -199688,9 +212667,9 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end dbg_d_gpr_data = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1026" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1104" *) casez (d_reg_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1026" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1104" */ 1'h1: dbg_d_gpr_data = core_dmi__data_o; endcase @@ -199698,9 +212677,9 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end dbg_d_gpr_ack = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1026" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1104" *) casez (d_reg_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1026" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1104" */ 1'h1: dbg_d_gpr_ack = 1'h1; endcase @@ -199708,9 +212687,9 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end core_full_rd2__ren = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1032" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1110" *) casez (dbg_d_cr_req) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1032" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1110" */ 1'h1: core_full_rd2__ren = 8'hff; endcase @@ -199718,7 +212697,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end \d_cr_delay$next = dbg_d_cr_req; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \d_cr_delay$next = 1'h0; @@ -199727,19 +212706,19 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end dbg_d_cr_data = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1036" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1114" *) casez (d_cr_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1036" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1114" */ 1'h1: - dbg_d_cr_data = \$262 ; + dbg_d_cr_data = \$264 ; endcase end always @* begin if (\initial ) begin end dbg_d_cr_ack = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1036" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1114" *) casez (d_cr_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1036" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1114" */ 1'h1: dbg_d_cr_ack = 1'h1; endcase @@ -199747,9 +212726,9 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end core_full_rd__ren = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1042" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1120" *) casez (dbg_d_xer_req) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1042" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1120" */ 1'h1: core_full_rd__ren = 3'h7; endcase @@ -199757,7 +212736,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end \d_xer_delay$next = dbg_d_xer_req; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \d_xer_delay$next = 1'h0; @@ -199766,57 +212745,57 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end dbg_d_xer_data = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1046" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1124" *) casez (d_xer_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1046" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1124" */ 1'h1: - dbg_d_xer_data = \$264 ; + dbg_d_xer_data = \$266 ; endcase end always @* begin if (\initial ) begin end dbg_d_xer_ack = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1046" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1124" *) casez (d_xer_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1046" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1124" */ 1'h1: dbg_d_xer_ack = 1'h1; endcase end always @* begin if (\initial ) begin end - core_issue__addr = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1067" *) + core_issue__addr = 4'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1070" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1148" */ 2'h0: - core_issue__addr = 3'h6; + core_issue__addr = 4'h6; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1076" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1154" */ 2'h1: /* empty */; /* \nmigen.decoding = "TB_READ/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1087" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1165" */ 2'h2: - core_issue__addr = 3'h7; + core_issue__addr = 4'h7; endcase end always @* begin if (\initial ) begin end core_issue__ren = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1067" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1070" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1148" */ 2'h0: core_issue__ren = 1'h1; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1076" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1154" */ 2'h1: /* empty */; /* \nmigen.decoding = "TB_READ/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1087" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1165" */ 2'h2: core_issue__ren = 1'h1; endcase @@ -199824,26 +212803,26 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1067" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1070" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1148" */ 2'h0: \fsm_state$next = 2'h1; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1076" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1154" */ 2'h1: \fsm_state$next = 2'h2; /* \nmigen.decoding = "TB_READ/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1087" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1165" */ 2'h2: \fsm_state$next = 2'h3; /* \nmigen.decoding = "TB_WRITE/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1093" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1171" */ 2'h3: \fsm_state$next = 2'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \fsm_state$next = 2'h0; @@ -199852,62 +212831,62 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end new_dec = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1067" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1070" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1148" */ 2'h0: /* empty */; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1076" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1154" */ 2'h1: - new_dec = \$266 [63:0]; + new_dec = \$268 [63:0]; endcase end always @* begin if (\initial ) begin end - \core_issue__addr$13 = 3'h0; + \core_issue__addr$13 = 4'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1067" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1070" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1148" */ 2'h0: /* empty */; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1076" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1154" */ 2'h1: - \core_issue__addr$13 = 3'h6; + \core_issue__addr$13 = 4'h6; /* \nmigen.decoding = "TB_READ/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1087" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1165" */ 2'h2: /* empty */; /* \nmigen.decoding = "TB_WRITE/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1093" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1171" */ 2'h3: - \core_issue__addr$13 = 3'h7; + \core_issue__addr$13 = 4'h7; endcase end always @* begin if (\initial ) begin end core_issue__wen = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1067" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1070" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1148" */ 2'h0: /* empty */; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1076" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1154" */ 2'h1: core_issue__wen = 1'h1; /* \nmigen.decoding = "TB_READ/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1087" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1165" */ 2'h2: /* empty */; /* \nmigen.decoding = "TB_WRITE/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1093" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1171" */ 2'h3: core_issue__wen = 1'h1; endcase @@ -199916,22 +212895,22 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end core_issue__data_i = 64'h0000000000000000; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1067" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1070" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1148" */ 2'h0: /* empty */; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1076" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1154" */ 2'h1: core_issue__data_i = new_dec; /* \nmigen.decoding = "TB_READ/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1087" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1165" */ 2'h2: /* empty */; /* \nmigen.decoding = "TB_WRITE/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1093" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1171" */ 2'h3: core_issue__data_i = new_tb; endcase @@ -199940,33 +212919,24 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end new_tb = 64'h0000000000000000; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1067" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1070" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1148" */ 2'h0: /* empty */; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1076" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1154" */ 2'h1: /* empty */; /* \nmigen.decoding = "TB_READ/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1087" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1165" */ 2'h2: /* empty */; /* \nmigen.decoding = "TB_WRITE/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1093" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1171" */ 2'h3: - new_tb = \$269 [63:0]; - endcase - end - always @* begin - if (\initial ) begin end - \dbg_dmi_we_i$next = jtag_dmi0__we_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) - casez (rst) - 1'h1: - \dbg_dmi_we_i$next = 1'h0; + new_tb = \$271 [63:0]; endcase end always @* begin @@ -199974,61 +212944,61 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus \dec2_cur_pc$next = dec2_cur_pc; \dec2_cur_msr$next = dec2_cur_msr; \dec2_cur_dec$next = dec2_cur_dec; - \cur_cur_svstep$next = cur_cur_svstep; - \cur_cur_subvl$next = cur_cur_subvl; - \cur_cur_dststep$next = cur_cur_dststep; - \cur_cur_srcstep$next = cur_cur_srcstep; - \cur_cur_vl$next = cur_cur_vl; - \cur_cur_maxvl$next = cur_cur_maxvl; + \dec2_cur_cur_svstep$next = dec2_cur_cur_svstep; + \dec2_cur_cur_subvl$next = dec2_cur_cur_subvl; + \dec2_cur_cur_dststep$next = dec2_cur_cur_dststep; + \dec2_cur_cur_srcstep$next = dec2_cur_cur_srcstep; + \dec2_cur_cur_vl$next = dec2_cur_cur_vl; + \dec2_cur_cur_maxvl$next = dec2_cur_cur_maxvl; \dec2_cur_eint$next = xics_icp_core_irq_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:894" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:971" *) casez (core_coresync_rst) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:894" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:971" */ 1'h1: - { \cur_cur_maxvl$next , \cur_cur_vl$next , \cur_cur_srcstep$next , \cur_cur_dststep$next , \cur_cur_subvl$next , \cur_cur_svstep$next , \dec2_cur_dec$next , \dec2_cur_eint$next , \dec2_cur_msr$next , \dec2_cur_pc$next } = 225'h000000000000000000000000000000000000000000000000000000000; + { \dec2_cur_cur_maxvl$next , \dec2_cur_cur_vl$next , \dec2_cur_cur_srcstep$next , \dec2_cur_cur_dststep$next , \dec2_cur_cur_subvl$next , \dec2_cur_cur_svstep$next , \dec2_cur_dec$next , \dec2_cur_eint$next , \dec2_cur_msr$next , \dec2_cur_pc$next } = 225'h000000000000000000000000000000000000000000000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */ 2'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *) casez (fetch_pc_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" */ 1'h1: begin \dec2_cur_pc$next = pc; - { \cur_cur_maxvl$next , \cur_cur_vl$next , \cur_cur_srcstep$next , \cur_cur_dststep$next , \cur_cur_subvl$next , \cur_cur_svstep$next } = svstate[31:0]; + { \dec2_cur_cur_maxvl$next , \dec2_cur_cur_vl$next , \dec2_cur_cur_srcstep$next , \dec2_cur_cur_dststep$next , \dec2_cur_cur_subvl$next , \dec2_cur_cur_svstep$next } = svstate[31:0]; end endcase /* \nmigen.decoding = "INSN_READ/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */ 2'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *) casez (\$23 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" */ 1'h1: \dec2_cur_msr$next = core_msr__data_o; endcase endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:751" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" *) casez (update_svstate) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:751" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" */ 1'h1: - { \cur_cur_maxvl$next , \cur_cur_vl$next , \cur_cur_srcstep$next , \cur_cur_dststep$next , \cur_cur_subvl$next , \cur_cur_svstep$next } = { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep }; + { \dec2_cur_cur_maxvl$next , \dec2_cur_cur_vl$next , \dec2_cur_cur_srcstep$next , \dec2_cur_cur_dststep$next , \dec2_cur_cur_subvl$next , \dec2_cur_cur_svstep$next } = { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep }; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1067" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1070" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1148" */ 2'h0: /* empty */; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1076" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1154" */ 2'h1: \dec2_cur_dec$next = new_dec; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: begin @@ -200036,56 +213006,65 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus \dec2_cur_pc$next = 64'h0000000000000000; \dec2_cur_msr$next = 64'h0000000000000000; \dec2_cur_dec$next = 64'h0000000000000000; - \cur_cur_svstep$next = 2'h0; - \cur_cur_subvl$next = 2'h0; - \cur_cur_dststep$next = 7'h00; - \cur_cur_srcstep$next = 7'h00; - \cur_cur_vl$next = 7'h00; - \cur_cur_maxvl$next = 7'h00; + \dec2_cur_cur_svstep$next = 2'h0; + \dec2_cur_cur_subvl$next = 2'h0; + \dec2_cur_cur_dststep$next = 7'h00; + \dec2_cur_cur_srcstep$next = 7'h00; + \dec2_cur_cur_vl$next = 7'h00; + \dec2_cur_cur_maxvl$next = 7'h00; end endcase end always @* begin if (\initial ) begin end - \dbg_dmi_din$next = jtag_dmi0__din; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \dbg_dmi_we_i$next = jtag_dmi0__we_i; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: - \dbg_dmi_din$next = 64'h0000000000000000; + \dbg_dmi_we_i$next = 1'h0; endcase end always @* begin if (\initial ) begin end \pc_ok_delay$next = pc_ok_delay; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) casez (\$40 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" */ 1'h1: \pc_ok_delay$next = \$42 ; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \pc_ok_delay$next = 1'h0; endcase end + always @* begin + if (\initial ) begin end + \dbg_dmi_din$next = jtag_dmi0__din; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + casez (rst) + 1'h1: + \dbg_dmi_din$next = 64'h0000000000000000; + endcase + end always @* begin if (\initial ) begin end pc = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) casez (\$44 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" */ 1'h1: begin - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:68" *) casez (pc_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:68" */ 1'h1: pc = pc_i; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:74" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:75" *) casez (pc_ok_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:74" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:75" */ 1'h1: pc = core_cia__data_o; endcase @@ -200095,17 +213074,17 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end core_cia__ren = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) casez (\$46 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:68" *) casez (pc_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:68" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:70" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:71" */ default: core_cia__ren = 3'h1; endcase @@ -200114,13 +213093,13 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end \svstate_ok_delay$next = svstate_ok_delay; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) casez (\$48 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" */ 1'h1: \svstate_ok_delay$next = \$50 ; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \svstate_ok_delay$next = 1'h0; @@ -200129,20 +213108,20 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end svstate = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) casez (\$52 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" */ 1'h1: begin - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:68" *) casez (svstate_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:68" */ 1'h1: svstate = \$54 ; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:74" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:75" *) casez (svstate_ok_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:74" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:75" */ 1'h1: svstate = core_sv__data_o; endcase @@ -200152,17 +213131,17 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end core_sv__ren = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) casez (\$56 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:68" *) casez (svstate_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:68" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:70" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:71" */ default: core_sv__ren = 3'h4; endcase @@ -200172,187 +213151,178 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end core_wen = 3'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ 3'h0: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) casez (\$62 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:567" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622" *) casez (pc_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:567" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622" */ 1'h1: core_wen = 3'h1; endcase endcase /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ 3'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:579" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634" *) casez (fetch_insn_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:579" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) casez (\$66 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" */ 1'h1: core_wen = 3'h1; endcase endcase /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:689" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */ 3'h7: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) casez (\$72 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:694" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" *) casez (exec_pc_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:694" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) casez ({ \$78 , \$74 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" */ 2'b?1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" */ 2'b1?: core_wen = 3'h1; endcase endcase - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:815" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:741" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:818" *) casez (pc_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:741" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:818" */ 1'h1: core_wen = 3'h1; endcase endcase endcase end - always @* begin - if (\initial ) begin end - \jtag_dmi0__ack_o$next = dbg_dmi_ack_o; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) - casez (rst) - 1'h1: - \jtag_dmi0__ack_o$next = 1'h0; - endcase - end always @* begin if (\initial ) begin end core_data_i = 64'h0000000000000000; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ 3'h0: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) casez (\$84 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:567" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622" *) casez (pc_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:567" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622" */ 1'h1: core_data_i = pc_i; endcase endcase /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ 3'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:579" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634" *) casez (fetch_insn_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:579" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) casez (\$88 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" */ 1'h1: core_data_i = nia; endcase endcase /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:689" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */ 3'h7: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) casez (\$94 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:694" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" *) casez (exec_pc_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:694" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) casez ({ \$100 , \$96 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" */ 2'b?1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" */ 2'b1?: core_data_i = nia; endcase endcase - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:815" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:741" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:818" *) casez (pc_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:741" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:818" */ 1'h1: core_data_i = pc_i; endcase @@ -200362,14 +213332,14 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end core_msr__ren = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */ 2'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *) casez (fetch_pc_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" */ 1'h1: core_msr__ren = 3'h2; endcase @@ -200377,20 +213347,20 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus end always @* begin if (\initial ) begin end - \jtag_dmi0__dout$next = dbg_dmi_dout; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \jtag_dmi0__ack_o$next = dbg_dmi_ack_o; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: - \jtag_dmi0__dout$next = 64'h0000000000000000; + \jtag_dmi0__ack_o$next = 1'h0; endcase end always @* begin if (\initial ) begin end fetch_pc_ready_o = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */ 2'h0: fetch_pc_ready_o = 1'h1; endcase @@ -200398,14 +213368,14 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end imem_a_pc_i = 48'h000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */ 2'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *) casez (fetch_pc_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" */ 1'h1: imem_a_pc_i = pc[47:0]; endcase @@ -200414,66 +213384,75 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end imem_a_valid_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */ 2'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *) casez (fetch_pc_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" */ 1'h1: imem_a_valid_i = 1'h1; endcase /* \nmigen.decoding = "INSN_READ/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */ 2'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" *) casez (imem_f_busy_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" */ 1'h1: imem_a_valid_i = 1'h1; endcase /* \nmigen.decoding = "INSN_READ2/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */ 2'h3: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" *) casez (imem_f_busy_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" */ 1'h1: imem_a_valid_i = 1'h1; endcase endcase end + always @* begin + if (\initial ) begin end + \jtag_dmi0__dout$next = dbg_dmi_dout; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + casez (rst) + 1'h1: + \jtag_dmi0__dout$next = 64'h0000000000000000; + endcase + end always @* begin if (\initial ) begin end imem_f_valid_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */ 2'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *) casez (fetch_pc_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" */ 1'h1: imem_f_valid_i = 1'h1; endcase /* \nmigen.decoding = "INSN_READ/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */ 2'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" *) casez (imem_f_busy_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" */ 1'h1: imem_f_valid_i = 1'h1; endcase /* \nmigen.decoding = "INSN_READ2/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */ 2'h3: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" *) casez (imem_f_busy_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" */ 1'h1: imem_f_valid_i = 1'h1; endcase @@ -200482,28 +213461,28 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end \msr_read$next = msr_read; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */ 2'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *) casez (fetch_pc_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" */ 1'h1: \msr_read$next = 1'h0; endcase /* \nmigen.decoding = "INSN_READ/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */ 2'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *) casez (\$102 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" */ 1'h1: \msr_read$next = 1'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \msr_read$next = 1'h1; @@ -200513,54 +213492,54 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end \fetch_fsm_state$next = fetch_fsm_state; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */ 2'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *) casez (fetch_pc_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" */ 1'h1: \fetch_fsm_state$next = 2'h1; endcase /* \nmigen.decoding = "INSN_READ/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */ 2'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" *) casez (imem_f_busy_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:324" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" */ default: \fetch_fsm_state$next = 2'h2; endcase /* \nmigen.decoding = "INSN_READ2/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */ 2'h3: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" *) casez (imem_f_busy_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:362" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" */ default: \fetch_fsm_state$next = 2'h2; endcase /* \nmigen.decoding = "INSN_READY/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:383" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:384" */ 2'h2: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387" *) casez (fetch_insn_ready_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387" */ 1'h1: \fetch_fsm_state$next = 2'h0; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \fetch_fsm_state$next = 2'h0; @@ -200569,33 +213548,33 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end \nia$next = nia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */ 2'h0: /* empty */; /* \nmigen.decoding = "INSN_READ/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */ 2'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" *) casez (imem_f_busy_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:324" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" */ default: \nia$next = \$104 [63:0]; endcase endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:992" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1070" *) casez (core_coresync_rst) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:992" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1070" */ 1'h1: \nia$next = 64'h0000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \nia$next = 64'h0000000000000000; @@ -200604,35 +213583,35 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end \dec2_raw_opcode_in$next = dec2_raw_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */ 2'h0: /* empty */; /* \nmigen.decoding = "INSN_READ/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */ 2'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" *) casez (imem_f_busy_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:324" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" */ default: \dec2_raw_opcode_in$next = \$107 ; endcase /* \nmigen.decoding = "INSN_READ2/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */ 2'h3: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" *) casez (imem_f_busy_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:362" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" */ default: \dec2_raw_opcode_in$next = \$111 ; endcase @@ -200642,99 +213621,99 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end fetch_insn_valid_o = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */ 2'h0: /* empty */; /* \nmigen.decoding = "INSN_READ/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */ 2'h1: /* empty */; /* \nmigen.decoding = "INSN_READ2/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */ 2'h3: /* empty */; /* \nmigen.decoding = "INSN_READY/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:383" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:384" */ 2'h2: fetch_insn_valid_o = 1'h1; endcase end always @* begin if (\initial ) begin end - { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep } = { cur_cur_maxvl, cur_cur_vl, cur_cur_srcstep, cur_cur_dststep, cur_cur_subvl, cur_cur_svstep }; + { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep } = { dec2_cur_cur_maxvl, dec2_cur_cur_vl, dec2_cur_cur_srcstep, dec2_cur_cur_dststep, dec2_cur_cur_subvl, dec2_cur_cur_svstep }; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ 3'h0: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) casez (\$122 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:571" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626" *) casez (svstate_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:571" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626" */ 1'h1: { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep } = svstate_i; endcase endcase /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:689" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */ 3'h7: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) casez (\$128 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:694" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" *) casez (exec_pc_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:694" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) casez ({ \$134 , \$130 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" */ 2'b?1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" */ 2'b1?: begin new_svstate_srcstep = 7'h00; new_svstate_dststep = 7'h00; end - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:808" */ default: begin new_svstate_srcstep = next_srcstep; @@ -200742,11 +213721,11 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus end endcase endcase - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:815" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:745" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:822" *) casez (svstate_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:745" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:822" */ 1'h1: { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep } = svstate_i; endcase @@ -200756,14 +213735,14 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end fetch_pc_valid_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ 3'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) - casez (\$146 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + casez (\$148 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */ 1'h1: fetch_pc_valid_i = 1'h1; endcase @@ -200773,108 +213752,108 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end \issue_fsm_state$next = issue_fsm_state; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ 3'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) - casez (\$152 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + casez (\$154 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:561" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:616" *) casez (fetch_pc_ready_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:561" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:616" */ 1'h1: \issue_fsm_state$next = 3'h1; endcase endcase /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ 3'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:579" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634" *) casez (fetch_insn_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:579" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *) - casez (\$156 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) + casez (\$158 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" */ 1'h1: \issue_fsm_state$next = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:592" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:647" */ default: \issue_fsm_state$next = 3'h2; endcase endcase /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ 3'h3: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:600" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:655" *) casez (pred_insn_ready_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:600" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:655" */ 1'h1: \issue_fsm_state$next = 3'h4; endcase /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */ 3'h4: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:660" *) casez (pred_mask_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:660" */ 1'h1: \issue_fsm_state$next = 3'h5; endcase /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */ 3'h5: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" *) - casez (\$158 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" *) + casez (\$160 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */ 1'h1: \issue_fsm_state$next = 3'h2; endcase /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */ 3'h2: \issue_fsm_state$next = 3'h6; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */ 3'h6: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:686" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:749" *) casez (exec_insn_ready_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:686" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:749" */ 1'h1: \issue_fsm_state$next = 3'h7; endcase /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:689" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */ 3'h7: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) - casez (\$164 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + casez (\$166 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:694" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" *) casez (exec_pc_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:694" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" *) - casez ({ \$170 , \$166 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) + casez ({ \$172 , \$168 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" */ 2'b?1: \issue_fsm_state$next = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" */ 2'b1?: \issue_fsm_state$next = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:808" */ default: \issue_fsm_state$next = 3'h5; endcase endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \issue_fsm_state$next = 3'h0; @@ -200884,55 +213863,55 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end dbg_core_stopped_i = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ 3'h0: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) - casez (\$176 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + casez (\$178 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" */ default: dbg_core_stopped_i = 1'h1; endcase /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:689" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */ 3'h7: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) - casez (\$182 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + casez (\$184 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:815" */ default: dbg_core_stopped_i = 1'h1; endcase @@ -200942,92 +213921,92 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end \pc_changed$next = pc_changed; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ 3'h0: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) - casez (\$188 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + casez (\$190 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:567" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622" *) casez (pc_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:567" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622" */ 1'h1: \pc_changed$next = 1'h1; endcase endcase /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:689" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */ 3'h7: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) - casez (\$194 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + casez (\$196 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:815" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:741" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:818" *) casez (pc_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:741" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:818" */ 1'h1: \pc_changed$next = 1'h1; endcase endcase endcase (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:777" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) casez (exec_fsm_state) /* \nmigen.decoding = "INSN_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:780" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:857" */ 1'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *) casez (exec_insn_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" */ 1'h1: \pc_changed$next = 1'h0; endcase /* \nmigen.decoding = "INSN_ACTIVE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:796" *) - casez (\$196 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:796" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:873" *) + casez (\$198 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:873" */ 1'h1: \pc_changed$next = 1'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \pc_changed$next = 1'h0; @@ -201037,81 +214016,81 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end update_svstate = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ 3'h0: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) - casez (\$204 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + casez (\$206 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:571" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626" *) casez (svstate_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:571" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626" */ 1'h1: update_svstate = 1'h1; endcase endcase /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:689" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */ 3'h7: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) - casez (\$210 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + casez (\$212 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:694" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" *) casez (exec_pc_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:694" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" *) - casez ({ \$216 , \$212 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) + casez ({ \$218 , \$214 }) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" */ 2'b?1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" */ 2'b1?: update_svstate = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:808" */ default: update_svstate = 1'h1; endcase endcase - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:815" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:745" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:822" *) casez (svstate_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:745" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:822" */ 1'h1: update_svstate = 1'h1; endcase @@ -201122,92 +214101,92 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end \sv_changed$next = sv_changed; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ 3'h0: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) - casez (\$222 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + casez (\$224 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:571" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626" *) casez (svstate_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:571" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626" */ 1'h1: \sv_changed$next = 1'h1; endcase endcase /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:689" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */ 3'h7: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) - casez (\$228 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + casez (\$230 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:815" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:745" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:822" *) casez (svstate_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:745" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:822" */ 1'h1: \sv_changed$next = 1'h1; endcase endcase endcase (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:777" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) casez (exec_fsm_state) /* \nmigen.decoding = "INSN_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:780" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:857" */ 1'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *) casez (exec_insn_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" */ 1'h1: \sv_changed$next = 1'h0; endcase /* \nmigen.decoding = "INSN_ACTIVE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794" *) - casez (\$230 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:871" *) + casez (\$232 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:871" */ 1'h1: \sv_changed$next = 1'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \sv_changed$next = 1'h0; @@ -201216,14 +214195,14 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end fetch_insn_ready_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ 3'h1: fetch_insn_ready_i = 1'h1; endcase @@ -201231,44 +214210,44 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end insn_done = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ 3'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:579" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634" *) casez (fetch_insn_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:579" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *) - casez (\$236 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) + casez (\$238 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" */ 1'h1: insn_done = 1'h1; endcase endcase endcase (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:777" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) casez (exec_fsm_state) /* \nmigen.decoding = "INSN_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:780" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:857" */ 1'h0: /* empty */; /* \nmigen.decoding = "INSN_ACTIVE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" *) - casez (\$238 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" */ + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *) + casez (\$240 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:877" *) casez (exec_pc_ready_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:877" */ 1'h1: insn_done = 1'h1; endcase @@ -201278,18 +214257,18 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end pred_insn_valid_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ 3'h3: pred_insn_valid_i = 1'h1; endcase @@ -201297,22 +214276,22 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end pred_mask_ready_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */ 3'h4: pred_mask_ready_i = 1'h1; endcase @@ -201340,10 +214319,14 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus \core_core_fast1_ok$next = core_core_fast1_ok; \core_core_fast2$next = core_core_fast2; \core_core_fast2_ok$next = core_core_fast2_ok; + \core_core_fast3$next = core_core_fast3; + \core_core_fast3_ok$next = core_core_fast3_ok; \core_core_fasto1$next = core_core_fasto1; \core_fasto1_ok$next = core_fasto1_ok; \core_core_fasto2$next = core_core_fasto2; \core_fasto2_ok$next = core_fasto2_ok; + \core_core_fasto3$next = core_core_fasto3; + \core_fasto3_ok$next = core_fasto3_ok; \core_core_cr_in1$next = core_core_cr_in1; \core_core_cr_in1_ok$next = core_core_cr_in1_ok; \core_core_cr_in2$next = core_core_cr_in2; @@ -201352,8 +214335,13 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus \core_core_cr_in2_ok$2$next = \core_core_cr_in2_ok$2 ; \core_core_cr_out$next = core_core_cr_out; \core_cr_out_ok$next = core_cr_out_ok; + \core_core_core__sv_pred_sz$next = core_core_core__sv_pred_sz; + \core_core_core__sv_pred_dz$next = core_core_core__sv_pred_dz; + \core_core_core__sv_saturate$next = core_core_core__sv_saturate; + \core_core_core__SV_Ptype$next = core_core_core__SV_Ptype; \core_core_core_msr$next = core_core_core_msr; \core_core_core_cia$next = core_core_core_cia; + \core_core_core_svstate$next = core_core_core_svstate; \core_core_core_insn$next = core_core_core_insn; \core_core_core_insn_type$next = core_core_core_insn_type; \core_core_core_fn_unit$next = core_core_core_fn_unit; @@ -201378,34 +214366,34 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus \core_core_core_cr_wr$next = core_core_core_cr_wr; \core_core_cr_wr_ok$next = core_core_cr_wr_ok; \core_core_core_is_32bit$next = core_core_core_is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */ 3'h2: - { \core_core_core_is_32bit$next , \core_core_cr_wr_ok$next , \core_core_core_cr_wr$next , \core_core_core_cr_rd_ok$next , \core_core_core_cr_rd$next , \core_core_core_trapaddr$next , \core_core_core_exc_$signal$9$next , \core_core_core_exc_$signal$8$next , \core_core_core_exc_$signal$7$next , \core_core_core_exc_$signal$6$next , \core_core_core_exc_$signal$5$next , \core_core_core_exc_$signal$4$next , \core_core_core_exc_$signal$3$next , \core_core_core_exc_$signal$next , \core_core_core_traptype$next , \core_core_core_input_carry$next , \core_core_core_oe_ok$next , \core_core_core_oe$next , \core_core_core_rc_ok$next , \core_core_core_rc$next , \core_core_lk$next , \core_core_core_fn_unit$next , \core_core_core_insn_type$next , \core_core_core_insn$next , \core_core_core_cia$next , \core_core_core_msr$next , \core_cr_out_ok$next , \core_core_cr_out$next , \core_core_cr_in2_ok$2$next , \core_core_cr_in2$1$next , \core_core_cr_in2_ok$next , \core_core_cr_in2$next , \core_core_cr_in1_ok$next , \core_core_cr_in1$next , \core_fasto2_ok$next , \core_core_fasto2$next , \core_fasto1_ok$next , \core_core_fasto1$next , \core_core_fast2_ok$next , \core_core_fast2$next , \core_core_fast1_ok$next , \core_core_fast1$next , \core_xer_out$next , \core_core_xer_in$next , \core_core_spr1_ok$next , \core_core_spr1$next , \core_spro_ok$next , \core_core_spro$next , \core_core_reg3_ok$next , \core_core_reg3$next , \core_core_reg2_ok$next , \core_core_reg2$next , \core_core_reg1_ok$next , \core_core_reg1$next , \core_ea_ok$next , \core_core_ea$next , \core_rego_ok$next , \core_core_rego$next , \core_asmcode$next } = { dec2_is_32bit, dec2_cr_wr_ok, dec2_cr_wr, dec2_cr_rd_ok, dec2_cr_rd, dec2_trapaddr, \dec2_exc_$signal$22 , \dec2_exc_$signal$21 , \dec2_exc_$signal$20 , \dec2_exc_$signal$19 , \dec2_exc_$signal$18 , \dec2_exc_$signal$17 , \dec2_exc_$signal$16 , \dec2_exc_$signal , dec2_traptype, dec2_input_carry, dec2_oe_ok, dec2_oe, dec2_rc_ok, dec2_rc, dec2_lk, dec2_fn_unit, dec2_insn_type, dec2_insn, dec2_cia, dec2_msr, dec2_cr_out_ok, dec2_cr_out, \dec2_cr_in2_ok$15 , \dec2_cr_in2$14 , dec2_cr_in2_ok, dec2_cr_in2, dec2_cr_in1_ok, dec2_cr_in1, dec2_fasto2_ok, dec2_fasto2, dec2_fasto1_ok, dec2_fasto1, dec2_fast2_ok, dec2_fast2, dec2_fast1_ok, dec2_fast1, dec2_xer_out, dec2_xer_in, dec2_spr1_ok, dec2_spr1, dec2_spro_ok, dec2_spro, dec2_reg3_ok, dec2_reg3, dec2_reg2_ok, dec2_reg2, dec2_reg1_ok, dec2_reg1, dec2_ea_ok, dec2_ea, dec2_rego_ok, dec2_rego, dec2_asmcode }; + { \core_core_core_is_32bit$next , \core_core_cr_wr_ok$next , \core_core_core_cr_wr$next , \core_core_core_cr_rd_ok$next , \core_core_core_cr_rd$next , \core_core_core_trapaddr$next , \core_core_core_exc_$signal$9$next , \core_core_core_exc_$signal$8$next , \core_core_core_exc_$signal$7$next , \core_core_core_exc_$signal$6$next , \core_core_core_exc_$signal$5$next , \core_core_core_exc_$signal$4$next , \core_core_core_exc_$signal$3$next , \core_core_core_exc_$signal$next , \core_core_core_traptype$next , \core_core_core_input_carry$next , \core_core_core_oe_ok$next , \core_core_core_oe$next , \core_core_core_rc_ok$next , \core_core_core_rc$next , \core_core_lk$next , \core_core_core_fn_unit$next , \core_core_core_insn_type$next , \core_core_core_insn$next , \core_core_core_svstate$next , \core_core_core_cia$next , \core_core_core_msr$next , \core_core_core__SV_Ptype$next , \core_core_core__sv_saturate$next , \core_core_core__sv_pred_dz$next , \core_core_core__sv_pred_sz$next , \core_cr_out_ok$next , \core_core_cr_out$next , \core_core_cr_in2_ok$2$next , \core_core_cr_in2$1$next , \core_core_cr_in2_ok$next , \core_core_cr_in2$next , \core_core_cr_in1_ok$next , \core_core_cr_in1$next , \core_fasto3_ok$next , \core_core_fasto3$next , \core_fasto2_ok$next , \core_core_fasto2$next , \core_fasto1_ok$next , \core_core_fasto1$next , \core_core_fast3_ok$next , \core_core_fast3$next , \core_core_fast2_ok$next , \core_core_fast2$next , \core_core_fast1_ok$next , \core_core_fast1$next , \core_xer_out$next , \core_core_xer_in$next , \core_core_spr1_ok$next , \core_core_spr1$next , \core_spro_ok$next , \core_core_spro$next , \core_core_reg3_ok$next , \core_core_reg3$next , \core_core_reg2_ok$next , \core_core_reg2$next , \core_core_reg1_ok$next , \core_core_reg1$next , \core_ea_ok$next , \core_core_ea$next , \core_rego_ok$next , \core_core_rego$next , \core_asmcode$next } = { dec2_is_32bit, dec2_cr_wr_ok, dec2_cr_wr, dec2_cr_rd_ok, dec2_cr_rd, dec2_trapaddr, \dec2_exc_$signal$22 , \dec2_exc_$signal$21 , \dec2_exc_$signal$20 , \dec2_exc_$signal$19 , \dec2_exc_$signal$18 , \dec2_exc_$signal$17 , \dec2_exc_$signal$16 , \dec2_exc_$signal , dec2_traptype, dec2_input_carry, dec2_oe_ok, dec2_oe, dec2_rc_ok, dec2_rc, dec2_lk, dec2_fn_unit, dec2_insn_type, dec2_insn, dec2_svstate, dec2_cia, dec2_msr, dec2_SV_Ptype, dec2_sv_saturate, dec2_sv_pred_dz, dec2_sv_pred_sz, dec2_cr_out_ok, dec2_cr_out, \dec2_cr_in2_ok$15 , \dec2_cr_in2$14 , dec2_cr_in2_ok, dec2_cr_in2, dec2_cr_in1_ok, dec2_cr_in1, dec2_fasto3_ok, dec2_fasto3, dec2_fasto2_ok, dec2_fasto2, dec2_fasto1_ok, dec2_fasto1, dec2_fast3_ok, dec2_fast3, dec2_fast2_ok, dec2_fast2, dec2_fast1_ok, dec2_fast1, dec2_xer_out, dec2_xer_in, dec2_spr1_ok, dec2_spr1, dec2_spro_ok, dec2_spro, dec2_reg3_ok, dec2_reg3, dec2_reg2_ok, dec2_reg2, dec2_reg1_ok, dec2_reg1, dec2_ea_ok, dec2_ea, dec2_rego_ok, dec2_rego, dec2_asmcode }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: begin @@ -201418,12 +214406,18 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus \core_core_spr1_ok$next = 1'h0; \core_core_fast1_ok$next = 1'h0; \core_core_fast2_ok$next = 1'h0; + \core_core_fast3_ok$next = 1'h0; \core_fasto1_ok$next = 1'h0; \core_fasto2_ok$next = 1'h0; + \core_fasto3_ok$next = 1'h0; \core_core_cr_in1_ok$next = 1'h0; \core_core_cr_in2_ok$next = 1'h0; \core_core_cr_in2_ok$2$next = 1'h0; \core_cr_out_ok$next = 1'h0; + \core_core_core__sv_pred_sz$next = 1'h0; + \core_core_core__sv_pred_dz$next = 1'h0; + \core_core_core__sv_saturate$next = 2'h0; + \core_core_core__SV_Ptype$next = 2'h0; \core_core_core_rc_ok$next = 1'h0; \core_core_core_oe_ok$next = 1'h0; \core_core_core_exc_$signal$next = 1'h0; @@ -201439,19 +214433,29 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus end endcase end + always @* begin + if (\initial ) begin end + \delay$next = delay; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:936" *) + casez (\$25 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:936" */ + 1'h1: + \delay$next = \$27 [1:0]; + endcase + end assign \$27 = \$28 ; assign \$104 = \$105 ; assign \$112 = \$113 ; assign \$136 = \$137 ; assign \$139 = \$140 ; - assign \$266 = \$267 ; - assign \$269 = \$270 ; - assign dec2_sv_a_nz = 1'h0; + assign \$268 = \$269 ; + assign \$271 = \$272 ; assign svstate_i_ok = 1'h0; assign svstate_i = 32'd0; assign is_svp64_mode = 1'h0; assign pred_insn_ready_o = 1'h0; assign pred_mask_valid_o = 1'h0; + assign exc_happened = \$142 ; assign next_dststep = \$140 [6:0]; assign next_srcstep = \$137 [6:0]; assign dbg_core_dbg_msr = dec2_cur_msr; @@ -201469,138 +214473,148 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus assign ti_rst = \$34 ; assign por_clk = clk; assign { xics_icp_ics_i_pri, xics_icp_ics_i_src } = { xics_ics_icp_o_pri, xics_ics_icp_o_src }; - assign sram4k_3_enable = jtag_wb_sram_en; - assign sram4k_2_enable = jtag_wb_sram_en; - assign sram4k_1_enable = jtag_wb_sram_en; - assign sram4k_0_enable = jtag_wb_sram_en; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0" *) (* generator = "nMigen" *) -module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_unit, oper_i_alu_trap0__insn, oper_i_alu_trap0__msr, oper_i_alu_trap0__cia, oper_i_alu_trap0__is_32bit, oper_i_alu_trap0__traptype, oper_i_alu_trap0__trapaddr, oper_i_alu_trap0__ldst_exc, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, src4_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, fast1_ok, fast2_ok, dest2_o, dest3_o, nia_ok, dest4_o, msr_ok, dest5_o, coresync_clk); +module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_unit, oper_i_alu_trap0__insn, oper_i_alu_trap0__msr, oper_i_alu_trap0__cia, oper_i_alu_trap0__svstate, oper_i_alu_trap0__is_32bit, oper_i_alu_trap0__traptype, oper_i_alu_trap0__trapaddr, oper_i_alu_trap0__ldst_exc, oper_i_alu_trap0__sv_pred_sz, oper_i_alu_trap0__sv_pred_dz, oper_i_alu_trap0__sv_saturate, oper_i_alu_trap0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, src4_i, src5_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, fast1_ok, fast2_ok, fast3_ok, dest2_o, dest3_o, dest4_o, nia_ok, dest5_o, msr_ok, dest6_o, svstate_ok, dest7_o, coresync_clk); reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [4:0] \$100 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [4:0] \$102 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [4:0] \$104 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) + wire [4:0] \$106 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) - wire \$101 ; + wire \$108 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) - wire \$103 ; + wire \$110 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) - wire \$105 ; + wire \$112 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) - wire \$107 ; + wire \$114 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) - wire \$109 ; + wire \$116 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$118 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) - wire \$11 ; + wire \$12 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) + wire \$120 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) - wire [4:0] \$111 ; + wire [6:0] \$122 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) - wire [4:0] \$113 ; + wire [6:0] \$124 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) - wire \$115 ; + wire \$126 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) - wire \$117 ; + wire \$128 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) - wire \$119 ; + wire \$130 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) - wire \$121 ; + wire \$132 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) - wire \$123 ; + wire \$134 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$136 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + wire \$138 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$13 ; + wire \$14 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$15 ; + wire \$16 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$17 ; + wire \$18 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) - wire \$19 ; + wire \$20 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *) - wire [4:0] \$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) - wire \$23 ; + wire [6:0] \$22 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) wire \$24 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) - wire [4:0] \$25 ; + wire \$25 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) - wire [4:0] \$27 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *) - wire \$3 ; + wire [6:0] \$26 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) - wire \$31 ; + wire [6:0] \$28 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) + wire \$32 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) - wire \$33 ; + wire \$34 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) - wire \$35 ; + wire \$36 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) - wire \$37 ; + wire \$38 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *) + wire \$4 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) - wire \$39 ; + wire \$40 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) - wire \$41 ; + wire \$42 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) - wire [4:0] \$43 ; + wire [6:0] \$44 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) - wire \$45 ; + wire \$46 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) - wire \$47 ; + wire \$48 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) - wire \$49 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) - wire \$5 ; + wire \$50 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) - wire \$51 ; + wire \$52 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) - wire \$53 ; + wire \$54 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) - wire \$55 ; + wire \$56 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *) - wire \$57 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *) - wire \$59 ; + wire \$58 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) - wire [3:0] \$6 ; + wire \$6 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *) + wire \$60 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *) - wire [4:0] \$61 ; + wire [6:0] \$62 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *) - wire [3:0] \$63 ; + wire [4:0] \$64 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *) - wire \$65 ; + wire \$66 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *) - wire [4:0] \$67 ; + wire [6:0] \$68 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire [4:0] \$7 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *) - wire [4:0] \$69 ; + wire [6:0] \$70 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) - wire \$71 ; + wire \$72 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) - wire \$73 ; + wire \$74 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) - wire \$75 ; + wire \$76 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) - wire \$77 ; + wire \$78 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) - wire \$79 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) - wire [3:0] \$8 ; + wire \$80 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$82 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) + wire \$84 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) - wire [63:0] \$81 ; + wire [63:0] \$86 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) - wire [63:0] \$83 ; + wire [63:0] \$88 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) + wire [4:0] \$9 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) - wire [63:0] \$85 ; + wire [63:0] \$90 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) + wire [63:0] \$92 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) - wire [63:0] \$87 ; + wire [63:0] \$94 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *) - wire \$89 ; + wire \$96 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) - wire \$91 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) - wire [3:0] \$93 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) - wire [3:0] \$95 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) - wire [3:0] \$97 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) - wire [3:0] \$99 ; + wire \$98 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" *) wire all_rd; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) @@ -201630,59 +214644,74 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" *) wire alu_pulse; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" *) - wire [4:0] alu_pulsem; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + wire [6:0] alu_pulsem; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] alu_trap0_fast1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] \alu_trap0_fast1$1 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] alu_trap0_fast2; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] \alu_trap0_fast2$2 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [63:0] alu_trap0_fast3; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) + wire [63:0] \alu_trap0_fast3$3 ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] alu_trap0_msr; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *) wire alu_trap0_n_ready_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *) wire alu_trap0_n_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] alu_trap0_nia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) wire [63:0] alu_trap0_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *) wire alu_trap0_p_ready_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *) wire alu_trap0_p_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] alu_trap0_ra; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] alu_trap0_rb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + wire [31:0] alu_trap0_svstate; + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] alu_trap0_trap_op__SV_Ptype = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \alu_trap0_trap_op__SV_Ptype$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] alu_trap0_trap_op__cia = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] \alu_trap0_trap_op__cia$next ; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] alu_trap0_trap_op__fn_unit = 14'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - reg [13:0] \alu_trap0_trap_op__fn_unit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] alu_trap0_trap_op__fn_unit = 15'h0000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [14:0] \alu_trap0_trap_op__fn_unit$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] alu_trap0_trap_op__insn = 32'd0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [31:0] \alu_trap0_trap_op__insn$next ; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -201759,29 +214788,51 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] alu_trap0_trap_op__insn_type = 7'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [6:0] \alu_trap0_trap_op__insn_type$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg alu_trap0_trap_op__is_32bit = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_trap0_trap_op__is_32bit$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [7:0] alu_trap0_trap_op__ldst_exc = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [7:0] \alu_trap0_trap_op__ldst_exc$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] alu_trap0_trap_op__msr = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [63:0] \alu_trap0_trap_op__msr$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg alu_trap0_trap_op__sv_pred_dz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \alu_trap0_trap_op__sv_pred_dz$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg alu_trap0_trap_op__sv_pred_sz = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg \alu_trap0_trap_op__sv_pred_sz$next ; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] alu_trap0_trap_op__sv_saturate = 2'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [1:0] \alu_trap0_trap_op__sv_saturate$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [31:0] alu_trap0_trap_op__svstate = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + reg [31:0] \alu_trap0_trap_op__svstate$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [12:0] alu_trap0_trap_op__trapaddr = 13'h0000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [12:0] \alu_trap0_trap_op__trapaddr$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [7:0] alu_trap0_trap_op__traptype = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg [7:0] \alu_trap0_trap_op__traptype$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire alui_l_q_alui; @@ -201791,9 +214842,9 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) output cu_busy_o; @@ -201804,19 +214855,19 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *) input cu_issue_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - input [3:0] cu_rd__go_i; + input [4:0] cu_rd__go_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - output [3:0] cu_rd__rel_o; + output [4:0] cu_rd__rel_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *) - input [3:0] cu_rdmaskn_i; + input [4:0] cu_rdmaskn_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" *) wire cu_shadown_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - input [4:0] cu_wr__go_i; + input [6:0] cu_wr__go_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) - output [4:0] cu_wr__rel_o; + output [6:0] cu_wr__rel_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" *) - wire [4:0] cu_wrmask_o; + wire [6:0] cu_wrmask_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) reg [63:0] data_r0__o = 64'h0000000000000000; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) @@ -201842,21 +214893,37 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) reg \data_r2__fast2_ok$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) - reg [63:0] data_r3__nia = 64'h0000000000000000; + reg [63:0] data_r3__fast3 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] \data_r3__fast3$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r3__fast3_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r3__fast3_ok$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] data_r4__nia = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg [63:0] \data_r4__nia$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r4__nia_ok = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) - reg [63:0] \data_r3__nia$next ; + reg \data_r4__nia_ok$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) - reg data_r3__nia_ok = 1'h0; + reg [63:0] data_r5__msr = 64'h0000000000000000; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) - reg \data_r3__nia_ok$next ; + reg [63:0] \data_r5__msr$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) - reg [63:0] data_r4__msr = 64'h0000000000000000; + reg data_r5__msr_ok = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) - reg [63:0] \data_r4__msr$next ; + reg \data_r5__msr_ok$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) - reg data_r4__msr_ok = 1'h0; + reg [31:0] data_r6__svstate = 32'd0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) - reg \data_r4__msr_ok$next ; + reg [31:0] \data_r6__svstate$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg data_r6__svstate_ok = 1'h0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *) + reg \data_r6__svstate_ok$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) output [63:0] dest1_o; reg [63:0] dest1_o; @@ -201872,15 +214939,23 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) output [63:0] dest5_o; reg [63:0] dest5_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [63:0] dest6_o; + reg [63:0] dest6_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *) + output [31:0] dest7_o; + reg [31:0] dest7_o; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output fast1_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output fast2_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output fast3_ok; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output msr_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output nia_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output o_ok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire opc_l_q_opc; @@ -201892,26 +214967,33 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni reg opc_l_s_opc = 1'h0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) reg \opc_l_s_opc$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_base_type = "SVPtype" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "P1" *) + (* enum_value_10 = "P2" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_trap0__SV_Ptype; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] oper_i_alu_trap0__cia; (* enum_base_type = "Function" *) - (* enum_value_00000000000000 = "NONE" *) - (* enum_value_00000000000010 = "ALU" *) - (* enum_value_00000000000100 = "LDST" *) - (* enum_value_00000000001000 = "SHIFT_ROT" *) - (* enum_value_00000000010000 = "LOGICAL" *) - (* enum_value_00000000100000 = "BRANCH" *) - (* enum_value_00000001000000 = "CR" *) - (* enum_value_00000010000000 = "TRAP" *) - (* enum_value_00000100000000 = "MUL" *) - (* enum_value_00001000000000 = "DIV" *) - (* enum_value_00010000000000 = "SPR" *) - (* enum_value_00100000000000 = "MMU" *) - (* enum_value_01000000000000 = "SV" *) - (* enum_value_10000000000000 = "VL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) - input [13:0] oper_i_alu_trap0__fn_unit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_000000000000000 = "NONE" *) + (* enum_value_000000000000010 = "ALU" *) + (* enum_value_000000000000100 = "LDST" *) + (* enum_value_000000000001000 = "SHIFT_ROT" *) + (* enum_value_000000000010000 = "LOGICAL" *) + (* enum_value_000000000100000 = "BRANCH" *) + (* enum_value_000000001000000 = "CR" *) + (* enum_value_000000010000000 = "TRAP" *) + (* enum_value_000000100000000 = "MUL" *) + (* enum_value_000001000000000 = "DIV" *) + (* enum_value_000010000000000 = "SPR" *) + (* enum_value_000100000000000 = "MMU" *) + (* enum_value_001000000000000 = "SV" *) + (* enum_value_010000000000000 = "VL" *) + (* enum_value_100000000000000 = "FPU" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [14:0] oper_i_alu_trap0__fn_unit; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [31:0] oper_i_alu_trap0__insn; (* enum_base_type = "MicrOp" *) (* enum_value_0000000 = "OP_ILLEGAL" *) @@ -201988,40 +215070,54 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni (* enum_value_1001010 = "OP_MTMSR" *) (* enum_value_1001011 = "OP_TLBIE" *) (* enum_value_1001100 = "OP_SETVL" *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* enum_value_1001101 = "OP_FPOP" *) + (* enum_value_1001110 = "OP_FPOP_I" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [6:0] oper_i_alu_trap0__insn_type; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input oper_i_alu_trap0__is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [7:0] oper_i_alu_trap0__ldst_exc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [63:0] oper_i_alu_trap0__msr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_trap0__sv_pred_dz; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input oper_i_alu_trap0__sv_pred_sz; + (* enum_base_type = "SVP64sat" *) + (* enum_value_00 = "NONE" *) + (* enum_value_01 = "SIGNED" *) + (* enum_value_10 = "UNSIGNED" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [1:0] oper_i_alu_trap0__sv_saturate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) + input [31:0] oper_i_alu_trap0__svstate; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [12:0] oper_i_alu_trap0__trapaddr; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) input [7:0] oper_i_alu_trap0__traptype; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *) - reg [4:0] prev_wr_go = 5'h00; + reg [6:0] prev_wr_go = 7'h00; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *) - reg [4:0] \prev_wr_go$next ; + reg [6:0] \prev_wr_go$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" *) reg req_done; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) - wire [4:0] req_l_q_req; + wire [6:0] req_l_q_req; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) - reg [4:0] req_l_r_req = 5'h1f; + reg [6:0] req_l_r_req = 7'h7f; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) - reg [4:0] \req_l_r_req$next ; + reg [6:0] \req_l_r_req$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) - reg [4:0] req_l_s_req = 5'h00; + reg [6:0] req_l_s_req = 7'h00; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) - reg [4:0] \req_l_s_req$next ; + reg [6:0] \req_l_s_req$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" *) wire reset; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" *) - wire [3:0] reset_r; + wire [4:0] reset_r; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" *) - wire [4:0] reset_w; + wire [6:0] reset_w; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire rok_l_q_rdok; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) @@ -202050,16 +215146,18 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni input [63:0] src3_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) input [63:0] src4_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *) + input [63:0] src5_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) - wire [3:0] src_l_q_src; + wire [4:0] src_l_q_src; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) - reg [3:0] src_l_r_src = 4'hf; + reg [4:0] src_l_r_src = 5'h1f; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *) - reg [3:0] \src_l_r_src$next ; + reg [4:0] \src_l_r_src$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) - reg [3:0] src_l_s_src = 4'h0; + reg [4:0] src_l_s_src = 5'h00; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) - reg [3:0] \src_l_s_src$next ; + reg [4:0] \src_l_s_src$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) reg [63:0] src_r0 = 64'h0000000000000000; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) @@ -202076,73 +215174,88 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni reg [63:0] src_r3 = 64'h0000000000000000; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) reg [63:0] \src_r3$next ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] src_r4 = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) + reg [63:0] \src_r4$next ; + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) + output svstate_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" *) wire wr_any; - assign \$5 = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$8 ; - assign \$99 = \$95 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) \$97 ; - assign \$101 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; - assign \$103 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; - assign \$105 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; - assign \$107 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; - assign \$109 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; - assign \$111 = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) { \$101 , \$103 , \$105 , \$107 , \$109 }; - assign \$113 = \$111 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) cu_wrmask_o; - assign \$115 = cu_wr__go_i[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; - assign \$117 = cu_wr__go_i[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; - assign \$11 = \$3 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$5 ; - assign \$119 = cu_wr__go_i[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; - assign \$121 = cu_wr__go_i[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; - assign \$123 = cu_wr__go_i[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; - assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) all_rd_dly; - assign \$15 = all_rd & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$13 ; - assign \$17 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) alu_done_dly; - assign \$19 = alu_done & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$17 ; - assign \$21 = cu_wr__go_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *) { cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o }; - assign \$25 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) cu_wrmask_o; - assign \$27 = cu_wr__rel_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$25 ; - assign \$24 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$27 ; - assign \$23 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$24 ; - assign \$31 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$23 ; - assign \$33 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) cu_wr__go_i; - assign \$35 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) prev_wr_go; - assign \$37 = \$33 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) \$35 ; - assign \$3 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *) rok_l_q_rdok; - assign \$39 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) alu_trap0_n_ready_i; - assign \$41 = wr_any & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) \$39 ; - assign \$43 = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) cu_wrmask_o; - assign \$45 = \$43 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) 1'h0; - assign \$47 = \$41 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) \$45 ; - assign \$49 = cu_wrmask_o == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) 1'h0; - assign \$51 = \$49 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_trap0_n_ready_i; - assign \$53 = \$51 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_trap0_n_valid_o; - assign \$55 = \$53 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) cu_busy_o; - assign \$57 = req_done | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *) cu_go_die_i; - assign \$59 = cu_issue_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *) cu_go_die_i; - assign \$61 = cu_wr__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i }; - assign \$63 = cu_rd__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i }; - assign \$65 = alu_trap0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *) cu_busy_o; - assign \$67 = alu_pulsem & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *) cu_wrmask_o; - assign \$6 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__rel_o; - assign \$69 = reset_w | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *) prev_wr_go; - assign \$71 = o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; - assign \$73 = fast1_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; - assign \$75 = fast2_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; - assign \$77 = nia_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; - assign \$79 = msr_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; - assign \$81 = src_l_q_src[0] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src1_i : src_r0; - assign \$83 = src_l_q_src[1] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src2_i : src_r1; - assign \$85 = src_l_q_src[2] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src3_i : src_r2; - assign \$87 = src_l_q_src[3] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src4_i : src_r3; - assign \$8 = \$6 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__go_i; - assign \$89 = alu_trap0_p_ready_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *) alui_l_q_alui; - assign \$91 = alu_trap0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) alu_l_q_alu; - assign \$93 = src_l_q_src & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) { cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o }; - assign \$95 = \$93 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) 4'hf; - assign \$97 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) cu_rdmaskn_i; + assign \$9 = \$7 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__go_i; + assign \$100 = src_l_q_src & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) { cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o }; + assign \$102 = \$100 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) 5'h1f; + assign \$104 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) cu_rdmaskn_i; + assign \$106 = \$102 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) \$104 ; + assign \$108 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$6 = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$9 ; + assign \$110 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$112 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$114 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$116 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$118 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$120 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i; + assign \$122 = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) { \$108 , \$110 , \$112 , \$114 , \$116 , \$118 , \$120 }; + assign \$124 = \$122 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) cu_wrmask_o; + assign \$126 = cu_wr__go_i[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$128 = cu_wr__go_i[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$12 = \$4 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$6 ; + assign \$130 = cu_wr__go_i[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$132 = cu_wr__go_i[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$134 = cu_wr__go_i[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$136 = cu_wr__go_i[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$138 = cu_wr__go_i[6] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o; + assign \$14 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) all_rd_dly; + assign \$16 = all_rd & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$14 ; + assign \$18 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) alu_done_dly; + assign \$20 = alu_done & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$18 ; + assign \$22 = cu_wr__go_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *) { cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o }; + assign \$26 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) cu_wrmask_o; + assign \$28 = cu_wr__rel_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$26 ; + assign \$25 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$28 ; + assign \$24 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$25 ; + assign \$32 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$24 ; + assign \$34 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) cu_wr__go_i; + assign \$36 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) prev_wr_go; + assign \$38 = \$34 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) \$36 ; + assign \$40 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) alu_trap0_n_ready_i; + assign \$42 = wr_any & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) \$40 ; + assign \$44 = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) cu_wrmask_o; + assign \$46 = \$44 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) 1'h0; + assign \$48 = \$42 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) \$46 ; + assign \$4 = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *) rok_l_q_rdok; + assign \$50 = cu_wrmask_o == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) 1'h0; + assign \$52 = \$50 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_trap0_n_ready_i; + assign \$54 = \$52 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_trap0_n_valid_o; + assign \$56 = \$54 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) cu_busy_o; + assign \$58 = req_done | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *) cu_go_die_i; + assign \$60 = cu_issue_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *) cu_go_die_i; + assign \$62 = cu_wr__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i }; + assign \$64 = cu_rd__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i }; + assign \$66 = alu_trap0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *) cu_busy_o; + assign \$68 = alu_pulsem & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *) cu_wrmask_o; + assign \$70 = reset_w | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *) prev_wr_go; + assign \$72 = o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$74 = fast1_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$76 = fast2_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$78 = fast3_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__rel_o; + assign \$80 = nia_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$82 = msr_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$84 = svstate_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o; + assign \$86 = src_l_q_src[0] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src1_i : src_r0; + assign \$88 = src_l_q_src[1] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src2_i : src_r1; + assign \$90 = src_l_q_src[2] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src3_i : src_r2; + assign \$92 = src_l_q_src[3] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src4_i : src_r3; + assign \$94 = src_l_q_src[4] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src5_i : src_r4; + assign \$96 = alu_trap0_p_ready_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *) alui_l_q_alui; + assign \$98 = alu_trap0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) alu_l_q_alu; always @(posedge coresync_clk) alu_l_r_alu <= \alu_l_r_alu$next ; always @(posedge coresync_clk) alui_l_r_alui <= \alui_l_r_alui$next ; + always @(posedge coresync_clk) + src_r4 <= \src_r4$next ; always @(posedge coresync_clk) src_r3 <= \src_r3$next ; always @(posedge coresync_clk) @@ -202152,13 +215265,21 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni always @(posedge coresync_clk) src_r0 <= \src_r0$next ; always @(posedge coresync_clk) - data_r4__msr <= \data_r4__msr$next ; + data_r6__svstate <= \data_r6__svstate$next ; + always @(posedge coresync_clk) + data_r6__svstate_ok <= \data_r6__svstate_ok$next ; + always @(posedge coresync_clk) + data_r5__msr <= \data_r5__msr$next ; always @(posedge coresync_clk) - data_r4__msr_ok <= \data_r4__msr_ok$next ; + data_r5__msr_ok <= \data_r5__msr_ok$next ; always @(posedge coresync_clk) - data_r3__nia <= \data_r3__nia$next ; + data_r4__nia <= \data_r4__nia$next ; always @(posedge coresync_clk) - data_r3__nia_ok <= \data_r3__nia_ok$next ; + data_r4__nia_ok <= \data_r4__nia_ok$next ; + always @(posedge coresync_clk) + data_r3__fast3 <= \data_r3__fast3$next ; + always @(posedge coresync_clk) + data_r3__fast3_ok <= \data_r3__fast3_ok$next ; always @(posedge coresync_clk) data_r2__fast2 <= \data_r2__fast2$next ; always @(posedge coresync_clk) @@ -202181,6 +215302,8 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni alu_trap0_trap_op__msr <= \alu_trap0_trap_op__msr$next ; always @(posedge coresync_clk) alu_trap0_trap_op__cia <= \alu_trap0_trap_op__cia$next ; + always @(posedge coresync_clk) + alu_trap0_trap_op__svstate <= \alu_trap0_trap_op__svstate$next ; always @(posedge coresync_clk) alu_trap0_trap_op__is_32bit <= \alu_trap0_trap_op__is_32bit$next ; always @(posedge coresync_clk) @@ -202189,6 +215312,14 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni alu_trap0_trap_op__trapaddr <= \alu_trap0_trap_op__trapaddr$next ; always @(posedge coresync_clk) alu_trap0_trap_op__ldst_exc <= \alu_trap0_trap_op__ldst_exc$next ; + always @(posedge coresync_clk) + alu_trap0_trap_op__sv_pred_sz <= \alu_trap0_trap_op__sv_pred_sz$next ; + always @(posedge coresync_clk) + alu_trap0_trap_op__sv_pred_dz <= \alu_trap0_trap_op__sv_pred_dz$next ; + always @(posedge coresync_clk) + alu_trap0_trap_op__sv_saturate <= \alu_trap0_trap_op__sv_saturate$next ; + always @(posedge coresync_clk) + alu_trap0_trap_op__SV_Ptype <= \alu_trap0_trap_op__SV_Ptype$next ; always @(posedge coresync_clk) req_l_r_req <= \req_l_r_req$next ; always @(posedge coresync_clk) @@ -202214,7 +215345,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni always @(posedge coresync_clk) alu_done_dly <= alu_trap0_n_valid_o; always @(posedge coresync_clk) - all_rd_dly <= \$11 ; + all_rd_dly <= \$12 ; \alu_l$45 alu_l ( .coresync_clk(coresync_clk), .coresync_rst(coresync_rst), @@ -202231,6 +215362,9 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni .fast2(alu_trap0_fast2), .\fast2$2 (\alu_trap0_fast2$2 ), .fast2_ok(fast2_ok), + .fast3(alu_trap0_fast3), + .\fast3$3 (\alu_trap0_fast3$3 ), + .fast3_ok(fast3_ok), .msr(alu_trap0_msr), .msr_ok(msr_ok), .n_ready_i(alu_trap0_n_ready_i), @@ -202243,6 +215377,9 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni .p_valid_i(alu_trap0_p_valid_i), .ra(alu_trap0_ra), .rb(alu_trap0_rb), + .svstate(alu_trap0_svstate), + .svstate_ok(svstate_ok), + .trap_op__SV_Ptype(alu_trap0_trap_op__SV_Ptype), .trap_op__cia(alu_trap0_trap_op__cia), .trap_op__fn_unit(alu_trap0_trap_op__fn_unit), .trap_op__insn(alu_trap0_trap_op__insn), @@ -202250,6 +215387,10 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni .trap_op__is_32bit(alu_trap0_trap_op__is_32bit), .trap_op__ldst_exc(alu_trap0_trap_op__ldst_exc), .trap_op__msr(alu_trap0_trap_op__msr), + .trap_op__sv_pred_dz(alu_trap0_trap_op__sv_pred_dz), + .trap_op__sv_pred_sz(alu_trap0_trap_op__sv_pred_sz), + .trap_op__sv_saturate(alu_trap0_trap_op__sv_saturate), + .trap_op__svstate(alu_trap0_trap_op__svstate), .trap_op__trapaddr(alu_trap0_trap_op__trapaddr), .trap_op__traptype(alu_trap0_trap_op__traptype) ); @@ -202296,9 +215437,9 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni ); always @* begin if (\initial ) begin end - req_done = \$47 ; + req_done = \$48 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) - casez (\$55 ) + casez (\$56 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" */ 1'h1: req_done = 1'h1; @@ -202307,7 +215448,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni always @* begin if (\initial ) begin end \rok_l_s_rdok$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_s_rdok$next = 1'h0; @@ -202315,8 +215456,8 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni end always @* begin if (\initial ) begin end - \rok_l_r_rdok$next = \$65 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \rok_l_r_rdok$next = \$66 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rok_l_r_rdok$next = 1'h1; @@ -202325,7 +215466,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni always @* begin if (\initial ) begin end \rst_l_s_rst$next = all_rd; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_s_rst$next = 1'h0; @@ -202334,7 +215475,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni always @* begin if (\initial ) begin end \rst_l_r_rst$next = rst_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \rst_l_r_rst$next = 1'h1; @@ -202343,7 +215484,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni always @* begin if (\initial ) begin end \opc_l_s_opc$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_s_opc$next = 1'h0; @@ -202352,7 +215493,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni always @* begin if (\initial ) begin end \opc_l_r_opc$next = req_done; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \opc_l_r_opc$next = 1'h1; @@ -202360,38 +215501,38 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni end always @* begin if (\initial ) begin end - \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i }; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \src_l_s_src$next = 4'h0; + \src_l_s_src$next = 5'h00; endcase end always @* begin if (\initial ) begin end \src_l_r_src$next = reset_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \src_l_r_src$next = 4'hf; + \src_l_r_src$next = 5'h1f; endcase end always @* begin if (\initial ) begin end - \req_l_s_req$next = \$67 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \req_l_s_req$next = \$68 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \req_l_s_req$next = 5'h00; + \req_l_s_req$next = 7'h00; endcase end always @* begin if (\initial ) begin end - \req_l_r_req$next = \$69 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \req_l_r_req$next = \$70 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \req_l_r_req$next = 5'h1f; + \req_l_r_req$next = 7'h7f; endcase end always @* begin @@ -202401,15 +215542,20 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni \alu_trap0_trap_op__insn$next = alu_trap0_trap_op__insn; \alu_trap0_trap_op__msr$next = alu_trap0_trap_op__msr; \alu_trap0_trap_op__cia$next = alu_trap0_trap_op__cia; + \alu_trap0_trap_op__svstate$next = alu_trap0_trap_op__svstate; \alu_trap0_trap_op__is_32bit$next = alu_trap0_trap_op__is_32bit; \alu_trap0_trap_op__traptype$next = alu_trap0_trap_op__traptype; \alu_trap0_trap_op__trapaddr$next = alu_trap0_trap_op__trapaddr; \alu_trap0_trap_op__ldst_exc$next = alu_trap0_trap_op__ldst_exc; + \alu_trap0_trap_op__sv_pred_sz$next = alu_trap0_trap_op__sv_pred_sz; + \alu_trap0_trap_op__sv_pred_dz$next = alu_trap0_trap_op__sv_pred_dz; + \alu_trap0_trap_op__sv_saturate$next = alu_trap0_trap_op__sv_saturate; + \alu_trap0_trap_op__SV_Ptype$next = alu_trap0_trap_op__SV_Ptype; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *) casez (cu_issue_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" */ 1'h1: - { \alu_trap0_trap_op__ldst_exc$next , \alu_trap0_trap_op__trapaddr$next , \alu_trap0_trap_op__traptype$next , \alu_trap0_trap_op__is_32bit$next , \alu_trap0_trap_op__cia$next , \alu_trap0_trap_op__msr$next , \alu_trap0_trap_op__insn$next , \alu_trap0_trap_op__fn_unit$next , \alu_trap0_trap_op__insn_type$next } = { oper_i_alu_trap0__ldst_exc, oper_i_alu_trap0__trapaddr, oper_i_alu_trap0__traptype, oper_i_alu_trap0__is_32bit, oper_i_alu_trap0__cia, oper_i_alu_trap0__msr, oper_i_alu_trap0__insn, oper_i_alu_trap0__fn_unit, oper_i_alu_trap0__insn_type }; + { \alu_trap0_trap_op__SV_Ptype$next , \alu_trap0_trap_op__sv_saturate$next , \alu_trap0_trap_op__sv_pred_dz$next , \alu_trap0_trap_op__sv_pred_sz$next , \alu_trap0_trap_op__ldst_exc$next , \alu_trap0_trap_op__trapaddr$next , \alu_trap0_trap_op__traptype$next , \alu_trap0_trap_op__is_32bit$next , \alu_trap0_trap_op__svstate$next , \alu_trap0_trap_op__cia$next , \alu_trap0_trap_op__msr$next , \alu_trap0_trap_op__insn$next , \alu_trap0_trap_op__fn_unit$next , \alu_trap0_trap_op__insn_type$next } = { oper_i_alu_trap0__SV_Ptype, oper_i_alu_trap0__sv_saturate, oper_i_alu_trap0__sv_pred_dz, oper_i_alu_trap0__sv_pred_sz, oper_i_alu_trap0__ldst_exc, oper_i_alu_trap0__trapaddr, oper_i_alu_trap0__traptype, oper_i_alu_trap0__is_32bit, oper_i_alu_trap0__svstate, oper_i_alu_trap0__cia, oper_i_alu_trap0__msr, oper_i_alu_trap0__insn, oper_i_alu_trap0__fn_unit, oper_i_alu_trap0__insn_type }; endcase end always @* begin @@ -202428,7 +215574,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni 1'h1: { \data_r0__o_ok$next , \data_r0__o$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r0__o_ok$next = 1'h0; @@ -202450,7 +215596,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni 1'h1: { \data_r1__fast1_ok$next , \data_r1__fast1$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r1__fast1_ok$next = 1'h0; @@ -202472,7 +215618,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni 1'h1: { \data_r2__fast2_ok$next , \data_r2__fast2$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \data_r2__fast2_ok$next = 1'h0; @@ -202480,46 +215626,90 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni end always @* begin if (\initial ) begin end - \data_r3__nia$next = data_r3__nia; - \data_r3__nia_ok$next = data_r3__nia_ok; + \data_r3__fast3$next = data_r3__fast3; + \data_r3__fast3_ok$next = data_r3__fast3_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r3__fast3_ok$next , \data_r3__fast3$next } = { fast3_ok, alu_trap0_fast3 }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r3__fast3_ok$next , \data_r3__fast3$next } = 65'h00000000000000000; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + casez (coresync_rst) + 1'h1: + \data_r3__fast3_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \data_r4__nia$next = data_r4__nia; + \data_r4__nia_ok$next = data_r4__nia_ok; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) + casez (alu_pulse) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ + 1'h1: + { \data_r4__nia_ok$next , \data_r4__nia$next } = { nia_ok, alu_trap0_nia }; + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) + casez (cu_issue_i) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ + 1'h1: + { \data_r4__nia_ok$next , \data_r4__nia$next } = 65'h00000000000000000; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + casez (coresync_rst) + 1'h1: + \data_r4__nia_ok$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \data_r5__msr$next = data_r5__msr; + \data_r5__msr_ok$next = data_r5__msr_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) casez (alu_pulse) /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ 1'h1: - { \data_r3__nia_ok$next , \data_r3__nia$next } = { nia_ok, alu_trap0_nia }; + { \data_r5__msr_ok$next , \data_r5__msr$next } = { msr_ok, alu_trap0_msr }; endcase (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) casez (cu_issue_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ 1'h1: - { \data_r3__nia_ok$next , \data_r3__nia$next } = 65'h00000000000000000; + { \data_r5__msr_ok$next , \data_r5__msr$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \data_r3__nia_ok$next = 1'h0; + \data_r5__msr_ok$next = 1'h0; endcase end always @* begin if (\initial ) begin end - \data_r4__msr$next = data_r4__msr; - \data_r4__msr_ok$next = data_r4__msr_ok; + \data_r6__svstate$next = data_r6__svstate; + \data_r6__svstate_ok$next = data_r6__svstate_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *) casez (alu_pulse) /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" */ 1'h1: - { \data_r4__msr_ok$next , \data_r4__msr$next } = { msr_ok, alu_trap0_msr }; + { \data_r6__svstate_ok$next , \data_r6__svstate$next } = { svstate_ok, alu_trap0_svstate }; endcase (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *) casez (cu_issue_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" */ 1'h1: - { \data_r4__msr_ok$next , \data_r4__msr$next } = 65'h00000000000000000; + { \data_r6__svstate_ok$next , \data_r6__svstate$next } = 33'h000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \data_r4__msr_ok$next = 1'h0; + \data_r6__svstate_ok$next = 1'h0; endcase end always @* begin @@ -202564,8 +215754,18 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni end always @* begin if (\initial ) begin end - \alui_l_r_alui$next = \$89 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \src_r4$next = src_r4; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *) + casez (src_l_q_src[4]) + /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" */ + 1'h1: + \src_r4$next = src5_i; + endcase + end + always @* begin + if (\initial ) begin end + \alui_l_r_alui$next = \$96 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alui_l_r_alui$next = 1'h1; @@ -202573,8 +215773,8 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni end always @* begin if (\initial ) begin end - \alu_l_r_alu$next = \$91 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + \alu_l_r_alu$next = \$98 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \alu_l_r_alu$next = 1'h1; @@ -202584,7 +215784,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni if (\initial ) begin end dest1_o = 64'h0000000000000000; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) - casez (\$115 ) + casez (\$126 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ 1'h1: dest1_o = data_r0__o; @@ -202594,7 +215794,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni if (\initial ) begin end dest2_o = 64'h0000000000000000; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) - casez (\$117 ) + casez (\$128 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ 1'h1: dest2_o = data_r1__fast1; @@ -202604,7 +215804,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni if (\initial ) begin end dest3_o = 64'h0000000000000000; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) - casez (\$119 ) + casez (\$130 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ 1'h1: dest3_o = data_r2__fast2; @@ -202614,60 +215814,81 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni if (\initial ) begin end dest4_o = 64'h0000000000000000; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) - casez (\$121 ) + casez (\$132 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ 1'h1: - dest4_o = data_r3__nia; + dest4_o = data_r3__fast3; endcase end always @* begin if (\initial ) begin end dest5_o = 64'h0000000000000000; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) - casez (\$123 ) + casez (\$134 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ 1'h1: - dest5_o = data_r4__msr; + dest5_o = data_r4__nia; endcase end always @* begin if (\initial ) begin end - \prev_wr_go$next = \$21 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + dest6_o = 64'h0000000000000000; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$136 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest6_o = data_r5__msr; + endcase + end + always @* begin + if (\initial ) begin end + dest7_o = 32'd0; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) + casez (\$138 ) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" */ + 1'h1: + dest7_o = data_r6__svstate; + endcase + end + always @* begin + if (\initial ) begin end + \prev_wr_go$next = \$22 ; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: - \prev_wr_go$next = 5'h00; + \prev_wr_go$next = 7'h00; endcase end assign cu_go_die_i = 1'h0; assign cu_shadown_i = 1'h1; - assign cu_wr__rel_o = \$113 ; - assign cu_rd__rel_o = \$99 ; + assign cu_wr__rel_o = \$124 ; + assign cu_rd__rel_o = \$106 ; assign cu_busy_o = opc_l_q_opc; assign alu_l_s_alu = all_rd_pulse; assign alu_trap0_n_ready_i = alu_l_q_alu; assign alui_l_s_alui = all_rd_pulse; assign alu_trap0_p_valid_i = alui_l_q_alui; - assign \alu_trap0_fast2$2 = \$87 ; - assign \alu_trap0_fast1$1 = \$85 ; - assign alu_trap0_rb = \$83 ; - assign alu_trap0_ra = \$81 ; - assign cu_wrmask_o = { \$79 , \$77 , \$75 , \$73 , \$71 }; - assign reset_r = \$63 ; - assign reset_w = \$61 ; - assign rst_r = \$59 ; - assign reset = \$57 ; - assign wr_any = \$37 ; - assign cu_done_o = \$31 ; - assign alu_pulsem = { alu_pulse, alu_pulse, alu_pulse, alu_pulse, alu_pulse }; + assign \alu_trap0_fast3$3 = \$94 ; + assign \alu_trap0_fast2$2 = \$92 ; + assign \alu_trap0_fast1$1 = \$90 ; + assign alu_trap0_rb = \$88 ; + assign alu_trap0_ra = \$86 ; + assign cu_wrmask_o = { \$84 , \$82 , \$80 , \$78 , \$76 , \$74 , \$72 }; + assign reset_r = \$64 ; + assign reset_w = \$62 ; + assign rst_r = \$60 ; + assign reset = \$58 ; + assign wr_any = \$38 ; + assign cu_done_o = \$32 ; + assign alu_pulsem = { alu_pulse, alu_pulse, alu_pulse, alu_pulse, alu_pulse, alu_pulse, alu_pulse }; assign alu_pulse = alu_done_rise; - assign alu_done_rise = \$19 ; + assign alu_done_rise = \$20 ; assign \alu_done_dly$next = alu_done; assign alu_done = alu_trap0_n_valid_o; assign all_rd_pulse = all_rd_rise; - assign all_rd_rise = \$15 ; + assign all_rd_rise = \$16 ; assign \all_rd_dly$next = all_rd; - assign all_rd = \$11 ; + assign all_rd = \$12 ; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.ldst0.upd_l" *) @@ -202690,9 +215911,9 @@ module upd_l(coresync_rst, s_upd, r_upd, q_upd, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -202721,7 +215942,7 @@ module upd_l(coresync_rst, s_upd, r_upd, q_upd, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -202752,9 +215973,9 @@ module valid_l(coresync_rst, s_valid, q_valid, r_valid, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -202783,7 +216004,7 @@ module valid_l(coresync_rst, s_valid, q_valid, r_valid, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -202794,6 +216015,29 @@ module valid_l(coresync_rst, s_valid, q_valid, r_valid, coresync_clk); assign q_valid = \$11 ; endmodule +(* \nmigen.hierarchy = "test_issuer.wrappll" *) +(* generator = "nMigen" *) +module wrappll(clk_24_i, pll_18_o, clk_sel_i, pll_ana_o, clk_pll_o); + (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" *) + input clk_24_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" *) + output clk_pll_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" *) + input [1:0] clk_sel_i; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:14" *) + output pll_18_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:15" *) + output pll_ana_o; + pll pll ( + .a0(clk_sel_i[0]), + .a1(clk_sel_i[1]), + .div_out_test(pll_18_o), + .out(clk_pll_o), + .\ref (clk_24_i), + .vco_test_ana(pll_ana_o) + ); +endmodule + (* \nmigen.hierarchy = "test_issuer.ti.core.fus.ldst0.wri_l" *) (* generator = "nMigen" *) module wri_l(coresync_rst, s_wri, r_wri, q_wri, coresync_clk); @@ -202814,9 +216058,9 @@ module wri_l(coresync_rst, s_wri, r_wri, q_wri, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -202845,7 +216089,7 @@ module wri_l(coresync_rst, s_wri, r_wri, q_wri, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -202955,7 +216199,7 @@ endmodule (* generator = "nMigen" *) module wrpick_FAST_fast1(o, en_o, i); (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) - wire [4:0] \$1 ; + wire [5:0] \$1 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) wire \$11 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) @@ -202964,9 +216208,13 @@ module wrpick_FAST_fast1(o, en_o, i); wire \$15 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) wire \$16 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) wire \$19 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) + wire \$20 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) + wire \$23 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) wire \$3 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) wire \$4 ; @@ -202977,11 +216225,11 @@ module wrpick_FAST_fast1(o, en_o, i); (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) output en_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) - input [4:0] i; + input [5:0] i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *) - wire [4:0] ni; + wire [5:0] ni; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) - output [4:0] o; + output [5:0] o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) wire t0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) @@ -202992,18 +216240,23 @@ module wrpick_FAST_fast1(o, en_o, i); wire t3; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) wire t4; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t5; assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$8 ; assign \$12 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[2:0], ni[3] }; assign \$11 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$12 ; assign \$16 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[3:0], ni[4] }; assign \$15 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$16 ; assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i; - assign \$19 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o; + assign \$20 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[4:0], ni[5] }; + assign \$19 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$20 ; + assign \$23 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o; assign \$4 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[0], ni[1] }; assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$4 ; assign \$8 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[1:0], ni[2] }; - assign en_o = \$19 ; - assign o = { t4, t3, t2, t1, t0 }; + assign en_o = \$23 ; + assign o = { t5, t4, t3, t2, t1, t0 }; + assign t5 = \$19 ; assign t4 = \$15 ; assign t3 = \$11 ; assign t2 = \$7 ; @@ -203202,6 +216455,31 @@ module wrpick_STATE_nia(o, en_o, i); assign ni = \$1 ; endmodule +(* \nmigen.hierarchy = "test_issuer.ti.core.wrpick_STATE_svstate" *) +(* generator = "nMigen" *) +module wrpick_STATE_svstate(o, en_o, i); + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *) + output en_o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *) + input i; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *) + wire ni; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *) + output o; + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *) + wire t0; + assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i; + assign \$3 = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o; + assign en_o = \$3 ; + assign o = t0; + assign t0 = i; + assign ni = \$1 ; +endmodule + (* \nmigen.hierarchy = "test_issuer.ti.core.wrpick_XER_xer_ca" *) (* generator = "nMigen" *) module wrpick_XER_xer_ca(o, en_o, i); @@ -203371,9 +216649,9 @@ module xer(coresync_rst, full_rd__ren, full_rd__data_o, src1__data_o, src1__ren, wire [1:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) wire [1:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [1:0] data_i; @@ -203485,17 +216763,17 @@ module xer(coresync_rst, full_rd__ren, full_rd__data_o, src1__data_o, src1__ren, wire [1:0] reg_2_w2__data_i; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire reg_2_w2__wen; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) reg [2:0] ren_delay = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) reg [2:0] \ren_delay$11 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) reg [2:0] \ren_delay$11$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) reg [2:0] \ren_delay$18 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) reg [2:0] \ren_delay$18$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" *) reg [2:0] \ren_delay$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) output [1:0] src1__data_o; @@ -203596,7 +216874,7 @@ module xer(coresync_rst, full_rd__ren, full_rd__data_o, src1__data_o, src1__ren, always @* begin if (\initial ) begin end \ren_delay$18$next = src3__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \ren_delay$18$next = 3'h0; @@ -203605,9 +216883,9 @@ module xer(coresync_rst, full_rd__ren, full_rd__data_o, src1__data_o, src1__ren, always @* begin if (\initial ) begin end src3__data_o = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" *) casez (\$19 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" */ 1'h1: src3__data_o = \$23 ; endcase @@ -203615,7 +216893,7 @@ module xer(coresync_rst, full_rd__ren, full_rd__data_o, src1__data_o, src1__ren, always @* begin if (\initial ) begin end \ren_delay$next = src1__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \ren_delay$next = 3'h0; @@ -203624,9 +216902,9 @@ module xer(coresync_rst, full_rd__ren, full_rd__data_o, src1__data_o, src1__ren, always @* begin if (\initial ) begin end src1__data_o = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" *) casez (\$5 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" */ 1'h1: src1__data_o = \$9 ; endcase @@ -203634,7 +216912,7 @@ module xer(coresync_rst, full_rd__ren, full_rd__data_o, src1__data_o, src1__ren, always @* begin if (\initial ) begin end \ren_delay$11$next = src2__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (coresync_rst) 1'h1: \ren_delay$11$next = 3'h0; @@ -203643,9 +216921,9 @@ module xer(coresync_rst, full_rd__ren, full_rd__data_o, src1__data_o, src1__ren, always @* begin if (\initial ) begin end src2__data_o = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" *) casez (\$12 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:173" */ 1'h1: src2__data_o = \$16 ; endcase @@ -203701,7 +216979,7 @@ module xics_icp(rst, ics_i_src, ics_i_pri, core_irq_o, icp_wb__ack, icp_wb__cyc, wire [31:0] be_in; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104" *) reg [31:0] be_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) input clk; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" *) output core_irq_o; @@ -203757,7 +217035,7 @@ module xics_icp(rst, ics_i_src, ics_i_pri, core_irq_o, icp_wb__ack, icp_wb__cyc, reg [7:0] min_pri; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106" *) reg [7:0] pending_priority; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) input rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" *) reg wb_ack = 1'h0; @@ -203812,7 +217090,7 @@ module xics_icp(rst, ics_i_src, ics_i_pri, core_irq_o, icp_wb__ack, icp_wb__cyc, always @* begin if (\initial ) begin end { \wb_ack$next , \wb_rd_data$next , \irq$next , \mfrr$next , \cppr$next , \xisr$next } = { \wb_ack$6 , \wb_rd_data$5 , \irq$4 , \mfrr$3 , \cppr$2 , \xisr$1 }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: begin @@ -203913,7 +217191,7 @@ module xics_icp(rst, ics_i_src, ics_i_pri, core_irq_o, icp_wb__ack, icp_wb__cyc, always @* begin if (\initial ) begin end \core_irq_o$next = irq; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \core_irq_o$next = 1'h0; @@ -204211,7 +217489,7 @@ module xics_ics(rst, icp_o_src, icp_o_pri, ics_wb__adr, int_level_i, ics_wb__cyc wire [31:0] be_in; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:308" *) reg [31:0] be_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) input clk; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *) reg [3:0] cur_idx0; @@ -204331,7 +217609,7 @@ module xics_ics(rst, icp_o_src, icp_o_pri, ics_wb__adr, int_level_i, ics_wb__cyc wire reg_is_debug; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:286" *) wire reg_is_xive; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) input rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:260" *) wire wb_valid; @@ -204608,7 +217886,7 @@ module xics_ics(rst, icp_o_src, icp_o_pri, ics_wb__adr, int_level_i, ics_wb__cyc endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: begin @@ -204724,7 +218002,7 @@ module xics_ics(rst, icp_o_src, icp_o_pri, ics_wb__adr, int_level_i, ics_wb__cyc always @* begin if (\initial ) begin end \int_level_l$next = int_level_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \int_level_l$next = 16'h0000; @@ -205024,7 +218302,7 @@ module xics_ics(rst, icp_o_src, icp_o_pri, ics_wb__adr, int_level_i, ics_wb__cyc always @* begin if (\initial ) begin end \ics_wb__dat_r$next = { be_out[7:0], be_out[15:8], be_out[23:16], be_out[31:24] }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \ics_wb__dat_r$next = 32'd0; @@ -205033,7 +218311,7 @@ module xics_ics(rst, icp_o_src, icp_o_pri, ics_wb__adr, int_level_i, ics_wb__cyc always @* begin if (\initial ) begin end \ics_wb__ack$next = wb_valid; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) casez (rst) 1'h1: \ics_wb__ack$next = 1'h0; diff --git a/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v b/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v index 200764c..6487cde 100644 --- a/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v +++ b/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v @@ -1,11 +1,7 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (7bc4eb1) & LiteX (35929c0f) on 2021-04-18 21:41:43 +// Auto-generated by Migen (7bc4eb1) & LiteX (35929c0f) on 2021-05-22 11:51:10 //-------------------------------------------------------------------------------- -module ls180( - output wire i2c_scl, - input wire i2c_sda_i, - output wire i2c_sda_o, - output wire i2c_sda_oe, +module ls180sram4k( output wire [12:0] sdram_a, input wire [15:0] sdram_dq_i, output wire [15:0] sdram_dq_o, @@ -18,18 +14,22 @@ module ls180( output wire [1:0] sdram_ba, output wire [1:0] sdram_dm, output wire sdram_clock, - input wire [15:0] gpio_i, - output wire [15:0] gpio_o, - output wire [15:0] gpio_oe, + output wire i2c_scl, + input wire i2c_sda_i, + output wire i2c_sda_o, + output wire i2c_sda_oe, + input wire eint_0, + input wire eint_1, + input wire eint_2, output wire spimaster_clk, output wire spimaster_mosi, output wire spimaster_cs_n, input wire spimaster_miso, input wire uart_tx, input wire uart_rx, - input wire eint_0, - input wire eint_1, - input wire eint_2, + input wire [15:0] gpio_i, + output wire [15:0] gpio_o, + output wire [15:0] gpio_oe, input wire sys_clk, input wire sys_rst, input wire [1:0] sys_clksel_i, @@ -39,7 +39,7 @@ module ls180( input wire jtag_tck, input wire jtag_tdi, output wire jtag_tdo, - input wire [39:0] nc + input wire [34:0] nc ); (* ram_style = "distributed" *) reg libresocsim_reset_storage = 1'd0; @@ -159,10 +159,6 @@ wire [63:0] libresocsim_libresoc3; wire libresocsim_libresoc_pll_18_o; wire [1:0] libresocsim_libresoc_clk_sel; wire libresocsim_libresoc_pll_ana_o; -wire libresocsim_libresoc_constraintmanager_i2c_scl; -wire libresocsim_libresoc_constraintmanager_i2c_sda_i; -wire libresocsim_libresoc_constraintmanager_i2c_sda_o; -wire libresocsim_libresoc_constraintmanager_i2c_sda_oe; reg [12:0] libresocsim_libresoc_constraintmanager_sdram_a = 13'd0; wire [15:0] libresocsim_libresoc_constraintmanager_sdram_dq_i; reg [15:0] libresocsim_libresoc_constraintmanager_sdram_dq_o = 16'd0; @@ -175,18 +171,22 @@ reg libresocsim_libresoc_constraintmanager_sdram_cke = 1'd0; reg [1:0] libresocsim_libresoc_constraintmanager_sdram_ba = 2'd0; reg [1:0] libresocsim_libresoc_constraintmanager_sdram_dm = 2'd0; reg libresocsim_libresoc_constraintmanager_sdram_clock = 1'd0; -wire [15:0] libresocsim_libresoc_constraintmanager_gpio_i; -reg [15:0] libresocsim_libresoc_constraintmanager_gpio_o = 16'd0; -reg [15:0] libresocsim_libresoc_constraintmanager_gpio_oe = 16'd0; +wire libresocsim_libresoc_constraintmanager_i2c_scl; +wire libresocsim_libresoc_constraintmanager_i2c_sda_i; +wire libresocsim_libresoc_constraintmanager_i2c_sda_o; +wire libresocsim_libresoc_constraintmanager_i2c_sda_oe; +wire libresocsim_libresoc_constraintmanager_eint_0; +wire libresocsim_libresoc_constraintmanager_eint_1; +wire libresocsim_libresoc_constraintmanager_eint_2; reg libresocsim_libresoc_constraintmanager_spimaster_clk = 1'd0; reg libresocsim_libresoc_constraintmanager_spimaster_mosi = 1'd0; reg libresocsim_libresoc_constraintmanager_spimaster_cs_n = 1'd0; wire libresocsim_libresoc_constraintmanager_spimaster_miso; reg libresocsim_libresoc_constraintmanager_uart_tx = 1'd1; reg libresocsim_libresoc_constraintmanager_uart_rx = 1'd0; -wire libresocsim_libresoc_constraintmanager_eint_0; -wire libresocsim_libresoc_constraintmanager_eint_1; -wire libresocsim_libresoc_constraintmanager_eint_2; +wire [15:0] libresocsim_libresoc_constraintmanager_gpio_i; +reg [15:0] libresocsim_libresoc_constraintmanager_gpio_o = 16'd0; +reg [15:0] libresocsim_libresoc_constraintmanager_gpio_oe = 16'd0; reg [29:0] libresocsim_interface0_converted_interface_adr = 30'd0; reg [31:0] libresocsim_interface0_converted_interface_dat_w = 32'd0; wire [31:0] libresocsim_interface0_converted_interface_dat_r; @@ -1071,8 +1071,8 @@ reg [7:0] gpio1_pads_gpio1i = 8'd0; reg [7:0] gpio1_pads_gpio1o = 8'd0; reg [7:0] gpio1_pads_gpio1oe = 8'd0; reg [2:0] eint_tmp = 3'd0; -wire [39:0] nc_1; -reg [39:0] dummy = 40'd0; +wire [34:0] nc_1; +reg [34:0] dummy = 35'd0; wire i2c_scl_1; wire i2c_oe; wire i2c_sda0; @@ -1618,14 +1618,14 @@ end assign libresocsim_libresoc_ibus_dat_r = {libresocsim_interface0_converted_interface_dat_r, libresocsim_converter0_dat_r[63:32]}; always @(*) begin libresocsim_interface0_converted_interface_cyc <= 1'd0; + subfragments_converter0_next_state <= 1'd0; libresocsim_interface0_converted_interface_stb <= 1'd0; + libresocsim_converter0_counter_subfragments_converter0_next_value <= 1'd0; libresocsim_libresoc_ibus_ack <= 1'd0; + libresocsim_converter0_counter_subfragments_converter0_next_value_ce <= 1'd0; libresocsim_interface0_converted_interface_we <= 1'd0; - libresocsim_converter0_counter_subfragments_converter0_next_value <= 1'd0; libresocsim_converter0_skip <= 1'd0; - subfragments_converter0_next_state <= 1'd0; libresocsim_interface0_converted_interface_adr <= 30'd0; - libresocsim_converter0_counter_subfragments_converter0_next_value_ce <= 1'd0; libresocsim_interface0_converted_interface_sel <= 4'd0; subfragments_converter0_next_state <= subfragments_converter0_state; case (subfragments_converter0_state) @@ -1677,16 +1677,16 @@ always @(*) begin end assign libresocsim_libresoc_dbus_dat_r = {libresocsim_interface1_converted_interface_dat_r, libresocsim_converter1_dat_r[63:32]}; always @(*) begin + libresocsim_converter1_counter_subfragments_converter1_next_value <= 1'd0; + libresocsim_converter1_counter_subfragments_converter1_next_value_ce <= 1'd0; libresocsim_converter1_skip <= 1'd0; libresocsim_libresoc_dbus_ack <= 1'd0; libresocsim_interface1_converted_interface_adr <= 30'd0; - subfragments_converter1_next_state <= 1'd0; - libresocsim_converter1_counter_subfragments_converter1_next_value <= 1'd0; libresocsim_interface1_converted_interface_sel <= 4'd0; - libresocsim_converter1_counter_subfragments_converter1_next_value_ce <= 1'd0; libresocsim_interface1_converted_interface_cyc <= 1'd0; libresocsim_interface1_converted_interface_stb <= 1'd0; libresocsim_interface1_converted_interface_we <= 1'd0; + subfragments_converter1_next_state <= 1'd0; subfragments_converter1_next_state <= subfragments_converter1_state; case (subfragments_converter1_state) 1'd1: begin @@ -2112,10 +2112,10 @@ assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (sdram_bankm assign sdram_bankmachine0_cmd_buffer_sink_ready = ((~sdram_bankmachine0_cmd_buffer_source_valid) | sdram_bankmachine0_cmd_buffer_source_ready); always @(*) begin sdram_bankmachine0_refresh_gnt <= 1'd0; - subfragments_bankmachine0_next_state <= 3'd0; sdram_bankmachine0_cmd_valid <= 1'd0; sdram_bankmachine0_row_open <= 1'd0; sdram_bankmachine0_row_close <= 1'd0; + subfragments_bankmachine0_next_state <= 3'd0; sdram_bankmachine0_cmd_payload_cas <= 1'd0; sdram_bankmachine0_cmd_payload_ras <= 1'd0; sdram_bankmachine0_cmd_payload_we <= 1'd0; @@ -2273,6 +2273,7 @@ always @(*) begin sdram_bankmachine1_req_wdata_ready <= 1'd0; sdram_bankmachine1_req_rdata_valid <= 1'd0; sdram_bankmachine1_refresh_gnt <= 1'd0; + subfragments_bankmachine1_next_state <= 3'd0; sdram_bankmachine1_cmd_valid <= 1'd0; sdram_bankmachine1_row_col_n_addr_sel <= 1'd0; sdram_bankmachine1_row_open <= 1'd0; @@ -2281,7 +2282,6 @@ always @(*) begin sdram_bankmachine1_cmd_payload_ras <= 1'd0; sdram_bankmachine1_cmd_payload_we <= 1'd0; sdram_bankmachine1_cmd_payload_is_cmd <= 1'd0; - subfragments_bankmachine1_next_state <= 3'd0; subfragments_bankmachine1_next_state <= subfragments_bankmachine1_state; case (subfragments_bankmachine1_state) 1'd1: begin @@ -2430,14 +2430,14 @@ always @(*) begin sdram_bankmachine2_cmd_payload_we <= 1'd0; sdram_bankmachine2_row_col_n_addr_sel <= 1'd0; sdram_bankmachine2_cmd_payload_is_cmd <= 1'd0; + subfragments_bankmachine2_next_state <= 3'd0; sdram_bankmachine2_cmd_payload_is_read <= 1'd0; sdram_bankmachine2_cmd_payload_is_write <= 1'd0; sdram_bankmachine2_req_wdata_ready <= 1'd0; sdram_bankmachine2_req_rdata_valid <= 1'd0; sdram_bankmachine2_refresh_gnt <= 1'd0; - sdram_bankmachine2_row_open <= 1'd0; sdram_bankmachine2_cmd_valid <= 1'd0; - subfragments_bankmachine2_next_state <= 3'd0; + sdram_bankmachine2_row_open <= 1'd0; sdram_bankmachine2_row_close <= 1'd0; subfragments_bankmachine2_next_state <= subfragments_bankmachine2_state; case (subfragments_bankmachine2_state) @@ -2582,6 +2582,7 @@ assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (sdram_bankm assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (sdram_bankmachine3_cmd_buffer_lookahead_level != 1'd0); assign sdram_bankmachine3_cmd_buffer_sink_ready = ((~sdram_bankmachine3_cmd_buffer_source_valid) | sdram_bankmachine3_cmd_buffer_source_ready); always @(*) begin + subfragments_bankmachine3_next_state <= 3'd0; sdram_bankmachine3_row_open <= 1'd0; sdram_bankmachine3_row_close <= 1'd0; sdram_bankmachine3_cmd_payload_cas <= 1'd0; @@ -2593,7 +2594,6 @@ always @(*) begin sdram_bankmachine3_cmd_payload_is_write <= 1'd0; sdram_bankmachine3_req_wdata_ready <= 1'd0; sdram_bankmachine3_req_rdata_valid <= 1'd0; - subfragments_bankmachine3_next_state <= 3'd0; sdram_bankmachine3_refresh_gnt <= 1'd0; sdram_bankmachine3_cmd_valid <= 1'd0; subfragments_bankmachine3_next_state <= subfragments_bankmachine3_state; @@ -2801,8 +2801,8 @@ assign sdram_dfi_p0_cke = {1{sdram_steerer0}}; assign sdram_dfi_p0_odt = {1{sdram_steerer1}}; always @(*) begin sdram_en0 <= 1'd0; - sdram_choose_req_want_writes <= 1'd0; subfragments_multiplexer_next_state <= 3'd0; + sdram_choose_req_want_writes <= 1'd0; sdram_en1 <= 1'd0; sdram_choose_req_want_reads <= 1'd0; sdram_choose_req_cmd_ready <= 1'd0; @@ -2930,14 +2930,14 @@ assign wb_sdram_dat_r = {litedram_wb_dat_r, converter_dat_r[31:16]}; always @(*) begin converter_skip <= 1'd0; wb_sdram_ack <= 1'd0; - litedram_wb_we <= 1'd0; + subfragments_next_state <= 1'd0; + converter_counter_subfragments_next_value <= 1'd0; + converter_counter_subfragments_next_value_ce <= 1'd0; litedram_wb_adr <= 30'd0; litedram_wb_sel <= 2'd0; litedram_wb_cyc <= 1'd0; litedram_wb_stb <= 1'd0; - subfragments_next_state <= 1'd0; - converter_counter_subfragments_next_value <= 1'd0; - converter_counter_subfragments_next_value_ce <= 1'd0; + litedram_wb_we <= 1'd0; subfragments_next_state <= subfragments_state; case (subfragments_state) 1'd1: begin @@ -3168,6 +3168,7 @@ assign libresocsim_libresoc_constraintmanager_i2c_sda_oe = i2c_oe; assign libresocsim_libresoc_constraintmanager_i2c_sda_o = i2c_sda0; assign i2c_sda1 = libresocsim_libresoc_constraintmanager_i2c_sda_i; always @(*) begin + libresocsim_libresocsim_we_libresocsim_next_value_ce2 <= 1'd0; libresocsim_libresocsim_wishbone_dat_r <= 32'd0; libresocsim_next_state <= 2'd0; libresocsim_libresocsim_dat_w_libresocsim_next_value0 <= 8'd0; @@ -3176,7 +3177,6 @@ always @(*) begin libresocsim_libresocsim_adr_libresocsim_next_value1 <= 13'd0; libresocsim_libresocsim_adr_libresocsim_next_value_ce1 <= 1'd0; libresocsim_libresocsim_we_libresocsim_next_value2 <= 1'd0; - libresocsim_libresocsim_we_libresocsim_next_value_ce2 <= 1'd0; libresocsim_next_state <= libresocsim_state; case (libresocsim_state) 1'd1: begin @@ -3318,9 +3318,9 @@ assign libresocsim_libresocsim_wishbone_cyc = (libresocsim_shared_cyc & libresoc assign libresocsim_shared_err = (((((((((libresocsim_ram_bus_err | ram_bus_ram_bus_err) | libresocsim_libresoc_xics_icp_err) | libresocsim_libresoc_xics_ics_err) | interface0_converted_interface_err) | interface1_converted_interface_err) | interface2_converted_interface_err) | interface3_converted_interface_err) | wb_sdram_err) | libresocsim_libresocsim_wishbone_err); assign libresocsim_wait = ((libresocsim_shared_stb & libresocsim_shared_cyc) & (~libresocsim_shared_ack)); always @(*) begin + libresocsim_shared_dat_r <= 32'd0; libresocsim_shared_ack <= 1'd0; libresocsim_error <= 1'd0; - libresocsim_shared_dat_r <= 32'd0; libresocsim_shared_ack <= (((((((((libresocsim_ram_bus_ack | ram_bus_ram_bus_ack) | libresocsim_libresoc_xics_icp_ack) | libresocsim_libresoc_xics_ics_ack) | interface0_converted_interface_ack) | interface1_converted_interface_ack) | interface2_converted_interface_ack) | interface3_converted_interface_ack) | wb_sdram_ack) | libresocsim_libresocsim_wishbone_ack); libresocsim_shared_dat_r <= (((((((((({32{libresocsim_slave_sel_r[0]}} & libresocsim_ram_bus_dat_r) | ({32{libresocsim_slave_sel_r[1]}} & ram_bus_ram_bus_dat_r)) | ({32{libresocsim_slave_sel_r[2]}} & libresocsim_libresoc_xics_icp_dat_r)) | ({32{libresocsim_slave_sel_r[3]}} & libresocsim_libresoc_xics_ics_dat_r)) | ({32{libresocsim_slave_sel_r[4]}} & interface0_converted_interface_dat_r)) | ({32{libresocsim_slave_sel_r[5]}} & interface1_converted_interface_dat_r)) | ({32{libresocsim_slave_sel_r[6]}} & interface2_converted_interface_dat_r)) | ({32{libresocsim_slave_sel_r[7]}} & interface3_converted_interface_dat_r)) | ({32{libresocsim_slave_sel_r[8]}} & wb_sdram_dat_r)) | ({32{libresocsim_slave_sel_r[9]}} & libresocsim_libresocsim_wishbone_dat_r)); if (libresocsim_done) begin @@ -4519,11 +4519,6 @@ always @(posedge sys_clk_1) begin dummy[32] <= (nc_1[32] | libresocsim_libresoc_interrupt[0]); dummy[33] <= (nc_1[33] | libresocsim_libresoc_interrupt[0]); dummy[34] <= (nc_1[34] | libresocsim_libresoc_interrupt[0]); - dummy[35] <= (nc_1[35] | libresocsim_libresoc_interrupt[0]); - dummy[36] <= (nc_1[36] | libresocsim_libresoc_interrupt[0]); - dummy[37] <= (nc_1[37] | libresocsim_libresoc_interrupt[0]); - dummy[38] <= (nc_1[38] | libresocsim_libresoc_interrupt[0]); - dummy[39] <= (nc_1[39] | libresocsim_libresoc_interrupt[0]); if ((libresocsim_interface0_converted_interface_ack | libresocsim_converter0_skip)) begin libresocsim_converter0_dat_r <= libresocsim_libresoc_ibus_dat_r; end @@ -5655,7 +5650,7 @@ always @(posedge sys_clk_1) begin gpio1_oe_re <= 1'd0; gpio1_out_storage <= 8'd0; gpio1_out_re <= 1'd0; - dummy <= 40'd0; + dummy <= 35'd0; i2c_storage <= 3'd0; i2c_re <= 1'd0; subfragments_converter0_state <= 1'd0;